OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [ata/] [ata_piix.c] - Blame information for rev 62

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 62 marcus.erl
/*
2
 *    ata_piix.c - Intel PATA/SATA controllers
3
 *
4
 *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
5
 *                  Please ALWAYS copy linux-ide@vger.kernel.org
6
 *                  on emails.
7
 *
8
 *
9
 *      Copyright 2003-2005 Red Hat Inc
10
 *      Copyright 2003-2005 Jeff Garzik
11
 *
12
 *
13
 *      Copyright header from piix.c:
14
 *
15
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18
 *
19
 *
20
 *  This program is free software; you can redistribute it and/or modify
21
 *  it under the terms of the GNU General Public License as published by
22
 *  the Free Software Foundation; either version 2, or (at your option)
23
 *  any later version.
24
 *
25
 *  This program is distributed in the hope that it will be useful,
26
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
27
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28
 *  GNU General Public License for more details.
29
 *
30
 *  You should have received a copy of the GNU General Public License
31
 *  along with this program; see the file COPYING.  If not, write to
32
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33
 *
34
 *
35
 *  libata documentation is available via 'make {ps|pdf}docs',
36
 *  as Documentation/DocBook/libata.*
37
 *
38
 *  Hardware documentation available at http://developer.intel.com/
39
 *
40
 * Documentation
41
 *      Publically available from Intel web site. Errata documentation
42
 * is also publically available. As an aide to anyone hacking on this
43
 * driver the list of errata that are relevant is below, going back to
44
 * PIIX4. Older device documentation is now a bit tricky to find.
45
 *
46
 * The chipsets all follow very much the same design. The orginal Triton
47
 * series chipsets do _not_ support independant device timings, but this
48
 * is fixed in Triton II. With the odd mobile exception the chips then
49
 * change little except in gaining more modes until SATA arrives. This
50
 * driver supports only the chips with independant timing (that is those
51
 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52
 * for the early chip drivers.
53
 *
54
 * Errata of note:
55
 *
56
 * Unfixable
57
 *      PIIX4    errata #9      - Only on ultra obscure hw
58
 *      ICH3     errata #13     - Not observed to affect real hw
59
 *                                by Intel
60
 *
61
 * Things we must deal with
62
 *      PIIX4   errata #10      - BM IDE hang with non UDMA
63
 *                                (must stop/start dma to recover)
64
 *      440MX   errata #15      - As PIIX4 errata #10
65
 *      PIIX4   errata #15      - Must not read control registers
66
 *                                during a PIO transfer
67
 *      440MX   errata #13      - As PIIX4 errata #15
68
 *      ICH2    errata #21      - DMA mode 0 doesn't work right
69
 *      ICH0/1  errata #55      - As ICH2 errata #21
70
 *      ICH2    spec c #9       - Extra operations needed to handle
71
 *                                drive hotswap [NOT YET SUPPORTED]
72
 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
73
 *                                and must be dword aligned
74
 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75
 *
76
 * Should have been BIOS fixed:
77
 *      450NX:  errata #19      - DMA hangs on old 450NX
78
 *      450NX:  errata #20      - DMA hangs on old 450NX
79
 *      450NX:  errata #25      - Corruption with DMA on old 450NX
80
 *      ICH3    errata #15      - IDE deadlock under high load
81
 *                                (BIOS must set dev 31 fn 0 bit 23)
82
 *      ICH3    errata #18      - Don't use native mode
83
 */
84
 
85
#include <linux/kernel.h>
86
#include <linux/module.h>
87
#include <linux/pci.h>
88
#include <linux/init.h>
89
#include <linux/blkdev.h>
90
#include <linux/delay.h>
91
#include <linux/device.h>
92
#include <scsi/scsi_host.h>
93
#include <linux/libata.h>
94
#include <linux/dmi.h>
95
 
96
#define DRV_NAME        "ata_piix"
97
#define DRV_VERSION     "2.12"
98
 
99
enum {
100
        PIIX_IOCFG              = 0x54, /* IDE I/O configuration register */
101
        ICH5_PMR                = 0x90, /* port mapping register */
102
        ICH5_PCS                = 0x92, /* port control and status */
103
        PIIX_SCC                = 0x0A, /* sub-class code register */
104
 
105
        PIIX_FLAG_SCR           = (1 << 26), /* SCR available */
106
        PIIX_FLAG_AHCI          = (1 << 27), /* AHCI possible */
107
        PIIX_FLAG_CHECKINTR     = (1 << 28), /* make sure PCI INTx enabled */
108
 
109
        PIIX_PATA_FLAGS         = ATA_FLAG_SLAVE_POSS,
110
        PIIX_SATA_FLAGS         = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111
 
112
        /* combined mode.  if set, PATA is channel 0.
113
         * if clear, PATA is channel 1.
114
         */
115
        PIIX_PORT_ENABLED       = (1 << 0),
116
        PIIX_PORT_PRESENT       = (1 << 4),
117
 
118
        PIIX_80C_PRI            = (1 << 5) | (1 << 4),
119
        PIIX_80C_SEC            = (1 << 7) | (1 << 6),
120
 
121
        /* controller IDs */
122
        piix_pata_mwdma         = 0,     /* PIIX3 MWDMA only */
123
        piix_pata_33,                   /* PIIX4 at 33Mhz */
124
        ich_pata_33,                    /* ICH up to UDMA 33 only */
125
        ich_pata_66,                    /* ICH up to 66 Mhz */
126
        ich_pata_100,                   /* ICH up to UDMA 100 */
127
        ich5_sata,
128
        ich6_sata,
129
        ich6_sata_ahci,
130
        ich6m_sata_ahci,
131
        ich8_sata_ahci,
132
        ich8_2port_sata,
133
        ich8m_apple_sata_ahci,          /* locks up on second port enable */
134
        tolapai_sata_ahci,
135
        piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
136
 
137
        /* constants for mapping table */
138
        P0                      = 0,  /* port 0 */
139
        P1                      = 1,  /* port 1 */
140
        P2                      = 2,  /* port 2 */
141
        P3                      = 3,  /* port 3 */
142
        IDE                     = -1, /* IDE */
143
        NA                      = -2, /* not avaliable */
144
        RV                      = -3, /* reserved */
145
 
146
        PIIX_AHCI_DEVICE        = 6,
147
 
148
        /* host->flags bits */
149
        PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
150
};
151
 
152
struct piix_map_db {
153
        const u32 mask;
154
        const u16 port_enable;
155
        const int map[][4];
156
};
157
 
158
struct piix_host_priv {
159
        const int *map;
160
};
161
 
162
static int piix_init_one(struct pci_dev *pdev,
163
                         const struct pci_device_id *ent);
164
static void piix_pata_error_handler(struct ata_port *ap);
165
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
166
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
167
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168
static int ich_pata_cable_detect(struct ata_port *ap);
169
static u8 piix_vmw_bmdma_status(struct ata_port *ap);
170
#ifdef CONFIG_PM
171
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
172
static int piix_pci_device_resume(struct pci_dev *pdev);
173
#endif
174
 
175
static unsigned int in_module_init = 1;
176
 
177
static const struct pci_device_id piix_pci_tbl[] = {
178
        /* Intel PIIX3 for the 430HX etc */
179
        { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
180
        /* VMware ICH4 */
181
        { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
182
        /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
183
        /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
184
        { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185
        /* Intel PIIX4 */
186
        { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187
        /* Intel PIIX4 */
188
        { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189
        /* Intel PIIX */
190
        { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191
        /* Intel ICH (i810, i815, i840) UDMA 66*/
192
        { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
193
        /* Intel ICH0 : UDMA 33*/
194
        { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
195
        /* Intel ICH2M */
196
        { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197
        /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
198
        { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199
        /*  Intel ICH3M */
200
        { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201
        /* Intel ICH3 (E7500/1) UDMA 100 */
202
        { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203
        /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
204
        { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205
        { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206
        /* Intel ICH5 */
207
        { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208
        /* C-ICH (i810E2) */
209
        { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210
        /* ESB (855GME/875P + 6300ESB) UDMA 100  */
211
        { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212
        /* ICH6 (and 6) (i915) UDMA 100 */
213
        { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214
        /* ICH7/7-R (i945, i975) UDMA 100*/
215
        { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216
        { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217
        /* ICH8 Mobile PATA Controller */
218
        { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219
 
220
        /* NOTE: The following PCI ids must be kept in sync with the
221
         * list in drivers/pci/quirks.c.
222
         */
223
 
224
        /* 82801EB (ICH5) */
225
        { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226
        /* 82801EB (ICH5) */
227
        { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228
        /* 6300ESB (ICH5 variant with broken PCS present bits) */
229
        { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230
        /* 6300ESB pretending RAID */
231
        { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232
        /* 82801FB/FW (ICH6/ICH6W) */
233
        { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
234
        /* 82801FR/FRW (ICH6R/ICH6RW) */
235
        { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
236
        /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
237
        { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
238
        /* 82801GB/GR/GH (ICH7, identical to ICH6) */
239
        { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
240
        /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
241
        { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
242
        /* Enterprise Southbridge 2 (631xESB/632xESB) */
243
        { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
244
        /* SATA Controller 1 IDE (ICH8) */
245
        { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246
        /* SATA Controller 2 IDE (ICH8) */
247
        { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
248
        /* Mobile SATA Controller IDE (ICH8M) */
249
        { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250
        /* Mobile SATA Controller IDE (ICH8M), Apple */
251
        { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
252
        /* SATA Controller IDE (ICH9) */
253
        { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
254
        /* SATA Controller IDE (ICH9) */
255
        { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256
        /* SATA Controller IDE (ICH9) */
257
        { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258
        /* SATA Controller IDE (ICH9M) */
259
        { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260
        /* SATA Controller IDE (ICH9M) */
261
        { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262
        /* SATA Controller IDE (ICH9M) */
263
        { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
264
        /* SATA Controller IDE (Tolapai) */
265
        { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
266
 
267
        { }     /* terminate list */
268
};
269
 
270
static struct pci_driver piix_pci_driver = {
271
        .name                   = DRV_NAME,
272
        .id_table               = piix_pci_tbl,
273
        .probe                  = piix_init_one,
274
        .remove                 = ata_pci_remove_one,
275
#ifdef CONFIG_PM
276
        .suspend                = piix_pci_device_suspend,
277
        .resume                 = piix_pci_device_resume,
278
#endif
279
};
280
 
281
static struct scsi_host_template piix_sht = {
282
        .module                 = THIS_MODULE,
283
        .name                   = DRV_NAME,
284
        .ioctl                  = ata_scsi_ioctl,
285
        .queuecommand           = ata_scsi_queuecmd,
286
        .can_queue              = ATA_DEF_QUEUE,
287
        .this_id                = ATA_SHT_THIS_ID,
288
        .sg_tablesize           = LIBATA_MAX_PRD,
289
        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
290
        .emulated               = ATA_SHT_EMULATED,
291
        .use_clustering         = ATA_SHT_USE_CLUSTERING,
292
        .proc_name              = DRV_NAME,
293
        .dma_boundary           = ATA_DMA_BOUNDARY,
294
        .slave_configure        = ata_scsi_slave_config,
295
        .slave_destroy          = ata_scsi_slave_destroy,
296
        .bios_param             = ata_std_bios_param,
297
};
298
 
299
static const struct ata_port_operations piix_pata_ops = {
300
        .set_piomode            = piix_set_piomode,
301
        .set_dmamode            = piix_set_dmamode,
302
        .mode_filter            = ata_pci_default_filter,
303
 
304
        .tf_load                = ata_tf_load,
305
        .tf_read                = ata_tf_read,
306
        .check_status           = ata_check_status,
307
        .exec_command           = ata_exec_command,
308
        .dev_select             = ata_std_dev_select,
309
 
310
        .bmdma_setup            = ata_bmdma_setup,
311
        .bmdma_start            = ata_bmdma_start,
312
        .bmdma_stop             = ata_bmdma_stop,
313
        .bmdma_status           = ata_bmdma_status,
314
        .qc_prep                = ata_qc_prep,
315
        .qc_issue               = ata_qc_issue_prot,
316
        .data_xfer              = ata_data_xfer,
317
 
318
        .freeze                 = ata_bmdma_freeze,
319
        .thaw                   = ata_bmdma_thaw,
320
        .error_handler          = piix_pata_error_handler,
321
        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
322
        .cable_detect           = ata_cable_40wire,
323
 
324
        .irq_handler            = ata_interrupt,
325
        .irq_clear              = ata_bmdma_irq_clear,
326
        .irq_on                 = ata_irq_on,
327
 
328
        .port_start             = ata_port_start,
329
};
330
 
331
static const struct ata_port_operations ich_pata_ops = {
332
        .set_piomode            = piix_set_piomode,
333
        .set_dmamode            = ich_set_dmamode,
334
        .mode_filter            = ata_pci_default_filter,
335
 
336
        .tf_load                = ata_tf_load,
337
        .tf_read                = ata_tf_read,
338
        .check_status           = ata_check_status,
339
        .exec_command           = ata_exec_command,
340
        .dev_select             = ata_std_dev_select,
341
 
342
        .bmdma_setup            = ata_bmdma_setup,
343
        .bmdma_start            = ata_bmdma_start,
344
        .bmdma_stop             = ata_bmdma_stop,
345
        .bmdma_status           = ata_bmdma_status,
346
        .qc_prep                = ata_qc_prep,
347
        .qc_issue               = ata_qc_issue_prot,
348
        .data_xfer              = ata_data_xfer,
349
 
350
        .freeze                 = ata_bmdma_freeze,
351
        .thaw                   = ata_bmdma_thaw,
352
        .error_handler          = piix_pata_error_handler,
353
        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
354
        .cable_detect           = ich_pata_cable_detect,
355
 
356
        .irq_handler            = ata_interrupt,
357
        .irq_clear              = ata_bmdma_irq_clear,
358
        .irq_on                 = ata_irq_on,
359
 
360
        .port_start             = ata_port_start,
361
};
362
 
363
static const struct ata_port_operations piix_sata_ops = {
364
        .tf_load                = ata_tf_load,
365
        .tf_read                = ata_tf_read,
366
        .check_status           = ata_check_status,
367
        .exec_command           = ata_exec_command,
368
        .dev_select             = ata_std_dev_select,
369
 
370
        .bmdma_setup            = ata_bmdma_setup,
371
        .bmdma_start            = ata_bmdma_start,
372
        .bmdma_stop             = ata_bmdma_stop,
373
        .bmdma_status           = ata_bmdma_status,
374
        .qc_prep                = ata_qc_prep,
375
        .qc_issue               = ata_qc_issue_prot,
376
        .data_xfer              = ata_data_xfer,
377
 
378
        .freeze                 = ata_bmdma_freeze,
379
        .thaw                   = ata_bmdma_thaw,
380
        .error_handler          = ata_bmdma_error_handler,
381
        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
382
 
383
        .irq_handler            = ata_interrupt,
384
        .irq_clear              = ata_bmdma_irq_clear,
385
        .irq_on                 = ata_irq_on,
386
 
387
        .port_start             = ata_port_start,
388
};
389
 
390
static const struct ata_port_operations piix_vmw_ops = {
391
        .set_piomode            = piix_set_piomode,
392
        .set_dmamode            = piix_set_dmamode,
393
        .mode_filter            = ata_pci_default_filter,
394
 
395
        .tf_load                = ata_tf_load,
396
        .tf_read                = ata_tf_read,
397
        .check_status           = ata_check_status,
398
        .exec_command           = ata_exec_command,
399
        .dev_select             = ata_std_dev_select,
400
 
401
        .bmdma_setup            = ata_bmdma_setup,
402
        .bmdma_start            = ata_bmdma_start,
403
        .bmdma_stop             = ata_bmdma_stop,
404
        .bmdma_status           = piix_vmw_bmdma_status,
405
        .qc_prep                = ata_qc_prep,
406
        .qc_issue               = ata_qc_issue_prot,
407
        .data_xfer              = ata_data_xfer,
408
 
409
        .freeze                 = ata_bmdma_freeze,
410
        .thaw                   = ata_bmdma_thaw,
411
        .error_handler          = piix_pata_error_handler,
412
        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
413
        .cable_detect           = ata_cable_40wire,
414
 
415
        .irq_handler            = ata_interrupt,
416
        .irq_clear              = ata_bmdma_irq_clear,
417
        .irq_on                 = ata_irq_on,
418
 
419
        .port_start             = ata_port_start,
420
};
421
 
422
static const struct piix_map_db ich5_map_db = {
423
        .mask = 0x7,
424
        .port_enable = 0x3,
425
        .map = {
426
                /* PM   PS   SM   SS       MAP  */
427
                {  P0,  NA,  P1,  NA }, /* 000b */
428
                {  P1,  NA,  P0,  NA }, /* 001b */
429
                {  RV,  RV,  RV,  RV },
430
                {  RV,  RV,  RV,  RV },
431
                {  P0,  P1, IDE, IDE }, /* 100b */
432
                {  P1,  P0, IDE, IDE }, /* 101b */
433
                { IDE, IDE,  P0,  P1 }, /* 110b */
434
                { IDE, IDE,  P1,  P0 }, /* 111b */
435
        },
436
};
437
 
438
static const struct piix_map_db ich6_map_db = {
439
        .mask = 0x3,
440
        .port_enable = 0xf,
441
        .map = {
442
                /* PM   PS   SM   SS       MAP */
443
                {  P0,  P2,  P1,  P3 }, /* 00b */
444
                { IDE, IDE,  P1,  P3 }, /* 01b */
445
                {  P0,  P2, IDE, IDE }, /* 10b */
446
                {  RV,  RV,  RV,  RV },
447
        },
448
};
449
 
450
static const struct piix_map_db ich6m_map_db = {
451
        .mask = 0x3,
452
        .port_enable = 0x5,
453
 
454
        /* Map 01b isn't specified in the doc but some notebooks use
455
         * it anyway.  MAP 01b have been spotted on both ICH6M and
456
         * ICH7M.
457
         */
458
        .map = {
459
                /* PM   PS   SM   SS       MAP */
460
                {  P0,  P2,  NA,  NA }, /* 00b */
461
                { IDE, IDE,  P1,  P3 }, /* 01b */
462
                {  P0,  P2, IDE, IDE }, /* 10b */
463
                {  RV,  RV,  RV,  RV },
464
        },
465
};
466
 
467
static const struct piix_map_db ich8_map_db = {
468
        .mask = 0x3,
469
        .port_enable = 0xf,
470
        .map = {
471
                /* PM   PS   SM   SS       MAP */
472
                {  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
473
                {  RV,  RV,  RV,  RV },
474
                {  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
475
                {  RV,  RV,  RV,  RV },
476
        },
477
};
478
 
479
static const struct piix_map_db ich8_2port_map_db = {
480
        .mask = 0x3,
481
        .port_enable = 0x3,
482
        .map = {
483
                /* PM   PS   SM   SS       MAP */
484
                {  P0,  NA,  P1,  NA }, /* 00b */
485
                {  RV,  RV,  RV,  RV }, /* 01b */
486
                {  RV,  RV,  RV,  RV }, /* 10b */
487
                {  RV,  RV,  RV,  RV },
488
        },
489
};
490
 
491
static const struct piix_map_db ich8m_apple_map_db = {
492
        .mask = 0x3,
493
        .port_enable = 0x1,
494
        .map = {
495
                /* PM   PS   SM   SS       MAP */
496
                {  P0,  NA,  NA,  NA }, /* 00b */
497
                {  RV,  RV,  RV,  RV },
498
                {  P0,  P2, IDE, IDE }, /* 10b */
499
                {  RV,  RV,  RV,  RV },
500
        },
501
};
502
 
503
static const struct piix_map_db tolapai_map_db = {
504
        .mask = 0x3,
505
        .port_enable = 0x3,
506
        .map = {
507
                /* PM   PS   SM   SS       MAP */
508
                {  P0,  NA,  P1,  NA }, /* 00b */
509
                {  RV,  RV,  RV,  RV }, /* 01b */
510
                {  RV,  RV,  RV,  RV }, /* 10b */
511
                {  RV,  RV,  RV,  RV },
512
        },
513
};
514
 
515
static const struct piix_map_db *piix_map_db_table[] = {
516
        [ich5_sata]             = &ich5_map_db,
517
        [ich6_sata]             = &ich6_map_db,
518
        [ich6_sata_ahci]        = &ich6_map_db,
519
        [ich6m_sata_ahci]       = &ich6m_map_db,
520
        [ich8_sata_ahci]        = &ich8_map_db,
521
        [ich8_2port_sata]       = &ich8_2port_map_db,
522
        [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
523
        [tolapai_sata_ahci]     = &tolapai_map_db,
524
};
525
 
526
static struct ata_port_info piix_port_info[] = {
527
        [piix_pata_mwdma] =     /* PIIX3 MWDMA only */
528
        {
529
                .sht            = &piix_sht,
530
                .flags          = PIIX_PATA_FLAGS,
531
                .pio_mask       = 0x1f, /* pio0-4 */
532
                .mwdma_mask     = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
533
                .port_ops       = &piix_pata_ops,
534
        },
535
 
536
        [piix_pata_33] =        /* PIIX4 at 33MHz */
537
        {
538
                .sht            = &piix_sht,
539
                .flags          = PIIX_PATA_FLAGS,
540
                .pio_mask       = 0x1f, /* pio0-4 */
541
                .mwdma_mask     = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
542
                .udma_mask      = ATA_UDMA_MASK_40C,
543
                .port_ops       = &piix_pata_ops,
544
        },
545
 
546
        [ich_pata_33] =         /* ICH0 - ICH at 33Mhz*/
547
        {
548
                .sht            = &piix_sht,
549
                .flags          = PIIX_PATA_FLAGS,
550
                .pio_mask       = 0x1f, /* pio 0-4 */
551
                .mwdma_mask     = 0x06, /* Check: maybe 0x07  */
552
                .udma_mask      = ATA_UDMA2, /* UDMA33 */
553
                .port_ops       = &ich_pata_ops,
554
        },
555
 
556
        [ich_pata_66] =         /* ICH controllers up to 66MHz */
557
        {
558
                .sht            = &piix_sht,
559
                .flags          = PIIX_PATA_FLAGS,
560
                .pio_mask       = 0x1f, /* pio 0-4 */
561
                .mwdma_mask     = 0x06, /* MWDMA0 is broken on chip */
562
                .udma_mask      = ATA_UDMA4,
563
                .port_ops       = &ich_pata_ops,
564
        },
565
 
566
        [ich_pata_100] =
567
        {
568
                .sht            = &piix_sht,
569
                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
570
                .pio_mask       = 0x1f, /* pio0-4 */
571
                .mwdma_mask     = 0x06, /* mwdma1-2 */
572
                .udma_mask      = ATA_UDMA5, /* udma0-5 */
573
                .port_ops       = &ich_pata_ops,
574
        },
575
 
576
        [ich5_sata] =
577
        {
578
                .sht            = &piix_sht,
579
                .flags          = PIIX_SATA_FLAGS,
580
                .pio_mask       = 0x1f, /* pio0-4 */
581
                .mwdma_mask     = 0x07, /* mwdma0-2 */
582
                .udma_mask      = ATA_UDMA6,
583
                .port_ops       = &piix_sata_ops,
584
        },
585
 
586
        [ich6_sata] =
587
        {
588
                .sht            = &piix_sht,
589
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
590
                .pio_mask       = 0x1f, /* pio0-4 */
591
                .mwdma_mask     = 0x07, /* mwdma0-2 */
592
                .udma_mask      = ATA_UDMA6,
593
                .port_ops       = &piix_sata_ops,
594
        },
595
 
596
        [ich6_sata_ahci] =
597
        {
598
                .sht            = &piix_sht,
599
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
600
                                  PIIX_FLAG_AHCI,
601
                .pio_mask       = 0x1f, /* pio0-4 */
602
                .mwdma_mask     = 0x07, /* mwdma0-2 */
603
                .udma_mask      = ATA_UDMA6,
604
                .port_ops       = &piix_sata_ops,
605
        },
606
 
607
        [ich6m_sata_ahci] =
608
        {
609
                .sht            = &piix_sht,
610
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
611
                                  PIIX_FLAG_AHCI,
612
                .pio_mask       = 0x1f, /* pio0-4 */
613
                .mwdma_mask     = 0x07, /* mwdma0-2 */
614
                .udma_mask      = ATA_UDMA6,
615
                .port_ops       = &piix_sata_ops,
616
        },
617
 
618
        [ich8_sata_ahci] =
619
        {
620
                .sht            = &piix_sht,
621
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
622
                                  PIIX_FLAG_AHCI,
623
                .pio_mask       = 0x1f, /* pio0-4 */
624
                .mwdma_mask     = 0x07, /* mwdma0-2 */
625
                .udma_mask      = ATA_UDMA6,
626
                .port_ops       = &piix_sata_ops,
627
        },
628
 
629
        [ich8_2port_sata] =
630
        {
631
                .sht            = &piix_sht,
632
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
633
                                  PIIX_FLAG_AHCI,
634
                .pio_mask       = 0x1f, /* pio0-4 */
635
                .mwdma_mask     = 0x07, /* mwdma0-2 */
636
                .udma_mask      = ATA_UDMA6,
637
                .port_ops       = &piix_sata_ops,
638
        },
639
 
640
        [tolapai_sata_ahci] =
641
        {
642
                .sht            = &piix_sht,
643
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
644
                                  PIIX_FLAG_AHCI,
645
                .pio_mask       = 0x1f, /* pio0-4 */
646
                .mwdma_mask     = 0x07, /* mwdma0-2 */
647
                .udma_mask      = ATA_UDMA6,
648
                .port_ops       = &piix_sata_ops,
649
        },
650
 
651
        [ich8m_apple_sata_ahci] =
652
        {
653
                .sht            = &piix_sht,
654
                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
655
                                  PIIX_FLAG_AHCI,
656
                .pio_mask       = 0x1f, /* pio0-4 */
657
                .mwdma_mask     = 0x07, /* mwdma0-2 */
658
                .udma_mask      = ATA_UDMA6,
659
                .port_ops       = &piix_sata_ops,
660
        },
661
 
662
        [piix_pata_vmw] =
663
        {
664
                .sht            = &piix_sht,
665
                .flags          = PIIX_PATA_FLAGS,
666
                .pio_mask       = 0x1f, /* pio0-4 */
667
                .mwdma_mask     = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
668
                .udma_mask      = ATA_UDMA_MASK_40C,
669
                .port_ops       = &piix_vmw_ops,
670
        },
671
 
672
};
673
 
674
static struct pci_bits piix_enable_bits[] = {
675
        { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
676
        { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
677
};
678
 
679
MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
680
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
681
MODULE_LICENSE("GPL");
682
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
683
MODULE_VERSION(DRV_VERSION);
684
 
685
struct ich_laptop {
686
        u16 device;
687
        u16 subvendor;
688
        u16 subdevice;
689
};
690
 
691
/*
692
 *      List of laptops that use short cables rather than 80 wire
693
 */
694
 
695
static const struct ich_laptop ich_laptop[] = {
696
        /* devid, subvendor, subdev */
697
        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
698
        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
699
        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
700
        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
701
        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
702
        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on ACER Aspire 2023WLMi */
703
        /* end marker */
704
        { 0, }
705
};
706
 
707
/**
708
 *      ich_pata_cable_detect - Probe host controller cable detect info
709
 *      @ap: Port for which cable detect info is desired
710
 *
711
 *      Read 80c cable indicator from ATA PCI device's PCI config
712
 *      register.  This register is normally set by firmware (BIOS).
713
 *
714
 *      LOCKING:
715
 *      None (inherited from caller).
716
 */
717
 
718
static int ich_pata_cable_detect(struct ata_port *ap)
719
{
720
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
721
        const struct ich_laptop *lap = &ich_laptop[0];
722
        u8 tmp, mask;
723
 
724
        /* Check for specials - Acer Aspire 5602WLMi */
725
        while (lap->device) {
726
                if (lap->device == pdev->device &&
727
                    lap->subvendor == pdev->subsystem_vendor &&
728
                    lap->subdevice == pdev->subsystem_device)
729
                        return ATA_CBL_PATA40_SHORT;
730
 
731
                lap++;
732
        }
733
 
734
        /* check BIOS cable detect results */
735
        mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
736
        pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
737
        if ((tmp & mask) == 0)
738
                return ATA_CBL_PATA40;
739
        return ATA_CBL_PATA80;
740
}
741
 
742
/**
743
 *      piix_pata_prereset - prereset for PATA host controller
744
 *      @link: Target link
745
 *      @deadline: deadline jiffies for the operation
746
 *
747
 *      LOCKING:
748
 *      None (inherited from caller).
749
 */
750
static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
751
{
752
        struct ata_port *ap = link->ap;
753
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
754
 
755
        if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
756
                return -ENOENT;
757
        return ata_std_prereset(link, deadline);
758
}
759
 
760
static void piix_pata_error_handler(struct ata_port *ap)
761
{
762
        ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
763
                           ata_std_postreset);
764
}
765
 
766
/**
767
 *      piix_set_piomode - Initialize host controller PATA PIO timings
768
 *      @ap: Port whose timings we are configuring
769
 *      @adev: um
770
 *
771
 *      Set PIO mode for device, in host controller PCI config space.
772
 *
773
 *      LOCKING:
774
 *      None (inherited from caller).
775
 */
776
 
777
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
778
{
779
        unsigned int pio        = adev->pio_mode - XFER_PIO_0;
780
        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
781
        unsigned int is_slave   = (adev->devno != 0);
782
        unsigned int master_port= ap->port_no ? 0x42 : 0x40;
783
        unsigned int slave_port = 0x44;
784
        u16 master_data;
785
        u8 slave_data;
786
        u8 udma_enable;
787
        int control = 0;
788
 
789
        /*
790
         *      See Intel Document 298600-004 for the timing programing rules
791
         *      for ICH controllers.
792
         */
793
 
794
        static const     /* ISP  RTC */
795
        u8 timings[][2] = { { 0, 0 },
796
                            { 0, 0 },
797
                            { 1, 0 },
798
                            { 2, 1 },
799
                            { 2, 3 }, };
800
 
801
        if (pio >= 2)
802
                control |= 1;   /* TIME1 enable */
803
        if (ata_pio_need_iordy(adev))
804
                control |= 2;   /* IE enable */
805
 
806
        /* Intel specifies that the PPE functionality is for disk only */
807
        if (adev->class == ATA_DEV_ATA)
808
                control |= 4;   /* PPE enable */
809
 
810
        /* PIO configuration clears DTE unconditionally.  It will be
811
         * programmed in set_dmamode which is guaranteed to be called
812
         * after set_piomode if any DMA mode is available.
813
         */
814
        pci_read_config_word(dev, master_port, &master_data);
815
        if (is_slave) {
816
                /* clear TIME1|IE1|PPE1|DTE1 */
817
                master_data &= 0xff0f;
818
                /* Enable SITRE (seperate slave timing register) */
819
                master_data |= 0x4000;
820
                /* enable PPE1, IE1 and TIME1 as needed */
821
                master_data |= (control << 4);
822
                pci_read_config_byte(dev, slave_port, &slave_data);
823
                slave_data &= (ap->port_no ? 0x0f : 0xf0);
824
                /* Load the timing nibble for this slave */
825
                slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
826
                                                << (ap->port_no ? 4 : 0);
827
        } else {
828
                /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
829
                master_data &= 0xccf0;
830
                /* Enable PPE, IE and TIME as appropriate */
831
                master_data |= control;
832
                /* load ISP and RCT */
833
                master_data |=
834
                        (timings[pio][0] << 12) |
835
                        (timings[pio][1] << 8);
836
        }
837
        pci_write_config_word(dev, master_port, master_data);
838
        if (is_slave)
839
                pci_write_config_byte(dev, slave_port, slave_data);
840
 
841
        /* Ensure the UDMA bit is off - it will be turned back on if
842
           UDMA is selected */
843
 
844
        if (ap->udma_mask) {
845
                pci_read_config_byte(dev, 0x48, &udma_enable);
846
                udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
847
                pci_write_config_byte(dev, 0x48, udma_enable);
848
        }
849
}
850
 
851
/**
852
 *      do_pata_set_dmamode - Initialize host controller PATA PIO timings
853
 *      @ap: Port whose timings we are configuring
854
 *      @adev: Drive in question
855
 *      @udma: udma mode, 0 - 6
856
 *      @isich: set if the chip is an ICH device
857
 *
858
 *      Set UDMA mode for device, in host controller PCI config space.
859
 *
860
 *      LOCKING:
861
 *      None (inherited from caller).
862
 */
863
 
864
static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
865
{
866
        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
867
        u8 master_port          = ap->port_no ? 0x42 : 0x40;
868
        u16 master_data;
869
        u8 speed                = adev->dma_mode;
870
        int devid               = adev->devno + 2 * ap->port_no;
871
        u8 udma_enable          = 0;
872
 
873
        static const     /* ISP  RTC */
874
        u8 timings[][2] = { { 0, 0 },
875
                            { 0, 0 },
876
                            { 1, 0 },
877
                            { 2, 1 },
878
                            { 2, 3 }, };
879
 
880
        pci_read_config_word(dev, master_port, &master_data);
881
        if (ap->udma_mask)
882
                pci_read_config_byte(dev, 0x48, &udma_enable);
883
 
884
        if (speed >= XFER_UDMA_0) {
885
                unsigned int udma = adev->dma_mode - XFER_UDMA_0;
886
                u16 udma_timing;
887
                u16 ideconf;
888
                int u_clock, u_speed;
889
 
890
                /*
891
                 * UDMA is handled by a combination of clock switching and
892
                 * selection of dividers
893
                 *
894
                 * Handy rule: Odd modes are UDMATIMx 01, even are 02
895
                 *             except UDMA0 which is 00
896
                 */
897
                u_speed = min(2 - (udma & 1), udma);
898
                if (udma == 5)
899
                        u_clock = 0x1000;       /* 100Mhz */
900
                else if (udma > 2)
901
                        u_clock = 1;            /* 66Mhz */
902
                else
903
                        u_clock = 0;             /* 33Mhz */
904
 
905
                udma_enable |= (1 << devid);
906
 
907
                /* Load the CT/RP selection */
908
                pci_read_config_word(dev, 0x4A, &udma_timing);
909
                udma_timing &= ~(3 << (4 * devid));
910
                udma_timing |= u_speed << (4 * devid);
911
                pci_write_config_word(dev, 0x4A, udma_timing);
912
 
913
                if (isich) {
914
                        /* Select a 33/66/100Mhz clock */
915
                        pci_read_config_word(dev, 0x54, &ideconf);
916
                        ideconf &= ~(0x1001 << devid);
917
                        ideconf |= u_clock << devid;
918
                        /* For ICH or later we should set bit 10 for better
919
                           performance (WR_PingPong_En) */
920
                        pci_write_config_word(dev, 0x54, ideconf);
921
                }
922
        } else {
923
                /*
924
                 * MWDMA is driven by the PIO timings. We must also enable
925
                 * IORDY unconditionally along with TIME1. PPE has already
926
                 * been set when the PIO timing was set.
927
                 */
928
                unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
929
                unsigned int control;
930
                u8 slave_data;
931
                const unsigned int needed_pio[3] = {
932
                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
933
                };
934
                int pio = needed_pio[mwdma] - XFER_PIO_0;
935
 
936
                control = 3;    /* IORDY|TIME1 */
937
 
938
                /* If the drive MWDMA is faster than it can do PIO then
939
                   we must force PIO into PIO0 */
940
 
941
                if (adev->pio_mode < needed_pio[mwdma])
942
                        /* Enable DMA timing only */
943
                        control |= 8;   /* PIO cycles in PIO0 */
944
 
945
                if (adev->devno) {      /* Slave */
946
                        master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
947
                        master_data |= control << 4;
948
                        pci_read_config_byte(dev, 0x44, &slave_data);
949
                        slave_data &= (ap->port_no ? 0x0f : 0xf0);
950
                        /* Load the matching timing */
951
                        slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
952
                        pci_write_config_byte(dev, 0x44, slave_data);
953
                } else {        /* Master */
954
                        master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
955
                                                   and master timing bits */
956
                        master_data |= control;
957
                        master_data |=
958
                                (timings[pio][0] << 12) |
959
                                (timings[pio][1] << 8);
960
                }
961
 
962
                if (ap->udma_mask) {
963
                        udma_enable &= ~(1 << devid);
964
                        pci_write_config_word(dev, master_port, master_data);
965
                }
966
        }
967
        /* Don't scribble on 0x48 if the controller does not support UDMA */
968
        if (ap->udma_mask)
969
                pci_write_config_byte(dev, 0x48, udma_enable);
970
}
971
 
972
/**
973
 *      piix_set_dmamode - Initialize host controller PATA DMA timings
974
 *      @ap: Port whose timings we are configuring
975
 *      @adev: um
976
 *
977
 *      Set MW/UDMA mode for device, in host controller PCI config space.
978
 *
979
 *      LOCKING:
980
 *      None (inherited from caller).
981
 */
982
 
983
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
984
{
985
        do_pata_set_dmamode(ap, adev, 0);
986
}
987
 
988
/**
989
 *      ich_set_dmamode - Initialize host controller PATA DMA timings
990
 *      @ap: Port whose timings we are configuring
991
 *      @adev: um
992
 *
993
 *      Set MW/UDMA mode for device, in host controller PCI config space.
994
 *
995
 *      LOCKING:
996
 *      None (inherited from caller).
997
 */
998
 
999
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
1000
{
1001
        do_pata_set_dmamode(ap, adev, 1);
1002
}
1003
 
1004
#ifdef CONFIG_PM
1005
static int piix_broken_suspend(void)
1006
{
1007
        static const struct dmi_system_id sysids[] = {
1008
                {
1009
                        .ident = "TECRA M3",
1010
                        .matches = {
1011
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1012
                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1013
                        },
1014
                },
1015
                {
1016
                        .ident = "TECRA M3",
1017
                        .matches = {
1018
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1019
                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1020
                        },
1021
                },
1022
                {
1023
                        .ident = "TECRA M4",
1024
                        .matches = {
1025
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1026
                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1027
                        },
1028
                },
1029
                {
1030
                        .ident = "TECRA M5",
1031
                        .matches = {
1032
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1033
                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1034
                        },
1035
                },
1036
                {
1037
                        .ident = "TECRA M7",
1038
                        .matches = {
1039
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1040
                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1041
                        },
1042
                },
1043
                {
1044
                        .ident = "TECRA A8",
1045
                        .matches = {
1046
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1047
                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1048
                        },
1049
                },
1050
                {
1051
                        .ident = "Satellite R25",
1052
                        .matches = {
1053
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1054
                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1055
                        },
1056
                },
1057
                {
1058
                        .ident = "Satellite U200",
1059
                        .matches = {
1060
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1061
                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1062
                        },
1063
                },
1064
                {
1065
                        .ident = "Satellite U200",
1066
                        .matches = {
1067
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1068
                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1069
                        },
1070
                },
1071
                {
1072
                        .ident = "Satellite Pro U200",
1073
                        .matches = {
1074
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1075
                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1076
                        },
1077
                },
1078
                {
1079
                        .ident = "Satellite U205",
1080
                        .matches = {
1081
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1082
                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1083
                        },
1084
                },
1085
                {
1086
                        .ident = "SATELLITE U205",
1087
                        .matches = {
1088
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1089
                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1090
                        },
1091
                },
1092
                {
1093
                        .ident = "Portege M500",
1094
                        .matches = {
1095
                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1096
                                DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1097
                        },
1098
                },
1099
 
1100
                { }     /* terminate list */
1101
        };
1102
        static const char *oemstrs[] = {
1103
                "Tecra M3,",
1104
        };
1105
        int i;
1106
 
1107
        if (dmi_check_system(sysids))
1108
                return 1;
1109
 
1110
        for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1111
                if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1112
                        return 1;
1113
 
1114
        return 0;
1115
}
1116
 
1117
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1118
{
1119
        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1120
        unsigned long flags;
1121
        int rc = 0;
1122
 
1123
        rc = ata_host_suspend(host, mesg);
1124
        if (rc)
1125
                return rc;
1126
 
1127
        /* Some braindamaged ACPI suspend implementations expect the
1128
         * controller to be awake on entry; otherwise, it burns cpu
1129
         * cycles and power trying to do something to the sleeping
1130
         * beauty.
1131
         */
1132
        if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1133
                pci_save_state(pdev);
1134
 
1135
                /* mark its power state as "unknown", since we don't
1136
                 * know if e.g. the BIOS will change its device state
1137
                 * when we suspend.
1138
                 */
1139
                if (pdev->current_state == PCI_D0)
1140
                        pdev->current_state = PCI_UNKNOWN;
1141
 
1142
                /* tell resume that it's waking up from broken suspend */
1143
                spin_lock_irqsave(&host->lock, flags);
1144
                host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1145
                spin_unlock_irqrestore(&host->lock, flags);
1146
        } else
1147
                ata_pci_device_do_suspend(pdev, mesg);
1148
 
1149
        return 0;
1150
}
1151
 
1152
static int piix_pci_device_resume(struct pci_dev *pdev)
1153
{
1154
        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1155
        unsigned long flags;
1156
        int rc;
1157
 
1158
        if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1159
                spin_lock_irqsave(&host->lock, flags);
1160
                host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1161
                spin_unlock_irqrestore(&host->lock, flags);
1162
 
1163
                pci_set_power_state(pdev, PCI_D0);
1164
                pci_restore_state(pdev);
1165
 
1166
                /* PCI device wasn't disabled during suspend.  Use
1167
                 * pci_reenable_device() to avoid affecting the enable
1168
                 * count.
1169
                 */
1170
                rc = pci_reenable_device(pdev);
1171
                if (rc)
1172
                        dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1173
                                   "device after resume (%d)\n", rc);
1174
        } else
1175
                rc = ata_pci_device_do_resume(pdev);
1176
 
1177
        if (rc == 0)
1178
                ata_host_resume(host);
1179
 
1180
        return rc;
1181
}
1182
#endif
1183
 
1184
static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1185
{
1186
        return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1187
}
1188
 
1189
#define AHCI_PCI_BAR 5
1190
#define AHCI_GLOBAL_CTL 0x04
1191
#define AHCI_ENABLE (1 << 31)
1192
static int piix_disable_ahci(struct pci_dev *pdev)
1193
{
1194
        void __iomem *mmio;
1195
        u32 tmp;
1196
        int rc = 0;
1197
 
1198
        /* BUG: pci_enable_device has not yet been called.  This
1199
         * works because this device is usually set up by BIOS.
1200
         */
1201
 
1202
        if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1203
            !pci_resource_len(pdev, AHCI_PCI_BAR))
1204
                return 0;
1205
 
1206
        mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1207
        if (!mmio)
1208
                return -ENOMEM;
1209
 
1210
        tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1211
        if (tmp & AHCI_ENABLE) {
1212
                tmp &= ~AHCI_ENABLE;
1213
                iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1214
 
1215
                tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1216
                if (tmp & AHCI_ENABLE)
1217
                        rc = -EIO;
1218
        }
1219
 
1220
        pci_iounmap(pdev, mmio);
1221
        return rc;
1222
}
1223
 
1224
/**
1225
 *      piix_check_450nx_errata -       Check for problem 450NX setup
1226
 *      @ata_dev: the PCI device to check
1227
 *
1228
 *      Check for the present of 450NX errata #19 and errata #25. If
1229
 *      they are found return an error code so we can turn off DMA
1230
 */
1231
 
1232
static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1233
{
1234
        struct pci_dev *pdev = NULL;
1235
        u16 cfg;
1236
        int no_piix_dma = 0;
1237
 
1238
        while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1239
                /* Look for 450NX PXB. Check for problem configurations
1240
                   A PCI quirk checks bit 6 already */
1241
                pci_read_config_word(pdev, 0x41, &cfg);
1242
                /* Only on the original revision: IDE DMA can hang */
1243
                if (pdev->revision == 0x00)
1244
                        no_piix_dma = 1;
1245
                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1246
                else if (cfg & (1<<14) && pdev->revision < 5)
1247
                        no_piix_dma = 2;
1248
        }
1249
        if (no_piix_dma)
1250
                dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1251
        if (no_piix_dma == 2)
1252
                dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1253
        return no_piix_dma;
1254
}
1255
 
1256
static void __devinit piix_init_pcs(struct pci_dev *pdev,
1257
                                    struct ata_port_info *pinfo,
1258
                                    const struct piix_map_db *map_db)
1259
{
1260
        u16 pcs, new_pcs;
1261
 
1262
        pci_read_config_word(pdev, ICH5_PCS, &pcs);
1263
 
1264
        new_pcs = pcs | map_db->port_enable;
1265
 
1266
        if (new_pcs != pcs) {
1267
                DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1268
                pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1269
                msleep(150);
1270
        }
1271
}
1272
 
1273
static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1274
                                         struct ata_port_info *pinfo,
1275
                                         const struct piix_map_db *map_db)
1276
{
1277
        struct piix_host_priv *hpriv = pinfo[0].private_data;
1278
        const int *map;
1279
        int i, invalid_map = 0;
1280
        u8 map_value;
1281
 
1282
        pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1283
 
1284
        map = map_db->map[map_value & map_db->mask];
1285
 
1286
        dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1287
        for (i = 0; i < 4; i++) {
1288
                switch (map[i]) {
1289
                case RV:
1290
                        invalid_map = 1;
1291
                        printk(" XX");
1292
                        break;
1293
 
1294
                case NA:
1295
                        printk(" --");
1296
                        break;
1297
 
1298
                case IDE:
1299
                        WARN_ON((i & 1) || map[i + 1] != IDE);
1300
                        pinfo[i / 2] = piix_port_info[ich_pata_100];
1301
                        pinfo[i / 2].private_data = hpriv;
1302
                        i++;
1303
                        printk(" IDE IDE");
1304
                        break;
1305
 
1306
                default:
1307
                        printk(" P%d", map[i]);
1308
                        if (i & 1)
1309
                                pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1310
                        break;
1311
                }
1312
        }
1313
        printk(" ]\n");
1314
 
1315
        if (invalid_map)
1316
                dev_printk(KERN_ERR, &pdev->dev,
1317
                           "invalid MAP value %u\n", map_value);
1318
 
1319
        hpriv->map = map;
1320
}
1321
 
1322
static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1323
{
1324
        static const struct dmi_system_id sysids[] = {
1325
                {
1326
                        /* Clevo M570U sets IOCFG bit 18 if the cdrom
1327
                         * isn't used to boot the system which
1328
                         * disables the channel.
1329
                         */
1330
                        .ident = "M570U",
1331
                        .matches = {
1332
                                DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1333
                                DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1334
                        },
1335
                },
1336
 
1337
                { }     /* terminate list */
1338
        };
1339
        u32 iocfg;
1340
 
1341
        if (!dmi_check_system(sysids))
1342
                return;
1343
 
1344
        /* The datasheet says that bit 18 is NOOP but certain systems
1345
         * seem to use it to disable a channel.  Clear the bit on the
1346
         * affected systems.
1347
         */
1348
        pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1349
        if (iocfg & (1 << 18)) {
1350
                dev_printk(KERN_INFO, &pdev->dev,
1351
                           "applying IOCFG bit18 quirk\n");
1352
                iocfg &= ~(1 << 18);
1353
                pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1354
        }
1355
}
1356
 
1357
/**
1358
 *      piix_init_one - Register PIIX ATA PCI device with kernel services
1359
 *      @pdev: PCI device to register
1360
 *      @ent: Entry in piix_pci_tbl matching with @pdev
1361
 *
1362
 *      Called from kernel PCI layer.  We probe for combined mode (sigh),
1363
 *      and then hand over control to libata, for it to do the rest.
1364
 *
1365
 *      LOCKING:
1366
 *      Inherited from PCI layer (may sleep).
1367
 *
1368
 *      RETURNS:
1369
 *      Zero on success, or -ERRNO value.
1370
 */
1371
 
1372
static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1373
{
1374
        static int printed_version;
1375
        struct device *dev = &pdev->dev;
1376
        struct ata_port_info port_info[2];
1377
        const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1378
        struct piix_host_priv *hpriv;
1379
        unsigned long port_flags;
1380
 
1381
        if (!printed_version++)
1382
                dev_printk(KERN_DEBUG, &pdev->dev,
1383
                           "version " DRV_VERSION "\n");
1384
 
1385
        /* no hotplugging support (FIXME) */
1386
        if (!in_module_init)
1387
                return -ENODEV;
1388
 
1389
        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1390
        if (!hpriv)
1391
                return -ENOMEM;
1392
 
1393
        port_info[0] = piix_port_info[ent->driver_data];
1394
        port_info[1] = piix_port_info[ent->driver_data];
1395
        port_info[0].private_data = hpriv;
1396
        port_info[1].private_data = hpriv;
1397
 
1398
        port_flags = port_info[0].flags;
1399
 
1400
        if (port_flags & PIIX_FLAG_AHCI) {
1401
                u8 tmp;
1402
                pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1403
                if (tmp == PIIX_AHCI_DEVICE) {
1404
                        int rc = piix_disable_ahci(pdev);
1405
                        if (rc)
1406
                                return rc;
1407
                }
1408
        }
1409
 
1410
        /* Initialize SATA map */
1411
        if (port_flags & ATA_FLAG_SATA) {
1412
                piix_init_sata_map(pdev, port_info,
1413
                                   piix_map_db_table[ent->driver_data]);
1414
                piix_init_pcs(pdev, port_info,
1415
                              piix_map_db_table[ent->driver_data]);
1416
        }
1417
 
1418
        /* apply IOCFG bit18 quirk */
1419
        piix_iocfg_bit18_quirk(pdev);
1420
 
1421
        /* On ICH5, some BIOSen disable the interrupt using the
1422
         * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1423
         * On ICH6, this bit has the same effect, but only when
1424
         * MSI is disabled (and it is disabled, as we don't use
1425
         * message-signalled interrupts currently).
1426
         */
1427
        if (port_flags & PIIX_FLAG_CHECKINTR)
1428
                pci_intx(pdev, 1);
1429
 
1430
        if (piix_check_450nx_errata(pdev)) {
1431
                /* This writes into the master table but it does not
1432
                   really matter for this errata as we will apply it to
1433
                   all the PIIX devices on the board */
1434
                port_info[0].mwdma_mask = 0;
1435
                port_info[0].udma_mask = 0;
1436
                port_info[1].mwdma_mask = 0;
1437
                port_info[1].udma_mask = 0;
1438
        }
1439
        return ata_pci_init_one(pdev, ppi);
1440
}
1441
 
1442
static int __init piix_init(void)
1443
{
1444
        int rc;
1445
 
1446
        DPRINTK("pci_register_driver\n");
1447
        rc = pci_register_driver(&piix_pci_driver);
1448
        if (rc)
1449
                return rc;
1450
 
1451
        in_module_init = 0;
1452
 
1453
        DPRINTK("done\n");
1454
        return 0;
1455
}
1456
 
1457
static void __exit piix_exit(void)
1458
{
1459
        pci_unregister_driver(&piix_pci_driver);
1460
}
1461
 
1462
module_init(piix_init);
1463
module_exit(piix_exit);

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.