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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [ata/] [pata_icside.c] - Blame information for rev 62

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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <scsi/scsi_host.h>
#include <linux/ata.h>
#include <linux/libata.h>
 
#include <asm/dma.h>
#include <asm/ecard.h>
 
#define DRV_NAME        "pata_icside"
 
#define ICS_IDENT_OFFSET                0x2280
 
#define ICS_ARCIN_V5_INTRSTAT           0x0000
#define ICS_ARCIN_V5_INTROFFSET         0x0004
 
#define ICS_ARCIN_V6_INTROFFSET_1       0x2200
#define ICS_ARCIN_V6_INTRSTAT_1         0x2290
#define ICS_ARCIN_V6_INTROFFSET_2       0x3200
#define ICS_ARCIN_V6_INTRSTAT_2         0x3290
 
struct portinfo {
        unsigned int dataoffset;
        unsigned int ctrloffset;
        unsigned int stepping;
};
 
static const struct portinfo pata_icside_portinfo_v5 = {
        .dataoffset     = 0x2800,
        .ctrloffset     = 0x2b80,
        .stepping       = 6,
};
 
static const struct portinfo pata_icside_portinfo_v6_1 = {
        .dataoffset     = 0x2000,
        .ctrloffset     = 0x2380,
        .stepping       = 6,
};
 
static const struct portinfo pata_icside_portinfo_v6_2 = {
        .dataoffset     = 0x3000,
        .ctrloffset     = 0x3380,
        .stepping       = 6,
};
 
#define PATA_ICSIDE_MAX_SG      128
 
struct pata_icside_state {
        void __iomem *irq_port;
        void __iomem *ioc_base;
        unsigned int type;
        unsigned int dma;
        struct {
                u8 port_sel;
                u8 disabled;
                unsigned int speed[ATA_MAX_DEVICES];
        } port[2];
        struct scatterlist sg[PATA_ICSIDE_MAX_SG];
};
 
struct pata_icside_info {
        struct pata_icside_state *state;
        struct expansion_card   *ec;
        void __iomem            *base;
        void __iomem            *irqaddr;
        unsigned int            irqmask;
        const expansioncard_ops_t *irqops;
        unsigned int            mwdma_mask;
        unsigned int            nr_ports;
        const struct portinfo   *port[2];
        unsigned long           raw_base;
        unsigned long           raw_ioc_base;
};
 
#define ICS_TYPE_A3IN   0
#define ICS_TYPE_A3USER 1
#define ICS_TYPE_V6     3
#define ICS_TYPE_V5     15
#define ICS_TYPE_NOTYPE ((unsigned int)-1)
 
/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
        struct pata_icside_state *state = ec->irq_data;
 
        writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}
 
/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
        struct pata_icside_state *state = ec->irq_data;
 
        readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}
 
static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
        .irqenable      = pata_icside_irqenable_arcin_v5,
        .irqdisable     = pata_icside_irqdisable_arcin_v5,
};
 
 
/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
        struct pata_icside_state *state = ec->irq_data;
        void __iomem *base = state->irq_port;
 
        if (!state->port[0].disabled)
                writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
        if (!state->port[1].disabled)
                writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
}
 
/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
        struct pata_icside_state *state = ec->irq_data;
 
        readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
        readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}
 
/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
{
        struct pata_icside_state *state = ec->irq_data;
 
        return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
               readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}
 
static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
        .irqenable      = pata_icside_irqenable_arcin_v6,
        .irqdisable     = pata_icside_irqdisable_arcin_v6,
        .irqpending     = pata_icside_irqpending_arcin_v6,
};
 
 
/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */
 
/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *      Type    Active          Recovery        Cycle
 *      A       250 (250)       312 (550)       562 (800)
 *      B       187 (200)       250 (550)       437 (750)
 *      C       125 (125)       125 (375)       250 (500)
 *      D       62  (50)        125 (375)       187 (425)
 *
 * (figures in brackets are actual measured timings on DIOR/DIOW)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *                      Read    Write
 *      Mode    Active  -- Recovery --  Cycle   IOMD type
 *      MW0     215     50      215     480     A
 *      MW1     80      50      50      150     C
 *      MW2     70      25      25      120     C
 */
static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
        struct pata_icside_state *state = ap->host->private_data;
        struct ata_timing t;
        unsigned int cycle;
        char iomd_type;
 
        /*
         * DMA is based on a 16MHz clock
         */
        if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
                return;
 
        /*
         * Choose the IOMD cycle timing which ensure that the interface
         * satisfies the measured active, recovery and cycle times.
         */
        if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
                iomd_type = 'D', cycle = 187;
        else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
                iomd_type = 'C', cycle = 250;
        else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
                iomd_type = 'B', cycle = 437;
        else
                iomd_type = 'A', cycle = 562;
 
        ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
                t.active, t.recover, t.cycle, iomd_type);
 
        state->port[ap->port_no].speed[adev->devno] = cycle;
}
 
static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
{
        struct ata_port *ap = qc->ap;
        struct pata_icside_state *state = ap->host->private_data;
        struct scatterlist *sg, *rsg = state->sg;
        unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
 
        /*
         * We are simplex; BUG if we try to fiddle with DMA
         * while it's active.
         */
        BUG_ON(dma_channel_active(state->dma));
 
        /*
         * Copy ATAs scattered sg list into a contiguous array of sg
         */
        ata_for_each_sg(sg, qc) {
                memcpy(rsg, sg, sizeof(*sg));
                rsg++;
        }
 
        /*
         * Route the DMA signals to the correct interface
         */
        writeb(state->port[ap->port_no].port_sel, state->ioc_base);
 
        set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
        set_dma_sg(state->dma, state->sg, rsg - state->sg);
        set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
 
        /* issue r/w command */
        ap->ops->exec_command(ap, &qc->tf);
}
 
static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
{
        struct ata_port *ap = qc->ap;
        struct pata_icside_state *state = ap->host->private_data;
 
        BUG_ON(dma_channel_active(state->dma));
        enable_dma(state->dma);
}
 
static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
{
        struct ata_port *ap = qc->ap;
        struct pata_icside_state *state = ap->host->private_data;
 
        disable_dma(state->dma);
 
        /* see ata_bmdma_stop */
        ata_altstatus(ap);
}
 
static u8 pata_icside_bmdma_status(struct ata_port *ap)
{
        struct pata_icside_state *state = ap->host->private_data;
        void __iomem *irq_port;
 
        irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
                                                    ICS_ARCIN_V6_INTRSTAT_1);
 
        return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
}
 
static int icside_dma_init(struct pata_icside_info *info)
{
        struct pata_icside_state *state = info->state;
        struct expansion_card *ec = info->ec;
        int i;
 
        for (i = 0; i < ATA_MAX_DEVICES; i++) {
                state->port[0].speed[i] = 480;
                state->port[1].speed[i] = 480;
        }
 
        if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
                state->dma = ec->dma;
                info->mwdma_mask = 0x07;        /* MW0..2 */
        }
 
        return 0;
}
 
 
static int pata_icside_port_start(struct ata_port *ap)
{
        /* No PRD to alloc */
        return ata_pad_alloc(ap, ap->dev);
}
 
static struct scsi_host_template pata_icside_sht = {
        .module                 = THIS_MODULE,
        .name                   = DRV_NAME,
        .ioctl                  = ata_scsi_ioctl,
        .queuecommand           = ata_scsi_queuecmd,
        .can_queue              = ATA_DEF_QUEUE,
        .this_id                = ATA_SHT_THIS_ID,
        .sg_tablesize           = PATA_ICSIDE_MAX_SG,
        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
        .emulated               = ATA_SHT_EMULATED,
        .use_clustering         = ATA_SHT_USE_CLUSTERING,
        .proc_name              = DRV_NAME,
        .dma_boundary           = ~0, /* no dma boundaries */
        .slave_configure        = ata_scsi_slave_config,
        .slave_destroy          = ata_scsi_slave_destroy,
        .bios_param             = ata_std_bios_param,
};
 
/* wish this was exported from libata-core */
static void ata_dummy_noret(struct ata_port *port)
{
}
 
static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
{
        struct ata_port *ap = link->ap;
        struct pata_icside_state *state = ap->host->private_data;
 
        if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
                return ata_std_postreset(link, classes);
 
        state->port[ap->port_no].disabled = 1;
 
        if (state->type == ICS_TYPE_V6) {
                /*
                 * Disable interrupts from this port, otherwise we
                 * receive spurious interrupts from the floating
                 * interrupt line.
                 */
                void __iomem *irq_port = state->irq_port +
                                (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
                readb(irq_port);
        }
}
 
static void pata_icside_error_handler(struct ata_port *ap)
{
        ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
                           pata_icside_postreset);
}
 
static struct ata_port_operations pata_icside_port_ops = {
        .set_dmamode            = pata_icside_set_dmamode,
 
        .tf_load                = ata_tf_load,
        .tf_read                = ata_tf_read,
        .exec_command           = ata_exec_command,
        .check_status           = ata_check_status,
        .dev_select             = ata_std_dev_select,
 
        .cable_detect           = ata_cable_40wire,
 
        .bmdma_setup            = pata_icside_bmdma_setup,
        .bmdma_start            = pata_icside_bmdma_start,
 
        .data_xfer              = ata_data_xfer_noirq,
 
        /* no need to build any PRD tables for DMA */
        .qc_prep                = ata_noop_qc_prep,
        .qc_issue               = ata_qc_issue_prot,
 
        .freeze                 = ata_bmdma_freeze,
        .thaw                   = ata_bmdma_thaw,
        .error_handler          = pata_icside_error_handler,
        .post_internal_cmd      = pata_icside_bmdma_stop,
 
        .irq_clear              = ata_dummy_noret,
        .irq_on                 = ata_irq_on,
 
        .port_start             = pata_icside_port_start,
 
        .bmdma_stop             = pata_icside_bmdma_stop,
        .bmdma_status           = pata_icside_bmdma_status,
};
 
static void __devinit
pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
                         struct pata_icside_info *info,
                         const struct portinfo *port)
{
        struct ata_ioports *ioaddr = &ap->ioaddr;
        void __iomem *cmd = base + port->dataoffset;
 
        ioaddr->cmd_addr        = cmd;
        ioaddr->data_addr       = cmd + (ATA_REG_DATA    << port->stepping);
        ioaddr->error_addr      = cmd + (ATA_REG_ERR     << port->stepping);
        ioaddr->feature_addr    = cmd + (ATA_REG_FEATURE << port->stepping);
        ioaddr->nsect_addr      = cmd + (ATA_REG_NSECT   << port->stepping);
        ioaddr->lbal_addr       = cmd + (ATA_REG_LBAL    << port->stepping);
        ioaddr->lbam_addr       = cmd + (ATA_REG_LBAM    << port->stepping);
        ioaddr->lbah_addr       = cmd + (ATA_REG_LBAH    << port->stepping);
        ioaddr->device_addr     = cmd + (ATA_REG_DEVICE  << port->stepping);
        ioaddr->status_addr     = cmd + (ATA_REG_STATUS  << port->stepping);
        ioaddr->command_addr    = cmd + (ATA_REG_CMD     << port->stepping);
 
        ioaddr->ctl_addr        = base + port->ctrloffset;
        ioaddr->altstatus_addr  = ioaddr->ctl_addr;
 
        ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
                      info->raw_base + port->dataoffset,
                      info->raw_base + port->ctrloffset);
 
        if (info->raw_ioc_base)
                ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
}
 
static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
{
        struct pata_icside_state *state = info->state;
        void __iomem *base;
 
        base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
        if (!base)
                return -ENOMEM;
 
        state->irq_port = base;
 
        info->base = base;
        info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
        info->irqmask = 1;
        info->irqops = &pata_icside_ops_arcin_v5;
        info->nr_ports = 1;
        info->port[0] = &pata_icside_portinfo_v5;
 
        info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
 
        return 0;
}
 
static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
{
        struct pata_icside_state *state = info->state;
        struct expansion_card *ec = info->ec;
        void __iomem *ioc_base, *easi_base;
        unsigned int sel = 0;
 
        ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
        if (!ioc_base)
                return -ENOMEM;
 
        easi_base = ioc_base;
 
        if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
                easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
                if (!easi_base)
                        return -ENOMEM;
 
                /*
                 * Enable access to the EASI region.
                 */
                sel = 1 << 5;
        }
 
        writeb(sel, ioc_base);
 
        state->irq_port = easi_base;
        state->ioc_base = ioc_base;
        state->port[0].port_sel = sel;
        state->port[1].port_sel = sel | 1;
 
        info->base = easi_base;
        info->irqops = &pata_icside_ops_arcin_v6;
        info->nr_ports = 2;
        info->port[0] = &pata_icside_portinfo_v6_1;
        info->port[1] = &pata_icside_portinfo_v6_2;
 
        info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
        info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
 
        return icside_dma_init(info);
}
 
static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
{
        struct expansion_card *ec = info->ec;
        struct ata_host *host;
        int i;
 
        if (info->irqaddr) {
                ec->irqaddr = info->irqaddr;
                ec->irqmask = info->irqmask;
        }
        if (info->irqops)
                ecard_setirq(ec, info->irqops, info->state);
 
        /*
         * Be on the safe side - disable interrupts
         */
        ec->ops->irqdisable(ec, ec->irq);
 
        host = ata_host_alloc(&ec->dev, info->nr_ports);
        if (!host)
                return -ENOMEM;
 
        host->private_data = info->state;
        host->flags = ATA_HOST_SIMPLEX;
 
        for (i = 0; i < info->nr_ports; i++) {
                struct ata_port *ap = host->ports[i];
 
                ap->pio_mask = 0x1f;
                ap->mwdma_mask = info->mwdma_mask;
                ap->flags |= ATA_FLAG_SLAVE_POSS;
                ap->ops = &pata_icside_port_ops;
 
                pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
        }
 
        return ata_host_activate(host, ec->irq, ata_interrupt, 0,
                                 &pata_icside_sht);
}
 
static int __devinit
pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
        struct pata_icside_state *state;
        struct pata_icside_info info;
        void __iomem *idmem;
        int ret;
 
        ret = ecard_request_resources(ec);
        if (ret)
                goto out;
 
        state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
        if (!state) {
                ret = -ENOMEM;
                goto release;
        }
 
        state->type = ICS_TYPE_NOTYPE;
        state->dma = NO_DMA;
 
        idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
        if (idmem) {
                unsigned int type;
 
                type = readb(idmem + ICS_IDENT_OFFSET) & 1;
                type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
                type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
                type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
                ecardm_iounmap(ec, idmem);
 
                state->type = type;
        }
 
        memset(&info, 0, sizeof(info));
        info.state = state;
        info.ec = ec;
 
        switch (state->type) {
        case ICS_TYPE_A3IN:
                dev_warn(&ec->dev, "A3IN unsupported\n");
                ret = -ENODEV;
                break;
 
        case ICS_TYPE_A3USER:
                dev_warn(&ec->dev, "A3USER unsupported\n");
                ret = -ENODEV;
                break;
 
        case ICS_TYPE_V5:
                ret = pata_icside_register_v5(&info);
                break;
 
        case ICS_TYPE_V6:
                ret = pata_icside_register_v6(&info);
                break;
 
        default:
                dev_warn(&ec->dev, "unknown interface type\n");
                ret = -ENODEV;
                break;
        }
 
        if (ret == 0)
                ret = pata_icside_add_ports(&info);
 
        if (ret == 0)
                goto out;
 
 release:
        ecard_release_resources(ec);
 out:
        return ret;
}
 
static void pata_icside_shutdown(struct expansion_card *ec)
{
        struct ata_host *host = ecard_get_drvdata(ec);
        unsigned long flags;
 
        /*
         * Disable interrupts from this card.  We need to do
         * this before disabling EASI since we may be accessing
         * this register via that region.
         */
        local_irq_save(flags);
        ec->ops->irqdisable(ec, ec->irq);
        local_irq_restore(flags);
 
        /*
         * Reset the ROM pointer so that we can read the ROM
         * after a soft reboot.  This also disables access to
         * the IDE taskfile via the EASI region.
         */
        if (host) {
                struct pata_icside_state *state = host->private_data;
                if (state->ioc_base)
                        writeb(0, state->ioc_base);
        }
}
 
static void __devexit pata_icside_remove(struct expansion_card *ec)
{
        struct ata_host *host = ecard_get_drvdata(ec);
        struct pata_icside_state *state = host->private_data;
 
        ata_host_detach(host);
 
        pata_icside_shutdown(ec);
 
        /*
         * don't NULL out the drvdata - devres/libata wants it
         * to free the ata_host structure.
         */
        if (state->dma != NO_DMA)
                free_dma(state->dma);
 
        ecard_release_resources(ec);
}
 
static const struct ecard_id pata_icside_ids[] = {
        { MANU_ICS,  PROD_ICS_IDE  },
        { MANU_ICS2, PROD_ICS2_IDE },
        { 0xffff, 0xffff }
};
 
static struct ecard_driver pata_icside_driver = {
        .probe          = pata_icside_probe,
        .remove         = __devexit_p(pata_icside_remove),
        .shutdown       = pata_icside_shutdown,
        .id_table       = pata_icside_ids,
        .drv = {
                .name   = DRV_NAME,
        },
};
 
static int __init pata_icside_init(void)
{
        return ecard_register_driver(&pata_icside_driver);
}
 
static void __exit pata_icside_exit(void)
{
        ecard_remove_driver(&pata_icside_driver);
}
 
MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS PATA driver");
 
module_init(pata_icside_init);
module_exit(pata_icside_exit);

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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [ata/] [pata_icside.c] - Blame information for rev 62

Line No.	Rev	Author	Line
1	62	marcus.erl	`#include <linux/kernel.h>`
2			`#include <linux/module.h>`
3			`#include <linux/init.h>`
4			`#include <linux/blkdev.h>`
5			`#include <scsi/scsi_host.h>`
6			`#include <linux/ata.h>`
7			`#include <linux/libata.h>`
8
9			`#include <asm/dma.h>`
10			`#include <asm/ecard.h>`
11
12			`#define DRV_NAME "pata_icside"`
13
14			`#define ICS_IDENT_OFFSET 0x2280`
15
16			`#define ICS_ARCIN_V5_INTRSTAT 0x0000`
17			`#define ICS_ARCIN_V5_INTROFFSET 0x0004`
18
19			`#define ICS_ARCIN_V6_INTROFFSET_1 0x2200`
20			`#define ICS_ARCIN_V6_INTRSTAT_1 0x2290`
21			`#define ICS_ARCIN_V6_INTROFFSET_2 0x3200`
22			`#define ICS_ARCIN_V6_INTRSTAT_2 0x3290`
23
24			`struct portinfo {`
25			`unsigned int dataoffset;`
26			`unsigned int ctrloffset;`
27			`unsigned int stepping;`
28			`};`
29
30			`static const struct portinfo pata_icside_portinfo_v5 = {`
31			`.dataoffset = 0x2800,`
32			`.ctrloffset = 0x2b80,`
33			`.stepping = 6,`
34			`};`
35
36			`static const struct portinfo pata_icside_portinfo_v6_1 = {`
37			`.dataoffset = 0x2000,`
38			`.ctrloffset = 0x2380,`
39			`.stepping = 6,`
40			`};`
41
42			`static const struct portinfo pata_icside_portinfo_v6_2 = {`
43			`.dataoffset = 0x3000,`
44			`.ctrloffset = 0x3380,`
45			`.stepping = 6,`
46			`};`
47
48			`#define PATA_ICSIDE_MAX_SG 128`
49
50			`struct pata_icside_state {`
51			`void __iomem *irq_port;`
52			`void __iomem *ioc_base;`
53			`unsigned int type;`
54			`unsigned int dma;`
55			`struct {`
56			`u8 port_sel;`
57			`u8 disabled;`
58			`unsigned int speed[ATA_MAX_DEVICES];`
59			`} port[2];`
60			`struct scatterlist sg[PATA_ICSIDE_MAX_SG];`
61			`};`
62
63			`struct pata_icside_info {`
64			`struct pata_icside_state *state;`
65			`struct expansion_card *ec;`
66			`void __iomem *base;`
67			`void __iomem *irqaddr;`
68			`unsigned int irqmask;`
69			`const expansioncard_ops_t *irqops;`
70			`unsigned int mwdma_mask;`
71			`unsigned int nr_ports;`
72			`const struct portinfo *port[2];`
73			`unsigned long raw_base;`
74			`unsigned long raw_ioc_base;`
75			`};`
76
77			`#define ICS_TYPE_A3IN 0`
78			`#define ICS_TYPE_A3USER 1`
79			`#define ICS_TYPE_V6 3`
80			`#define ICS_TYPE_V5 15`
81			`#define ICS_TYPE_NOTYPE ((unsigned int)-1)`
82
83			`/* ---------------- Version 5 PCB Support Functions --------------------- */`
84			`/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)`
85			`* Purpose : enable interrupts from card`
86			`*/`
87			`static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)`
88			`{`
89			`struct pata_icside_state *state = ec->irq_data;`
90
91			`writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);`
92			`}`
93
94			`/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)`
95			`* Purpose : disable interrupts from card`
96			`*/`
97			`static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)`
98			`{`
99			`struct pata_icside_state *state = ec->irq_data;`
100
101			`readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);`
102			`}`
103
104			`static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {`
105			`.irqenable = pata_icside_irqenable_arcin_v5,`
106			`.irqdisable = pata_icside_irqdisable_arcin_v5,`
107			`};`
108
109
110			`/* ---------------- Version 6 PCB Support Functions --------------------- */`
111			`/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)`
112			`* Purpose : enable interrupts from card`
113			`*/`
114			`static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)`
115			`{`
116			`struct pata_icside_state *state = ec->irq_data;`
117			`void __iomem *base = state->irq_port;`
118
119			`if (!state->port[0].disabled)`
120			`writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);`
121			`if (!state->port[1].disabled)`
122			`writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);`
123			`}`
124
125			`/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)`
126			`* Purpose : disable interrupts from card`
127			`*/`
128			`static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)`
129			`{`
130			`struct pata_icside_state *state = ec->irq_data;`
131
132			`readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);`
133			`readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);`
134			`}`
135
136			`/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)`
137			`* Purpose : detect an active interrupt from card`
138			`*/`
139			`static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)`
140			`{`
141			`struct pata_icside_state *state = ec->irq_data;`
142
143			`return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|`
144			`readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;`
145			`}`
146
147			`static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {`
148			`.irqenable = pata_icside_irqenable_arcin_v6,`
149			`.irqdisable = pata_icside_irqdisable_arcin_v6,`
150			`.irqpending = pata_icside_irqpending_arcin_v6,`
151			`};`
152
153
154			`/*`
155			`* SG-DMA support.`
156			`*`
157			`* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.`
158			`* There is only one DMA controller per card, which means that only`
159			`* one drive can be accessed at one time. NOTE! We do not enforce that`
160			`* here, but we rely on the main IDE driver spotting that both`
161			`* interfaces use the same IRQ, which should guarantee this.`
162			`*/`
163
164			`/*`
165			`* Configure the IOMD to give the appropriate timings for the transfer`
166			`* mode being requested. We take the advice of the ATA standards, and`
167			`* calculate the cycle time based on the transfer mode, and the EIDE`
168			`* MW DMA specs that the drive provides in the IDENTIFY command.`
169			`*`
170			`* We have the following IOMD DMA modes to choose from:`
171			`*`
172			`* Type Active Recovery Cycle`
173			`* A 250 (250) 312 (550) 562 (800)`
174			`* B 187 (200) 250 (550) 437 (750)`
175			`* C 125 (125) 125 (375) 250 (500)`
176			`* D 62 (50) 125 (375) 187 (425)`
177			`*`
178			`* (figures in brackets are actual measured timings on DIOR/DIOW)`
179			`*`
180			`* However, we also need to take care of the read/write active and`
181			`* recovery timings:`
182			`*`
183			`* Read Write`
184			`* Mode Active -- Recovery -- Cycle IOMD type`
185			`* MW0 215 50 215 480 A`
186			`* MW1 80 50 50 150 C`
187			`* MW2 70 25 25 120 C`
188			`*/`
189			`static void pata_icside_set_dmamode(struct ata_port ap, struct ata_device adev)`
190			`{`
191			`struct pata_icside_state *state = ap->host->private_data;`
192			`struct ata_timing t;`
193			`unsigned int cycle;`
194			`char iomd_type;`
195
196			`/*`
197			`* DMA is based on a 16MHz clock`
198			`*/`
199			`if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))`
200			`return;`
201
202			`/*`
203			`* Choose the IOMD cycle timing which ensure that the interface`
204			`* satisfies the measured active, recovery and cycle times.`
205			`*/`
206			`if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)`
207			`iomd_type = 'D', cycle = 187;`
208			`else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)`
209			`iomd_type = 'C', cycle = 250;`
210			`else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)`
211			`iomd_type = 'B', cycle = 437;`
212			`else`
213			`iomd_type = 'A', cycle = 562;`
214
215			`ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",`
216			`t.active, t.recover, t.cycle, iomd_type);`
217
218			`state->port[ap->port_no].speed[adev->devno] = cycle;`
219			`}`
220
221			`static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)`
222			`{`
223			`struct ata_port *ap = qc->ap;`
224			`struct pata_icside_state *state = ap->host->private_data;`
225			`struct scatterlist sg, rsg = state->sg;`
226			`unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;`
227
228			`/*`
229			`* We are simplex; BUG if we try to fiddle with DMA`
230			`* while it's active.`
231			`*/`
232			`BUG_ON(dma_channel_active(state->dma));`
233
234			`/*`
235			`* Copy ATAs scattered sg list into a contiguous array of sg`
236			`*/`
237			`ata_for_each_sg(sg, qc) {`
238			`memcpy(rsg, sg, sizeof(*sg));`
239			`rsg++;`
240			`}`
241
242			`/*`
243			`* Route the DMA signals to the correct interface`
244			`*/`
245			`writeb(state->port[ap->port_no].port_sel, state->ioc_base);`
246
247			`set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);`
248			`set_dma_sg(state->dma, state->sg, rsg - state->sg);`
249			`set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);`
250
251			`/* issue r/w command */`
252			`ap->ops->exec_command(ap, &qc->tf);`
253			`}`
254
255			`static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)`
256			`{`
257			`struct ata_port *ap = qc->ap;`
258			`struct pata_icside_state *state = ap->host->private_data;`
259
260			`BUG_ON(dma_channel_active(state->dma));`
261			`enable_dma(state->dma);`
262			`}`
263
264			`static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)`
265			`{`
266			`struct ata_port *ap = qc->ap;`
267			`struct pata_icside_state *state = ap->host->private_data;`
268
269			`disable_dma(state->dma);`
270
271			`/* see ata_bmdma_stop */`
272			`ata_altstatus(ap);`
273			`}`
274
275			`static u8 pata_icside_bmdma_status(struct ata_port *ap)`
276			`{`
277			`struct pata_icside_state *state = ap->host->private_data;`
278			`void __iomem *irq_port;`
279
280			`irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :`
281			`ICS_ARCIN_V6_INTRSTAT_1);`
282
283			`return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;`
284			`}`
285
286			`static int icside_dma_init(struct pata_icside_info *info)`
287			`{`
288			`struct pata_icside_state *state = info->state;`
289			`struct expansion_card *ec = info->ec;`
290			`int i;`
291
292			`for (i = 0; i < ATA_MAX_DEVICES; i++) {`
293			`state->port[0].speed[i] = 480;`
294			`state->port[1].speed[i] = 480;`
295			`}`
296
297			`if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {`
298			`state->dma = ec->dma;`
299			`info->mwdma_mask = 0x07; /* MW0..2 */`
300			`}`
301
302			`return 0;`
303			`}`
304
305
306			`static int pata_icside_port_start(struct ata_port *ap)`
307			`{`
308			`/* No PRD to alloc */`
309			`return ata_pad_alloc(ap, ap->dev);`
310			`}`
311
312			`static struct scsi_host_template pata_icside_sht = {`
313			`.module = THIS_MODULE,`
314			`.name = DRV_NAME,`
315			`.ioctl = ata_scsi_ioctl,`
316			`.queuecommand = ata_scsi_queuecmd,`
317			`.can_queue = ATA_DEF_QUEUE,`
318			`.this_id = ATA_SHT_THIS_ID,`
319			`.sg_tablesize = PATA_ICSIDE_MAX_SG,`
320			`.cmd_per_lun = ATA_SHT_CMD_PER_LUN,`
321			`.emulated = ATA_SHT_EMULATED,`
322			`.use_clustering = ATA_SHT_USE_CLUSTERING,`
323			`.proc_name = DRV_NAME,`
324			`.dma_boundary = ~0, /* no dma boundaries */`
325			`.slave_configure = ata_scsi_slave_config,`
326			`.slave_destroy = ata_scsi_slave_destroy,`
327			`.bios_param = ata_std_bios_param,`
328			`};`
329
330			`/* wish this was exported from libata-core */`
331			`static void ata_dummy_noret(struct ata_port *port)`
332			`{`
333			`}`
334
335			`static void pata_icside_postreset(struct ata_link link, unsigned int classes)`
336			`{`
337			`struct ata_port *ap = link->ap;`
338			`struct pata_icside_state *state = ap->host->private_data;`
339
340			`if (classes[0] != ATA_DEV_NONE \|\| classes[1] != ATA_DEV_NONE)`
341			`return ata_std_postreset(link, classes);`
342
343			`state->port[ap->port_no].disabled = 1;`
344
345			`if (state->type == ICS_TYPE_V6) {`
346			`/*`
347			`* Disable interrupts from this port, otherwise we`
348			`* receive spurious interrupts from the floating`
349			`* interrupt line.`
350			`*/`
351			`void __iomem *irq_port = state->irq_port +`
352			`(ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);`
353			`readb(irq_port);`
354			`}`
355			`}`
356
357			`static void pata_icside_error_handler(struct ata_port *ap)`
358			`{`
359			`ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,`
360			`pata_icside_postreset);`
361			`}`
362
363			`static struct ata_port_operations pata_icside_port_ops = {`
364			`.set_dmamode = pata_icside_set_dmamode,`
365
366			`.tf_load = ata_tf_load,`
367			`.tf_read = ata_tf_read,`
368			`.exec_command = ata_exec_command,`
369			`.check_status = ata_check_status,`
370			`.dev_select = ata_std_dev_select,`
371
372			`.cable_detect = ata_cable_40wire,`
373
374			`.bmdma_setup = pata_icside_bmdma_setup,`
375			`.bmdma_start = pata_icside_bmdma_start,`
376
377			`.data_xfer = ata_data_xfer_noirq,`
378
379			`/* no need to build any PRD tables for DMA */`
380			`.qc_prep = ata_noop_qc_prep,`
381			`.qc_issue = ata_qc_issue_prot,`
382
383			`.freeze = ata_bmdma_freeze,`
384			`.thaw = ata_bmdma_thaw,`
385			`.error_handler = pata_icside_error_handler,`
386			`.post_internal_cmd = pata_icside_bmdma_stop,`
387
388			`.irq_clear = ata_dummy_noret,`
389			`.irq_on = ata_irq_on,`
390
391			`.port_start = pata_icside_port_start,`
392
393			`.bmdma_stop = pata_icside_bmdma_stop,`
394			`.bmdma_status = pata_icside_bmdma_status,`
395			`};`
396
397			`static void __devinit`
398			`pata_icside_setup_ioaddr(struct ata_port ap, void __iomem base,`
399			`struct pata_icside_info *info,`
400			`const struct portinfo *port)`
401			`{`
402			`struct ata_ioports *ioaddr = &ap->ioaddr;`
403			`void __iomem *cmd = base + port->dataoffset;`
404
405			`ioaddr->cmd_addr = cmd;`
406			`ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);`
407			`ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);`
408			`ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);`
409			`ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);`
410			`ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);`
411			`ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);`
412			`ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);`
413			`ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);`
414			`ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);`
415			`ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);`
416
417			`ioaddr->ctl_addr = base + port->ctrloffset;`
418			`ioaddr->altstatus_addr = ioaddr->ctl_addr;`
419
420			`ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",`
421			`info->raw_base + port->dataoffset,`
422			`info->raw_base + port->ctrloffset);`
423
424			`if (info->raw_ioc_base)`
425			`ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);`
426			`}`
427
428			`static int __devinit pata_icside_register_v5(struct pata_icside_info *info)`
429			`{`
430			`struct pata_icside_state *state = info->state;`
431			`void __iomem *base;`
432
433			`base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);`
434			`if (!base)`
435			`return -ENOMEM;`
436
437			`state->irq_port = base;`
438
439			`info->base = base;`
440			`info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;`
441			`info->irqmask = 1;`
442			`info->irqops = &pata_icside_ops_arcin_v5;`
443			`info->nr_ports = 1;`
444			`info->port[0] = &pata_icside_portinfo_v5;`
445
446			`info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);`
447
448			`return 0;`
449			`}`
450
451			`static int __devinit pata_icside_register_v6(struct pata_icside_info *info)`
452			`{`
453			`struct pata_icside_state *state = info->state;`
454			`struct expansion_card *ec = info->ec;`
455			`void __iomem ioc_base, easi_base;`
456			`unsigned int sel = 0;`
457
458			`ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);`
459			`if (!ioc_base)`
460			`return -ENOMEM;`
461
462			`easi_base = ioc_base;`
463
464			`if (ecard_resource_flags(ec, ECARD_RES_EASI)) {`
465			`easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);`
466			`if (!easi_base)`
467			`return -ENOMEM;`
468
469			`/*`
470			`* Enable access to the EASI region.`
471			`*/`
472			`sel = 1 << 5;`
473			`}`
474
475			`writeb(sel, ioc_base);`
476
477			`state->irq_port = easi_base;`
478			`state->ioc_base = ioc_base;`
479			`state->port[0].port_sel = sel;`
480			`state->port[1].port_sel = sel \| 1;`
481
482			`info->base = easi_base;`
483			`info->irqops = &pata_icside_ops_arcin_v6;`
484			`info->nr_ports = 2;`
485			`info->port[0] = &pata_icside_portinfo_v6_1;`
486			`info->port[1] = &pata_icside_portinfo_v6_2;`
487
488			`info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);`
489			`info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);`
490
491			`return icside_dma_init(info);`
492			`}`
493
494			`static int __devinit pata_icside_add_ports(struct pata_icside_info *info)`
495			`{`
496			`struct expansion_card *ec = info->ec;`
497			`struct ata_host *host;`
498			`int i;`
499
500			`if (info->irqaddr) {`
501			`ec->irqaddr = info->irqaddr;`
502			`ec->irqmask = info->irqmask;`
503			`}`
504			`if (info->irqops)`
505			`ecard_setirq(ec, info->irqops, info->state);`
506
507			`/*`
508			`* Be on the safe side - disable interrupts`
509			`*/`
510			`ec->ops->irqdisable(ec, ec->irq);`
511
512			`host = ata_host_alloc(&ec->dev, info->nr_ports);`
513			`if (!host)`
514			`return -ENOMEM;`
515
516			`host->private_data = info->state;`
517			`host->flags = ATA_HOST_SIMPLEX;`
518
519			`for (i = 0; i < info->nr_ports; i++) {`
520			`struct ata_port *ap = host->ports[i];`
521
522			`ap->pio_mask = 0x1f;`
523			`ap->mwdma_mask = info->mwdma_mask;`
524			`ap->flags \|= ATA_FLAG_SLAVE_POSS;`
525			`ap->ops = &pata_icside_port_ops;`
526
527			`pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);`
528			`}`
529
530			`return ata_host_activate(host, ec->irq, ata_interrupt, 0,`
531			`&pata_icside_sht);`
532			`}`
533
534			`static int __devinit`
535			`pata_icside_probe(struct expansion_card ec, const struct ecard_id id)`
536			`{`
537			`struct pata_icside_state *state;`
538			`struct pata_icside_info info;`
539			`void __iomem *idmem;`
540			`int ret;`
541
542			`ret = ecard_request_resources(ec);`
543			`if (ret)`
544			`goto out;`
545
546			`state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);`
547			`if (!state) {`
548			`ret = -ENOMEM;`
549			`goto release;`
550			`}`
551
552			`state->type = ICS_TYPE_NOTYPE;`
553			`state->dma = NO_DMA;`
554
555			`idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);`
556			`if (idmem) {`
557			`unsigned int type;`
558
559			`type = readb(idmem + ICS_IDENT_OFFSET) & 1;`
560			`type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;`
561			`type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;`
562			`type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;`
563			`ecardm_iounmap(ec, idmem);`
564
565			`state->type = type;`
566			`}`
567
568			`memset(&info, 0, sizeof(info));`
569			`info.state = state;`
570			`info.ec = ec;`
571
572			`switch (state->type) {`
573			`case ICS_TYPE_A3IN:`
574			`dev_warn(&ec->dev, "A3IN unsupported\n");`
575			`ret = -ENODEV;`
576			`break;`
577
578			`case ICS_TYPE_A3USER:`
579			`dev_warn(&ec->dev, "A3USER unsupported\n");`
580			`ret = -ENODEV;`
581			`break;`
582
583			`case ICS_TYPE_V5:`
584			`ret = pata_icside_register_v5(&info);`
585			`break;`
586
587			`case ICS_TYPE_V6:`
588			`ret = pata_icside_register_v6(&info);`
589			`break;`
590
591			`default:`
592			`dev_warn(&ec->dev, "unknown interface type\n");`
593			`ret = -ENODEV;`
594			`break;`
595			`}`
596
597			`if (ret == 0)`
598			`ret = pata_icside_add_ports(&info);`
599
600			`if (ret == 0)`
601			`goto out;`
602
603			`release:`
604			`ecard_release_resources(ec);`
605			`out:`
606			`return ret;`
607			`}`
608
609			`static void pata_icside_shutdown(struct expansion_card *ec)`
610			`{`
611			`struct ata_host *host = ecard_get_drvdata(ec);`
612			`unsigned long flags;`
613
614			`/*`
615			`* Disable interrupts from this card. We need to do`
616			`* this before disabling EASI since we may be accessing`
617			`* this register via that region.`
618			`*/`
619			`local_irq_save(flags);`
620			`ec->ops->irqdisable(ec, ec->irq);`
621			`local_irq_restore(flags);`
622
623			`/*`
624			`* Reset the ROM pointer so that we can read the ROM`
625			`* after a soft reboot. This also disables access to`
626			`* the IDE taskfile via the EASI region.`
627			`*/`
628			`if (host) {`
629			`struct pata_icside_state *state = host->private_data;`
630			`if (state->ioc_base)`
631			`writeb(0, state->ioc_base);`
632			`}`
633			`}`
634
635			`static void __devexit pata_icside_remove(struct expansion_card *ec)`
636			`{`
637			`struct ata_host *host = ecard_get_drvdata(ec);`
638			`struct pata_icside_state *state = host->private_data;`
639
640			`ata_host_detach(host);`
641
642			`pata_icside_shutdown(ec);`
643
644			`/*`
645			`* don't NULL out the drvdata - devres/libata wants it`
646			`* to free the ata_host structure.`
647			`*/`
648			`if (state->dma != NO_DMA)`
649			`free_dma(state->dma);`
650
651			`ecard_release_resources(ec);`
652			`}`
653
654			`static const struct ecard_id pata_icside_ids[] = {`
655			`{ MANU_ICS, PROD_ICS_IDE },`
656			`{ MANU_ICS2, PROD_ICS2_IDE },`
657			`{ 0xffff, 0xffff }`
658			`};`
659
660			`static struct ecard_driver pata_icside_driver = {`
661			`.probe = pata_icside_probe,`
662			`.remove = __devexit_p(pata_icside_remove),`
663			`.shutdown = pata_icside_shutdown,`
664			`.id_table = pata_icside_ids,`
665			`.drv = {`
666			`.name = DRV_NAME,`
667			`},`
668			`};`
669
670			`static int __init pata_icside_init(void)`
671			`{`
672			`return ecard_register_driver(&pata_icside_driver);`
673			`}`
674
675			`static void __exit pata_icside_exit(void)`
676			`{`
677			`ecard_remove_driver(&pata_icside_driver);`
678			`}`
679
680			`MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");`
681			`MODULE_LICENSE("GPL");`
682			`MODULE_DESCRIPTION("ICS PATA driver");`
683
684			`module_init(pata_icside_init);`
685			`module_exit(pata_icside_exit);`