1 |
62 |
marcus.erl |
/*
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2 |
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* pata_sis.c - SiS ATA driver
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3 |
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*
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4 |
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* (C) 2005 Red Hat <alan@redhat.com>
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* (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* Based upon linux/drivers/ide/pci/sis5513.c
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
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* Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
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* SiS Taiwan : for direct support and hardware.
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12 |
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* Daniela Engert : for initial ATA100 advices and numerous others.
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* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
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* for checking code correctness, providing patches.
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* Original tests and design on the SiS620 chipset.
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* ATA100 tests and design on the SiS735 chipset.
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* ATA16/33 support from specs
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* ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
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*
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*
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* TODO
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* Check MWDMA on drives that don't support MWDMA speed pio cycles ?
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* More Testing
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*/
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#include <linux/kernel.h>
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27 |
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#include <linux/module.h>
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#include <linux/pci.h>
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29 |
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#include <linux/init.h>
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30 |
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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32 |
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#include "sis.h"
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#define DRV_NAME "pata_sis"
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#define DRV_VERSION "0.5.2"
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struct sis_chipset {
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u16 device; /* PCI host ID */
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const struct ata_port_info *info; /* Info block */
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/* Probably add family, cable detect type etc here to clean
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up code later */
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};
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struct sis_laptop {
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u16 device;
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u16 subvendor;
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u16 subdevice;
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};
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static const struct sis_laptop sis_laptop[] = {
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/* devid, subvendor, subdev */
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{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
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{ 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
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{ 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
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/* end marker */
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{ 0, }
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};
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static int sis_short_ata40(struct pci_dev *dev)
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{
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const struct sis_laptop *lap = &sis_laptop[0];
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67 |
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while (lap->device) {
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if (lap->device == dev->device &&
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lap->subvendor == dev->subsystem_vendor &&
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lap->subdevice == dev->subsystem_device)
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return 1;
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lap++;
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}
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return 0;
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}
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/**
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* sis_old_port_base - return PCI configuration base for dev
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80 |
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* @adev: device
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*
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* Returns the base of the PCI configuration registers for this port
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* number.
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*/
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static int sis_old_port_base(struct ata_device *adev)
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{
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return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
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}
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/**
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* sis_133_cable_detect - check for 40/80 pin
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* @ap: Port
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* @deadline: deadline jiffies for the operation
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*
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* Perform cable detection for the later UDMA133 capable
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* SiS chipset.
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*/
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static int sis_133_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 tmp;
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/* The top bit of this register is the cable detect bit */
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pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
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if ((tmp & 0x8000) && !sis_short_ata40(pdev))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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/**
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* sis_66_cable_detect - check for 40/80 pin
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* @ap: Port
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* @deadline: deadline jiffies for the operation
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*
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* Perform cable detection on the UDMA66, UDMA100 and early UDMA133
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* SiS IDE controllers.
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*/
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static int sis_66_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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/* Older chips keep cable detect in bits 4/5 of reg 0x48 */
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pci_read_config_byte(pdev, 0x48, &tmp);
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tmp >>= ap->port_no;
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if ((tmp & 0x10) && !sis_short_ata40(pdev))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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/**
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* sis_pre_reset - probe begin
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Set up cable type and use generic probe init
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*/
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static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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static const struct pci_bits sis_enable_bits[] = {
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{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
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{ 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
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};
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
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return -ENOENT;
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/* Clear the FIFO settings. We can't enable the FIFO until
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we know we are poking at a disk */
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pci_write_config_byte(pdev, 0x4B, 0);
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return ata_std_prereset(link, deadline);
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}
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/**
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* sis_error_handler - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void sis_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* sis_set_fifo - Set RWP fifo bits for this device
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* @ap: Port
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* @adev: Device
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*
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* SIS chipsets implement prefetch/postwrite bits for each device
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* on both channels. This functionality is not ATAPI compatible and
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* must be configured according to the class of device present
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*/
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static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 fifoctrl;
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u8 mask = 0x11;
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mask <<= (2 * ap->port_no);
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mask <<= adev->devno;
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/* This holds various bits including the FIFO control */
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pci_read_config_byte(pdev, 0x4B, &fifoctrl);
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fifoctrl &= ~mask;
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/* Enable for ATA (disk) only */
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if (adev->class == ATA_DEV_ATA)
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fifoctrl |= mask;
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pci_write_config_byte(pdev, 0x4B, fifoctrl);
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}
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/**
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* sis_old_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring for.
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*
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* Set PIO mode for device, in host controller PCI config space. This
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* function handles PIO set up for all chips that are pre ATA100 and
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* also early ATA100 devices.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = sis_old_port_base(adev);
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u8 t1, t2;
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int speed = adev->pio_mode - XFER_PIO_0;
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const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
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const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
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sis_set_fifo(ap, adev);
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pci_read_config_byte(pdev, port, &t1);
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pci_read_config_byte(pdev, port + 1, &t2);
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t1 &= ~0x0F; /* Clear active/recovery timings */
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t2 &= ~0x07;
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t1 |= active[speed];
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t2 |= recovery[speed];
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pci_write_config_byte(pdev, port, t1);
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pci_write_config_byte(pdev, port + 1, t2);
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}
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/**
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* sis_100_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring for.
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*
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248 |
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* Set PIO mode for device, in host controller PCI config space. This
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* function handles PIO set up for ATA100 devices and early ATA133.
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*
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251 |
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* LOCKING:
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* None (inherited from caller).
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*/
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255 |
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static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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257 |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = sis_old_port_base(adev);
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int speed = adev->pio_mode - XFER_PIO_0;
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261 |
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const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
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sis_set_fifo(ap, adev);
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264 |
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265 |
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pci_write_config_byte(pdev, port, actrec[speed]);
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266 |
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}
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267 |
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268 |
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/**
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269 |
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* sis_133_set_piomode - Initialize host controller PATA PIO timings
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270 |
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* @ap: Port whose timings we are configuring
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271 |
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* @adev: Device we are configuring for.
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272 |
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*
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273 |
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* Set PIO mode for device, in host controller PCI config space. This
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274 |
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* function handles PIO set up for the later ATA133 devices.
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275 |
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*
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276 |
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* LOCKING:
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277 |
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* None (inherited from caller).
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278 |
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*/
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279 |
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280 |
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static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
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281 |
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{
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282 |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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283 |
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int port = 0x40;
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284 |
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u32 t1;
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285 |
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u32 reg54;
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286 |
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int speed = adev->pio_mode - XFER_PIO_0;
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287 |
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288 |
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const u32 timing133[] = {
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289 |
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0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
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290 |
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0x0C266000,
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291 |
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0x04263000,
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292 |
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0x0C0A3000,
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293 |
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0x05093000
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294 |
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};
|
295 |
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const u32 timing100[] = {
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296 |
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0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
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297 |
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0x091C4000,
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298 |
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0x031C2000,
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299 |
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0x09072000,
|
300 |
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0x04062000
|
301 |
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};
|
302 |
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|
303 |
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sis_set_fifo(ap, adev);
|
304 |
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|
305 |
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/* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
|
306 |
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pci_read_config_dword(pdev, 0x54, ®54);
|
307 |
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if (reg54 & 0x40000000)
|
308 |
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port = 0x70;
|
309 |
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port += 8 * ap->port_no + 4 * adev->devno;
|
310 |
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|
311 |
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pci_read_config_dword(pdev, port, &t1);
|
312 |
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t1 &= 0xC0C00FFF; /* Mask out timing */
|
313 |
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|
314 |
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if (t1 & 0x08) /* 100 or 133 ? */
|
315 |
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t1 |= timing133[speed];
|
316 |
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else
|
317 |
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t1 |= timing100[speed];
|
318 |
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pci_write_config_byte(pdev, port, t1);
|
319 |
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}
|
320 |
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|
321 |
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|
/**
|
322 |
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|
* sis_old_set_dmamode - Initialize host controller PATA DMA timings
|
323 |
|
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* @ap: Port whose timings we are configuring
|
324 |
|
|
* @adev: Device to program
|
325 |
|
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*
|
326 |
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
327 |
|
|
* Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
|
328 |
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* the old ide/pci driver.
|
329 |
|
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*
|
330 |
|
|
* LOCKING:
|
331 |
|
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* None (inherited from caller).
|
332 |
|
|
*/
|
333 |
|
|
|
334 |
|
|
static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
335 |
|
|
{
|
336 |
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
337 |
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
338 |
|
|
int drive_pci = sis_old_port_base(adev);
|
339 |
|
|
u16 timing;
|
340 |
|
|
|
341 |
|
|
const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
|
342 |
|
|
const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
|
343 |
|
|
|
344 |
|
|
pci_read_config_word(pdev, drive_pci, &timing);
|
345 |
|
|
|
346 |
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
347 |
|
|
/* bits 3-0 hold recovery timing bits 8-10 active timing and
|
348 |
|
|
the higer bits are dependant on the device */
|
349 |
|
|
timing &= ~0x870F;
|
350 |
|
|
timing |= mwdma_bits[speed];
|
351 |
|
|
} else {
|
352 |
|
|
/* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
|
353 |
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
354 |
|
|
timing &= ~0x6000;
|
355 |
|
|
timing |= udma_bits[speed];
|
356 |
|
|
}
|
357 |
|
|
pci_write_config_word(pdev, drive_pci, timing);
|
358 |
|
|
}
|
359 |
|
|
|
360 |
|
|
/**
|
361 |
|
|
* sis_66_set_dmamode - Initialize host controller PATA DMA timings
|
362 |
|
|
* @ap: Port whose timings we are configuring
|
363 |
|
|
* @adev: Device to program
|
364 |
|
|
*
|
365 |
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
366 |
|
|
* Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
|
367 |
|
|
* the old ide/pci driver.
|
368 |
|
|
*
|
369 |
|
|
* LOCKING:
|
370 |
|
|
* None (inherited from caller).
|
371 |
|
|
*/
|
372 |
|
|
|
373 |
|
|
static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
374 |
|
|
{
|
375 |
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
376 |
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
377 |
|
|
int drive_pci = sis_old_port_base(adev);
|
378 |
|
|
u16 timing;
|
379 |
|
|
|
380 |
|
|
/* MWDMA 0-2 and UDMA 0-5 */
|
381 |
|
|
const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
|
382 |
|
|
const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
|
383 |
|
|
|
384 |
|
|
pci_read_config_word(pdev, drive_pci, &timing);
|
385 |
|
|
|
386 |
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
387 |
|
|
/* bits 3-0 hold recovery timing bits 8-10 active timing and
|
388 |
|
|
the higer bits are dependant on the device, bit 15 udma */
|
389 |
|
|
timing &= ~0x870F;
|
390 |
|
|
timing |= mwdma_bits[speed];
|
391 |
|
|
} else {
|
392 |
|
|
/* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
|
393 |
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
394 |
|
|
timing &= ~0xF000;
|
395 |
|
|
timing |= udma_bits[speed];
|
396 |
|
|
}
|
397 |
|
|
pci_write_config_word(pdev, drive_pci, timing);
|
398 |
|
|
}
|
399 |
|
|
|
400 |
|
|
/**
|
401 |
|
|
* sis_100_set_dmamode - Initialize host controller PATA DMA timings
|
402 |
|
|
* @ap: Port whose timings we are configuring
|
403 |
|
|
* @adev: Device to program
|
404 |
|
|
*
|
405 |
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
406 |
|
|
* Handles UDMA66 and early UDMA100 devices.
|
407 |
|
|
*
|
408 |
|
|
* LOCKING:
|
409 |
|
|
* None (inherited from caller).
|
410 |
|
|
*/
|
411 |
|
|
|
412 |
|
|
static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
413 |
|
|
{
|
414 |
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
415 |
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
416 |
|
|
int drive_pci = sis_old_port_base(adev);
|
417 |
|
|
u8 timing;
|
418 |
|
|
|
419 |
|
|
const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
|
420 |
|
|
|
421 |
|
|
pci_read_config_byte(pdev, drive_pci + 1, &timing);
|
422 |
|
|
|
423 |
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
424 |
|
|
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
|
425 |
|
|
} else {
|
426 |
|
|
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
|
427 |
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
428 |
|
|
timing &= ~0x8F;
|
429 |
|
|
timing |= udma_bits[speed];
|
430 |
|
|
}
|
431 |
|
|
pci_write_config_byte(pdev, drive_pci + 1, timing);
|
432 |
|
|
}
|
433 |
|
|
|
434 |
|
|
/**
|
435 |
|
|
* sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
|
436 |
|
|
* @ap: Port whose timings we are configuring
|
437 |
|
|
* @adev: Device to program
|
438 |
|
|
*
|
439 |
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
440 |
|
|
* Handles early SiS 961 bridges.
|
441 |
|
|
*
|
442 |
|
|
* LOCKING:
|
443 |
|
|
* None (inherited from caller).
|
444 |
|
|
*/
|
445 |
|
|
|
446 |
|
|
static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
447 |
|
|
{
|
448 |
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
449 |
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
450 |
|
|
int drive_pci = sis_old_port_base(adev);
|
451 |
|
|
u8 timing;
|
452 |
|
|
/* Low 4 bits are timing */
|
453 |
|
|
static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
|
454 |
|
|
|
455 |
|
|
pci_read_config_byte(pdev, drive_pci + 1, &timing);
|
456 |
|
|
|
457 |
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
458 |
|
|
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
|
459 |
|
|
} else {
|
460 |
|
|
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
|
461 |
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
462 |
|
|
timing &= ~0x8F;
|
463 |
|
|
timing |= udma_bits[speed];
|
464 |
|
|
}
|
465 |
|
|
pci_write_config_byte(pdev, drive_pci + 1, timing);
|
466 |
|
|
}
|
467 |
|
|
|
468 |
|
|
/**
|
469 |
|
|
* sis_133_set_dmamode - Initialize host controller PATA DMA timings
|
470 |
|
|
* @ap: Port whose timings we are configuring
|
471 |
|
|
* @adev: Device to program
|
472 |
|
|
*
|
473 |
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
474 |
|
|
*
|
475 |
|
|
* LOCKING:
|
476 |
|
|
* None (inherited from caller).
|
477 |
|
|
*/
|
478 |
|
|
|
479 |
|
|
static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
480 |
|
|
{
|
481 |
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
482 |
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
483 |
|
|
int port = 0x40;
|
484 |
|
|
u32 t1;
|
485 |
|
|
u32 reg54;
|
486 |
|
|
|
487 |
|
|
/* bits 4- cycle time 8 - cvs time */
|
488 |
|
|
static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
|
489 |
|
|
static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
|
490 |
|
|
|
491 |
|
|
/* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
|
492 |
|
|
pci_read_config_dword(pdev, 0x54, ®54);
|
493 |
|
|
if (reg54 & 0x40000000)
|
494 |
|
|
port = 0x70;
|
495 |
|
|
port += (8 * ap->port_no) + (4 * adev->devno);
|
496 |
|
|
|
497 |
|
|
pci_read_config_dword(pdev, port, &t1);
|
498 |
|
|
|
499 |
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
500 |
|
|
t1 &= ~0x00000004;
|
501 |
|
|
/* FIXME: need data sheet to add MWDMA here. Also lacking on
|
502 |
|
|
ide/pci driver */
|
503 |
|
|
} else {
|
504 |
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
505 |
|
|
/* if & 8 no UDMA133 - need info for ... */
|
506 |
|
|
t1 &= ~0x00000FF0;
|
507 |
|
|
t1 |= 0x00000004;
|
508 |
|
|
if (t1 & 0x08)
|
509 |
|
|
t1 |= timing_u133[speed];
|
510 |
|
|
else
|
511 |
|
|
t1 |= timing_u100[speed];
|
512 |
|
|
}
|
513 |
|
|
pci_write_config_dword(pdev, port, t1);
|
514 |
|
|
}
|
515 |
|
|
|
516 |
|
|
static struct scsi_host_template sis_sht = {
|
517 |
|
|
.module = THIS_MODULE,
|
518 |
|
|
.name = DRV_NAME,
|
519 |
|
|
.ioctl = ata_scsi_ioctl,
|
520 |
|
|
.queuecommand = ata_scsi_queuecmd,
|
521 |
|
|
.can_queue = ATA_DEF_QUEUE,
|
522 |
|
|
.this_id = ATA_SHT_THIS_ID,
|
523 |
|
|
.sg_tablesize = LIBATA_MAX_PRD,
|
524 |
|
|
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
525 |
|
|
.emulated = ATA_SHT_EMULATED,
|
526 |
|
|
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
527 |
|
|
.proc_name = DRV_NAME,
|
528 |
|
|
.dma_boundary = ATA_DMA_BOUNDARY,
|
529 |
|
|
.slave_configure = ata_scsi_slave_config,
|
530 |
|
|
.slave_destroy = ata_scsi_slave_destroy,
|
531 |
|
|
.bios_param = ata_std_bios_param,
|
532 |
|
|
};
|
533 |
|
|
|
534 |
|
|
static const struct ata_port_operations sis_133_ops = {
|
535 |
|
|
.set_piomode = sis_133_set_piomode,
|
536 |
|
|
.set_dmamode = sis_133_set_dmamode,
|
537 |
|
|
.mode_filter = ata_pci_default_filter,
|
538 |
|
|
|
539 |
|
|
.tf_load = ata_tf_load,
|
540 |
|
|
.tf_read = ata_tf_read,
|
541 |
|
|
.check_status = ata_check_status,
|
542 |
|
|
.exec_command = ata_exec_command,
|
543 |
|
|
.dev_select = ata_std_dev_select,
|
544 |
|
|
|
545 |
|
|
.freeze = ata_bmdma_freeze,
|
546 |
|
|
.thaw = ata_bmdma_thaw,
|
547 |
|
|
.error_handler = sis_error_handler,
|
548 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
549 |
|
|
.cable_detect = sis_133_cable_detect,
|
550 |
|
|
|
551 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
552 |
|
|
.bmdma_start = ata_bmdma_start,
|
553 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
554 |
|
|
.bmdma_status = ata_bmdma_status,
|
555 |
|
|
.qc_prep = ata_qc_prep,
|
556 |
|
|
.qc_issue = ata_qc_issue_prot,
|
557 |
|
|
.data_xfer = ata_data_xfer,
|
558 |
|
|
|
559 |
|
|
.irq_handler = ata_interrupt,
|
560 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
561 |
|
|
.irq_on = ata_irq_on,
|
562 |
|
|
|
563 |
|
|
.port_start = ata_sff_port_start,
|
564 |
|
|
};
|
565 |
|
|
|
566 |
|
|
static const struct ata_port_operations sis_133_for_sata_ops = {
|
567 |
|
|
.set_piomode = sis_133_set_piomode,
|
568 |
|
|
.set_dmamode = sis_133_set_dmamode,
|
569 |
|
|
.mode_filter = ata_pci_default_filter,
|
570 |
|
|
|
571 |
|
|
.tf_load = ata_tf_load,
|
572 |
|
|
.tf_read = ata_tf_read,
|
573 |
|
|
.check_status = ata_check_status,
|
574 |
|
|
.exec_command = ata_exec_command,
|
575 |
|
|
.dev_select = ata_std_dev_select,
|
576 |
|
|
|
577 |
|
|
.freeze = ata_bmdma_freeze,
|
578 |
|
|
.thaw = ata_bmdma_thaw,
|
579 |
|
|
.error_handler = ata_bmdma_error_handler,
|
580 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
581 |
|
|
.cable_detect = sis_133_cable_detect,
|
582 |
|
|
|
583 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
584 |
|
|
.bmdma_start = ata_bmdma_start,
|
585 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
586 |
|
|
.bmdma_status = ata_bmdma_status,
|
587 |
|
|
.qc_prep = ata_qc_prep,
|
588 |
|
|
.qc_issue = ata_qc_issue_prot,
|
589 |
|
|
.data_xfer = ata_data_xfer,
|
590 |
|
|
|
591 |
|
|
.irq_handler = ata_interrupt,
|
592 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
593 |
|
|
.irq_on = ata_irq_on,
|
594 |
|
|
|
595 |
|
|
.port_start = ata_sff_port_start,
|
596 |
|
|
};
|
597 |
|
|
|
598 |
|
|
static const struct ata_port_operations sis_133_early_ops = {
|
599 |
|
|
.set_piomode = sis_100_set_piomode,
|
600 |
|
|
.set_dmamode = sis_133_early_set_dmamode,
|
601 |
|
|
.mode_filter = ata_pci_default_filter,
|
602 |
|
|
|
603 |
|
|
.tf_load = ata_tf_load,
|
604 |
|
|
.tf_read = ata_tf_read,
|
605 |
|
|
.check_status = ata_check_status,
|
606 |
|
|
.exec_command = ata_exec_command,
|
607 |
|
|
.dev_select = ata_std_dev_select,
|
608 |
|
|
|
609 |
|
|
.freeze = ata_bmdma_freeze,
|
610 |
|
|
.thaw = ata_bmdma_thaw,
|
611 |
|
|
.error_handler = sis_error_handler,
|
612 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
613 |
|
|
.cable_detect = sis_66_cable_detect,
|
614 |
|
|
|
615 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
616 |
|
|
.bmdma_start = ata_bmdma_start,
|
617 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
618 |
|
|
.bmdma_status = ata_bmdma_status,
|
619 |
|
|
.qc_prep = ata_qc_prep,
|
620 |
|
|
.qc_issue = ata_qc_issue_prot,
|
621 |
|
|
.data_xfer = ata_data_xfer,
|
622 |
|
|
|
623 |
|
|
.irq_handler = ata_interrupt,
|
624 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
625 |
|
|
.irq_on = ata_irq_on,
|
626 |
|
|
|
627 |
|
|
.port_start = ata_sff_port_start,
|
628 |
|
|
};
|
629 |
|
|
|
630 |
|
|
static const struct ata_port_operations sis_100_ops = {
|
631 |
|
|
.set_piomode = sis_100_set_piomode,
|
632 |
|
|
.set_dmamode = sis_100_set_dmamode,
|
633 |
|
|
.mode_filter = ata_pci_default_filter,
|
634 |
|
|
|
635 |
|
|
.tf_load = ata_tf_load,
|
636 |
|
|
.tf_read = ata_tf_read,
|
637 |
|
|
.check_status = ata_check_status,
|
638 |
|
|
.exec_command = ata_exec_command,
|
639 |
|
|
.dev_select = ata_std_dev_select,
|
640 |
|
|
|
641 |
|
|
.freeze = ata_bmdma_freeze,
|
642 |
|
|
.thaw = ata_bmdma_thaw,
|
643 |
|
|
.error_handler = sis_error_handler,
|
644 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
645 |
|
|
.cable_detect = sis_66_cable_detect,
|
646 |
|
|
|
647 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
648 |
|
|
.bmdma_start = ata_bmdma_start,
|
649 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
650 |
|
|
.bmdma_status = ata_bmdma_status,
|
651 |
|
|
.qc_prep = ata_qc_prep,
|
652 |
|
|
.qc_issue = ata_qc_issue_prot,
|
653 |
|
|
.data_xfer = ata_data_xfer,
|
654 |
|
|
|
655 |
|
|
.irq_handler = ata_interrupt,
|
656 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
657 |
|
|
.irq_on = ata_irq_on,
|
658 |
|
|
|
659 |
|
|
.port_start = ata_sff_port_start,
|
660 |
|
|
};
|
661 |
|
|
|
662 |
|
|
static const struct ata_port_operations sis_66_ops = {
|
663 |
|
|
.set_piomode = sis_old_set_piomode,
|
664 |
|
|
.set_dmamode = sis_66_set_dmamode,
|
665 |
|
|
.mode_filter = ata_pci_default_filter,
|
666 |
|
|
|
667 |
|
|
.tf_load = ata_tf_load,
|
668 |
|
|
.tf_read = ata_tf_read,
|
669 |
|
|
.check_status = ata_check_status,
|
670 |
|
|
.exec_command = ata_exec_command,
|
671 |
|
|
.dev_select = ata_std_dev_select,
|
672 |
|
|
.cable_detect = sis_66_cable_detect,
|
673 |
|
|
|
674 |
|
|
.freeze = ata_bmdma_freeze,
|
675 |
|
|
.thaw = ata_bmdma_thaw,
|
676 |
|
|
.error_handler = sis_error_handler,
|
677 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
678 |
|
|
|
679 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
680 |
|
|
.bmdma_start = ata_bmdma_start,
|
681 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
682 |
|
|
.bmdma_status = ata_bmdma_status,
|
683 |
|
|
.qc_prep = ata_qc_prep,
|
684 |
|
|
.qc_issue = ata_qc_issue_prot,
|
685 |
|
|
.data_xfer = ata_data_xfer,
|
686 |
|
|
|
687 |
|
|
.irq_handler = ata_interrupt,
|
688 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
689 |
|
|
.irq_on = ata_irq_on,
|
690 |
|
|
|
691 |
|
|
.port_start = ata_sff_port_start,
|
692 |
|
|
};
|
693 |
|
|
|
694 |
|
|
static const struct ata_port_operations sis_old_ops = {
|
695 |
|
|
.set_piomode = sis_old_set_piomode,
|
696 |
|
|
.set_dmamode = sis_old_set_dmamode,
|
697 |
|
|
.mode_filter = ata_pci_default_filter,
|
698 |
|
|
|
699 |
|
|
.tf_load = ata_tf_load,
|
700 |
|
|
.tf_read = ata_tf_read,
|
701 |
|
|
.check_status = ata_check_status,
|
702 |
|
|
.exec_command = ata_exec_command,
|
703 |
|
|
.dev_select = ata_std_dev_select,
|
704 |
|
|
|
705 |
|
|
.freeze = ata_bmdma_freeze,
|
706 |
|
|
.thaw = ata_bmdma_thaw,
|
707 |
|
|
.error_handler = sis_error_handler,
|
708 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
709 |
|
|
.cable_detect = ata_cable_40wire,
|
710 |
|
|
|
711 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
712 |
|
|
.bmdma_start = ata_bmdma_start,
|
713 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
714 |
|
|
.bmdma_status = ata_bmdma_status,
|
715 |
|
|
.qc_prep = ata_qc_prep,
|
716 |
|
|
.qc_issue = ata_qc_issue_prot,
|
717 |
|
|
.data_xfer = ata_data_xfer,
|
718 |
|
|
|
719 |
|
|
.irq_handler = ata_interrupt,
|
720 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
721 |
|
|
.irq_on = ata_irq_on,
|
722 |
|
|
|
723 |
|
|
.port_start = ata_sff_port_start,
|
724 |
|
|
};
|
725 |
|
|
|
726 |
|
|
static const struct ata_port_info sis_info = {
|
727 |
|
|
.sht = &sis_sht,
|
728 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
729 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
730 |
|
|
.mwdma_mask = 0x07,
|
731 |
|
|
.udma_mask = 0,
|
732 |
|
|
.port_ops = &sis_old_ops,
|
733 |
|
|
};
|
734 |
|
|
static const struct ata_port_info sis_info33 = {
|
735 |
|
|
.sht = &sis_sht,
|
736 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
737 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
738 |
|
|
.mwdma_mask = 0x07,
|
739 |
|
|
.udma_mask = ATA_UDMA2, /* UDMA 33 */
|
740 |
|
|
.port_ops = &sis_old_ops,
|
741 |
|
|
};
|
742 |
|
|
static const struct ata_port_info sis_info66 = {
|
743 |
|
|
.sht = &sis_sht,
|
744 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
745 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
746 |
|
|
.udma_mask = ATA_UDMA4, /* UDMA 66 */
|
747 |
|
|
.port_ops = &sis_66_ops,
|
748 |
|
|
};
|
749 |
|
|
static const struct ata_port_info sis_info100 = {
|
750 |
|
|
.sht = &sis_sht,
|
751 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
752 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
753 |
|
|
.udma_mask = ATA_UDMA5,
|
754 |
|
|
.port_ops = &sis_100_ops,
|
755 |
|
|
};
|
756 |
|
|
static const struct ata_port_info sis_info100_early = {
|
757 |
|
|
.sht = &sis_sht,
|
758 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
759 |
|
|
.udma_mask = ATA_UDMA5,
|
760 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
761 |
|
|
.port_ops = &sis_66_ops,
|
762 |
|
|
};
|
763 |
|
|
static const struct ata_port_info sis_info133 = {
|
764 |
|
|
.sht = &sis_sht,
|
765 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
766 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
767 |
|
|
.udma_mask = ATA_UDMA6,
|
768 |
|
|
.port_ops = &sis_133_ops,
|
769 |
|
|
};
|
770 |
|
|
const struct ata_port_info sis_info133_for_sata = {
|
771 |
|
|
.sht = &sis_sht,
|
772 |
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
773 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
774 |
|
|
.udma_mask = ATA_UDMA6,
|
775 |
|
|
.port_ops = &sis_133_for_sata_ops,
|
776 |
|
|
};
|
777 |
|
|
static const struct ata_port_info sis_info133_early = {
|
778 |
|
|
.sht = &sis_sht,
|
779 |
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
780 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
781 |
|
|
.udma_mask = ATA_UDMA6,
|
782 |
|
|
.port_ops = &sis_133_early_ops,
|
783 |
|
|
};
|
784 |
|
|
|
785 |
|
|
/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
|
786 |
|
|
EXPORT_SYMBOL_GPL(sis_info133_for_sata);
|
787 |
|
|
|
788 |
|
|
static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
|
789 |
|
|
{
|
790 |
|
|
u16 regw;
|
791 |
|
|
u8 reg;
|
792 |
|
|
|
793 |
|
|
if (sis->info == &sis_info133) {
|
794 |
|
|
pci_read_config_word(pdev, 0x50, ®w);
|
795 |
|
|
if (regw & 0x08)
|
796 |
|
|
pci_write_config_word(pdev, 0x50, regw & ~0x08);
|
797 |
|
|
pci_read_config_word(pdev, 0x52, ®w);
|
798 |
|
|
if (regw & 0x08)
|
799 |
|
|
pci_write_config_word(pdev, 0x52, regw & ~0x08);
|
800 |
|
|
return;
|
801 |
|
|
}
|
802 |
|
|
|
803 |
|
|
if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
|
804 |
|
|
/* Fix up latency */
|
805 |
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
|
806 |
|
|
/* Set compatibility bit */
|
807 |
|
|
pci_read_config_byte(pdev, 0x49, ®);
|
808 |
|
|
if (!(reg & 0x01))
|
809 |
|
|
pci_write_config_byte(pdev, 0x49, reg | 0x01);
|
810 |
|
|
return;
|
811 |
|
|
}
|
812 |
|
|
|
813 |
|
|
if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
|
814 |
|
|
/* Fix up latency */
|
815 |
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
|
816 |
|
|
/* Set compatibility bit */
|
817 |
|
|
pci_read_config_byte(pdev, 0x52, ®);
|
818 |
|
|
if (!(reg & 0x04))
|
819 |
|
|
pci_write_config_byte(pdev, 0x52, reg | 0x04);
|
820 |
|
|
return;
|
821 |
|
|
}
|
822 |
|
|
|
823 |
|
|
if (sis->info == &sis_info33) {
|
824 |
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, ®);
|
825 |
|
|
if (( reg & 0x0F ) != 0x00)
|
826 |
|
|
pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
|
827 |
|
|
/* Fall through to ATA16 fixup below */
|
828 |
|
|
}
|
829 |
|
|
|
830 |
|
|
if (sis->info == &sis_info || sis->info == &sis_info33) {
|
831 |
|
|
/* force per drive recovery and active timings
|
832 |
|
|
needed on ATA_33 and below chips */
|
833 |
|
|
pci_read_config_byte(pdev, 0x52, ®);
|
834 |
|
|
if (!(reg & 0x08))
|
835 |
|
|
pci_write_config_byte(pdev, 0x52, reg|0x08);
|
836 |
|
|
return;
|
837 |
|
|
}
|
838 |
|
|
|
839 |
|
|
BUG();
|
840 |
|
|
}
|
841 |
|
|
|
842 |
|
|
/**
|
843 |
|
|
* sis_init_one - Register SiS ATA PCI device with kernel services
|
844 |
|
|
* @pdev: PCI device to register
|
845 |
|
|
* @ent: Entry in sis_pci_tbl matching with @pdev
|
846 |
|
|
*
|
847 |
|
|
* Called from kernel PCI layer. We probe for combined mode (sigh),
|
848 |
|
|
* and then hand over control to libata, for it to do the rest.
|
849 |
|
|
*
|
850 |
|
|
* LOCKING:
|
851 |
|
|
* Inherited from PCI layer (may sleep).
|
852 |
|
|
*
|
853 |
|
|
* RETURNS:
|
854 |
|
|
* Zero on success, or -ERRNO value.
|
855 |
|
|
*/
|
856 |
|
|
|
857 |
|
|
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
858 |
|
|
{
|
859 |
|
|
static int printed_version;
|
860 |
|
|
struct ata_port_info port;
|
861 |
|
|
const struct ata_port_info *ppi[] = { &port, NULL };
|
862 |
|
|
struct pci_dev *host = NULL;
|
863 |
|
|
struct sis_chipset *chipset = NULL;
|
864 |
|
|
struct sis_chipset *sets;
|
865 |
|
|
|
866 |
|
|
static struct sis_chipset sis_chipsets[] = {
|
867 |
|
|
|
868 |
|
|
{ 0x0968, &sis_info133 },
|
869 |
|
|
{ 0x0966, &sis_info133 },
|
870 |
|
|
{ 0x0965, &sis_info133 },
|
871 |
|
|
{ 0x0745, &sis_info100 },
|
872 |
|
|
{ 0x0735, &sis_info100 },
|
873 |
|
|
{ 0x0733, &sis_info100 },
|
874 |
|
|
{ 0x0635, &sis_info100 },
|
875 |
|
|
{ 0x0633, &sis_info100 },
|
876 |
|
|
|
877 |
|
|
{ 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
|
878 |
|
|
{ 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
|
879 |
|
|
|
880 |
|
|
{ 0x0640, &sis_info66 },
|
881 |
|
|
{ 0x0630, &sis_info66 },
|
882 |
|
|
{ 0x0620, &sis_info66 },
|
883 |
|
|
{ 0x0540, &sis_info66 },
|
884 |
|
|
{ 0x0530, &sis_info66 },
|
885 |
|
|
|
886 |
|
|
{ 0x5600, &sis_info33 },
|
887 |
|
|
{ 0x5598, &sis_info33 },
|
888 |
|
|
{ 0x5597, &sis_info33 },
|
889 |
|
|
{ 0x5591, &sis_info33 },
|
890 |
|
|
{ 0x5582, &sis_info33 },
|
891 |
|
|
{ 0x5581, &sis_info33 },
|
892 |
|
|
|
893 |
|
|
{ 0x5596, &sis_info },
|
894 |
|
|
{ 0x5571, &sis_info },
|
895 |
|
|
{ 0x5517, &sis_info },
|
896 |
|
|
{ 0x5511, &sis_info },
|
897 |
|
|
|
898 |
|
|
{0}
|
899 |
|
|
};
|
900 |
|
|
static struct sis_chipset sis133_early = {
|
901 |
|
|
0x0, &sis_info133_early
|
902 |
|
|
};
|
903 |
|
|
static struct sis_chipset sis133 = {
|
904 |
|
|
0x0, &sis_info133
|
905 |
|
|
};
|
906 |
|
|
static struct sis_chipset sis100_early = {
|
907 |
|
|
0x0, &sis_info100_early
|
908 |
|
|
};
|
909 |
|
|
static struct sis_chipset sis100 = {
|
910 |
|
|
0x0, &sis_info100
|
911 |
|
|
};
|
912 |
|
|
|
913 |
|
|
if (!printed_version++)
|
914 |
|
|
dev_printk(KERN_DEBUG, &pdev->dev,
|
915 |
|
|
"version " DRV_VERSION "\n");
|
916 |
|
|
|
917 |
|
|
/* We have to find the bridge first */
|
918 |
|
|
|
919 |
|
|
for (sets = &sis_chipsets[0]; sets->device; sets++) {
|
920 |
|
|
host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
|
921 |
|
|
if (host != NULL) {
|
922 |
|
|
chipset = sets; /* Match found */
|
923 |
|
|
if (sets->device == 0x630) { /* SIS630 */
|
924 |
|
|
if (host->revision >= 0x30) /* 630 ET */
|
925 |
|
|
chipset = &sis100_early;
|
926 |
|
|
}
|
927 |
|
|
break;
|
928 |
|
|
}
|
929 |
|
|
}
|
930 |
|
|
|
931 |
|
|
/* Look for concealed bridges */
|
932 |
|
|
if (chipset == NULL) {
|
933 |
|
|
/* Second check */
|
934 |
|
|
u32 idemisc;
|
935 |
|
|
u16 trueid;
|
936 |
|
|
|
937 |
|
|
/* Disable ID masking and register remapping then
|
938 |
|
|
see what the real ID is */
|
939 |
|
|
|
940 |
|
|
pci_read_config_dword(pdev, 0x54, &idemisc);
|
941 |
|
|
pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
|
942 |
|
|
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
|
943 |
|
|
pci_write_config_dword(pdev, 0x54, idemisc);
|
944 |
|
|
|
945 |
|
|
switch(trueid) {
|
946 |
|
|
case 0x5518: /* SIS 962/963 */
|
947 |
|
|
chipset = &sis133;
|
948 |
|
|
if ((idemisc & 0x40000000) == 0) {
|
949 |
|
|
pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
|
950 |
|
|
printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
|
951 |
|
|
}
|
952 |
|
|
break;
|
953 |
|
|
case 0x0180: /* SIS 965/965L */
|
954 |
|
|
chipset = &sis133;
|
955 |
|
|
break;
|
956 |
|
|
case 0x1180: /* SIS 966/966L */
|
957 |
|
|
chipset = &sis133;
|
958 |
|
|
break;
|
959 |
|
|
}
|
960 |
|
|
}
|
961 |
|
|
|
962 |
|
|
/* Further check */
|
963 |
|
|
if (chipset == NULL) {
|
964 |
|
|
struct pci_dev *lpc_bridge;
|
965 |
|
|
u16 trueid;
|
966 |
|
|
u8 prefctl;
|
967 |
|
|
u8 idecfg;
|
968 |
|
|
|
969 |
|
|
/* Try the second unmasking technique */
|
970 |
|
|
pci_read_config_byte(pdev, 0x4a, &idecfg);
|
971 |
|
|
pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
|
972 |
|
|
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
|
973 |
|
|
pci_write_config_byte(pdev, 0x4a, idecfg);
|
974 |
|
|
|
975 |
|
|
switch(trueid) {
|
976 |
|
|
case 0x5517:
|
977 |
|
|
lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
|
978 |
|
|
if (lpc_bridge == NULL)
|
979 |
|
|
break;
|
980 |
|
|
pci_read_config_byte(pdev, 0x49, &prefctl);
|
981 |
|
|
pci_dev_put(lpc_bridge);
|
982 |
|
|
|
983 |
|
|
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
|
984 |
|
|
chipset = &sis133_early;
|
985 |
|
|
break;
|
986 |
|
|
}
|
987 |
|
|
chipset = &sis100;
|
988 |
|
|
break;
|
989 |
|
|
}
|
990 |
|
|
}
|
991 |
|
|
pci_dev_put(host);
|
992 |
|
|
|
993 |
|
|
/* No chipset info, no support */
|
994 |
|
|
if (chipset == NULL)
|
995 |
|
|
return -ENODEV;
|
996 |
|
|
|
997 |
|
|
port = *chipset->info;
|
998 |
|
|
port.private_data = chipset;
|
999 |
|
|
|
1000 |
|
|
sis_fixup(pdev, chipset);
|
1001 |
|
|
|
1002 |
|
|
return ata_pci_init_one(pdev, ppi);
|
1003 |
|
|
}
|
1004 |
|
|
|
1005 |
|
|
static const struct pci_device_id sis_pci_tbl[] = {
|
1006 |
|
|
{ PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
|
1007 |
|
|
{ PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
|
1008 |
|
|
{ PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
|
1009 |
|
|
|
1010 |
|
|
{ }
|
1011 |
|
|
};
|
1012 |
|
|
|
1013 |
|
|
static struct pci_driver sis_pci_driver = {
|
1014 |
|
|
.name = DRV_NAME,
|
1015 |
|
|
.id_table = sis_pci_tbl,
|
1016 |
|
|
.probe = sis_init_one,
|
1017 |
|
|
.remove = ata_pci_remove_one,
|
1018 |
|
|
#ifdef CONFIG_PM
|
1019 |
|
|
.suspend = ata_pci_device_suspend,
|
1020 |
|
|
.resume = ata_pci_device_resume,
|
1021 |
|
|
#endif
|
1022 |
|
|
};
|
1023 |
|
|
|
1024 |
|
|
static int __init sis_init(void)
|
1025 |
|
|
{
|
1026 |
|
|
return pci_register_driver(&sis_pci_driver);
|
1027 |
|
|
}
|
1028 |
|
|
|
1029 |
|
|
static void __exit sis_exit(void)
|
1030 |
|
|
{
|
1031 |
|
|
pci_unregister_driver(&sis_pci_driver);
|
1032 |
|
|
}
|
1033 |
|
|
|
1034 |
|
|
module_init(sis_init);
|
1035 |
|
|
module_exit(sis_exit);
|
1036 |
|
|
|
1037 |
|
|
MODULE_AUTHOR("Alan Cox");
|
1038 |
|
|
MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
|
1039 |
|
|
MODULE_LICENSE("GPL");
|
1040 |
|
|
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
|
1041 |
|
|
MODULE_VERSION(DRV_VERSION);
|
1042 |
|
|
|