OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [ata/] [pdc_adma.c] - Blame information for rev 65

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 62 marcus.erl
/*
2
 *  pdc_adma.c - Pacific Digital Corporation ADMA
3
 *
4
 *  Maintained by:  Mark Lord <mlord@pobox.com>
5
 *
6
 *  Copyright 2005 Mark Lord
7
 *
8
 *  This program is free software; you can redistribute it and/or modify
9
 *  it under the terms of the GNU General Public License as published by
10
 *  the Free Software Foundation; either version 2, or (at your option)
11
 *  any later version.
12
 *
13
 *  This program is distributed in the hope that it will be useful,
14
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
 *  GNU General Public License for more details.
17
 *
18
 *  You should have received a copy of the GNU General Public License
19
 *  along with this program; see the file COPYING.  If not, write to
20
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
 *
22
 *
23
 *  libata documentation is available via 'make {ps|pdf}docs',
24
 *  as Documentation/DocBook/libata.*
25
 *
26
 *
27
 *  Supports ATA disks in single-packet ADMA mode.
28
 *  Uses PIO for everything else.
29
 *
30
 *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
31
 *  This requires careful attention to a number of quirks of the chip.
32
 *
33
 */
34
 
35
#include <linux/kernel.h>
36
#include <linux/module.h>
37
#include <linux/pci.h>
38
#include <linux/init.h>
39
#include <linux/blkdev.h>
40
#include <linux/delay.h>
41
#include <linux/interrupt.h>
42
#include <linux/device.h>
43
#include <scsi/scsi_host.h>
44
#include <linux/libata.h>
45
 
46
#define DRV_NAME        "pdc_adma"
47
#define DRV_VERSION     "1.0"
48
 
49
/* macro to calculate base address for ATA regs */
50
#define ADMA_ATA_REGS(base, port_no)    ((base) + ((port_no) * 0x40))
51
 
52
/* macro to calculate base address for ADMA regs */
53
#define ADMA_REGS(base, port_no)        ((base) + 0x80 + ((port_no) * 0x20))
54
 
55
/* macro to obtain addresses from ata_port */
56
#define ADMA_PORT_REGS(ap) \
57
        ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
 
59
enum {
60
        ADMA_MMIO_BAR           = 4,
61
 
62
        ADMA_PORTS              = 2,
63
        ADMA_CPB_BYTES          = 40,
64
        ADMA_PRD_BYTES          = LIBATA_MAX_PRD * 16,
65
        ADMA_PKT_BYTES          = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
 
67
        ADMA_DMA_BOUNDARY       = 0xffffffff,
68
 
69
        /* global register offsets */
70
        ADMA_MODE_LOCK          = 0x00c7,
71
 
72
        /* per-channel register offsets */
73
        ADMA_CONTROL            = 0x0000, /* ADMA control */
74
        ADMA_STATUS             = 0x0002, /* ADMA status */
75
        ADMA_CPB_COUNT          = 0x0004, /* CPB count */
76
        ADMA_CPB_CURRENT        = 0x000c, /* current CPB address */
77
        ADMA_CPB_NEXT           = 0x000c, /* next CPB address */
78
        ADMA_CPB_LOOKUP         = 0x0010, /* CPB lookup table */
79
        ADMA_FIFO_IN            = 0x0014, /* input FIFO threshold */
80
        ADMA_FIFO_OUT           = 0x0016, /* output FIFO threshold */
81
 
82
        /* ADMA_CONTROL register bits */
83
        aNIEN                   = (1 << 8), /* irq mask: 1==masked */
84
        aGO                     = (1 << 7), /* packet trigger ("Go!") */
85
        aRSTADM                 = (1 << 5), /* ADMA logic reset */
86
        aPIOMD4                 = 0x0003,   /* PIO mode 4 */
87
 
88
        /* ADMA_STATUS register bits */
89
        aPSD                    = (1 << 6),
90
        aUIRQ                   = (1 << 4),
91
        aPERR                   = (1 << 0),
92
 
93
        /* CPB bits */
94
        cDONE                   = (1 << 0),
95
        cATERR                  = (1 << 3),
96
 
97
        cVLD                    = (1 << 0),
98
        cDAT                    = (1 << 2),
99
        cIEN                    = (1 << 3),
100
 
101
        /* PRD bits */
102
        pORD                    = (1 << 4),
103
        pDIRO                   = (1 << 5),
104
        pEND                    = (1 << 7),
105
 
106
        /* ATA register flags */
107
        rIGN                    = (1 << 5),
108
        rEND                    = (1 << 7),
109
 
110
        /* ATA register addresses */
111
        ADMA_REGS_CONTROL       = 0x0e,
112
        ADMA_REGS_SECTOR_COUNT  = 0x12,
113
        ADMA_REGS_LBA_LOW       = 0x13,
114
        ADMA_REGS_LBA_MID       = 0x14,
115
        ADMA_REGS_LBA_HIGH      = 0x15,
116
        ADMA_REGS_DEVICE        = 0x16,
117
        ADMA_REGS_COMMAND       = 0x17,
118
 
119
        /* PCI device IDs */
120
        board_1841_idx          = 0,     /* ADMA 2-port controller */
121
};
122
 
123
typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
 
125
struct adma_port_priv {
126
        u8                      *pkt;
127
        dma_addr_t              pkt_dma;
128
        adma_state_t            state;
129
};
130
 
131
static int adma_ata_init_one(struct pci_dev *pdev,
132
                                const struct pci_device_id *ent);
133
static int adma_port_start(struct ata_port *ap);
134
static void adma_host_stop(struct ata_host *host);
135
static void adma_port_stop(struct ata_port *ap);
136
static void adma_qc_prep(struct ata_queued_cmd *qc);
137
static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138
static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139
static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140
static u8 adma_bmdma_status(struct ata_port *ap);
141
static void adma_irq_clear(struct ata_port *ap);
142
static void adma_freeze(struct ata_port *ap);
143
static void adma_thaw(struct ata_port *ap);
144
static void adma_error_handler(struct ata_port *ap);
145
 
146
static struct scsi_host_template adma_ata_sht = {
147
        .module                 = THIS_MODULE,
148
        .name                   = DRV_NAME,
149
        .ioctl                  = ata_scsi_ioctl,
150
        .queuecommand           = ata_scsi_queuecmd,
151
        .slave_configure        = ata_scsi_slave_config,
152
        .slave_destroy          = ata_scsi_slave_destroy,
153
        .bios_param             = ata_std_bios_param,
154
        .proc_name              = DRV_NAME,
155
        .can_queue              = ATA_DEF_QUEUE,
156
        .this_id                = ATA_SHT_THIS_ID,
157
        .sg_tablesize           = LIBATA_MAX_PRD,
158
        .dma_boundary           = ADMA_DMA_BOUNDARY,
159
        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
160
        .use_clustering         = ENABLE_CLUSTERING,
161
        .emulated               = ATA_SHT_EMULATED,
162
};
163
 
164
static const struct ata_port_operations adma_ata_ops = {
165
        .tf_load                = ata_tf_load,
166
        .tf_read                = ata_tf_read,
167
        .exec_command           = ata_exec_command,
168
        .check_status           = ata_check_status,
169
        .dev_select             = ata_std_dev_select,
170
        .check_atapi_dma        = adma_check_atapi_dma,
171
        .data_xfer              = ata_data_xfer,
172
        .qc_prep                = adma_qc_prep,
173
        .qc_issue               = adma_qc_issue,
174
        .freeze                 = adma_freeze,
175
        .thaw                   = adma_thaw,
176
        .error_handler          = adma_error_handler,
177
        .irq_clear              = adma_irq_clear,
178
        .irq_on                 = ata_irq_on,
179
        .port_start             = adma_port_start,
180
        .port_stop              = adma_port_stop,
181
        .host_stop              = adma_host_stop,
182
        .bmdma_stop             = adma_bmdma_stop,
183
        .bmdma_status           = adma_bmdma_status,
184
};
185
 
186
static struct ata_port_info adma_port_info[] = {
187
        /* board_1841_idx */
188
        {
189
                .flags          = ATA_FLAG_SLAVE_POSS |
190
                                  ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
191
                                  ATA_FLAG_PIO_POLLING,
192
                .pio_mask       = 0x10, /* pio4 */
193
                .udma_mask      = ATA_UDMA4,
194
                .port_ops       = &adma_ata_ops,
195
        },
196
};
197
 
198
static const struct pci_device_id adma_ata_pci_tbl[] = {
199
        { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
200
 
201
        { }     /* terminate list */
202
};
203
 
204
static struct pci_driver adma_ata_pci_driver = {
205
        .name                   = DRV_NAME,
206
        .id_table               = adma_ata_pci_tbl,
207
        .probe                  = adma_ata_init_one,
208
        .remove                 = ata_pci_remove_one,
209
};
210
 
211
static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
212
{
213
        return 1;       /* ATAPI DMA not yet supported */
214
}
215
 
216
static void adma_bmdma_stop(struct ata_queued_cmd *qc)
217
{
218
        /* nothing */
219
}
220
 
221
static u8 adma_bmdma_status(struct ata_port *ap)
222
{
223
        return 0;
224
}
225
 
226
static void adma_irq_clear(struct ata_port *ap)
227
{
228
        /* nothing */
229
}
230
 
231
static void adma_reset_engine(struct ata_port *ap)
232
{
233
        void __iomem *chan = ADMA_PORT_REGS(ap);
234
 
235
        /* reset ADMA to idle state */
236
        writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
237
        udelay(2);
238
        writew(aPIOMD4, chan + ADMA_CONTROL);
239
        udelay(2);
240
}
241
 
242
static void adma_reinit_engine(struct ata_port *ap)
243
{
244
        struct adma_port_priv *pp = ap->private_data;
245
        void __iomem *chan = ADMA_PORT_REGS(ap);
246
 
247
        /* mask/clear ATA interrupts */
248
        writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
249
        ata_check_status(ap);
250
 
251
        /* reset the ADMA engine */
252
        adma_reset_engine(ap);
253
 
254
        /* set in-FIFO threshold to 0x100 */
255
        writew(0x100, chan + ADMA_FIFO_IN);
256
 
257
        /* set CPB pointer */
258
        writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
259
 
260
        /* set out-FIFO threshold to 0x100 */
261
        writew(0x100, chan + ADMA_FIFO_OUT);
262
 
263
        /* set CPB count */
264
        writew(1, chan + ADMA_CPB_COUNT);
265
 
266
        /* read/discard ADMA status */
267
        readb(chan + ADMA_STATUS);
268
}
269
 
270
static inline void adma_enter_reg_mode(struct ata_port *ap)
271
{
272
        void __iomem *chan = ADMA_PORT_REGS(ap);
273
 
274
        writew(aPIOMD4, chan + ADMA_CONTROL);
275
        readb(chan + ADMA_STATUS);      /* flush */
276
}
277
 
278
static void adma_freeze(struct ata_port *ap)
279
{
280
        void __iomem *chan = ADMA_PORT_REGS(ap);
281
 
282
        /* mask/clear ATA interrupts */
283
        writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
284
        ata_check_status(ap);
285
 
286
        /* reset ADMA to idle state */
287
        writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
288
        udelay(2);
289
        writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
290
        udelay(2);
291
}
292
 
293
static void adma_thaw(struct ata_port *ap)
294
{
295
        adma_reinit_engine(ap);
296
}
297
 
298
static int adma_prereset(struct ata_link *link, unsigned long deadline)
299
{
300
        struct ata_port *ap = link->ap;
301
        struct adma_port_priv *pp = ap->private_data;
302
 
303
        if (pp->state != adma_state_idle) /* healthy paranoia */
304
                pp->state = adma_state_mmio;
305
        adma_reinit_engine(ap);
306
 
307
        return ata_std_prereset(link, deadline);
308
}
309
 
310
static void adma_error_handler(struct ata_port *ap)
311
{
312
        ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
313
                  ata_std_postreset);
314
}
315
 
316
static int adma_fill_sg(struct ata_queued_cmd *qc)
317
{
318
        struct scatterlist *sg;
319
        struct ata_port *ap = qc->ap;
320
        struct adma_port_priv *pp = ap->private_data;
321
        u8  *buf = pp->pkt, *last_buf = NULL;
322
        int i = (2 + buf[3]) * 8;
323
        u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
324
 
325
        ata_for_each_sg(sg, qc) {
326
                u32 addr;
327
                u32 len;
328
 
329
                addr = (u32)sg_dma_address(sg);
330
                *(__le32 *)(buf + i) = cpu_to_le32(addr);
331
                i += 4;
332
 
333
                len = sg_dma_len(sg) >> 3;
334
                *(__le32 *)(buf + i) = cpu_to_le32(len);
335
                i += 4;
336
 
337
                last_buf = &buf[i];
338
                buf[i++] = pFLAGS;
339
                buf[i++] = qc->dev->dma_mode & 0xf;
340
                buf[i++] = 0;    /* pPKLW */
341
                buf[i++] = 0;    /* reserved */
342
 
343
                *(__le32 *)(buf + i) =
344
                        (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
345
                i += 4;
346
 
347
                VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
348
                                        (unsigned long)addr, len);
349
        }
350
 
351
        if (likely(last_buf))
352
                *last_buf |= pEND;
353
 
354
        return i;
355
}
356
 
357
static void adma_qc_prep(struct ata_queued_cmd *qc)
358
{
359
        struct adma_port_priv *pp = qc->ap->private_data;
360
        u8  *buf = pp->pkt;
361
        u32 pkt_dma = (u32)pp->pkt_dma;
362
        int i = 0;
363
 
364
        VPRINTK("ENTER\n");
365
 
366
        adma_enter_reg_mode(qc->ap);
367
        if (qc->tf.protocol != ATA_PROT_DMA) {
368
                ata_qc_prep(qc);
369
                return;
370
        }
371
 
372
        buf[i++] = 0;    /* Response flags */
373
        buf[i++] = 0;    /* reserved */
374
        buf[i++] = cVLD | cDAT | cIEN;
375
        i++;            /* cLEN, gets filled in below */
376
 
377
        *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);      /* cNCPB */
378
        i += 4;         /* cNCPB */
379
        i += 4;         /* cPRD, gets filled in below */
380
 
381
        buf[i++] = 0;    /* reserved */
382
        buf[i++] = 0;    /* reserved */
383
        buf[i++] = 0;    /* reserved */
384
        buf[i++] = 0;    /* reserved */
385
 
386
        /* ATA registers; must be a multiple of 4 */
387
        buf[i++] = qc->tf.device;
388
        buf[i++] = ADMA_REGS_DEVICE;
389
        if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
390
                buf[i++] = qc->tf.hob_nsect;
391
                buf[i++] = ADMA_REGS_SECTOR_COUNT;
392
                buf[i++] = qc->tf.hob_lbal;
393
                buf[i++] = ADMA_REGS_LBA_LOW;
394
                buf[i++] = qc->tf.hob_lbam;
395
                buf[i++] = ADMA_REGS_LBA_MID;
396
                buf[i++] = qc->tf.hob_lbah;
397
                buf[i++] = ADMA_REGS_LBA_HIGH;
398
        }
399
        buf[i++] = qc->tf.nsect;
400
        buf[i++] = ADMA_REGS_SECTOR_COUNT;
401
        buf[i++] = qc->tf.lbal;
402
        buf[i++] = ADMA_REGS_LBA_LOW;
403
        buf[i++] = qc->tf.lbam;
404
        buf[i++] = ADMA_REGS_LBA_MID;
405
        buf[i++] = qc->tf.lbah;
406
        buf[i++] = ADMA_REGS_LBA_HIGH;
407
        buf[i++] = 0;
408
        buf[i++] = ADMA_REGS_CONTROL;
409
        buf[i++] = rIGN;
410
        buf[i++] = 0;
411
        buf[i++] = qc->tf.command;
412
        buf[i++] = ADMA_REGS_COMMAND | rEND;
413
 
414
        buf[3] = (i >> 3) - 2;                          /* cLEN */
415
        *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);  /* cPRD */
416
 
417
        i = adma_fill_sg(qc);
418
        wmb();  /* flush PRDs and pkt to memory */
419
#if 0
420
        /* dump out CPB + PRDs for debug */
421
        {
422
                int j, len = 0;
423
                static char obuf[2048];
424
                for (j = 0; j < i; ++j) {
425
                        len += sprintf(obuf+len, "%02x ", buf[j]);
426
                        if ((j & 7) == 7) {
427
                                printk("%s\n", obuf);
428
                                len = 0;
429
                        }
430
                }
431
                if (len)
432
                        printk("%s\n", obuf);
433
        }
434
#endif
435
}
436
 
437
static inline void adma_packet_start(struct ata_queued_cmd *qc)
438
{
439
        struct ata_port *ap = qc->ap;
440
        void __iomem *chan = ADMA_PORT_REGS(ap);
441
 
442
        VPRINTK("ENTER, ap %p\n", ap);
443
 
444
        /* fire up the ADMA engine */
445
        writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
446
}
447
 
448
static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
449
{
450
        struct adma_port_priv *pp = qc->ap->private_data;
451
 
452
        switch (qc->tf.protocol) {
453
        case ATA_PROT_DMA:
454
                pp->state = adma_state_pkt;
455
                adma_packet_start(qc);
456
                return 0;
457
 
458
        case ATA_PROT_ATAPI_DMA:
459
                BUG();
460
                break;
461
 
462
        default:
463
                break;
464
        }
465
 
466
        pp->state = adma_state_mmio;
467
        return ata_qc_issue_prot(qc);
468
}
469
 
470
static inline unsigned int adma_intr_pkt(struct ata_host *host)
471
{
472
        unsigned int handled = 0, port_no;
473
 
474
        for (port_no = 0; port_no < host->n_ports; ++port_no) {
475
                struct ata_port *ap = host->ports[port_no];
476
                struct adma_port_priv *pp;
477
                struct ata_queued_cmd *qc;
478
                void __iomem *chan = ADMA_PORT_REGS(ap);
479
                u8 status = readb(chan + ADMA_STATUS);
480
 
481
                if (status == 0)
482
                        continue;
483
                handled = 1;
484
                adma_enter_reg_mode(ap);
485
                if (ap->flags & ATA_FLAG_DISABLED)
486
                        continue;
487
                pp = ap->private_data;
488
                if (!pp || pp->state != adma_state_pkt)
489
                        continue;
490
                qc = ata_qc_from_tag(ap, ap->link.active_tag);
491
                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
492
                        if (status & aPERR)
493
                                qc->err_mask |= AC_ERR_HOST_BUS;
494
                        else if ((status & (aPSD | aUIRQ)))
495
                                qc->err_mask |= AC_ERR_OTHER;
496
 
497
                        if (pp->pkt[0] & cATERR)
498
                                qc->err_mask |= AC_ERR_DEV;
499
                        else if (pp->pkt[0] != cDONE)
500
                                qc->err_mask |= AC_ERR_OTHER;
501
 
502
                        if (!qc->err_mask)
503
                                ata_qc_complete(qc);
504
                        else {
505
                                struct ata_eh_info *ehi = &ap->link.eh_info;
506
                                ata_ehi_clear_desc(ehi);
507
                                ata_ehi_push_desc(ehi,
508
                                        "ADMA-status 0x%02X", status);
509
                                ata_ehi_push_desc(ehi,
510
                                        "pkt[0] 0x%02X", pp->pkt[0]);
511
 
512
                                if (qc->err_mask == AC_ERR_DEV)
513
                                        ata_port_abort(ap);
514
                                else
515
                                        ata_port_freeze(ap);
516
                        }
517
                }
518
        }
519
        return handled;
520
}
521
 
522
static inline unsigned int adma_intr_mmio(struct ata_host *host)
523
{
524
        unsigned int handled = 0, port_no;
525
 
526
        for (port_no = 0; port_no < host->n_ports; ++port_no) {
527
                struct ata_port *ap;
528
                ap = host->ports[port_no];
529
                if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
530
                        struct ata_queued_cmd *qc;
531
                        struct adma_port_priv *pp = ap->private_data;
532
                        if (!pp || pp->state != adma_state_mmio)
533
                                continue;
534
                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
535
                        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
536
 
537
                                /* check main status, clearing INTRQ */
538
                                u8 status = ata_check_status(ap);
539
                                if ((status & ATA_BUSY))
540
                                        continue;
541
                                DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
542
                                        ap->print_id, qc->tf.protocol, status);
543
 
544
                                /* complete taskfile transaction */
545
                                pp->state = adma_state_idle;
546
                                qc->err_mask |= ac_err_mask(status);
547
                                if (!qc->err_mask)
548
                                        ata_qc_complete(qc);
549
                                else {
550
                                        struct ata_eh_info *ehi =
551
                                                &ap->link.eh_info;
552
                                        ata_ehi_clear_desc(ehi);
553
                                        ata_ehi_push_desc(ehi,
554
                                                "status 0x%02X", status);
555
 
556
                                        if (qc->err_mask == AC_ERR_DEV)
557
                                                ata_port_abort(ap);
558
                                        else
559
                                                ata_port_freeze(ap);
560
                                }
561
                                handled = 1;
562
                        }
563
                }
564
        }
565
        return handled;
566
}
567
 
568
static irqreturn_t adma_intr(int irq, void *dev_instance)
569
{
570
        struct ata_host *host = dev_instance;
571
        unsigned int handled = 0;
572
 
573
        VPRINTK("ENTER\n");
574
 
575
        spin_lock(&host->lock);
576
        handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
577
        spin_unlock(&host->lock);
578
 
579
        VPRINTK("EXIT\n");
580
 
581
        return IRQ_RETVAL(handled);
582
}
583
 
584
static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
585
{
586
        port->cmd_addr          =
587
        port->data_addr         = base + 0x000;
588
        port->error_addr        =
589
        port->feature_addr      = base + 0x004;
590
        port->nsect_addr        = base + 0x008;
591
        port->lbal_addr         = base + 0x00c;
592
        port->lbam_addr         = base + 0x010;
593
        port->lbah_addr         = base + 0x014;
594
        port->device_addr       = base + 0x018;
595
        port->status_addr       =
596
        port->command_addr      = base + 0x01c;
597
        port->altstatus_addr    =
598
        port->ctl_addr          = base + 0x038;
599
}
600
 
601
static int adma_port_start(struct ata_port *ap)
602
{
603
        struct device *dev = ap->host->dev;
604
        struct adma_port_priv *pp;
605
        int rc;
606
 
607
        rc = ata_port_start(ap);
608
        if (rc)
609
                return rc;
610
        adma_enter_reg_mode(ap);
611
        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
612
        if (!pp)
613
                return -ENOMEM;
614
        pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
615
                                      GFP_KERNEL);
616
        if (!pp->pkt)
617
                return -ENOMEM;
618
        /* paranoia? */
619
        if ((pp->pkt_dma & 7) != 0) {
620
                printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
621
                                                (u32)pp->pkt_dma);
622
                return -ENOMEM;
623
        }
624
        memset(pp->pkt, 0, ADMA_PKT_BYTES);
625
        ap->private_data = pp;
626
        adma_reinit_engine(ap);
627
        return 0;
628
}
629
 
630
static void adma_port_stop(struct ata_port *ap)
631
{
632
        adma_reset_engine(ap);
633
}
634
 
635
static void adma_host_stop(struct ata_host *host)
636
{
637
        unsigned int port_no;
638
 
639
        for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
640
                adma_reset_engine(host->ports[port_no]);
641
}
642
 
643
static void adma_host_init(struct ata_host *host, unsigned int chip_id)
644
{
645
        unsigned int port_no;
646
 
647
        /* enable/lock aGO operation */
648
        writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
649
 
650
        /* reset the ADMA logic */
651
        for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
652
                adma_reset_engine(host->ports[port_no]);
653
}
654
 
655
static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
656
{
657
        int rc;
658
 
659
        rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
660
        if (rc) {
661
                dev_printk(KERN_ERR, &pdev->dev,
662
                        "32-bit DMA enable failed\n");
663
                return rc;
664
        }
665
        rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
666
        if (rc) {
667
                dev_printk(KERN_ERR, &pdev->dev,
668
                        "32-bit consistent DMA enable failed\n");
669
                return rc;
670
        }
671
        return 0;
672
}
673
 
674
static int adma_ata_init_one(struct pci_dev *pdev,
675
                             const struct pci_device_id *ent)
676
{
677
        static int printed_version;
678
        unsigned int board_idx = (unsigned int) ent->driver_data;
679
        const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
680
        struct ata_host *host;
681
        void __iomem *mmio_base;
682
        int rc, port_no;
683
 
684
        if (!printed_version++)
685
                dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
686
 
687
        /* alloc host */
688
        host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
689
        if (!host)
690
                return -ENOMEM;
691
 
692
        /* acquire resources and fill host */
693
        rc = pcim_enable_device(pdev);
694
        if (rc)
695
                return rc;
696
 
697
        if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
698
                return -ENODEV;
699
 
700
        rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
701
        if (rc)
702
                return rc;
703
        host->iomap = pcim_iomap_table(pdev);
704
        mmio_base = host->iomap[ADMA_MMIO_BAR];
705
 
706
        rc = adma_set_dma_masks(pdev, mmio_base);
707
        if (rc)
708
                return rc;
709
 
710
        for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
711
                struct ata_port *ap = host->ports[port_no];
712
                void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
713
                unsigned int offset = port_base - mmio_base;
714
 
715
                adma_ata_setup_port(&ap->ioaddr, port_base);
716
 
717
                ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
718
                ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
719
        }
720
 
721
        /* initialize adapter */
722
        adma_host_init(host, board_idx);
723
 
724
        pci_set_master(pdev);
725
        return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
726
                                 &adma_ata_sht);
727
}
728
 
729
static int __init adma_ata_init(void)
730
{
731
        return pci_register_driver(&adma_ata_pci_driver);
732
}
733
 
734
static void __exit adma_ata_exit(void)
735
{
736
        pci_unregister_driver(&adma_ata_pci_driver);
737
}
738
 
739
MODULE_AUTHOR("Mark Lord");
740
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
741
MODULE_LICENSE("GPL");
742
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
743
MODULE_VERSION(DRV_VERSION);
744
 
745
module_init(adma_ata_init);
746
module_exit(adma_ata_exit);

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.