1 |
62 |
marcus.erl |
/*
|
2 |
|
|
* sata_qstor.c - Pacific Digital Corporation QStor SATA
|
3 |
|
|
*
|
4 |
|
|
* Maintained by: Mark Lord <mlord@pobox.com>
|
5 |
|
|
*
|
6 |
|
|
* Copyright 2005 Pacific Digital Corporation.
|
7 |
|
|
* (OSL/GPL code release authorized by Jalil Fadavi).
|
8 |
|
|
*
|
9 |
|
|
*
|
10 |
|
|
* This program is free software; you can redistribute it and/or modify
|
11 |
|
|
* it under the terms of the GNU General Public License as published by
|
12 |
|
|
* the Free Software Foundation; either version 2, or (at your option)
|
13 |
|
|
* any later version.
|
14 |
|
|
*
|
15 |
|
|
* This program is distributed in the hope that it will be useful,
|
16 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
17 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
18 |
|
|
* GNU General Public License for more details.
|
19 |
|
|
*
|
20 |
|
|
* You should have received a copy of the GNU General Public License
|
21 |
|
|
* along with this program; see the file COPYING. If not, write to
|
22 |
|
|
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
23 |
|
|
*
|
24 |
|
|
*
|
25 |
|
|
* libata documentation is available via 'make {ps|pdf}docs',
|
26 |
|
|
* as Documentation/DocBook/libata.*
|
27 |
|
|
*
|
28 |
|
|
*/
|
29 |
|
|
|
30 |
|
|
#include <linux/kernel.h>
|
31 |
|
|
#include <linux/module.h>
|
32 |
|
|
#include <linux/pci.h>
|
33 |
|
|
#include <linux/init.h>
|
34 |
|
|
#include <linux/blkdev.h>
|
35 |
|
|
#include <linux/delay.h>
|
36 |
|
|
#include <linux/interrupt.h>
|
37 |
|
|
#include <linux/device.h>
|
38 |
|
|
#include <scsi/scsi_host.h>
|
39 |
|
|
#include <linux/libata.h>
|
40 |
|
|
|
41 |
|
|
#define DRV_NAME "sata_qstor"
|
42 |
|
|
#define DRV_VERSION "0.09"
|
43 |
|
|
|
44 |
|
|
enum {
|
45 |
|
|
QS_MMIO_BAR = 4,
|
46 |
|
|
|
47 |
|
|
QS_PORTS = 4,
|
48 |
|
|
QS_MAX_PRD = LIBATA_MAX_PRD,
|
49 |
|
|
QS_CPB_ORDER = 6,
|
50 |
|
|
QS_CPB_BYTES = (1 << QS_CPB_ORDER),
|
51 |
|
|
QS_PRD_BYTES = QS_MAX_PRD * 16,
|
52 |
|
|
QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
|
53 |
|
|
|
54 |
|
|
/* global register offsets */
|
55 |
|
|
QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
|
56 |
|
|
QS_HID_HPHY = 0x0004, /* host physical interface info */
|
57 |
|
|
QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
|
58 |
|
|
QS_HST_SFF = 0x0100, /* host status fifo offset */
|
59 |
|
|
QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
|
60 |
|
|
|
61 |
|
|
/* global control bits */
|
62 |
|
|
QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
|
63 |
|
|
QS_CNFG3_GSRST = 0x01, /* global chip reset */
|
64 |
|
|
QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
|
65 |
|
|
|
66 |
|
|
/* per-channel register offsets */
|
67 |
|
|
QS_CCF_CPBA = 0x0710, /* chan CPB base address */
|
68 |
|
|
QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
|
69 |
|
|
QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
|
70 |
|
|
QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
|
71 |
|
|
QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
|
72 |
|
|
QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
|
73 |
|
|
QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
|
74 |
|
|
QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
|
75 |
|
|
QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
|
76 |
|
|
|
77 |
|
|
/* channel control bits */
|
78 |
|
|
QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
|
79 |
|
|
QS_CTR0_CLER = (1 << 2), /* clear channel errors */
|
80 |
|
|
QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
|
81 |
|
|
QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
|
82 |
|
|
QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
|
83 |
|
|
|
84 |
|
|
/* pkt sub-field headers */
|
85 |
|
|
QS_HCB_HDR = 0x01, /* Host Control Block header */
|
86 |
|
|
QS_DCB_HDR = 0x02, /* Device Control Block header */
|
87 |
|
|
|
88 |
|
|
/* pkt HCB flag bits */
|
89 |
|
|
QS_HF_DIRO = (1 << 0), /* data DIRection Out */
|
90 |
|
|
QS_HF_DAT = (1 << 3), /* DATa pkt */
|
91 |
|
|
QS_HF_IEN = (1 << 4), /* Interrupt ENable */
|
92 |
|
|
QS_HF_VLD = (1 << 5), /* VaLiD pkt */
|
93 |
|
|
|
94 |
|
|
/* pkt DCB flag bits */
|
95 |
|
|
QS_DF_PORD = (1 << 2), /* Pio OR Dma */
|
96 |
|
|
QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
|
97 |
|
|
|
98 |
|
|
/* PCI device IDs */
|
99 |
|
|
board_2068_idx = 0, /* QStor 4-port SATA/RAID */
|
100 |
|
|
};
|
101 |
|
|
|
102 |
|
|
enum {
|
103 |
|
|
QS_DMA_BOUNDARY = ~0UL
|
104 |
|
|
};
|
105 |
|
|
|
106 |
|
|
typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
|
107 |
|
|
|
108 |
|
|
struct qs_port_priv {
|
109 |
|
|
u8 *pkt;
|
110 |
|
|
dma_addr_t pkt_dma;
|
111 |
|
|
qs_state_t state;
|
112 |
|
|
};
|
113 |
|
|
|
114 |
|
|
static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
115 |
|
|
static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
116 |
|
|
static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
117 |
|
|
static int qs_port_start(struct ata_port *ap);
|
118 |
|
|
static void qs_host_stop(struct ata_host *host);
|
119 |
|
|
static void qs_qc_prep(struct ata_queued_cmd *qc);
|
120 |
|
|
static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
|
121 |
|
|
static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
|
122 |
|
|
static void qs_bmdma_stop(struct ata_queued_cmd *qc);
|
123 |
|
|
static u8 qs_bmdma_status(struct ata_port *ap);
|
124 |
|
|
static void qs_irq_clear(struct ata_port *ap);
|
125 |
|
|
static void qs_freeze(struct ata_port *ap);
|
126 |
|
|
static void qs_thaw(struct ata_port *ap);
|
127 |
|
|
static void qs_error_handler(struct ata_port *ap);
|
128 |
|
|
|
129 |
|
|
static struct scsi_host_template qs_ata_sht = {
|
130 |
|
|
.module = THIS_MODULE,
|
131 |
|
|
.name = DRV_NAME,
|
132 |
|
|
.ioctl = ata_scsi_ioctl,
|
133 |
|
|
.queuecommand = ata_scsi_queuecmd,
|
134 |
|
|
.can_queue = ATA_DEF_QUEUE,
|
135 |
|
|
.this_id = ATA_SHT_THIS_ID,
|
136 |
|
|
.sg_tablesize = QS_MAX_PRD,
|
137 |
|
|
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
138 |
|
|
.emulated = ATA_SHT_EMULATED,
|
139 |
|
|
.use_clustering = ENABLE_CLUSTERING,
|
140 |
|
|
.proc_name = DRV_NAME,
|
141 |
|
|
.dma_boundary = QS_DMA_BOUNDARY,
|
142 |
|
|
.slave_configure = ata_scsi_slave_config,
|
143 |
|
|
.slave_destroy = ata_scsi_slave_destroy,
|
144 |
|
|
.bios_param = ata_std_bios_param,
|
145 |
|
|
};
|
146 |
|
|
|
147 |
|
|
static const struct ata_port_operations qs_ata_ops = {
|
148 |
|
|
.tf_load = ata_tf_load,
|
149 |
|
|
.tf_read = ata_tf_read,
|
150 |
|
|
.check_status = ata_check_status,
|
151 |
|
|
.check_atapi_dma = qs_check_atapi_dma,
|
152 |
|
|
.exec_command = ata_exec_command,
|
153 |
|
|
.dev_select = ata_std_dev_select,
|
154 |
|
|
.qc_prep = qs_qc_prep,
|
155 |
|
|
.qc_issue = qs_qc_issue,
|
156 |
|
|
.data_xfer = ata_data_xfer,
|
157 |
|
|
.freeze = qs_freeze,
|
158 |
|
|
.thaw = qs_thaw,
|
159 |
|
|
.error_handler = qs_error_handler,
|
160 |
|
|
.irq_clear = qs_irq_clear,
|
161 |
|
|
.irq_on = ata_irq_on,
|
162 |
|
|
.scr_read = qs_scr_read,
|
163 |
|
|
.scr_write = qs_scr_write,
|
164 |
|
|
.port_start = qs_port_start,
|
165 |
|
|
.host_stop = qs_host_stop,
|
166 |
|
|
.bmdma_stop = qs_bmdma_stop,
|
167 |
|
|
.bmdma_status = qs_bmdma_status,
|
168 |
|
|
};
|
169 |
|
|
|
170 |
|
|
static const struct ata_port_info qs_port_info[] = {
|
171 |
|
|
/* board_2068_idx */
|
172 |
|
|
{
|
173 |
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
|
174 |
|
|
ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
|
175 |
|
|
.pio_mask = 0x10, /* pio4 */
|
176 |
|
|
.udma_mask = ATA_UDMA6,
|
177 |
|
|
.port_ops = &qs_ata_ops,
|
178 |
|
|
},
|
179 |
|
|
};
|
180 |
|
|
|
181 |
|
|
static const struct pci_device_id qs_ata_pci_tbl[] = {
|
182 |
|
|
{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
|
183 |
|
|
|
184 |
|
|
{ } /* terminate list */
|
185 |
|
|
};
|
186 |
|
|
|
187 |
|
|
static struct pci_driver qs_ata_pci_driver = {
|
188 |
|
|
.name = DRV_NAME,
|
189 |
|
|
.id_table = qs_ata_pci_tbl,
|
190 |
|
|
.probe = qs_ata_init_one,
|
191 |
|
|
.remove = ata_pci_remove_one,
|
192 |
|
|
};
|
193 |
|
|
|
194 |
|
|
static void __iomem *qs_mmio_base(struct ata_host *host)
|
195 |
|
|
{
|
196 |
|
|
return host->iomap[QS_MMIO_BAR];
|
197 |
|
|
}
|
198 |
|
|
|
199 |
|
|
static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
|
200 |
|
|
{
|
201 |
|
|
return 1; /* ATAPI DMA not supported */
|
202 |
|
|
}
|
203 |
|
|
|
204 |
|
|
static void qs_bmdma_stop(struct ata_queued_cmd *qc)
|
205 |
|
|
{
|
206 |
|
|
/* nothing */
|
207 |
|
|
}
|
208 |
|
|
|
209 |
|
|
static u8 qs_bmdma_status(struct ata_port *ap)
|
210 |
|
|
{
|
211 |
|
|
return 0;
|
212 |
|
|
}
|
213 |
|
|
|
214 |
|
|
static void qs_irq_clear(struct ata_port *ap)
|
215 |
|
|
{
|
216 |
|
|
/* nothing */
|
217 |
|
|
}
|
218 |
|
|
|
219 |
|
|
static inline void qs_enter_reg_mode(struct ata_port *ap)
|
220 |
|
|
{
|
221 |
|
|
u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
|
222 |
|
|
struct qs_port_priv *pp = ap->private_data;
|
223 |
|
|
|
224 |
|
|
pp->state = qs_state_mmio;
|
225 |
|
|
writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
|
226 |
|
|
readb(chan + QS_CCT_CTR0); /* flush */
|
227 |
|
|
}
|
228 |
|
|
|
229 |
|
|
static inline void qs_reset_channel_logic(struct ata_port *ap)
|
230 |
|
|
{
|
231 |
|
|
u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
|
232 |
|
|
|
233 |
|
|
writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
|
234 |
|
|
readb(chan + QS_CCT_CTR0); /* flush */
|
235 |
|
|
qs_enter_reg_mode(ap);
|
236 |
|
|
}
|
237 |
|
|
|
238 |
|
|
static void qs_freeze(struct ata_port *ap)
|
239 |
|
|
{
|
240 |
|
|
u8 __iomem *mmio_base = qs_mmio_base(ap->host);
|
241 |
|
|
|
242 |
|
|
writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
|
243 |
|
|
qs_enter_reg_mode(ap);
|
244 |
|
|
}
|
245 |
|
|
|
246 |
|
|
static void qs_thaw(struct ata_port *ap)
|
247 |
|
|
{
|
248 |
|
|
u8 __iomem *mmio_base = qs_mmio_base(ap->host);
|
249 |
|
|
|
250 |
|
|
qs_enter_reg_mode(ap);
|
251 |
|
|
writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
|
252 |
|
|
}
|
253 |
|
|
|
254 |
|
|
static int qs_prereset(struct ata_link *link, unsigned long deadline)
|
255 |
|
|
{
|
256 |
|
|
struct ata_port *ap = link->ap;
|
257 |
|
|
|
258 |
|
|
qs_reset_channel_logic(ap);
|
259 |
|
|
return ata_std_prereset(link, deadline);
|
260 |
|
|
}
|
261 |
|
|
|
262 |
|
|
static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
263 |
|
|
{
|
264 |
|
|
if (sc_reg > SCR_CONTROL)
|
265 |
|
|
return -EINVAL;
|
266 |
|
|
*val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
|
267 |
|
|
return 0;
|
268 |
|
|
}
|
269 |
|
|
|
270 |
|
|
static void qs_error_handler(struct ata_port *ap)
|
271 |
|
|
{
|
272 |
|
|
qs_enter_reg_mode(ap);
|
273 |
|
|
ata_do_eh(ap, qs_prereset, NULL, sata_std_hardreset,
|
274 |
|
|
ata_std_postreset);
|
275 |
|
|
}
|
276 |
|
|
|
277 |
|
|
static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
278 |
|
|
{
|
279 |
|
|
if (sc_reg > SCR_CONTROL)
|
280 |
|
|
return -EINVAL;
|
281 |
|
|
writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
|
282 |
|
|
return 0;
|
283 |
|
|
}
|
284 |
|
|
|
285 |
|
|
static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
|
286 |
|
|
{
|
287 |
|
|
struct scatterlist *sg;
|
288 |
|
|
struct ata_port *ap = qc->ap;
|
289 |
|
|
struct qs_port_priv *pp = ap->private_data;
|
290 |
|
|
unsigned int nelem;
|
291 |
|
|
u8 *prd = pp->pkt + QS_CPB_BYTES;
|
292 |
|
|
|
293 |
|
|
WARN_ON(qc->__sg == NULL);
|
294 |
|
|
WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
|
295 |
|
|
|
296 |
|
|
nelem = 0;
|
297 |
|
|
ata_for_each_sg(sg, qc) {
|
298 |
|
|
u64 addr;
|
299 |
|
|
u32 len;
|
300 |
|
|
|
301 |
|
|
addr = sg_dma_address(sg);
|
302 |
|
|
*(__le64 *)prd = cpu_to_le64(addr);
|
303 |
|
|
prd += sizeof(u64);
|
304 |
|
|
|
305 |
|
|
len = sg_dma_len(sg);
|
306 |
|
|
*(__le32 *)prd = cpu_to_le32(len);
|
307 |
|
|
prd += sizeof(u64);
|
308 |
|
|
|
309 |
|
|
VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
|
310 |
|
|
(unsigned long long)addr, len);
|
311 |
|
|
nelem++;
|
312 |
|
|
}
|
313 |
|
|
|
314 |
|
|
return nelem;
|
315 |
|
|
}
|
316 |
|
|
|
317 |
|
|
static void qs_qc_prep(struct ata_queued_cmd *qc)
|
318 |
|
|
{
|
319 |
|
|
struct qs_port_priv *pp = qc->ap->private_data;
|
320 |
|
|
u8 dflags = QS_DF_PORD, *buf = pp->pkt;
|
321 |
|
|
u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
|
322 |
|
|
u64 addr;
|
323 |
|
|
unsigned int nelem;
|
324 |
|
|
|
325 |
|
|
VPRINTK("ENTER\n");
|
326 |
|
|
|
327 |
|
|
qs_enter_reg_mode(qc->ap);
|
328 |
|
|
if (qc->tf.protocol != ATA_PROT_DMA) {
|
329 |
|
|
ata_qc_prep(qc);
|
330 |
|
|
return;
|
331 |
|
|
}
|
332 |
|
|
|
333 |
|
|
nelem = qs_fill_sg(qc);
|
334 |
|
|
|
335 |
|
|
if ((qc->tf.flags & ATA_TFLAG_WRITE))
|
336 |
|
|
hflags |= QS_HF_DIRO;
|
337 |
|
|
if ((qc->tf.flags & ATA_TFLAG_LBA48))
|
338 |
|
|
dflags |= QS_DF_ELBA;
|
339 |
|
|
|
340 |
|
|
/* host control block (HCB) */
|
341 |
|
|
buf[ 0] = QS_HCB_HDR;
|
342 |
|
|
buf[ 1] = hflags;
|
343 |
|
|
*(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
|
344 |
|
|
*(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
|
345 |
|
|
addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
|
346 |
|
|
*(__le64 *)(&buf[16]) = cpu_to_le64(addr);
|
347 |
|
|
|
348 |
|
|
/* device control block (DCB) */
|
349 |
|
|
buf[24] = QS_DCB_HDR;
|
350 |
|
|
buf[28] = dflags;
|
351 |
|
|
|
352 |
|
|
/* frame information structure (FIS) */
|
353 |
|
|
ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
|
354 |
|
|
}
|
355 |
|
|
|
356 |
|
|
static inline void qs_packet_start(struct ata_queued_cmd *qc)
|
357 |
|
|
{
|
358 |
|
|
struct ata_port *ap = qc->ap;
|
359 |
|
|
u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
|
360 |
|
|
|
361 |
|
|
VPRINTK("ENTER, ap %p\n", ap);
|
362 |
|
|
|
363 |
|
|
writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
|
364 |
|
|
wmb(); /* flush PRDs and pkt to memory */
|
365 |
|
|
writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
|
366 |
|
|
readl(chan + QS_CCT_CFF); /* flush */
|
367 |
|
|
}
|
368 |
|
|
|
369 |
|
|
static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
|
370 |
|
|
{
|
371 |
|
|
struct qs_port_priv *pp = qc->ap->private_data;
|
372 |
|
|
|
373 |
|
|
switch (qc->tf.protocol) {
|
374 |
|
|
case ATA_PROT_DMA:
|
375 |
|
|
pp->state = qs_state_pkt;
|
376 |
|
|
qs_packet_start(qc);
|
377 |
|
|
return 0;
|
378 |
|
|
|
379 |
|
|
case ATA_PROT_ATAPI_DMA:
|
380 |
|
|
BUG();
|
381 |
|
|
break;
|
382 |
|
|
|
383 |
|
|
default:
|
384 |
|
|
break;
|
385 |
|
|
}
|
386 |
|
|
|
387 |
|
|
pp->state = qs_state_mmio;
|
388 |
|
|
return ata_qc_issue_prot(qc);
|
389 |
|
|
}
|
390 |
|
|
|
391 |
|
|
static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
|
392 |
|
|
{
|
393 |
|
|
qc->err_mask |= ac_err_mask(status);
|
394 |
|
|
|
395 |
|
|
if (!qc->err_mask) {
|
396 |
|
|
ata_qc_complete(qc);
|
397 |
|
|
} else {
|
398 |
|
|
struct ata_port *ap = qc->ap;
|
399 |
|
|
struct ata_eh_info *ehi = &ap->link.eh_info;
|
400 |
|
|
|
401 |
|
|
ata_ehi_clear_desc(ehi);
|
402 |
|
|
ata_ehi_push_desc(ehi, "status 0x%02X", status);
|
403 |
|
|
|
404 |
|
|
if (qc->err_mask == AC_ERR_DEV)
|
405 |
|
|
ata_port_abort(ap);
|
406 |
|
|
else
|
407 |
|
|
ata_port_freeze(ap);
|
408 |
|
|
}
|
409 |
|
|
}
|
410 |
|
|
|
411 |
|
|
static inline unsigned int qs_intr_pkt(struct ata_host *host)
|
412 |
|
|
{
|
413 |
|
|
unsigned int handled = 0;
|
414 |
|
|
u8 sFFE;
|
415 |
|
|
u8 __iomem *mmio_base = qs_mmio_base(host);
|
416 |
|
|
|
417 |
|
|
do {
|
418 |
|
|
u32 sff0 = readl(mmio_base + QS_HST_SFF);
|
419 |
|
|
u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
|
420 |
|
|
u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
|
421 |
|
|
sFFE = sff1 >> 31; /* empty flag */
|
422 |
|
|
|
423 |
|
|
if (sEVLD) {
|
424 |
|
|
u8 sDST = sff0 >> 16; /* dev status */
|
425 |
|
|
u8 sHST = sff1 & 0x3f; /* host status */
|
426 |
|
|
unsigned int port_no = (sff1 >> 8) & 0x03;
|
427 |
|
|
struct ata_port *ap = host->ports[port_no];
|
428 |
|
|
|
429 |
|
|
DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
|
430 |
|
|
sff1, sff0, port_no, sHST, sDST);
|
431 |
|
|
handled = 1;
|
432 |
|
|
if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
|
433 |
|
|
struct ata_queued_cmd *qc;
|
434 |
|
|
struct qs_port_priv *pp = ap->private_data;
|
435 |
|
|
if (!pp || pp->state != qs_state_pkt)
|
436 |
|
|
continue;
|
437 |
|
|
qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
438 |
|
|
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
|
439 |
|
|
switch (sHST) {
|
440 |
|
|
case 0: /* successful CPB */
|
441 |
|
|
case 3: /* device error */
|
442 |
|
|
qs_enter_reg_mode(qc->ap);
|
443 |
|
|
qs_do_or_die(qc, sDST);
|
444 |
|
|
break;
|
445 |
|
|
default:
|
446 |
|
|
break;
|
447 |
|
|
}
|
448 |
|
|
}
|
449 |
|
|
}
|
450 |
|
|
}
|
451 |
|
|
} while (!sFFE);
|
452 |
|
|
return handled;
|
453 |
|
|
}
|
454 |
|
|
|
455 |
|
|
static inline unsigned int qs_intr_mmio(struct ata_host *host)
|
456 |
|
|
{
|
457 |
|
|
unsigned int handled = 0, port_no;
|
458 |
|
|
|
459 |
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
460 |
|
|
struct ata_port *ap;
|
461 |
|
|
ap = host->ports[port_no];
|
462 |
|
|
if (ap &&
|
463 |
|
|
!(ap->flags & ATA_FLAG_DISABLED)) {
|
464 |
|
|
struct ata_queued_cmd *qc;
|
465 |
|
|
struct qs_port_priv *pp;
|
466 |
|
|
qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
467 |
|
|
if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
|
468 |
|
|
/*
|
469 |
|
|
* The qstor hardware generates spurious
|
470 |
|
|
* interrupts from time to time when switching
|
471 |
|
|
* in and out of packet mode.
|
472 |
|
|
* There's no obvious way to know if we're
|
473 |
|
|
* here now due to that, so just ack the irq
|
474 |
|
|
* and pretend we knew it was ours.. (ugh).
|
475 |
|
|
* This does not affect packet mode.
|
476 |
|
|
*/
|
477 |
|
|
ata_check_status(ap);
|
478 |
|
|
handled = 1;
|
479 |
|
|
continue;
|
480 |
|
|
}
|
481 |
|
|
pp = ap->private_data;
|
482 |
|
|
if (!pp || pp->state != qs_state_mmio)
|
483 |
|
|
continue;
|
484 |
|
|
if (!(qc->tf.flags & ATA_TFLAG_POLLING))
|
485 |
|
|
handled |= ata_host_intr(ap, qc);
|
486 |
|
|
}
|
487 |
|
|
}
|
488 |
|
|
return handled;
|
489 |
|
|
}
|
490 |
|
|
|
491 |
|
|
static irqreturn_t qs_intr(int irq, void *dev_instance)
|
492 |
|
|
{
|
493 |
|
|
struct ata_host *host = dev_instance;
|
494 |
|
|
unsigned int handled = 0;
|
495 |
|
|
unsigned long flags;
|
496 |
|
|
|
497 |
|
|
VPRINTK("ENTER\n");
|
498 |
|
|
|
499 |
|
|
spin_lock_irqsave(&host->lock, flags);
|
500 |
|
|
handled = qs_intr_pkt(host) | qs_intr_mmio(host);
|
501 |
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
502 |
|
|
|
503 |
|
|
VPRINTK("EXIT\n");
|
504 |
|
|
|
505 |
|
|
return IRQ_RETVAL(handled);
|
506 |
|
|
}
|
507 |
|
|
|
508 |
|
|
static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
|
509 |
|
|
{
|
510 |
|
|
port->cmd_addr =
|
511 |
|
|
port->data_addr = base + 0x400;
|
512 |
|
|
port->error_addr =
|
513 |
|
|
port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
|
514 |
|
|
port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
|
515 |
|
|
port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
|
516 |
|
|
port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
|
517 |
|
|
port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
|
518 |
|
|
port->device_addr = base + 0x430;
|
519 |
|
|
port->status_addr =
|
520 |
|
|
port->command_addr = base + 0x438;
|
521 |
|
|
port->altstatus_addr =
|
522 |
|
|
port->ctl_addr = base + 0x440;
|
523 |
|
|
port->scr_addr = base + 0xc00;
|
524 |
|
|
}
|
525 |
|
|
|
526 |
|
|
static int qs_port_start(struct ata_port *ap)
|
527 |
|
|
{
|
528 |
|
|
struct device *dev = ap->host->dev;
|
529 |
|
|
struct qs_port_priv *pp;
|
530 |
|
|
void __iomem *mmio_base = qs_mmio_base(ap->host);
|
531 |
|
|
void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
|
532 |
|
|
u64 addr;
|
533 |
|
|
int rc;
|
534 |
|
|
|
535 |
|
|
rc = ata_port_start(ap);
|
536 |
|
|
if (rc)
|
537 |
|
|
return rc;
|
538 |
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
539 |
|
|
if (!pp)
|
540 |
|
|
return -ENOMEM;
|
541 |
|
|
pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
|
542 |
|
|
GFP_KERNEL);
|
543 |
|
|
if (!pp->pkt)
|
544 |
|
|
return -ENOMEM;
|
545 |
|
|
memset(pp->pkt, 0, QS_PKT_BYTES);
|
546 |
|
|
ap->private_data = pp;
|
547 |
|
|
|
548 |
|
|
qs_enter_reg_mode(ap);
|
549 |
|
|
addr = (u64)pp->pkt_dma;
|
550 |
|
|
writel((u32) addr, chan + QS_CCF_CPBA);
|
551 |
|
|
writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
|
552 |
|
|
return 0;
|
553 |
|
|
}
|
554 |
|
|
|
555 |
|
|
static void qs_host_stop(struct ata_host *host)
|
556 |
|
|
{
|
557 |
|
|
void __iomem *mmio_base = qs_mmio_base(host);
|
558 |
|
|
|
559 |
|
|
writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
|
560 |
|
|
writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
|
561 |
|
|
}
|
562 |
|
|
|
563 |
|
|
static void qs_host_init(struct ata_host *host, unsigned int chip_id)
|
564 |
|
|
{
|
565 |
|
|
void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
|
566 |
|
|
unsigned int port_no;
|
567 |
|
|
|
568 |
|
|
writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
|
569 |
|
|
writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
|
570 |
|
|
|
571 |
|
|
/* reset each channel in turn */
|
572 |
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
573 |
|
|
u8 __iomem *chan = mmio_base + (port_no * 0x4000);
|
574 |
|
|
writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
|
575 |
|
|
writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
|
576 |
|
|
readb(chan + QS_CCT_CTR0); /* flush */
|
577 |
|
|
}
|
578 |
|
|
writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
|
579 |
|
|
|
580 |
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
581 |
|
|
u8 __iomem *chan = mmio_base + (port_no * 0x4000);
|
582 |
|
|
/* set FIFO depths to same settings as Windows driver */
|
583 |
|
|
writew(32, chan + QS_CFC_HUFT);
|
584 |
|
|
writew(32, chan + QS_CFC_HDFT);
|
585 |
|
|
writew(10, chan + QS_CFC_DUFT);
|
586 |
|
|
writew( 8, chan + QS_CFC_DDFT);
|
587 |
|
|
/* set CPB size in bytes, as a power of two */
|
588 |
|
|
writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
|
589 |
|
|
}
|
590 |
|
|
writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
|
591 |
|
|
}
|
592 |
|
|
|
593 |
|
|
/*
|
594 |
|
|
* The QStor understands 64-bit buses, and uses 64-bit fields
|
595 |
|
|
* for DMA pointers regardless of bus width. We just have to
|
596 |
|
|
* make sure our DMA masks are set appropriately for whatever
|
597 |
|
|
* bridge lies between us and the QStor, and then the DMA mapping
|
598 |
|
|
* code will ensure we only ever "see" appropriate buffer addresses.
|
599 |
|
|
* If we're 32-bit limited somewhere, then our 64-bit fields will
|
600 |
|
|
* just end up with zeros in the upper 32-bits, without any special
|
601 |
|
|
* logic required outside of this routine (below).
|
602 |
|
|
*/
|
603 |
|
|
static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
|
604 |
|
|
{
|
605 |
|
|
u32 bus_info = readl(mmio_base + QS_HID_HPHY);
|
606 |
|
|
int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
|
607 |
|
|
|
608 |
|
|
if (have_64bit_bus &&
|
609 |
|
|
!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
|
610 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
|
611 |
|
|
if (rc) {
|
612 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
613 |
|
|
if (rc) {
|
614 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
615 |
|
|
"64-bit DMA enable failed\n");
|
616 |
|
|
return rc;
|
617 |
|
|
}
|
618 |
|
|
}
|
619 |
|
|
} else {
|
620 |
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
621 |
|
|
if (rc) {
|
622 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
623 |
|
|
"32-bit DMA enable failed\n");
|
624 |
|
|
return rc;
|
625 |
|
|
}
|
626 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
627 |
|
|
if (rc) {
|
628 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
629 |
|
|
"32-bit consistent DMA enable failed\n");
|
630 |
|
|
return rc;
|
631 |
|
|
}
|
632 |
|
|
}
|
633 |
|
|
return 0;
|
634 |
|
|
}
|
635 |
|
|
|
636 |
|
|
static int qs_ata_init_one(struct pci_dev *pdev,
|
637 |
|
|
const struct pci_device_id *ent)
|
638 |
|
|
{
|
639 |
|
|
static int printed_version;
|
640 |
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
641 |
|
|
const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
|
642 |
|
|
struct ata_host *host;
|
643 |
|
|
int rc, port_no;
|
644 |
|
|
|
645 |
|
|
if (!printed_version++)
|
646 |
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
647 |
|
|
|
648 |
|
|
/* alloc host */
|
649 |
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
|
650 |
|
|
if (!host)
|
651 |
|
|
return -ENOMEM;
|
652 |
|
|
|
653 |
|
|
/* acquire resources and fill host */
|
654 |
|
|
rc = pcim_enable_device(pdev);
|
655 |
|
|
if (rc)
|
656 |
|
|
return rc;
|
657 |
|
|
|
658 |
|
|
if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
|
659 |
|
|
return -ENODEV;
|
660 |
|
|
|
661 |
|
|
rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
|
662 |
|
|
if (rc)
|
663 |
|
|
return rc;
|
664 |
|
|
host->iomap = pcim_iomap_table(pdev);
|
665 |
|
|
|
666 |
|
|
rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
|
667 |
|
|
if (rc)
|
668 |
|
|
return rc;
|
669 |
|
|
|
670 |
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
671 |
|
|
struct ata_port *ap = host->ports[port_no];
|
672 |
|
|
unsigned int offset = port_no * 0x4000;
|
673 |
|
|
void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
|
674 |
|
|
|
675 |
|
|
qs_ata_setup_port(&ap->ioaddr, chan);
|
676 |
|
|
|
677 |
|
|
ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
|
678 |
|
|
ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
|
679 |
|
|
}
|
680 |
|
|
|
681 |
|
|
/* initialize adapter */
|
682 |
|
|
qs_host_init(host, board_idx);
|
683 |
|
|
|
684 |
|
|
pci_set_master(pdev);
|
685 |
|
|
return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
|
686 |
|
|
&qs_ata_sht);
|
687 |
|
|
}
|
688 |
|
|
|
689 |
|
|
static int __init qs_ata_init(void)
|
690 |
|
|
{
|
691 |
|
|
return pci_register_driver(&qs_ata_pci_driver);
|
692 |
|
|
}
|
693 |
|
|
|
694 |
|
|
static void __exit qs_ata_exit(void)
|
695 |
|
|
{
|
696 |
|
|
pci_unregister_driver(&qs_ata_pci_driver);
|
697 |
|
|
}
|
698 |
|
|
|
699 |
|
|
MODULE_AUTHOR("Mark Lord");
|
700 |
|
|
MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
|
701 |
|
|
MODULE_LICENSE("GPL");
|
702 |
|
|
MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
|
703 |
|
|
MODULE_VERSION(DRV_VERSION);
|
704 |
|
|
|
705 |
|
|
module_init(qs_ata_init);
|
706 |
|
|
module_exit(qs_ata_exit);
|