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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [ata/] [sata_svw.c] - Blame information for rev 65

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1 62 marcus.erl
/*
2
 *  sata_svw.c - ServerWorks / Apple K2 SATA
3
 *
4
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5
 *                 Jeff Garzik <jgarzik@pobox.com>
6
 *                  Please ALWAYS copy linux-ide@vger.kernel.org
7
 *                  on emails.
8
 *
9
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
10
 *
11
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
12
 *
13
 *  This driver probably works with non-Apple versions of the
14
 *  Broadcom chipset...
15
 *
16
 *
17
 *  This program is free software; you can redistribute it and/or modify
18
 *  it under the terms of the GNU General Public License as published by
19
 *  the Free Software Foundation; either version 2, or (at your option)
20
 *  any later version.
21
 *
22
 *  This program is distributed in the hope that it will be useful,
23
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
24
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25
 *  GNU General Public License for more details.
26
 *
27
 *  You should have received a copy of the GNU General Public License
28
 *  along with this program; see the file COPYING.  If not, write to
29
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
30
 *
31
 *
32
 *  libata documentation is available via 'make {ps|pdf}docs',
33
 *  as Documentation/DocBook/libata.*
34
 *
35
 *  Hardware documentation available under NDA.
36
 *
37
 */
38
 
39
#include <linux/kernel.h>
40
#include <linux/module.h>
41
#include <linux/pci.h>
42
#include <linux/init.h>
43
#include <linux/blkdev.h>
44
#include <linux/delay.h>
45
#include <linux/interrupt.h>
46
#include <linux/device.h>
47
#include <scsi/scsi_host.h>
48
#include <linux/libata.h>
49
 
50
#ifdef CONFIG_PPC_OF
51
#include <asm/prom.h>
52
#include <asm/pci-bridge.h>
53
#endif /* CONFIG_PPC_OF */
54
 
55
#define DRV_NAME        "sata_svw"
56
#define DRV_VERSION     "2.3"
57
 
58
enum {
59
        /* ap->flags bits */
60
        K2_FLAG_SATA_8_PORTS            = (1 << 24),
61
        K2_FLAG_NO_ATAPI_DMA            = (1 << 25),
62
 
63
        /* Taskfile registers offsets */
64
        K2_SATA_TF_CMD_OFFSET           = 0x00,
65
        K2_SATA_TF_DATA_OFFSET          = 0x00,
66
        K2_SATA_TF_ERROR_OFFSET         = 0x04,
67
        K2_SATA_TF_NSECT_OFFSET         = 0x08,
68
        K2_SATA_TF_LBAL_OFFSET          = 0x0c,
69
        K2_SATA_TF_LBAM_OFFSET          = 0x10,
70
        K2_SATA_TF_LBAH_OFFSET          = 0x14,
71
        K2_SATA_TF_DEVICE_OFFSET        = 0x18,
72
        K2_SATA_TF_CMDSTAT_OFFSET       = 0x1c,
73
        K2_SATA_TF_CTL_OFFSET           = 0x20,
74
 
75
        /* DMA base */
76
        K2_SATA_DMA_CMD_OFFSET          = 0x30,
77
 
78
        /* SCRs base */
79
        K2_SATA_SCR_STATUS_OFFSET       = 0x40,
80
        K2_SATA_SCR_ERROR_OFFSET        = 0x44,
81
        K2_SATA_SCR_CONTROL_OFFSET      = 0x48,
82
 
83
        /* Others */
84
        K2_SATA_SICR1_OFFSET            = 0x80,
85
        K2_SATA_SICR2_OFFSET            = 0x84,
86
        K2_SATA_SIM_OFFSET              = 0x88,
87
 
88
        /* Port stride */
89
        K2_SATA_PORT_OFFSET             = 0x100,
90
 
91
        board_svw4                      = 0,
92
        board_svw8                      = 1,
93
};
94
 
95
static u8 k2_stat_check_status(struct ata_port *ap);
96
 
97
 
98
static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
99
{
100
        if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
101
                return -1;      /* ATAPI DMA not supported */
102
 
103
        return 0;
104
}
105
 
106
static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
107
{
108
        if (sc_reg > SCR_CONTROL)
109
                return -EINVAL;
110
        *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
111
        return 0;
112
}
113
 
114
 
115
static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
116
{
117
        if (sc_reg > SCR_CONTROL)
118
                return -EINVAL;
119
        writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
120
        return 0;
121
}
122
 
123
 
124
static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
125
{
126
        struct ata_ioports *ioaddr = &ap->ioaddr;
127
        unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
128
 
129
        if (tf->ctl != ap->last_ctl) {
130
                writeb(tf->ctl, ioaddr->ctl_addr);
131
                ap->last_ctl = tf->ctl;
132
                ata_wait_idle(ap);
133
        }
134
        if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
135
                writew(tf->feature | (((u16)tf->hob_feature) << 8),
136
                       ioaddr->feature_addr);
137
                writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
138
                       ioaddr->nsect_addr);
139
                writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
140
                       ioaddr->lbal_addr);
141
                writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
142
                       ioaddr->lbam_addr);
143
                writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
144
                       ioaddr->lbah_addr);
145
        } else if (is_addr) {
146
                writew(tf->feature, ioaddr->feature_addr);
147
                writew(tf->nsect, ioaddr->nsect_addr);
148
                writew(tf->lbal, ioaddr->lbal_addr);
149
                writew(tf->lbam, ioaddr->lbam_addr);
150
                writew(tf->lbah, ioaddr->lbah_addr);
151
        }
152
 
153
        if (tf->flags & ATA_TFLAG_DEVICE)
154
                writeb(tf->device, ioaddr->device_addr);
155
 
156
        ata_wait_idle(ap);
157
}
158
 
159
 
160
static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
161
{
162
        struct ata_ioports *ioaddr = &ap->ioaddr;
163
        u16 nsect, lbal, lbam, lbah, feature;
164
 
165
        tf->command = k2_stat_check_status(ap);
166
        tf->device = readw(ioaddr->device_addr);
167
        feature = readw(ioaddr->error_addr);
168
        nsect = readw(ioaddr->nsect_addr);
169
        lbal = readw(ioaddr->lbal_addr);
170
        lbam = readw(ioaddr->lbam_addr);
171
        lbah = readw(ioaddr->lbah_addr);
172
 
173
        tf->feature = feature;
174
        tf->nsect = nsect;
175
        tf->lbal = lbal;
176
        tf->lbam = lbam;
177
        tf->lbah = lbah;
178
 
179
        if (tf->flags & ATA_TFLAG_LBA48) {
180
                tf->hob_feature = feature >> 8;
181
                tf->hob_nsect = nsect >> 8;
182
                tf->hob_lbal = lbal >> 8;
183
                tf->hob_lbam = lbam >> 8;
184
                tf->hob_lbah = lbah >> 8;
185
        }
186
}
187
 
188
/**
189
 *      k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
190
 *      @qc: Info associated with this ATA transaction.
191
 *
192
 *      LOCKING:
193
 *      spin_lock_irqsave(host lock)
194
 */
195
 
196
static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
197
{
198
        struct ata_port *ap = qc->ap;
199
        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
200
        u8 dmactl;
201
        void __iomem *mmio = ap->ioaddr.bmdma_addr;
202
 
203
        /* load PRD table addr. */
204
        mb();   /* make sure PRD table writes are visible to controller */
205
        writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
206
 
207
        /* specify data direction, triple-check start bit is clear */
208
        dmactl = readb(mmio + ATA_DMA_CMD);
209
        dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
210
        if (!rw)
211
                dmactl |= ATA_DMA_WR;
212
        writeb(dmactl, mmio + ATA_DMA_CMD);
213
 
214
        /* issue r/w command if this is not a ATA DMA command*/
215
        if (qc->tf.protocol != ATA_PROT_DMA)
216
                ap->ops->exec_command(ap, &qc->tf);
217
}
218
 
219
/**
220
 *      k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
221
 *      @qc: Info associated with this ATA transaction.
222
 *
223
 *      LOCKING:
224
 *      spin_lock_irqsave(host lock)
225
 */
226
 
227
static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
228
{
229
        struct ata_port *ap = qc->ap;
230
        void __iomem *mmio = ap->ioaddr.bmdma_addr;
231
        u8 dmactl;
232
 
233
        /* start host DMA transaction */
234
        dmactl = readb(mmio + ATA_DMA_CMD);
235
        writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
236
        /* There is a race condition in certain SATA controllers that can
237
           be seen when the r/w command is given to the controller before the
238
           host DMA is started. On a Read command, the controller would initiate
239
           the command to the drive even before it sees the DMA start. When there
240
           are very fast drives connected to the controller, or when the data request
241
           hits in the drive cache, there is the possibility that the drive returns a part
242
           or all of the requested data to the controller before the DMA start is issued.
243
           In this case, the controller would become confused as to what to do with the data.
244
           In the worst case when all the data is returned back to the controller, the
245
           controller could hang. In other cases it could return partial data returning
246
           in data corruption. This problem has been seen in PPC systems and can also appear
247
           on an system with very fast disks, where the SATA controller is sitting behind a
248
           number of bridges, and hence there is significant latency between the r/w command
249
           and the start command. */
250
        /* issue r/w command if the access is to ATA*/
251
        if (qc->tf.protocol == ATA_PROT_DMA)
252
                ap->ops->exec_command(ap, &qc->tf);
253
}
254
 
255
 
256
static u8 k2_stat_check_status(struct ata_port *ap)
257
{
258
        return readl(ap->ioaddr.status_addr);
259
}
260
 
261
#ifdef CONFIG_PPC_OF
262
/*
263
 * k2_sata_proc_info
264
 * inout : decides on the direction of the dataflow and the meaning of the
265
 *         variables
266
 * buffer: If inout==FALSE data is being written to it else read from it
267
 * *start: If inout==FALSE start of the valid data in the buffer
268
 * offset: If inout==FALSE offset from the beginning of the imaginary file
269
 *         from which we start writing into the buffer
270
 * length: If inout==FALSE max number of bytes to be written into the buffer
271
 *         else number of bytes in the buffer
272
 */
273
static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
274
                             off_t offset, int count, int inout)
275
{
276
        struct ata_port *ap;
277
        struct device_node *np;
278
        int len, index;
279
 
280
        /* Find  the ata_port */
281
        ap = ata_shost_to_port(shost);
282
        if (ap == NULL)
283
                return 0;
284
 
285
        /* Find the OF node for the PCI device proper */
286
        np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
287
        if (np == NULL)
288
                return 0;
289
 
290
        /* Match it to a port node */
291
        index = (ap == ap->host->ports[0]) ? 0 : 1;
292
        for (np = np->child; np != NULL; np = np->sibling) {
293
                const u32 *reg = of_get_property(np, "reg", NULL);
294
                if (!reg)
295
                        continue;
296
                if (index == *reg)
297
                        break;
298
        }
299
        if (np == NULL)
300
                return 0;
301
 
302
        len = sprintf(page, "devspec: %s\n", np->full_name);
303
 
304
        return len;
305
}
306
#endif /* CONFIG_PPC_OF */
307
 
308
 
309
static struct scsi_host_template k2_sata_sht = {
310
        .module                 = THIS_MODULE,
311
        .name                   = DRV_NAME,
312
        .ioctl                  = ata_scsi_ioctl,
313
        .queuecommand           = ata_scsi_queuecmd,
314
        .can_queue              = ATA_DEF_QUEUE,
315
        .this_id                = ATA_SHT_THIS_ID,
316
        .sg_tablesize           = LIBATA_MAX_PRD,
317
        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
318
        .emulated               = ATA_SHT_EMULATED,
319
        .use_clustering         = ATA_SHT_USE_CLUSTERING,
320
        .proc_name              = DRV_NAME,
321
        .dma_boundary           = ATA_DMA_BOUNDARY,
322
        .slave_configure        = ata_scsi_slave_config,
323
        .slave_destroy          = ata_scsi_slave_destroy,
324
#ifdef CONFIG_PPC_OF
325
        .proc_info              = k2_sata_proc_info,
326
#endif
327
        .bios_param             = ata_std_bios_param,
328
};
329
 
330
 
331
static const struct ata_port_operations k2_sata_ops = {
332
        .tf_load                = k2_sata_tf_load,
333
        .tf_read                = k2_sata_tf_read,
334
        .check_status           = k2_stat_check_status,
335
        .exec_command           = ata_exec_command,
336
        .dev_select             = ata_std_dev_select,
337
        .check_atapi_dma        = k2_sata_check_atapi_dma,
338
        .bmdma_setup            = k2_bmdma_setup_mmio,
339
        .bmdma_start            = k2_bmdma_start_mmio,
340
        .bmdma_stop             = ata_bmdma_stop,
341
        .bmdma_status           = ata_bmdma_status,
342
        .qc_prep                = ata_qc_prep,
343
        .qc_issue               = ata_qc_issue_prot,
344
        .data_xfer              = ata_data_xfer,
345
        .freeze                 = ata_bmdma_freeze,
346
        .thaw                   = ata_bmdma_thaw,
347
        .error_handler          = ata_bmdma_error_handler,
348
        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
349
        .irq_clear              = ata_bmdma_irq_clear,
350
        .irq_on                 = ata_irq_on,
351
        .scr_read               = k2_sata_scr_read,
352
        .scr_write              = k2_sata_scr_write,
353
        .port_start             = ata_port_start,
354
};
355
 
356
static const struct ata_port_info k2_port_info[] = {
357
        /* board_svw4 */
358
        {
359
                .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
360
                                  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
361
                .pio_mask       = 0x1f,
362
                .mwdma_mask     = 0x07,
363
                .udma_mask      = ATA_UDMA6,
364
                .port_ops       = &k2_sata_ops,
365
        },
366
        /* board_svw8 */
367
        {
368
                .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
369
                                  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
370
                                  K2_FLAG_SATA_8_PORTS,
371
                .pio_mask       = 0x1f,
372
                .mwdma_mask     = 0x07,
373
                .udma_mask      = ATA_UDMA6,
374
                .port_ops       = &k2_sata_ops,
375
        },
376
};
377
 
378
static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
379
{
380
        port->cmd_addr          = base + K2_SATA_TF_CMD_OFFSET;
381
        port->data_addr         = base + K2_SATA_TF_DATA_OFFSET;
382
        port->feature_addr      =
383
        port->error_addr        = base + K2_SATA_TF_ERROR_OFFSET;
384
        port->nsect_addr        = base + K2_SATA_TF_NSECT_OFFSET;
385
        port->lbal_addr         = base + K2_SATA_TF_LBAL_OFFSET;
386
        port->lbam_addr         = base + K2_SATA_TF_LBAM_OFFSET;
387
        port->lbah_addr         = base + K2_SATA_TF_LBAH_OFFSET;
388
        port->device_addr       = base + K2_SATA_TF_DEVICE_OFFSET;
389
        port->command_addr      =
390
        port->status_addr       = base + K2_SATA_TF_CMDSTAT_OFFSET;
391
        port->altstatus_addr    =
392
        port->ctl_addr          = base + K2_SATA_TF_CTL_OFFSET;
393
        port->bmdma_addr        = base + K2_SATA_DMA_CMD_OFFSET;
394
        port->scr_addr          = base + K2_SATA_SCR_STATUS_OFFSET;
395
}
396
 
397
 
398
static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
399
{
400
        static int printed_version;
401
        const struct ata_port_info *ppi[] =
402
                { &k2_port_info[ent->driver_data], NULL };
403
        struct ata_host *host;
404
        void __iomem *mmio_base;
405
        int n_ports, i, rc;
406
 
407
        if (!printed_version++)
408
                dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
409
 
410
        /* allocate host */
411
        n_ports = 4;
412
        if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
413
                n_ports = 8;
414
 
415
        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
416
        if (!host)
417
                return -ENOMEM;
418
 
419
        /*
420
         * If this driver happens to only be useful on Apple's K2, then
421
         * we should check that here as it has a normal Serverworks ID
422
         */
423
        rc = pcim_enable_device(pdev);
424
        if (rc)
425
                return rc;
426
 
427
        /*
428
         * Check if we have resources mapped at all (second function may
429
         * have been disabled by firmware)
430
         */
431
        if (pci_resource_len(pdev, 5) == 0)
432
                return -ENODEV;
433
 
434
        /* Request and iomap PCI regions */
435
        rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
436
        if (rc == -EBUSY)
437
                pcim_pin_device(pdev);
438
        if (rc)
439
                return rc;
440
        host->iomap = pcim_iomap_table(pdev);
441
        mmio_base = host->iomap[5];
442
 
443
        /* different controllers have different number of ports - currently 4 or 8 */
444
        /* All ports are on the same function. Multi-function device is no
445
         * longer available. This should not be seen in any system. */
446
        for (i = 0; i < host->n_ports; i++) {
447
                struct ata_port *ap = host->ports[i];
448
                unsigned int offset = i * K2_SATA_PORT_OFFSET;
449
 
450
                k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
451
 
452
                ata_port_pbar_desc(ap, 5, -1, "mmio");
453
                ata_port_pbar_desc(ap, 5, offset, "port");
454
        }
455
 
456
        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
457
        if (rc)
458
                return rc;
459
        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
460
        if (rc)
461
                return rc;
462
 
463
        /* Clear a magic bit in SCR1 according to Darwin, those help
464
         * some funky seagate drives (though so far, those were already
465
         * set by the firmware on the machines I had access to)
466
         */
467
        writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
468
               mmio_base + K2_SATA_SICR1_OFFSET);
469
 
470
        /* Clear SATA error & interrupts we don't use */
471
        writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
472
        writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
473
 
474
        pci_set_master(pdev);
475
        return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
476
                                 &k2_sata_sht);
477
}
478
 
479
/* 0x240 is device ID for Apple K2 device
480
 * 0x241 is device ID for Serverworks Frodo4
481
 * 0x242 is device ID for Serverworks Frodo8
482
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
483
 * controller
484
 * */
485
static const struct pci_device_id k2_sata_pci_tbl[] = {
486
        { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 },
487
        { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 },
488
        { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 },
489
        { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 },
490
        { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 },
491
 
492
        { }
493
};
494
 
495
static struct pci_driver k2_sata_pci_driver = {
496
        .name                   = DRV_NAME,
497
        .id_table               = k2_sata_pci_tbl,
498
        .probe                  = k2_sata_init_one,
499
        .remove                 = ata_pci_remove_one,
500
};
501
 
502
static int __init k2_sata_init(void)
503
{
504
        return pci_register_driver(&k2_sata_pci_driver);
505
}
506
 
507
static void __exit k2_sata_exit(void)
508
{
509
        pci_unregister_driver(&k2_sata_pci_driver);
510
}
511
 
512
MODULE_AUTHOR("Benjamin Herrenschmidt");
513
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
514
MODULE_LICENSE("GPL");
515
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
516
MODULE_VERSION(DRV_VERSION);
517
 
518
module_init(k2_sata_init);
519
module_exit(k2_sata_exit);

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