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marcus.erl |
/*
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* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
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*
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* Maintained by: Jeremy Higdon @ SGI
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004 SGI
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*
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* Bits from Jeff Garzik, Copyright RedHat, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Vitesse hardware documentation presumably available under NDA.
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* Intel 31244 (same hardware interface) documentation presumably
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* available from http://developer.intel.com/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_vsc"
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#define DRV_VERSION "2.3"
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enum {
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VSC_MMIO_BAR = 0,
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55 |
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/* Interrupt register offsets (from chip base address) */
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VSC_SATA_INT_STAT_OFFSET = 0x00,
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VSC_SATA_INT_MASK_OFFSET = 0x04,
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58 |
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59 |
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/* Taskfile registers offsets */
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VSC_SATA_TF_CMD_OFFSET = 0x00,
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VSC_SATA_TF_DATA_OFFSET = 0x00,
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VSC_SATA_TF_ERROR_OFFSET = 0x04,
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VSC_SATA_TF_FEATURE_OFFSET = 0x06,
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VSC_SATA_TF_NSECT_OFFSET = 0x08,
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VSC_SATA_TF_LBAL_OFFSET = 0x0c,
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VSC_SATA_TF_LBAM_OFFSET = 0x10,
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VSC_SATA_TF_LBAH_OFFSET = 0x14,
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VSC_SATA_TF_DEVICE_OFFSET = 0x18,
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VSC_SATA_TF_STATUS_OFFSET = 0x1c,
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70 |
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VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
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VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
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VSC_SATA_TF_CTL_OFFSET = 0x29,
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/* DMA base */
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VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
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VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
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VSC_SATA_DMA_CMD_OFFSET = 0x70,
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/* SCRs base */
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VSC_SATA_SCR_STATUS_OFFSET = 0x100,
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VSC_SATA_SCR_ERROR_OFFSET = 0x104,
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VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
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/* Port stride */
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VSC_SATA_PORT_OFFSET = 0x200,
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/* Error interrupt status bit offsets */
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VSC_SATA_INT_ERROR_CRC = 0x40,
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VSC_SATA_INT_ERROR_T = 0x20,
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VSC_SATA_INT_ERROR_P = 0x10,
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VSC_SATA_INT_ERROR_R = 0x8,
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VSC_SATA_INT_ERROR_E = 0x4,
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VSC_SATA_INT_ERROR_M = 0x2,
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VSC_SATA_INT_PHY_CHANGE = 0x1,
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VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
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VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
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VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
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VSC_SATA_INT_PHY_CHANGE),
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};
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static int vsc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
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return 0;
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}
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static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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return 0;
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}
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static void vsc_freeze(struct ata_port *ap)
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{
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void __iomem *mask_addr;
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
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VSC_SATA_INT_MASK_OFFSET + ap->port_no;
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writeb(0, mask_addr);
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}
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static void vsc_thaw(struct ata_port *ap)
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{
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void __iomem *mask_addr;
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
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VSC_SATA_INT_MASK_OFFSET + ap->port_no;
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writeb(0xff, mask_addr);
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}
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static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
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{
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void __iomem *mask_addr;
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u8 mask;
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
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VSC_SATA_INT_MASK_OFFSET + ap->port_no;
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mask = readb(mask_addr);
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if (ctl & ATA_NIEN)
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mask |= 0x80;
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else
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mask &= 0x7F;
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writeb(mask, mask_addr);
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}
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static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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/*
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* The only thing the ctl register is used for is SRST.
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* That is not enabled or disabled via tf_load.
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* However, if ATA_NIEN is changed, then we need to change
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* the interrupt register.
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*/
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if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
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ap->last_ctl = tf->ctl;
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vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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writew(tf->feature | (((u16)tf->hob_feature) << 8),
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ioaddr->feature_addr);
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writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
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ioaddr->nsect_addr);
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writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
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ioaddr->lbal_addr);
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writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
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ioaddr->lbam_addr);
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writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
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ioaddr->lbah_addr);
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} else if (is_addr) {
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writew(tf->feature, ioaddr->feature_addr);
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writew(tf->nsect, ioaddr->nsect_addr);
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writew(tf->lbal, ioaddr->lbal_addr);
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writew(tf->lbam, ioaddr->lbam_addr);
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writew(tf->lbah, ioaddr->lbah_addr);
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}
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if (tf->flags & ATA_TFLAG_DEVICE)
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writeb(tf->device, ioaddr->device_addr);
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ata_wait_idle(ap);
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}
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198 |
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static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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u16 nsect, lbal, lbam, lbah, feature;
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tf->command = ata_check_status(ap);
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tf->device = readw(ioaddr->device_addr);
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feature = readw(ioaddr->error_addr);
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nsect = readw(ioaddr->nsect_addr);
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lbal = readw(ioaddr->lbal_addr);
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lbam = readw(ioaddr->lbam_addr);
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lbah = readw(ioaddr->lbah_addr);
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tf->feature = feature;
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tf->nsect = nsect;
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tf->lbal = lbal;
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tf->lbam = lbam;
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tf->lbah = lbah;
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if (tf->flags & ATA_TFLAG_LBA48) {
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218 |
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tf->hob_feature = feature >> 8;
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tf->hob_nsect = nsect >> 8;
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tf->hob_lbal = lbal >> 8;
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tf->hob_lbam = lbam >> 8;
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tf->hob_lbah = lbah >> 8;
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}
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}
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226 |
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static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
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{
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if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
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ata_port_freeze(ap);
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else
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ata_port_abort(ap);
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232 |
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}
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233 |
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234 |
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static void vsc_port_intr(u8 port_status, struct ata_port *ap)
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{
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struct ata_queued_cmd *qc;
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237 |
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int handled = 0;
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238 |
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239 |
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if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
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240 |
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vsc_error_intr(port_status, ap);
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241 |
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return;
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242 |
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}
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243 |
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244 |
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qc = ata_qc_from_tag(ap, ap->link.active_tag);
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if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
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handled = ata_host_intr(ap, qc);
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247 |
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248 |
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/* We received an interrupt during a polled command,
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* or some other spurious condition. Interrupt reporting
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250 |
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* with this hardware is fairly reliable so it is safe to
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* simply clear the interrupt
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252 |
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*/
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253 |
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if (unlikely(!handled))
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254 |
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ata_chk_status(ap);
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255 |
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}
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256 |
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257 |
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/*
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258 |
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* vsc_sata_interrupt
|
259 |
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*
|
260 |
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* Read the interrupt register and process for the devices that have
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261 |
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* them pending.
|
262 |
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*/
|
263 |
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static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
|
264 |
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{
|
265 |
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struct ata_host *host = dev_instance;
|
266 |
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unsigned int i;
|
267 |
|
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unsigned int handled = 0;
|
268 |
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u32 status;
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269 |
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|
270 |
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status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
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271 |
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|
272 |
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if (unlikely(status == 0xffffffff || status == 0)) {
|
273 |
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if (status)
|
274 |
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dev_printk(KERN_ERR, host->dev,
|
275 |
|
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": IRQ status == 0xffffffff, "
|
276 |
|
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"PCI fault or device removal?\n");
|
277 |
|
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goto out;
|
278 |
|
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}
|
279 |
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|
280 |
|
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spin_lock(&host->lock);
|
281 |
|
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|
282 |
|
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for (i = 0; i < host->n_ports; i++) {
|
283 |
|
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u8 port_status = (status >> (8 * i)) & 0xff;
|
284 |
|
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if (port_status) {
|
285 |
|
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struct ata_port *ap = host->ports[i];
|
286 |
|
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|
287 |
|
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if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
|
288 |
|
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vsc_port_intr(port_status, ap);
|
289 |
|
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handled++;
|
290 |
|
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} else
|
291 |
|
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dev_printk(KERN_ERR, host->dev,
|
292 |
|
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"interrupt from disabled port %d\n", i);
|
293 |
|
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}
|
294 |
|
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}
|
295 |
|
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|
296 |
|
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spin_unlock(&host->lock);
|
297 |
|
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out:
|
298 |
|
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return IRQ_RETVAL(handled);
|
299 |
|
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}
|
300 |
|
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|
301 |
|
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|
302 |
|
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static struct scsi_host_template vsc_sata_sht = {
|
303 |
|
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.module = THIS_MODULE,
|
304 |
|
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.name = DRV_NAME,
|
305 |
|
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.ioctl = ata_scsi_ioctl,
|
306 |
|
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.queuecommand = ata_scsi_queuecmd,
|
307 |
|
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.can_queue = ATA_DEF_QUEUE,
|
308 |
|
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.this_id = ATA_SHT_THIS_ID,
|
309 |
|
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.sg_tablesize = LIBATA_MAX_PRD,
|
310 |
|
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
311 |
|
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.emulated = ATA_SHT_EMULATED,
|
312 |
|
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.use_clustering = ATA_SHT_USE_CLUSTERING,
|
313 |
|
|
.proc_name = DRV_NAME,
|
314 |
|
|
.dma_boundary = ATA_DMA_BOUNDARY,
|
315 |
|
|
.slave_configure = ata_scsi_slave_config,
|
316 |
|
|
.slave_destroy = ata_scsi_slave_destroy,
|
317 |
|
|
.bios_param = ata_std_bios_param,
|
318 |
|
|
};
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
static const struct ata_port_operations vsc_sata_ops = {
|
322 |
|
|
.tf_load = vsc_sata_tf_load,
|
323 |
|
|
.tf_read = vsc_sata_tf_read,
|
324 |
|
|
.exec_command = ata_exec_command,
|
325 |
|
|
.check_status = ata_check_status,
|
326 |
|
|
.dev_select = ata_std_dev_select,
|
327 |
|
|
.bmdma_setup = ata_bmdma_setup,
|
328 |
|
|
.bmdma_start = ata_bmdma_start,
|
329 |
|
|
.bmdma_stop = ata_bmdma_stop,
|
330 |
|
|
.bmdma_status = ata_bmdma_status,
|
331 |
|
|
.qc_prep = ata_qc_prep,
|
332 |
|
|
.qc_issue = ata_qc_issue_prot,
|
333 |
|
|
.data_xfer = ata_data_xfer,
|
334 |
|
|
.freeze = vsc_freeze,
|
335 |
|
|
.thaw = vsc_thaw,
|
336 |
|
|
.error_handler = ata_bmdma_error_handler,
|
337 |
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
338 |
|
|
.irq_clear = ata_bmdma_irq_clear,
|
339 |
|
|
.irq_on = ata_irq_on,
|
340 |
|
|
.scr_read = vsc_sata_scr_read,
|
341 |
|
|
.scr_write = vsc_sata_scr_write,
|
342 |
|
|
.port_start = ata_port_start,
|
343 |
|
|
};
|
344 |
|
|
|
345 |
|
|
static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
|
346 |
|
|
void __iomem *base)
|
347 |
|
|
{
|
348 |
|
|
port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
|
349 |
|
|
port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
|
350 |
|
|
port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
|
351 |
|
|
port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
|
352 |
|
|
port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
|
353 |
|
|
port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
|
354 |
|
|
port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
|
355 |
|
|
port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
|
356 |
|
|
port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
|
357 |
|
|
port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
|
358 |
|
|
port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
|
359 |
|
|
port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
|
360 |
|
|
port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
|
361 |
|
|
port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
|
362 |
|
|
port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
|
363 |
|
|
writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
|
364 |
|
|
writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
|
365 |
|
|
}
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
static int __devinit vsc_sata_init_one(struct pci_dev *pdev,
|
369 |
|
|
const struct pci_device_id *ent)
|
370 |
|
|
{
|
371 |
|
|
static const struct ata_port_info pi = {
|
372 |
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
|
373 |
|
|
ATA_FLAG_MMIO,
|
374 |
|
|
.pio_mask = 0x1f,
|
375 |
|
|
.mwdma_mask = 0x07,
|
376 |
|
|
.udma_mask = ATA_UDMA6,
|
377 |
|
|
.port_ops = &vsc_sata_ops,
|
378 |
|
|
};
|
379 |
|
|
const struct ata_port_info *ppi[] = { &pi, NULL };
|
380 |
|
|
static int printed_version;
|
381 |
|
|
struct ata_host *host;
|
382 |
|
|
void __iomem *mmio_base;
|
383 |
|
|
int i, rc;
|
384 |
|
|
u8 cls;
|
385 |
|
|
|
386 |
|
|
if (!printed_version++)
|
387 |
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
388 |
|
|
|
389 |
|
|
/* allocate host */
|
390 |
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
|
391 |
|
|
if (!host)
|
392 |
|
|
return -ENOMEM;
|
393 |
|
|
|
394 |
|
|
rc = pcim_enable_device(pdev);
|
395 |
|
|
if (rc)
|
396 |
|
|
return rc;
|
397 |
|
|
|
398 |
|
|
/* check if we have needed resource mapped */
|
399 |
|
|
if (pci_resource_len(pdev, 0) == 0)
|
400 |
|
|
return -ENODEV;
|
401 |
|
|
|
402 |
|
|
/* map IO regions and intialize host accordingly */
|
403 |
|
|
rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
|
404 |
|
|
if (rc == -EBUSY)
|
405 |
|
|
pcim_pin_device(pdev);
|
406 |
|
|
if (rc)
|
407 |
|
|
return rc;
|
408 |
|
|
host->iomap = pcim_iomap_table(pdev);
|
409 |
|
|
|
410 |
|
|
mmio_base = host->iomap[VSC_MMIO_BAR];
|
411 |
|
|
|
412 |
|
|
for (i = 0; i < host->n_ports; i++) {
|
413 |
|
|
struct ata_port *ap = host->ports[i];
|
414 |
|
|
unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
|
415 |
|
|
|
416 |
|
|
vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
|
417 |
|
|
|
418 |
|
|
ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
|
419 |
|
|
ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
|
420 |
|
|
}
|
421 |
|
|
|
422 |
|
|
/*
|
423 |
|
|
* Use 32 bit DMA mask, because 64 bit address support is poor.
|
424 |
|
|
*/
|
425 |
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
426 |
|
|
if (rc)
|
427 |
|
|
return rc;
|
428 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
429 |
|
|
if (rc)
|
430 |
|
|
return rc;
|
431 |
|
|
|
432 |
|
|
/*
|
433 |
|
|
* Due to a bug in the chip, the default cache line size can't be
|
434 |
|
|
* used (unless the default is non-zero).
|
435 |
|
|
*/
|
436 |
|
|
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
|
437 |
|
|
if (cls == 0x00)
|
438 |
|
|
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
|
439 |
|
|
|
440 |
|
|
if (pci_enable_msi(pdev) == 0)
|
441 |
|
|
pci_intx(pdev, 0);
|
442 |
|
|
|
443 |
|
|
/*
|
444 |
|
|
* Config offset 0x98 is "Extended Control and Status Register 0"
|
445 |
|
|
* Default value is (1 << 28). All bits except bit 28 are reserved in
|
446 |
|
|
* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
|
447 |
|
|
* If bit 28 is clear, each port has its own LED.
|
448 |
|
|
*/
|
449 |
|
|
pci_write_config_dword(pdev, 0x98, 0);
|
450 |
|
|
|
451 |
|
|
pci_set_master(pdev);
|
452 |
|
|
return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
|
453 |
|
|
IRQF_SHARED, &vsc_sata_sht);
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
static const struct pci_device_id vsc_sata_pci_tbl[] = {
|
457 |
|
|
{ PCI_VENDOR_ID_VITESSE, 0x7174,
|
458 |
|
|
PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
|
459 |
|
|
{ PCI_VENDOR_ID_INTEL, 0x3200,
|
460 |
|
|
PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
|
461 |
|
|
|
462 |
|
|
{ } /* terminate list */
|
463 |
|
|
};
|
464 |
|
|
|
465 |
|
|
static struct pci_driver vsc_sata_pci_driver = {
|
466 |
|
|
.name = DRV_NAME,
|
467 |
|
|
.id_table = vsc_sata_pci_tbl,
|
468 |
|
|
.probe = vsc_sata_init_one,
|
469 |
|
|
.remove = ata_pci_remove_one,
|
470 |
|
|
};
|
471 |
|
|
|
472 |
|
|
static int __init vsc_sata_init(void)
|
473 |
|
|
{
|
474 |
|
|
return pci_register_driver(&vsc_sata_pci_driver);
|
475 |
|
|
}
|
476 |
|
|
|
477 |
|
|
static void __exit vsc_sata_exit(void)
|
478 |
|
|
{
|
479 |
|
|
pci_unregister_driver(&vsc_sata_pci_driver);
|
480 |
|
|
}
|
481 |
|
|
|
482 |
|
|
MODULE_AUTHOR("Jeremy Higdon");
|
483 |
|
|
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
|
484 |
|
|
MODULE_LICENSE("GPL");
|
485 |
|
|
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
|
486 |
|
|
MODULE_VERSION(DRV_VERSION);
|
487 |
|
|
|
488 |
|
|
module_init(vsc_sata_init);
|
489 |
|
|
module_exit(vsc_sata_exit);
|