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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [atm/] [nicstar.h] - Blame information for rev 62

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1 62 marcus.erl
/******************************************************************************
2
 *
3
 * nicstar.h
4
 *
5
 * Header file for the nicstar device driver.
6
 *
7
 * Author: Rui Prior (rprior@inescn.pt)
8
 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
9
 *
10
 * (C) INESC 1998
11
 *
12
 ******************************************************************************/
13
 
14
 
15
#ifndef _LINUX_NICSTAR_H_
16
#define _LINUX_NICSTAR_H_
17
 
18
 
19
/* Includes *******************************************************************/
20
 
21
#include <linux/types.h>
22
#include <linux/pci.h>
23
#include <linux/uio.h>
24
#include <linux/skbuff.h>
25
#include <linux/atmdev.h>
26
#include <linux/atm_nicstar.h>
27
 
28
 
29
/* Options ********************************************************************/
30
 
31
#undef NS_DEBUG_SPINLOCKS
32
 
33
#define NS_MAX_CARDS 4          /* Maximum number of NICStAR based cards
34
                                   controlled by the device driver. Must
35
                                   be <= 5 */
36
 
37
#undef RCQ_SUPPORT              /* Do not define this for now */
38
 
39
#define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
40
#define NS_TST_RESERVED 340     /* N. entries reserved for UBR/ABR/VBR */
41
 
42
#define NS_SMBUFSIZE 48         /* 48, 96, 240 or 2048 */
43
#define NS_LGBUFSIZE 16384      /* 2048, 4096, 8192 or 16384 */
44
#define NS_RSQSIZE 8192         /* 2048, 4096 or 8192 */
45
#define NS_VPIBITS 2            /* 0, 1, 2, or 8 */
46
 
47
#define NS_MAX_RCTSIZE 4096     /* Number of entries. 4096 or 16384.
48
                                   Define 4096 only if (all) your card(s)
49
                                   have 32K x 32bit SRAM, in which case
50
                                   setting this to 16384 will just waste a
51
                                   lot of memory.
52
                                   Setting this to 4096 for a card with
53
                                   128K x 32bit SRAM will limit the maximum
54
                                   VCI. */
55
 
56
/*#define NS_PCI_LATENCY 64*/   /* Must be a multiple of 32 */
57
 
58
        /* Number of buffers initially allocated */
59
#define NUM_SB 32       /* Must be even */
60
#define NUM_LB 24       /* Must be even */
61
#define NUM_HB 8        /* Pre-allocated huge buffers */
62
#define NUM_IOVB 48     /* Iovec buffers */
63
 
64
        /* Lower level for count of buffers */
65
#define MIN_SB 8        /* Must be even */
66
#define MIN_LB 8        /* Must be even */
67
#define MIN_HB 6
68
#define MIN_IOVB 8
69
 
70
        /* Upper level for count of buffers */
71
#define MAX_SB 64       /* Must be even, <= 508 */
72
#define MAX_LB 48       /* Must be even, <= 508 */
73
#define MAX_HB 10
74
#define MAX_IOVB 80
75
 
76
        /* These are the absolute maximum allowed for the ioctl() */
77
#define TOP_SB 256      /* Must be even, <= 508 */
78
#define TOP_LB 128      /* Must be even, <= 508 */
79
#define TOP_HB 64
80
#define TOP_IOVB 256
81
 
82
 
83
#define MAX_TBD_PER_VC 1        /* Number of TBDs before a TSR */
84
#define MAX_TBD_PER_SCQ 10      /* Only meaningful for variable rate SCQs */
85
 
86
#undef ENABLE_TSQFIE
87
 
88
#define SCQFULL_TIMEOUT (5 * HZ)
89
 
90
#define NS_POLL_PERIOD (HZ)
91
 
92
#define PCR_TOLERANCE (1.0001)
93
 
94
 
95
 
96
/* ESI stuff ******************************************************************/
97
 
98
#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
99
#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
100
 
101
 
102
/* #defines *******************************************************************/
103
 
104
#define NS_IOREMAP_SIZE 4096
105
 
106
/*
107
 * BUF_XX distinguish the Rx buffers depending on their (small/large) size.
108
 * BUG_SM and BUG_LG are both used by the driver and the device.
109
 * BUF_NONE is only used by the driver.
110
 */
111
#define BUF_SM          0x00000000      /* These two are used for push_rxbufs() */
112
#define BUF_LG          0x00000001      /* CMD, Write_FreeBufQ, LBUF bit */
113
#define BUF_NONE        0xffffffff      /* Software only: */
114
 
115
#define NS_HBUFSIZE 65568       /* Size of max. AAL5 PDU */
116
#define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
117
                       (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
118
#define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
119
 
120
#define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
121
#define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
122
 
123
#define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD)        /* 4 bytes */
124
 
125
#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
126
#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
127
 
128
 
129
/* NICStAR structures located in host memory **********************************/
130
 
131
 
132
 
133
/* RSQ - Receive Status Queue
134
 *
135
 * Written by the NICStAR, read by the device driver.
136
 */
137
 
138
typedef struct ns_rsqe
139
{
140
   u32 word_1;
141
   u32 buffer_handle;
142
   u32 final_aal5_crc32;
143
   u32 word_4;
144
} ns_rsqe;
145
 
146
#define ns_rsqe_vpi(ns_rsqep) \
147
        ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
148
#define ns_rsqe_vci(ns_rsqep) \
149
        (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
150
 
151
#define NS_RSQE_VALID      0x80000000
152
#define NS_RSQE_NZGFC      0x00004000
153
#define NS_RSQE_EOPDU      0x00002000
154
#define NS_RSQE_BUFSIZE    0x00001000
155
#define NS_RSQE_CONGESTION 0x00000800
156
#define NS_RSQE_CLP        0x00000400
157
#define NS_RSQE_CRCERR     0x00000200
158
 
159
#define NS_RSQE_BUFSIZE_SM 0x00000000
160
#define NS_RSQE_BUFSIZE_LG 0x00001000
161
 
162
#define ns_rsqe_valid(ns_rsqep) \
163
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
164
#define ns_rsqe_nzgfc(ns_rsqep) \
165
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
166
#define ns_rsqe_eopdu(ns_rsqep) \
167
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
168
#define ns_rsqe_bufsize(ns_rsqep) \
169
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
170
#define ns_rsqe_congestion(ns_rsqep) \
171
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
172
#define ns_rsqe_clp(ns_rsqep) \
173
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
174
#define ns_rsqe_crcerr(ns_rsqep) \
175
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
176
 
177
#define ns_rsqe_cellcount(ns_rsqep) \
178
        (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
179
#define ns_rsqe_init(ns_rsqep) \
180
        ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
181
 
182
#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
183
#define NS_RSQ_ALIGNMENT NS_RSQSIZE
184
 
185
 
186
 
187
/* RCQ - Raw Cell Queue
188
 *
189
 * Written by the NICStAR, read by the device driver.
190
 */
191
 
192
typedef struct cell_payload
193
{
194
   u32 word[12];
195
} cell_payload;
196
 
197
typedef struct ns_rcqe
198
{
199
   u32 word_1;
200
   u32 word_2;
201
   u32 word_3;
202
   u32 word_4;
203
   cell_payload payload;
204
} ns_rcqe;
205
 
206
#define NS_RCQE_SIZE 64         /* bytes */
207
 
208
#define ns_rcqe_islast(ns_rcqep) \
209
        (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
210
#define ns_rcqe_cellheader(ns_rcqep) \
211
        (le32_to_cpu((ns_rcqep)->word_1))
212
#define ns_rcqe_nextbufhandle(ns_rcqep) \
213
        (le32_to_cpu((ns_rcqep)->word_2))
214
 
215
 
216
 
217
/* SCQ - Segmentation Channel Queue
218
 *
219
 * Written by the device driver, read by the NICStAR.
220
 */
221
 
222
typedef struct ns_scqe
223
{
224
   u32 word_1;
225
   u32 word_2;
226
   u32 word_3;
227
   u32 word_4;
228
} ns_scqe;
229
 
230
   /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
231
            or TSR (Transmit Status Requests) */
232
 
233
#define NS_SCQE_TYPE_TBD 0x00000000
234
#define NS_SCQE_TYPE_TSR 0x80000000
235
 
236
 
237
#define NS_TBD_EOPDU 0x40000000
238
#define NS_TBD_AAL0  0x00000000
239
#define NS_TBD_AAL34 0x04000000
240
#define NS_TBD_AAL5  0x08000000
241
 
242
#define NS_TBD_VPI_MASK 0x0FF00000
243
#define NS_TBD_VCI_MASK 0x000FFFF0
244
#define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
245
 
246
#define NS_TBD_VPI_SHIFT 20
247
#define NS_TBD_VCI_SHIFT 4
248
 
249
#define ns_tbd_mkword_1(flags, m, n, buflen) \
250
      (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
251
#define ns_tbd_mkword_1_novbr(flags, buflen) \
252
      (cpu_to_le32((flags) | (buflen) | 0x00810000))
253
#define ns_tbd_mkword_3(control, pdulen) \
254
      (cpu_to_le32((control) << 16 | (pdulen)))
255
#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
256
      (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
257
 
258
 
259
#define NS_TSR_INTENABLE 0x20000000
260
 
261
#define NS_TSR_SCDISVBR 0xFFFF          /* Use as scdi for VBR SCD */
262
 
263
#define ns_tsr_mkword_1(flags) \
264
        (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
265
#define ns_tsr_mkword_2(scdi, scqi) \
266
        (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
267
 
268
#define ns_scqe_is_tsr(ns_scqep) \
269
        (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
270
 
271
#define VBR_SCQ_NUM_ENTRIES 512
272
#define VBR_SCQSIZE 8192
273
#define CBR_SCQ_NUM_ENTRIES 64
274
#define CBR_SCQSIZE 1024
275
 
276
#define NS_SCQE_SIZE 16
277
 
278
 
279
 
280
/* TSQ - Transmit Status Queue
281
 *
282
 * Written by the NICStAR, read by the device driver.
283
 */
284
 
285
typedef struct ns_tsi
286
{
287
   u32 word_1;
288
   u32 word_2;
289
} ns_tsi;
290
 
291
   /* NOTE: The first word can be a status word copied from the TSR which
292
            originated the TSI, or a timer overflow indicator. In this last
293
            case, the value of the first word is all zeroes. */
294
 
295
#define NS_TSI_EMPTY          0x80000000
296
#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
297
 
298
#define ns_tsi_isempty(ns_tsip) \
299
        (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
300
#define ns_tsi_gettimestamp(ns_tsip) \
301
        (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
302
 
303
#define ns_tsi_init(ns_tsip) \
304
        ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
305
 
306
 
307
#define NS_TSQSIZE 8192
308
#define NS_TSQ_NUM_ENTRIES 1024
309
#define NS_TSQ_ALIGNMENT 8192
310
 
311
 
312
#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
313
 
314
#define ns_tsi_tmrof(ns_tsip) \
315
        (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
316
#define ns_tsi_getscdindex(ns_tsip) \
317
        ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
318
#define ns_tsi_getscqpos(ns_tsip) \
319
        (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
320
 
321
 
322
 
323
/* NICStAR structures located in local SRAM ***********************************/
324
 
325
 
326
 
327
/* RCT - Receive Connection Table
328
 *
329
 * Written by both the NICStAR and the device driver.
330
 */
331
 
332
typedef struct ns_rcte
333
{
334
   u32 word_1;
335
   u32 buffer_handle;
336
   u32 dma_address;
337
   u32 aal5_crc32;
338
} ns_rcte;
339
 
340
#define NS_RCTE_BSFB            0x00200000  /* Rev. D only */
341
#define NS_RCTE_NZGFC           0x00100000
342
#define NS_RCTE_CONNECTOPEN     0x00080000
343
#define NS_RCTE_AALMASK         0x00070000
344
#define NS_RCTE_AAL0            0x00000000
345
#define NS_RCTE_AAL34           0x00010000
346
#define NS_RCTE_AAL5            0x00020000
347
#define NS_RCTE_RCQ             0x00030000
348
#define NS_RCTE_RAWCELLINTEN    0x00008000
349
#define NS_RCTE_RXCONSTCELLADDR 0x00004000
350
#define NS_RCTE_BUFFVALID       0x00002000
351
#define NS_RCTE_FBDSIZE         0x00001000
352
#define NS_RCTE_EFCI            0x00000800
353
#define NS_RCTE_CLP             0x00000400
354
#define NS_RCTE_CRCERROR        0x00000200
355
#define NS_RCTE_CELLCOUNT_MASK  0x000001FF
356
 
357
#define NS_RCTE_FBDSIZE_SM 0x00000000
358
#define NS_RCTE_FBDSIZE_LG 0x00001000
359
 
360
#define NS_RCT_ENTRY_SIZE 4     /* Number of dwords */
361
 
362
   /* NOTE: We could make macros to contruct the first word of the RCTE,
363
            but that doesn't seem to make much sense... */
364
 
365
 
366
 
367
/* FBD - Free Buffer Descriptor
368
 *
369
 * Written by the device driver using via the command register.
370
 */
371
 
372
typedef struct ns_fbd
373
{
374
   u32 buffer_handle;
375
   u32 dma_address;
376
} ns_fbd;
377
 
378
 
379
 
380
 
381
/* TST - Transmit Schedule Table
382
 *
383
 * Written by the device driver.
384
 */
385
 
386
typedef u32 ns_tste;
387
 
388
#define NS_TST_OPCODE_MASK 0x60000000
389
 
390
#define NS_TST_OPCODE_NULL     0x00000000 /* Insert null cell */
391
#define NS_TST_OPCODE_FIXED    0x20000000 /* Cell from a fixed rate channel */
392
#define NS_TST_OPCODE_VARIABLE 0x40000000
393
#define NS_TST_OPCODE_END      0x60000000 /* Jump */
394
 
395
#define ns_tste_make(opcode, sramad) (opcode | sramad)
396
 
397
   /* NOTE:
398
 
399
      - When the opcode is FIXED, sramad specifies the SRAM address of the
400
        SCD for that fixed rate channel.
401
      - When the opcode is END, sramad specifies the SRAM address of the
402
        location of the next TST entry to read.
403
    */
404
 
405
 
406
 
407
/* SCD - Segmentation Channel Descriptor
408
 *
409
 * Written by both the device driver and the NICStAR
410
 */
411
 
412
typedef struct ns_scd
413
{
414
   u32 word_1;
415
   u32 word_2;
416
   u32 partial_aal5_crc;
417
   u32 reserved;
418
   ns_scqe cache_a;
419
   ns_scqe cache_b;
420
} ns_scd;
421
 
422
#define NS_SCD_BASE_MASK_VAR 0xFFFFE000         /* Variable rate */
423
#define NS_SCD_BASE_MASK_FIX 0xFFFFFC00         /* Fixed rate */
424
#define NS_SCD_TAIL_MASK_VAR 0x00001FF0
425
#define NS_SCD_TAIL_MASK_FIX 0x000003F0
426
#define NS_SCD_HEAD_MASK_VAR 0x00001FF0
427
#define NS_SCD_HEAD_MASK_FIX 0x000003F0
428
#define NS_SCD_XMITFOREVER   0x02000000
429
 
430
   /* NOTE: There are other fields in word 2 of the SCD, but as they should
431
            not be needed in the device driver they are not defined here. */
432
 
433
 
434
 
435
 
436
/* NICStAR local SRAM memory map **********************************************/
437
 
438
 
439
#define NS_RCT           0x00000
440
#define NS_RCT_32_END    0x03FFF
441
#define NS_RCT_128_END   0x0FFFF
442
#define NS_UNUSED_32     0x04000
443
#define NS_UNUSED_128    0x10000
444
#define NS_UNUSED_END    0x1BFFF
445
#define NS_TST_FRSCD     0x1C000
446
#define NS_TST_FRSCD_END 0x1E7DB
447
#define NS_VRSCD2        0x1E7DC
448
#define NS_VRSCD2_END    0x1E7E7
449
#define NS_VRSCD1        0x1E7E8
450
#define NS_VRSCD1_END    0x1E7F3
451
#define NS_VRSCD0        0x1E7F4
452
#define NS_VRSCD0_END    0x1E7FF
453
#define NS_RXFIFO        0x1E800
454
#define NS_RXFIFO_END    0x1F7FF
455
#define NS_SMFBQ         0x1F800
456
#define NS_SMFBQ_END     0x1FBFF
457
#define NS_LGFBQ         0x1FC00
458
#define NS_LGFBQ_END     0x1FFFF
459
 
460
 
461
 
462
/* NISCtAR operation registers ************************************************/
463
 
464
 
465
/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
466
 
467
enum ns_regs
468
{
469
   DR0   = 0x00,      /* Data Register 0 R/W*/
470
   DR1   = 0x04,      /* Data Register 1 W */
471
   DR2   = 0x08,      /* Data Register 2 W */
472
   DR3   = 0x0C,      /* Data Register 3 W */
473
   CMD   = 0x10,      /* Command W */
474
   CFG   = 0x14,      /* Configuration R/W */
475
   STAT  = 0x18,      /* Status R/W */
476
   RSQB  = 0x1C,      /* Receive Status Queue Base W */
477
   RSQT  = 0x20,      /* Receive Status Queue Tail R */
478
   RSQH  = 0x24,      /* Receive Status Queue Head W */
479
   CDC   = 0x28,      /* Cell Drop Counter R/clear */
480
   VPEC  = 0x2C,      /* VPI/VCI Lookup Error Count R/clear */
481
   ICC   = 0x30,      /* Invalid Cell Count R/clear */
482
   RAWCT = 0x34,      /* Raw Cell Tail R */
483
   TMR   = 0x38,      /* Timer R */
484
   TSTB  = 0x3C,      /* Transmit Schedule Table Base R/W */
485
   TSQB  = 0x40,      /* Transmit Status Queue Base W */
486
   TSQT  = 0x44,      /* Transmit Status Queue Tail R */
487
   TSQH  = 0x48,      /* Transmit Status Queue Head W */
488
   GP    = 0x4C,      /* General Purpose R/W */
489
   VPM   = 0x50       /* VPI/VCI Mask W */
490
};
491
 
492
 
493
/* NICStAR commands issued to the CMD register ********************************/
494
 
495
 
496
/* Top 4 bits are command opcode, lower 28 are parameters. */
497
 
498
#define NS_CMD_NO_OPERATION         0x00000000
499
        /* params always 0 */
500
 
501
#define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
502
        /* b19{1=open,0=close} b18-2{SRAM addr} */
503
 
504
#define NS_CMD_WRITE_SRAM           0x40000000
505
        /* b18-2{SRAM addr} b1-0{burst size} */
506
 
507
#define NS_CMD_READ_SRAM            0x50000000
508
        /* b18-2{SRAM addr} */
509
 
510
#define NS_CMD_WRITE_FREEBUFQ       0x60000000
511
        /* b0{large buf indicator} */
512
 
513
#define NS_CMD_READ_UTILITY         0x80000000
514
        /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
515
 
516
#define NS_CMD_WRITE_UTILITY        0x90000000
517
        /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
518
 
519
#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
520
#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
521
 
522
 
523
/* NICStAR configuration bits *************************************************/
524
 
525
#define NS_CFG_SWRST          0x80000000    /* Software Reset */
526
#define NS_CFG_RXPATH         0x20000000    /* Receive Path Enable */
527
#define NS_CFG_SMBUFSIZE_MASK 0x18000000    /* Small Receive Buffer Size */
528
#define NS_CFG_LGBUFSIZE_MASK 0x06000000    /* Large Receive Buffer Size */
529
#define NS_CFG_EFBIE          0x01000000    /* Empty Free Buffer Queue
530
                                               Interrupt Enable */
531
#define NS_CFG_RSQSIZE_MASK   0x00C00000    /* Receive Status Queue Size */
532
#define NS_CFG_ICACCEPT       0x00200000    /* Invalid Cell Accept */
533
#define NS_CFG_IGNOREGFC      0x00100000    /* Ignore General Flow Control */
534
#define NS_CFG_VPIBITS_MASK   0x000C0000    /* VPI/VCI Bits Size Select */
535
#define NS_CFG_RCTSIZE_MASK   0x00030000    /* Receive Connection Table Size */
536
#define NS_CFG_VCERRACCEPT    0x00008000    /* VPI/VCI Error Cell Accept */
537
#define NS_CFG_RXINT_MASK     0x00007000    /* End of Receive PDU Interrupt
538
                                               Handling */
539
#define NS_CFG_RAWIE          0x00000800    /* Raw Cell Qu' Interrupt Enable */
540
#define NS_CFG_RSQAFIE        0x00000400    /* Receive Queue Almost Full
541
                                               Interrupt Enable */
542
#define NS_CFG_RXRM           0x00000200    /* Receive RM Cells */
543
#define NS_CFG_TMRROIE        0x00000080    /* Timer Roll Over Interrupt
544
                                               Enable */
545
#define NS_CFG_TXEN           0x00000020    /* Transmit Operation Enable */
546
#define NS_CFG_TXIE           0x00000010    /* Transmit Status Interrupt
547
                                               Enable */
548
#define NS_CFG_TXURIE         0x00000008    /* Transmit Under-run Interrupt
549
                                               Enable */
550
#define NS_CFG_UMODE          0x00000004    /* Utopia Mode (cell/byte) Select */
551
#define NS_CFG_TSQFIE         0x00000002    /* Transmit Status Queue Full
552
                                               Interrupt Enable */
553
#define NS_CFG_PHYIE          0x00000001    /* PHY Interrupt Enable */
554
 
555
#define NS_CFG_SMBUFSIZE_48    0x00000000
556
#define NS_CFG_SMBUFSIZE_96    0x08000000
557
#define NS_CFG_SMBUFSIZE_240   0x10000000
558
#define NS_CFG_SMBUFSIZE_2048  0x18000000
559
 
560
#define NS_CFG_LGBUFSIZE_2048  0x00000000
561
#define NS_CFG_LGBUFSIZE_4096  0x02000000
562
#define NS_CFG_LGBUFSIZE_8192  0x04000000
563
#define NS_CFG_LGBUFSIZE_16384 0x06000000
564
 
565
#define NS_CFG_RSQSIZE_2048 0x00000000
566
#define NS_CFG_RSQSIZE_4096 0x00400000
567
#define NS_CFG_RSQSIZE_8192 0x00800000
568
 
569
#define NS_CFG_VPIBITS_0 0x00000000
570
#define NS_CFG_VPIBITS_1 0x00040000
571
#define NS_CFG_VPIBITS_2 0x00080000
572
#define NS_CFG_VPIBITS_8 0x000C0000
573
 
574
#define NS_CFG_RCTSIZE_4096_ENTRIES  0x00000000
575
#define NS_CFG_RCTSIZE_8192_ENTRIES  0x00010000
576
#define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
577
 
578
#define NS_CFG_RXINT_NOINT   0x00000000
579
#define NS_CFG_RXINT_NODELAY 0x00001000
580
#define NS_CFG_RXINT_314US   0x00002000
581
#define NS_CFG_RXINT_624US   0x00003000
582
#define NS_CFG_RXINT_899US   0x00004000
583
 
584
 
585
/* NICStAR STATus bits ********************************************************/
586
 
587
#define NS_STAT_SFBQC_MASK 0xFF000000   /* hi 8 bits Small Buffer Queue Count */
588
#define NS_STAT_LFBQC_MASK 0x00FF0000   /* hi 8 bits Large Buffer Queue Count */
589
#define NS_STAT_TSIF       0x00008000   /* Transmit Status Queue Indicator */
590
#define NS_STAT_TXICP      0x00004000   /* Transmit Incomplete PDU */
591
#define NS_STAT_TSQF       0x00001000   /* Transmit Status Queue Full */
592
#define NS_STAT_TMROF      0x00000800   /* Timer Overflow */
593
#define NS_STAT_PHYI       0x00000400   /* PHY Device Interrupt */
594
#define NS_STAT_CMDBZ      0x00000200   /* Command Busy */
595
#define NS_STAT_SFBQF      0x00000100   /* Small Buffer Queue Full */
596
#define NS_STAT_LFBQF      0x00000080   /* Large Buffer Queue Full */
597
#define NS_STAT_RSQF       0x00000040   /* Receive Status Queue Full */
598
#define NS_STAT_EOPDU      0x00000020   /* End of PDU */
599
#define NS_STAT_RAWCF      0x00000010   /* Raw Cell Flag */
600
#define NS_STAT_SFBQE      0x00000008   /* Small Buffer Queue Empty */
601
#define NS_STAT_LFBQE      0x00000004   /* Large Buffer Queue Empty */
602
#define NS_STAT_RSQAF      0x00000002   /* Receive Status Queue Almost Full */
603
 
604
#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
605
#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
606
 
607
 
608
 
609
/* #defines which depend on other #defines ************************************/
610
 
611
 
612
#define NS_TST0 NS_TST_FRSCD
613
#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
614
 
615
#define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
616
#define NS_FRSCD_SIZE 12        /* 12 dwords */
617
#define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
618
 
619
#if (NS_SMBUFSIZE == 48)
620
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
621
#elif (NS_SMBUFSIZE == 96)
622
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
623
#elif (NS_SMBUFSIZE == 240)
624
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
625
#elif (NS_SMBUFSIZE == 2048)
626
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
627
#else
628
#error NS_SMBUFSIZE is incorrect in nicstar.h
629
#endif /* NS_SMBUFSIZE */
630
 
631
#if (NS_LGBUFSIZE == 2048)
632
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
633
#elif (NS_LGBUFSIZE == 4096)
634
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
635
#elif (NS_LGBUFSIZE == 8192)
636
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
637
#elif (NS_LGBUFSIZE == 16384)
638
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
639
#else
640
#error NS_LGBUFSIZE is incorrect in nicstar.h
641
#endif /* NS_LGBUFSIZE */
642
 
643
#if (NS_RSQSIZE == 2048)
644
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
645
#elif (NS_RSQSIZE == 4096)
646
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
647
#elif (NS_RSQSIZE == 8192)
648
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
649
#else
650
#error NS_RSQSIZE is incorrect in nicstar.h
651
#endif /* NS_RSQSIZE */
652
 
653
#if (NS_VPIBITS == 0)
654
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
655
#elif (NS_VPIBITS == 1)
656
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
657
#elif (NS_VPIBITS == 2)
658
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
659
#elif (NS_VPIBITS == 8)
660
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
661
#else
662
#error NS_VPIBITS is incorrect in nicstar.h
663
#endif /* NS_VPIBITS */
664
 
665
#ifdef RCQ_SUPPORT
666
#define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
667
#else
668
#define NS_CFG_RAWIE_OPT 0x00000000
669
#endif /* RCQ_SUPPORT */
670
 
671
#ifdef ENABLE_TSQFIE
672
#define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
673
#else
674
#define NS_CFG_TSQFIE_OPT 0x00000000
675
#endif /* ENABLE_TSQFIE */
676
 
677
 
678
/* PCI stuff ******************************************************************/
679
 
680
#ifndef PCI_VENDOR_ID_IDT
681
#define PCI_VENDOR_ID_IDT 0x111D
682
#endif /* PCI_VENDOR_ID_IDT */
683
 
684
#ifndef PCI_DEVICE_ID_IDT_IDT77201
685
#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
686
#endif /* PCI_DEVICE_ID_IDT_IDT77201 */
687
 
688
 
689
 
690
/* Device driver structures ***************************************************/
691
 
692
 
693
struct ns_skb_cb {
694
        u32 buf_type;                   /* BUF_SM/BUF_LG/BUF_NONE */
695
};
696
 
697
#define NS_SKB_CB(skb)  ((struct ns_skb_cb *)((skb)->cb))
698
 
699
typedef struct tsq_info
700
{
701
   void *org;
702
   ns_tsi *base;
703
   ns_tsi *next;
704
   ns_tsi *last;
705
} tsq_info;
706
 
707
 
708
typedef struct scq_info
709
{
710
   void *org;
711
   ns_scqe *base;
712
   ns_scqe *last;
713
   ns_scqe *next;
714
   volatile ns_scqe *tail;              /* Not related to the nicstar register */
715
   unsigned num_entries;
716
   struct sk_buff **skb;                /* Pointer to an array of pointers
717
                                           to the sk_buffs used for tx */
718
   u32 scd;                             /* SRAM address of the corresponding
719
                                           SCD */
720
   int tbd_count;                       /* Only meaningful on variable rate */
721
   wait_queue_head_t scqfull_waitq;
722
   volatile char full;                  /* SCQ full indicator */
723
   spinlock_t lock;                     /* SCQ spinlock */
724
#ifdef NS_DEBUG_SPINLOCKS
725
   volatile long has_lock;
726
   volatile int cpu_lock;
727
#endif /* NS_DEBUG_SPINLOCKS */
728
} scq_info;
729
 
730
 
731
 
732
typedef struct rsq_info
733
{
734
   void *org;
735
   ns_rsqe *base;
736
   ns_rsqe *next;
737
   ns_rsqe *last;
738
} rsq_info;
739
 
740
 
741
typedef struct skb_pool
742
{
743
   volatile int count;                  /* number of buffers in the queue */
744
   struct sk_buff_head queue;
745
} skb_pool;
746
 
747
/* NOTE: for small and large buffer pools, the count is not used, as the
748
         actual value used for buffer management is the one read from the
749
         card. */
750
 
751
 
752
typedef struct vc_map
753
{
754
   volatile unsigned int tx:1;                          /* TX vc? */
755
   volatile unsigned int rx:1;                          /* RX vc? */
756
   struct atm_vcc *tx_vcc, *rx_vcc;
757
   struct sk_buff *rx_iov;              /* RX iovector skb */
758
   scq_info *scq;                       /* To keep track of the SCQ */
759
   u32 cbr_scd;                         /* SRAM address of the corresponding
760
                                           SCD. 0x00000000 for UBR/VBR/ABR */
761
   int tbd_count;
762
} vc_map;
763
 
764
 
765
struct ns_skb_data
766
{
767
        struct atm_vcc *vcc;
768
        int iovcnt;
769
};
770
 
771
#define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb))
772
 
773
 
774
typedef struct ns_dev
775
{
776
   int index;                           /* Card ID to the device driver */
777
   int sram_size;                       /* In k x 32bit words. 32 or 128 */
778
   void __iomem *membase;               /* Card's memory base address */
779
   unsigned long max_pcr;
780
   int rct_size;                        /* Number of entries */
781
   int vpibits;
782
   int vcibits;
783
   struct pci_dev *pcidev;
784
   struct atm_dev *atmdev;
785
   tsq_info tsq;
786
   rsq_info rsq;
787
   scq_info *scq0, *scq1, *scq2;        /* VBR SCQs */
788
   skb_pool sbpool;                     /* Small buffers */
789
   skb_pool lbpool;                     /* Large buffers */
790
   skb_pool hbpool;                     /* Pre-allocated huge buffers */
791
   skb_pool iovpool;                    /* iovector buffers */
792
   volatile int efbie;                  /* Empty free buf. queue int. enabled */
793
   volatile u32 tst_addr;               /* SRAM address of the TST in use */
794
   volatile int tst_free_entries;
795
   vc_map vcmap[NS_MAX_RCTSIZE];
796
   vc_map *tste2vc[NS_TST_NUM_ENTRIES];
797
   vc_map *scd2vc[NS_FRSCD_NUM];
798
   buf_nr sbnr;
799
   buf_nr lbnr;
800
   buf_nr hbnr;
801
   buf_nr iovnr;
802
   int sbfqc;
803
   int lbfqc;
804
   u32 sm_handle;
805
   u32 sm_addr;
806
   u32 lg_handle;
807
   u32 lg_addr;
808
   struct sk_buff *rcbuf;               /* Current raw cell buffer */
809
   u32 rawch;                           /* Raw cell queue head */
810
   unsigned intcnt;                     /* Interrupt counter */
811
   spinlock_t int_lock;         /* Interrupt lock */
812
   spinlock_t res_lock;         /* Card resource lock */
813
#ifdef NS_DEBUG_SPINLOCKS
814
   volatile long has_int_lock;
815
   volatile int cpu_int;
816
   volatile long has_res_lock;
817
   volatile int cpu_res;
818
#endif /* NS_DEBUG_SPINLOCKS */
819
} ns_dev;
820
 
821
 
822
   /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
823
            CBR vc. If the entry is not allocated, it must be NULL.
824
 
825
            There are two TSTs so the driver can modify them on the fly
826
            without stopping the transmission.
827
 
828
            scd2vc allows us to find out unused fixed rate SCDs, because
829
            they must have a NULL pointer here. */
830
 
831
 
832
#endif /* _LINUX_NICSTAR_H_ */

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