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marcus.erl |
/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
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/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
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#ifndef DRIVER_ATM_ZATM_H
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#define DRIVER_ATM_ZATM_H
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#include <linux/skbuff.h>
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#include <linux/atm.h>
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#include <linux/atmdev.h>
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#include <linux/sonet.h>
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#include <linux/pci.h>
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#define DEV_LABEL "zatm"
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#define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */
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#define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */
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#define LOW_MARK 12 /* start adding new buffers if less than 12 */
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#define HIGH_MARK 30 /* stop adding buffers after reaching 30 */
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#define OFF_CNG_THRES 5 /* threshold for offset changes */
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#define RX_SIZE 2 /* RX lookup entry size (in bytes) */
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#define NR_POOLS 32 /* number of free buffer pointers */
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#define POOL_SIZE 8 /* buffer entry size (in bytes) */
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#define NR_SHAPERS 16 /* number of shapers */
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#define SHAPER_SIZE 4 /* shaper entry size (in bytes) */
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#define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */
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#define RING_ENTRIES 32 /* ring entries (without back pointer) */
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#define RING_WORDS 4 /* ring element size */
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#define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
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#define NR_MBX 4 /* four mailboxes */
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#define MBX_RX_0 0 /* mailbox indices */
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#define MBX_RX_1 1
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#define MBX_TX_0 2
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#define MBX_TX_1 3
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struct zatm_vcc {
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/*-------------------------------- RX part */
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int rx_chan; /* RX channel, 0 if none */
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int pool; /* free buffer pool */
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/*-------------------------------- TX part */
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int tx_chan; /* TX channel, 0 if none */
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int shaper; /* shaper, <0 if none */
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struct sk_buff_head tx_queue; /* list of buffers in transit */
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wait_queue_head_t tx_wait; /* for close */
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u32 *ring; /* transmit ring */
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int ring_curr; /* current write position */
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int txing; /* number of transmits in progress */
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struct sk_buff_head backlog; /* list of buffers waiting for ring */
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};
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struct zatm_dev {
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/*-------------------------------- TX part */
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int tx_bw; /* remaining bandwidth */
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u32 free_shapers; /* bit set */
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int ubr; /* UBR shaper; -1 if none */
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int ubr_ref_cnt; /* number of VCs using UBR shaper */
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/*-------------------------------- RX part */
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int pool_ref[NR_POOLS]; /* free buffer pool usage counters */
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volatile struct sk_buff *last_free[NR_POOLS];
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/* last entry in respective pool */
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struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
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struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
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/*-------------------------------- maps */
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struct atm_vcc **tx_map; /* TX VCCs */
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struct atm_vcc **rx_map; /* RX VCCs */
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int chans; /* map size, must be 2^n */
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/*-------------------------------- mailboxes */
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unsigned long mbx_start[NR_MBX];/* start addresses */
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dma_addr_t mbx_dma[NR_MBX];
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u16 mbx_end[NR_MBX]; /* end offset (in bytes) */
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/*-------------------------------- other pointers */
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u32 pool_base; /* Free buffer pool dsc (word addr) */
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/*-------------------------------- ZATM links */
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struct atm_dev *more; /* other ZATM devices */
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/*-------------------------------- general information */
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int mem; /* RAM on board (in bytes) */
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int khz; /* timer clock */
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int copper; /* PHY type */
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unsigned char irq; /* IRQ */
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unsigned int base; /* IO base address */
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struct pci_dev *pci_dev; /* PCI stuff */
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spinlock_t lock;
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};
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#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
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#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
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struct zatm_skb_prv {
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struct atm_skb_data _; /* reserved */
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u32 *dsc; /* pointer to skb's descriptor */
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};
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#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
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#endif
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