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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [char/] [mxser_new.h] - Blame information for rev 65

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#ifndef _MXSER_H
#define _MXSER_H
 
/*
 *      Semi-public control interfaces
 */
 
/*
 *      MOXA ioctls
 */
 
#define MOXA                    0x400
#define MOXA_GETDATACOUNT       (MOXA + 23)
#define MOXA_GET_CONF           (MOXA + 35)
#define MOXA_DIAGNOSE           (MOXA + 50)
#define MOXA_CHKPORTENABLE      (MOXA + 60)
#define MOXA_HighSpeedOn        (MOXA + 61)
#define MOXA_GET_MAJOR          (MOXA + 63)
#define MOXA_GET_CUMAJOR        (MOXA + 64)
#define MOXA_GETMSTATUS         (MOXA + 65)
#define MOXA_SET_OP_MODE        (MOXA + 66)
#define MOXA_GET_OP_MODE        (MOXA + 67)
 
#define RS232_MODE              0
#define RS485_2WIRE_MODE        1
#define RS422_MODE              2
#define RS485_4WIRE_MODE        3
#define OP_MODE_MASK            3
 
#define MOXA_SDS_RSTICOUNTER    (MOXA + 69)
#define MOXA_ASPP_OQUEUE        (MOXA + 70)
#define MOXA_ASPP_SETBAUD       (MOXA + 71)
#define MOXA_ASPP_GETBAUD       (MOXA + 72)
#define MOXA_ASPP_MON           (MOXA + 73)
#define MOXA_ASPP_LSTATUS       (MOXA + 74)
#define MOXA_ASPP_MON_EXT       (MOXA + 75)
#define MOXA_SET_BAUD_METHOD    (MOXA + 76)
#define MOXA_SET_SPECIAL_BAUD_RATE      (MOXA + 77)
#define MOXA_GET_SPECIAL_BAUD_RATE      (MOXA + 78)
 
/* --------------------------------------------------- */
 
#define NPPI_NOTIFY_PARITY      0x01
#define NPPI_NOTIFY_FRAMING     0x02
#define NPPI_NOTIFY_HW_OVERRUN  0x04
#define NPPI_NOTIFY_SW_OVERRUN  0x08
#define NPPI_NOTIFY_BREAK       0x10
 
#define NPPI_NOTIFY_CTSHOLD         0x01        /* Tx hold by CTS low */
#define NPPI_NOTIFY_DSRHOLD         0x02        /* Tx hold by DSR low */
#define NPPI_NOTIFY_XOFFHOLD        0x08        /* Tx hold by Xoff received */
#define NPPI_NOTIFY_XOFFXENT        0x10        /* Xoff Sent */
 
/* follow just for Moxa Must chip define. */
/* */
/* when LCR register (offset 0x03) write following value, */
/* the Must chip will enter enchance mode. And write value */
/* on EFR (offset 0x02) bit 6,7 to change bank. */
#define MOXA_MUST_ENTER_ENCHANCE        0xBF
 
/* when enhance mode enable, access on general bank register */
#define MOXA_MUST_GDL_REGISTER          0x07
#define MOXA_MUST_GDL_MASK              0x7F
#define MOXA_MUST_GDL_HAS_BAD_DATA      0x80
 
#define MOXA_MUST_LSR_RERR              0x80    /* error in receive FIFO */
/* enchance register bank select and enchance mode setting register */
/* when LCR register equal to 0xBF */
#define MOXA_MUST_EFR_REGISTER          0x02
/* enchance mode enable */
#define MOXA_MUST_EFR_EFRB_ENABLE       0x10
/* enchance reister bank set 0, 1, 2 */
#define MOXA_MUST_EFR_BANK0             0x00
#define MOXA_MUST_EFR_BANK1             0x40
#define MOXA_MUST_EFR_BANK2             0x80
#define MOXA_MUST_EFR_BANK3             0xC0
#define MOXA_MUST_EFR_BANK_MASK         0xC0
 
/* set XON1 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XON1_REGISTER         0x04
 
/* set XON2 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XON2_REGISTER         0x05
 
/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XOFF1_REGISTER        0x06
 
/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XOFF2_REGISTER        0x07
 
#define MOXA_MUST_RBRTL_REGISTER        0x04
#define MOXA_MUST_RBRTH_REGISTER        0x05
#define MOXA_MUST_RBRTI_REGISTER        0x06
#define MOXA_MUST_THRTL_REGISTER        0x07
#define MOXA_MUST_ENUM_REGISTER         0x04
#define MOXA_MUST_HWID_REGISTER         0x05
#define MOXA_MUST_ECR_REGISTER          0x06
#define MOXA_MUST_CSR_REGISTER          0x07
 
/* good data mode enable */
#define MOXA_MUST_FCR_GDA_MODE_ENABLE   0x20
/* only good data put into RxFIFO */
#define MOXA_MUST_FCR_GDA_ONLY_ENABLE   0x10
 
/* enable CTS interrupt */
#define MOXA_MUST_IER_ECTSI             0x80
/* enable RTS interrupt */
#define MOXA_MUST_IER_ERTSI             0x40
/* enable Xon/Xoff interrupt */
#define MOXA_MUST_IER_XINT              0x20
/* enable GDA interrupt */
#define MOXA_MUST_IER_EGDAI             0x10
 
#define MOXA_MUST_RECV_ISR              (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
 
/* GDA interrupt pending */
#define MOXA_MUST_IIR_GDA               0x1C
#define MOXA_MUST_IIR_RDA               0x04
#define MOXA_MUST_IIR_RTO               0x0C
#define MOXA_MUST_IIR_LSR               0x06
 
/* recieved Xon/Xoff or specical interrupt pending */
#define MOXA_MUST_IIR_XSC               0x10
 
/* RTS/CTS change state interrupt pending */
#define MOXA_MUST_IIR_RTSCTS            0x20
#define MOXA_MUST_IIR_MASK              0x3E
 
#define MOXA_MUST_MCR_XON_FLAG          0x40
#define MOXA_MUST_MCR_XON_ANY           0x80
#define MOXA_MUST_MCR_TX_XON            0x08
 
/* software flow control on chip mask value */
#define MOXA_MUST_EFR_SF_MASK           0x0F
/* send Xon1/Xoff1 */
#define MOXA_MUST_EFR_SF_TX1            0x08
/* send Xon2/Xoff2 */
#define MOXA_MUST_EFR_SF_TX2            0x04
/* send Xon1,Xon2/Xoff1,Xoff2 */
#define MOXA_MUST_EFR_SF_TX12           0x0C
/* don't send Xon/Xoff */
#define MOXA_MUST_EFR_SF_TX_NO          0x00
/* Tx software flow control mask */
#define MOXA_MUST_EFR_SF_TX_MASK        0x0C
/* don't receive Xon/Xoff */
#define MOXA_MUST_EFR_SF_RX_NO          0x00
/* receive Xon1/Xoff1 */
#define MOXA_MUST_EFR_SF_RX1            0x02
/* receive Xon2/Xoff2 */
#define MOXA_MUST_EFR_SF_RX2            0x01
/* receive Xon1,Xon2/Xoff1,Xoff2 */
#define MOXA_MUST_EFR_SF_RX12           0x03
/* Rx software flow control mask */
#define MOXA_MUST_EFR_SF_RX_MASK        0x03
 
#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do {             \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr |= MOXA_MUST_EFR_EFRB_ENABLE;                     \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do {            \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;                    \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do {            \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
        __efr |= MOXA_MUST_EFR_BANK0;                           \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER);    \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do {           \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
        __efr |= MOXA_MUST_EFR_BANK0;                           \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER);   \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define SET_MOXA_MUST_FIFO_VALUE(info) do {                     \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((info)->ioaddr+UART_LCR);                \
        outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
        __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER);     \
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
        __efr |= MOXA_MUST_EFR_BANK1;                           \
        outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER);     \
        outb((u8)((info)->rx_high_water), (info)->ioaddr+       \
                        MOXA_MUST_RBRTH_REGISTER);              \
        outb((u8)((info)->rx_trigger), (info)->ioaddr+          \
                        MOXA_MUST_RBRTI_REGISTER);              \
        outb((u8)((info)->rx_low_water), (info)->ioaddr+        \
                        MOXA_MUST_RBRTL_REGISTER);              \
        outb(__oldlcr, (info)->ioaddr+UART_LCR);                \
} while (0)
 
#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do {            \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
        __efr |= MOXA_MUST_EFR_BANK2;                           \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER);    \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do {             \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
        __efr |= MOXA_MUST_EFR_BANK2;                           \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do {     \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_SF_MASK;                        \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do {  \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_SF_TX_MASK;                     \
        __efr |= MOXA_MUST_EFR_SF_TX1;                          \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_SF_TX_MASK;                     \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do {  \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_SF_RX_MASK;                     \
        __efr |= MOXA_MUST_EFR_SF_RX1;                          \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
        u8      __oldlcr, __efr;                                \
        __oldlcr = inb((baseio)+UART_LCR);                      \
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
        __efr &= ~MOXA_MUST_EFR_SF_RX_MASK;                     \
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
        outb(__oldlcr, (baseio)+UART_LCR);                      \
} while (0)
 
#endif

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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [char/] [mxser_new.h] - Blame information for rev 65

Line No.	Rev	Author	Line
1	62	marcus.erl	`#ifndef _MXSER_H`
2			`#define _MXSER_H`
3
4			`/*`
5			`* Semi-public control interfaces`
6			`*/`
7
8			`/*`
9			`* MOXA ioctls`
10			`*/`
11
12			`#define MOXA 0x400`
13			`#define MOXA_GETDATACOUNT (MOXA + 23)`
14			`#define MOXA_GET_CONF (MOXA + 35)`
15			`#define MOXA_DIAGNOSE (MOXA + 50)`
16			`#define MOXA_CHKPORTENABLE (MOXA + 60)`
17			`#define MOXA_HighSpeedOn (MOXA + 61)`
18			`#define MOXA_GET_MAJOR (MOXA + 63)`
19			`#define MOXA_GET_CUMAJOR (MOXA + 64)`
20			`#define MOXA_GETMSTATUS (MOXA + 65)`
21			`#define MOXA_SET_OP_MODE (MOXA + 66)`
22			`#define MOXA_GET_OP_MODE (MOXA + 67)`
23
24			`#define RS232_MODE 0`
25			`#define RS485_2WIRE_MODE 1`
26			`#define RS422_MODE 2`
27			`#define RS485_4WIRE_MODE 3`
28			`#define OP_MODE_MASK 3`
29
30			`#define MOXA_SDS_RSTICOUNTER (MOXA + 69)`
31			`#define MOXA_ASPP_OQUEUE (MOXA + 70)`
32			`#define MOXA_ASPP_SETBAUD (MOXA + 71)`
33			`#define MOXA_ASPP_GETBAUD (MOXA + 72)`
34			`#define MOXA_ASPP_MON (MOXA + 73)`
35			`#define MOXA_ASPP_LSTATUS (MOXA + 74)`
36			`#define MOXA_ASPP_MON_EXT (MOXA + 75)`
37			`#define MOXA_SET_BAUD_METHOD (MOXA + 76)`
38			`#define MOXA_SET_SPECIAL_BAUD_RATE (MOXA + 77)`
39			`#define MOXA_GET_SPECIAL_BAUD_RATE (MOXA + 78)`
40
41			`/* --------------------------------------------------- */`
42
43			`#define NPPI_NOTIFY_PARITY 0x01`
44			`#define NPPI_NOTIFY_FRAMING 0x02`
45			`#define NPPI_NOTIFY_HW_OVERRUN 0x04`
46			`#define NPPI_NOTIFY_SW_OVERRUN 0x08`
47			`#define NPPI_NOTIFY_BREAK 0x10`
48
49			`#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */`
50			`#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */`
51			`#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */`
52			`#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */`
53
54			`/* follow just for Moxa Must chip define. */`
55			`/* */`
56			`/* when LCR register (offset 0x03) write following value, */`
57			`/* the Must chip will enter enchance mode. And write value */`
58			`/* on EFR (offset 0x02) bit 6,7 to change bank. */`
59			`#define MOXA_MUST_ENTER_ENCHANCE 0xBF`
60
61			`/* when enhance mode enable, access on general bank register */`
62			`#define MOXA_MUST_GDL_REGISTER 0x07`
63			`#define MOXA_MUST_GDL_MASK 0x7F`
64			`#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80`
65
66			`#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */`
67			`/* enchance register bank select and enchance mode setting register */`
68			`/* when LCR register equal to 0xBF */`
69			`#define MOXA_MUST_EFR_REGISTER 0x02`
70			`/* enchance mode enable */`
71			`#define MOXA_MUST_EFR_EFRB_ENABLE 0x10`
72			`/* enchance reister bank set 0, 1, 2 */`
73			`#define MOXA_MUST_EFR_BANK0 0x00`
74			`#define MOXA_MUST_EFR_BANK1 0x40`
75			`#define MOXA_MUST_EFR_BANK2 0x80`
76			`#define MOXA_MUST_EFR_BANK3 0xC0`
77			`#define MOXA_MUST_EFR_BANK_MASK 0xC0`
78
79			`/* set XON1 value register, when LCR=0xBF and change to bank0 */`
80			`#define MOXA_MUST_XON1_REGISTER 0x04`
81
82			`/* set XON2 value register, when LCR=0xBF and change to bank0 */`
83			`#define MOXA_MUST_XON2_REGISTER 0x05`
84
85			`/* set XOFF1 value register, when LCR=0xBF and change to bank0 */`
86			`#define MOXA_MUST_XOFF1_REGISTER 0x06`
87
88			`/* set XOFF2 value register, when LCR=0xBF and change to bank0 */`
89			`#define MOXA_MUST_XOFF2_REGISTER 0x07`
90
91			`#define MOXA_MUST_RBRTL_REGISTER 0x04`
92			`#define MOXA_MUST_RBRTH_REGISTER 0x05`
93			`#define MOXA_MUST_RBRTI_REGISTER 0x06`
94			`#define MOXA_MUST_THRTL_REGISTER 0x07`
95			`#define MOXA_MUST_ENUM_REGISTER 0x04`
96			`#define MOXA_MUST_HWID_REGISTER 0x05`
97			`#define MOXA_MUST_ECR_REGISTER 0x06`
98			`#define MOXA_MUST_CSR_REGISTER 0x07`
99
100			`/* good data mode enable */`
101			`#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20`
102			`/* only good data put into RxFIFO */`
103			`#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10`
104
105			`/* enable CTS interrupt */`
106			`#define MOXA_MUST_IER_ECTSI 0x80`
107			`/* enable RTS interrupt */`
108			`#define MOXA_MUST_IER_ERTSI 0x40`
109			`/* enable Xon/Xoff interrupt */`
110			`#define MOXA_MUST_IER_XINT 0x20`
111			`/* enable GDA interrupt */`
112			`#define MOXA_MUST_IER_EGDAI 0x10`
113
114			`#define MOXA_MUST_RECV_ISR (UART_IER_RDI \| MOXA_MUST_IER_EGDAI)`
115
116			`/* GDA interrupt pending */`
117			`#define MOXA_MUST_IIR_GDA 0x1C`
118			`#define MOXA_MUST_IIR_RDA 0x04`
119			`#define MOXA_MUST_IIR_RTO 0x0C`
120			`#define MOXA_MUST_IIR_LSR 0x06`
121
122			`/* recieved Xon/Xoff or specical interrupt pending */`
123			`#define MOXA_MUST_IIR_XSC 0x10`
124
125			`/* RTS/CTS change state interrupt pending */`
126			`#define MOXA_MUST_IIR_RTSCTS 0x20`
127			`#define MOXA_MUST_IIR_MASK 0x3E`
128
129			`#define MOXA_MUST_MCR_XON_FLAG 0x40`
130			`#define MOXA_MUST_MCR_XON_ANY 0x80`
131			`#define MOXA_MUST_MCR_TX_XON 0x08`
132
133			`/* software flow control on chip mask value */`
134			`#define MOXA_MUST_EFR_SF_MASK 0x0F`
135			`/* send Xon1/Xoff1 */`
136			`#define MOXA_MUST_EFR_SF_TX1 0x08`
137			`/* send Xon2/Xoff2 */`
138			`#define MOXA_MUST_EFR_SF_TX2 0x04`
139			`/* send Xon1,Xon2/Xoff1,Xoff2 */`
140			`#define MOXA_MUST_EFR_SF_TX12 0x0C`
141			`/* don't send Xon/Xoff */`
142			`#define MOXA_MUST_EFR_SF_TX_NO 0x00`
143			`/* Tx software flow control mask */`
144			`#define MOXA_MUST_EFR_SF_TX_MASK 0x0C`
145			`/* don't receive Xon/Xoff */`
146			`#define MOXA_MUST_EFR_SF_RX_NO 0x00`
147			`/* receive Xon1/Xoff1 */`
148			`#define MOXA_MUST_EFR_SF_RX1 0x02`
149			`/* receive Xon2/Xoff2 */`
150			`#define MOXA_MUST_EFR_SF_RX2 0x01`
151			`/* receive Xon1,Xon2/Xoff1,Xoff2 */`
152			`#define MOXA_MUST_EFR_SF_RX12 0x03`
153			`/* Rx software flow control mask */`
154			`#define MOXA_MUST_EFR_SF_RX_MASK 0x03`
155
156			`#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \`
157			`u8 __oldlcr, __efr; \`
158			`__oldlcr = inb((baseio)+UART_LCR); \`
159			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
160			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
161			`__efr \|= MOXA_MUST_EFR_EFRB_ENABLE; \`
162			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
163			`outb(__oldlcr, (baseio)+UART_LCR); \`
164			`} while (0)`
165
166			`#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \`
167			`u8 __oldlcr, __efr; \`
168			`__oldlcr = inb((baseio)+UART_LCR); \`
169			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
170			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
171			`__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \`
172			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
173			`outb(__oldlcr, (baseio)+UART_LCR); \`
174			`} while (0)`
175
176			`#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \`
177			`u8 __oldlcr, __efr; \`
178			`__oldlcr = inb((baseio)+UART_LCR); \`
179			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
180			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
181			`__efr &= ~MOXA_MUST_EFR_BANK_MASK; \`
182			`__efr \|= MOXA_MUST_EFR_BANK0; \`
183			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
184			`outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \`
185			`outb(__oldlcr, (baseio)+UART_LCR); \`
186			`} while (0)`
187
188			`#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \`
189			`u8 __oldlcr, __efr; \`
190			`__oldlcr = inb((baseio)+UART_LCR); \`
191			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
192			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
193			`__efr &= ~MOXA_MUST_EFR_BANK_MASK; \`
194			`__efr \|= MOXA_MUST_EFR_BANK0; \`
195			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
196			`outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \`
197			`outb(__oldlcr, (baseio)+UART_LCR); \`
198			`} while (0)`
199
200			`#define SET_MOXA_MUST_FIFO_VALUE(info) do { \`
201			`u8 __oldlcr, __efr; \`
202			`__oldlcr = inb((info)->ioaddr+UART_LCR); \`
203			`outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\`
204			`__efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \`
205			`__efr &= ~MOXA_MUST_EFR_BANK_MASK; \`
206			`__efr \|= MOXA_MUST_EFR_BANK1; \`
207			`outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \`
208			`outb((u8)((info)->rx_high_water), (info)->ioaddr+ \`
209			`MOXA_MUST_RBRTH_REGISTER); \`
210			`outb((u8)((info)->rx_trigger), (info)->ioaddr+ \`
211			`MOXA_MUST_RBRTI_REGISTER); \`
212			`outb((u8)((info)->rx_low_water), (info)->ioaddr+ \`
213			`MOXA_MUST_RBRTL_REGISTER); \`
214			`outb(__oldlcr, (info)->ioaddr+UART_LCR); \`
215			`} while (0)`
216
217			`#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \`
218			`u8 __oldlcr, __efr; \`
219			`__oldlcr = inb((baseio)+UART_LCR); \`
220			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
221			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
222			`__efr &= ~MOXA_MUST_EFR_BANK_MASK; \`
223			`__efr \|= MOXA_MUST_EFR_BANK2; \`
224			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
225			`outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \`
226			`outb(__oldlcr, (baseio)+UART_LCR); \`
227			`} while (0)`
228
229			`#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \`
230			`u8 __oldlcr, __efr; \`
231			`__oldlcr = inb((baseio)+UART_LCR); \`
232			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
233			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
234			`__efr &= ~MOXA_MUST_EFR_BANK_MASK; \`
235			`__efr \|= MOXA_MUST_EFR_BANK2; \`
236			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
237			`*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \`
238			`outb(__oldlcr, (baseio)+UART_LCR); \`
239			`} while (0)`
240
241			`#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \`
242			`u8 __oldlcr, __efr; \`
243			`__oldlcr = inb((baseio)+UART_LCR); \`
244			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
245			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
246			`__efr &= ~MOXA_MUST_EFR_SF_MASK; \`
247			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
248			`outb(__oldlcr, (baseio)+UART_LCR); \`
249			`} while (0)`
250
251			`#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \`
252			`u8 __oldlcr, __efr; \`
253			`__oldlcr = inb((baseio)+UART_LCR); \`
254			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
255			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
256			`__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \`
257			`__efr \|= MOXA_MUST_EFR_SF_TX1; \`
258			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
259			`outb(__oldlcr, (baseio)+UART_LCR); \`
260			`} while (0)`
261
262			`#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \`
263			`u8 __oldlcr, __efr; \`
264			`__oldlcr = inb((baseio)+UART_LCR); \`
265			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
266			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
267			`__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \`
268			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
269			`outb(__oldlcr, (baseio)+UART_LCR); \`
270			`} while (0)`
271
272			`#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \`
273			`u8 __oldlcr, __efr; \`
274			`__oldlcr = inb((baseio)+UART_LCR); \`
275			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
276			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
277			`__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \`
278			`__efr \|= MOXA_MUST_EFR_SF_RX1; \`
279			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
280			`outb(__oldlcr, (baseio)+UART_LCR); \`
281			`} while (0)`
282
283			`#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \`
284			`u8 __oldlcr, __efr; \`
285			`__oldlcr = inb((baseio)+UART_LCR); \`
286			`outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \`
287			`__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \`
288			`__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \`
289			`outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \`
290			`outb(__oldlcr, (baseio)+UART_LCR); \`
291			`} while (0)`
292
293			`#endif`