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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [char/] [mxser_new.h] - Blame information for rev 65

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1 62 marcus.erl
#ifndef _MXSER_H
2
#define _MXSER_H
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4
/*
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 *      Semi-public control interfaces
6
 */
7
 
8
/*
9
 *      MOXA ioctls
10
 */
11
 
12
#define MOXA                    0x400
13
#define MOXA_GETDATACOUNT       (MOXA + 23)
14
#define MOXA_GET_CONF           (MOXA + 35)
15
#define MOXA_DIAGNOSE           (MOXA + 50)
16
#define MOXA_CHKPORTENABLE      (MOXA + 60)
17
#define MOXA_HighSpeedOn        (MOXA + 61)
18
#define MOXA_GET_MAJOR          (MOXA + 63)
19
#define MOXA_GET_CUMAJOR        (MOXA + 64)
20
#define MOXA_GETMSTATUS         (MOXA + 65)
21
#define MOXA_SET_OP_MODE        (MOXA + 66)
22
#define MOXA_GET_OP_MODE        (MOXA + 67)
23
 
24
#define RS232_MODE              0
25
#define RS485_2WIRE_MODE        1
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#define RS422_MODE              2
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#define RS485_4WIRE_MODE        3
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#define OP_MODE_MASK            3
29
 
30
#define MOXA_SDS_RSTICOUNTER    (MOXA + 69)
31
#define MOXA_ASPP_OQUEUE        (MOXA + 70)
32
#define MOXA_ASPP_SETBAUD       (MOXA + 71)
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#define MOXA_ASPP_GETBAUD       (MOXA + 72)
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#define MOXA_ASPP_MON           (MOXA + 73)
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#define MOXA_ASPP_LSTATUS       (MOXA + 74)
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#define MOXA_ASPP_MON_EXT       (MOXA + 75)
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#define MOXA_SET_BAUD_METHOD    (MOXA + 76)
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#define MOXA_SET_SPECIAL_BAUD_RATE      (MOXA + 77)
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#define MOXA_GET_SPECIAL_BAUD_RATE      (MOXA + 78)
40
 
41
/* --------------------------------------------------- */
42
 
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#define NPPI_NOTIFY_PARITY      0x01
44
#define NPPI_NOTIFY_FRAMING     0x02
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#define NPPI_NOTIFY_HW_OVERRUN  0x04
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#define NPPI_NOTIFY_SW_OVERRUN  0x08
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#define NPPI_NOTIFY_BREAK       0x10
48
 
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#define NPPI_NOTIFY_CTSHOLD         0x01        /* Tx hold by CTS low */
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#define NPPI_NOTIFY_DSRHOLD         0x02        /* Tx hold by DSR low */
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#define NPPI_NOTIFY_XOFFHOLD        0x08        /* Tx hold by Xoff received */
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#define NPPI_NOTIFY_XOFFXENT        0x10        /* Xoff Sent */
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/* follow just for Moxa Must chip define. */
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/* */
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/* when LCR register (offset 0x03) write following value, */
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/* the Must chip will enter enchance mode. And write value */
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/* on EFR (offset 0x02) bit 6,7 to change bank. */
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#define MOXA_MUST_ENTER_ENCHANCE        0xBF
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/* when enhance mode enable, access on general bank register */
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#define MOXA_MUST_GDL_REGISTER          0x07
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#define MOXA_MUST_GDL_MASK              0x7F
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#define MOXA_MUST_GDL_HAS_BAD_DATA      0x80
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#define MOXA_MUST_LSR_RERR              0x80    /* error in receive FIFO */
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/* enchance register bank select and enchance mode setting register */
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/* when LCR register equal to 0xBF */
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#define MOXA_MUST_EFR_REGISTER          0x02
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/* enchance mode enable */
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#define MOXA_MUST_EFR_EFRB_ENABLE       0x10
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/* enchance reister bank set 0, 1, 2 */
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#define MOXA_MUST_EFR_BANK0             0x00
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#define MOXA_MUST_EFR_BANK1             0x40
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#define MOXA_MUST_EFR_BANK2             0x80
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#define MOXA_MUST_EFR_BANK3             0xC0
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#define MOXA_MUST_EFR_BANK_MASK         0xC0
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/* set XON1 value register, when LCR=0xBF and change to bank0 */
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#define MOXA_MUST_XON1_REGISTER         0x04
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/* set XON2 value register, when LCR=0xBF and change to bank0 */
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#define MOXA_MUST_XON2_REGISTER         0x05
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/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
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#define MOXA_MUST_XOFF1_REGISTER        0x06
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/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
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#define MOXA_MUST_XOFF2_REGISTER        0x07
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#define MOXA_MUST_RBRTL_REGISTER        0x04
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#define MOXA_MUST_RBRTH_REGISTER        0x05
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#define MOXA_MUST_RBRTI_REGISTER        0x06
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#define MOXA_MUST_THRTL_REGISTER        0x07
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#define MOXA_MUST_ENUM_REGISTER         0x04
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#define MOXA_MUST_HWID_REGISTER         0x05
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#define MOXA_MUST_ECR_REGISTER          0x06
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#define MOXA_MUST_CSR_REGISTER          0x07
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100
/* good data mode enable */
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#define MOXA_MUST_FCR_GDA_MODE_ENABLE   0x20
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/* only good data put into RxFIFO */
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#define MOXA_MUST_FCR_GDA_ONLY_ENABLE   0x10
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105
/* enable CTS interrupt */
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#define MOXA_MUST_IER_ECTSI             0x80
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/* enable RTS interrupt */
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#define MOXA_MUST_IER_ERTSI             0x40
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/* enable Xon/Xoff interrupt */
110
#define MOXA_MUST_IER_XINT              0x20
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/* enable GDA interrupt */
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#define MOXA_MUST_IER_EGDAI             0x10
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#define MOXA_MUST_RECV_ISR              (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
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116
/* GDA interrupt pending */
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#define MOXA_MUST_IIR_GDA               0x1C
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#define MOXA_MUST_IIR_RDA               0x04
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#define MOXA_MUST_IIR_RTO               0x0C
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#define MOXA_MUST_IIR_LSR               0x06
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122
/* recieved Xon/Xoff or specical interrupt pending */
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#define MOXA_MUST_IIR_XSC               0x10
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125
/* RTS/CTS change state interrupt pending */
126
#define MOXA_MUST_IIR_RTSCTS            0x20
127
#define MOXA_MUST_IIR_MASK              0x3E
128
 
129
#define MOXA_MUST_MCR_XON_FLAG          0x40
130
#define MOXA_MUST_MCR_XON_ANY           0x80
131
#define MOXA_MUST_MCR_TX_XON            0x08
132
 
133
/* software flow control on chip mask value */
134
#define MOXA_MUST_EFR_SF_MASK           0x0F
135
/* send Xon1/Xoff1 */
136
#define MOXA_MUST_EFR_SF_TX1            0x08
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/* send Xon2/Xoff2 */
138
#define MOXA_MUST_EFR_SF_TX2            0x04
139
/* send Xon1,Xon2/Xoff1,Xoff2 */
140
#define MOXA_MUST_EFR_SF_TX12           0x0C
141
/* don't send Xon/Xoff */
142
#define MOXA_MUST_EFR_SF_TX_NO          0x00
143
/* Tx software flow control mask */
144
#define MOXA_MUST_EFR_SF_TX_MASK        0x0C
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/* don't receive Xon/Xoff */
146
#define MOXA_MUST_EFR_SF_RX_NO          0x00
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/* receive Xon1/Xoff1 */
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#define MOXA_MUST_EFR_SF_RX1            0x02
149
/* receive Xon2/Xoff2 */
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#define MOXA_MUST_EFR_SF_RX2            0x01
151
/* receive Xon1,Xon2/Xoff1,Xoff2 */
152
#define MOXA_MUST_EFR_SF_RX12           0x03
153
/* Rx software flow control mask */
154
#define MOXA_MUST_EFR_SF_RX_MASK        0x03
155
 
156
#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do {             \
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        u8      __oldlcr, __efr;                                \
158
        __oldlcr = inb((baseio)+UART_LCR);                      \
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        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
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        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
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        __efr |= MOXA_MUST_EFR_EFRB_ENABLE;                     \
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        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
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        outb(__oldlcr, (baseio)+UART_LCR);                      \
164
} while (0)
165
 
166
#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do {            \
167
        u8      __oldlcr, __efr;                                \
168
        __oldlcr = inb((baseio)+UART_LCR);                      \
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        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
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        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
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        __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;                    \
172
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
173
        outb(__oldlcr, (baseio)+UART_LCR);                      \
174
} while (0)
175
 
176
#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do {            \
177
        u8      __oldlcr, __efr;                                \
178
        __oldlcr = inb((baseio)+UART_LCR);                      \
179
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
180
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
181
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
182
        __efr |= MOXA_MUST_EFR_BANK0;                           \
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        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
184
        outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER);    \
185
        outb(__oldlcr, (baseio)+UART_LCR);                      \
186
} while (0)
187
 
188
#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do {           \
189
        u8      __oldlcr, __efr;                                \
190
        __oldlcr = inb((baseio)+UART_LCR);                      \
191
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
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        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
193
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
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        __efr |= MOXA_MUST_EFR_BANK0;                           \
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        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
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        outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER);   \
197
        outb(__oldlcr, (baseio)+UART_LCR);                      \
198
} while (0)
199
 
200
#define SET_MOXA_MUST_FIFO_VALUE(info) do {                     \
201
        u8      __oldlcr, __efr;                                \
202
        __oldlcr = inb((info)->ioaddr+UART_LCR);                \
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        outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
204
        __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER);     \
205
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
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        __efr |= MOXA_MUST_EFR_BANK1;                           \
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        outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER);     \
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        outb((u8)((info)->rx_high_water), (info)->ioaddr+       \
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                        MOXA_MUST_RBRTH_REGISTER);              \
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        outb((u8)((info)->rx_trigger), (info)->ioaddr+          \
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                        MOXA_MUST_RBRTI_REGISTER);              \
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        outb((u8)((info)->rx_low_water), (info)->ioaddr+        \
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                        MOXA_MUST_RBRTL_REGISTER);              \
214
        outb(__oldlcr, (info)->ioaddr+UART_LCR);                \
215
} while (0)
216
 
217
#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do {            \
218
        u8      __oldlcr, __efr;                                \
219
        __oldlcr = inb((baseio)+UART_LCR);                      \
220
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
221
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
222
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
223
        __efr |= MOXA_MUST_EFR_BANK2;                           \
224
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
225
        outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER);    \
226
        outb(__oldlcr, (baseio)+UART_LCR);                      \
227
} while (0)
228
 
229
#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do {             \
230
        u8      __oldlcr, __efr;                                \
231
        __oldlcr = inb((baseio)+UART_LCR);                      \
232
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
233
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
234
        __efr &= ~MOXA_MUST_EFR_BANK_MASK;                      \
235
        __efr |= MOXA_MUST_EFR_BANK2;                           \
236
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
237
        *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER);           \
238
        outb(__oldlcr, (baseio)+UART_LCR);                      \
239
} while (0)
240
 
241
#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do {     \
242
        u8      __oldlcr, __efr;                                \
243
        __oldlcr = inb((baseio)+UART_LCR);                      \
244
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
245
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
246
        __efr &= ~MOXA_MUST_EFR_SF_MASK;                        \
247
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
248
        outb(__oldlcr, (baseio)+UART_LCR);                      \
249
} while (0)
250
 
251
#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do {  \
252
        u8      __oldlcr, __efr;                                \
253
        __oldlcr = inb((baseio)+UART_LCR);                      \
254
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
255
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
256
        __efr &= ~MOXA_MUST_EFR_SF_TX_MASK;                     \
257
        __efr |= MOXA_MUST_EFR_SF_TX1;                          \
258
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
259
        outb(__oldlcr, (baseio)+UART_LCR);                      \
260
} while (0)
261
 
262
#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
263
        u8      __oldlcr, __efr;                                \
264
        __oldlcr = inb((baseio)+UART_LCR);                      \
265
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
266
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
267
        __efr &= ~MOXA_MUST_EFR_SF_TX_MASK;                     \
268
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
269
        outb(__oldlcr, (baseio)+UART_LCR);                      \
270
} while (0)
271
 
272
#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do {  \
273
        u8      __oldlcr, __efr;                                \
274
        __oldlcr = inb((baseio)+UART_LCR);                      \
275
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
276
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
277
        __efr &= ~MOXA_MUST_EFR_SF_RX_MASK;                     \
278
        __efr |= MOXA_MUST_EFR_SF_RX1;                          \
279
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
280
        outb(__oldlcr, (baseio)+UART_LCR);                      \
281
} while (0)
282
 
283
#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
284
        u8      __oldlcr, __efr;                                \
285
        __oldlcr = inb((baseio)+UART_LCR);                      \
286
        outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);      \
287
        __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);           \
288
        __efr &= ~MOXA_MUST_EFR_SF_RX_MASK;                     \
289
        outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);           \
290
        outb(__oldlcr, (baseio)+UART_LCR);                      \
291
} while (0)
292
 
293
#endif

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