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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [mmc/] [host/] [pxamci.c] - Blame information for rev 78

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/*
 *  linux/drivers/mmc/host/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *      1 and 3 byte data transfers not supported
 *      max block length up to 1023
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mmc/host.h>
 
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/sizes.h>
 
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>
 
#include "pxamci.h"
 
#define DRIVER_NAME     "pxa2xx-mci"
 
#define NR_SG   1
#define CLKRT_OFF       (~0)
 
struct pxamci_host {
        struct mmc_host         *mmc;
        spinlock_t              lock;
        struct resource         *res;
        void __iomem            *base;
        struct clk              *clk;
        unsigned long           clkrate;
        int                     irq;
        int                     dma;
        unsigned int            clkrt;
        unsigned int            cmdat;
        unsigned int            imask;
        unsigned int            power_mode;
        struct pxamci_platform_data *pdata;
 
        struct mmc_request      *mrq;
        struct mmc_command      *cmd;
        struct mmc_data         *data;
 
        dma_addr_t              sg_dma;
        struct pxa_dma_desc     *sg_cpu;
        unsigned int            dma_len;
 
        unsigned int            dma_dir;
};
 
static void pxamci_stop_clock(struct pxamci_host *host)
{
        if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
                unsigned long timeout = 10000;
                unsigned int v;
 
                writel(STOP_CLOCK, host->base + MMC_STRPCL);
 
                do {
                        v = readl(host->base + MMC_STAT);
                        if (!(v & STAT_CLK_EN))
                                break;
                        udelay(1);
                } while (timeout--);
 
                if (v & STAT_CLK_EN)
                        dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
        }
}
 
static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
        host->imask &= ~mask;
        writel(host->imask, host->base + MMC_I_MASK);
        spin_unlock_irqrestore(&host->lock, flags);
}
 
static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
        host->imask |= mask;
        writel(host->imask, host->base + MMC_I_MASK);
        spin_unlock_irqrestore(&host->lock, flags);
}
 
static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
        unsigned int nob = data->blocks;
        unsigned long long clks;
        unsigned int timeout;
        u32 dcmd;
        int i;
 
        host->data = data;
 
        if (data->flags & MMC_DATA_STREAM)
                nob = 0xffff;
 
        writel(nob, host->base + MMC_NOB);
        writel(data->blksz, host->base + MMC_BLKLEN);
 
        clks = (unsigned long long)data->timeout_ns * host->clkrate;
        do_div(clks, 1000000000UL);
        timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
        writel((timeout + 255) / 256, host->base + MMC_RDTO);
 
        if (data->flags & MMC_DATA_READ) {
                host->dma_dir = DMA_FROM_DEVICE;
                dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
                DRCMRTXMMC = 0;
                DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
        } else {
                host->dma_dir = DMA_TO_DEVICE;
                dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
                DRCMRRXMMC = 0;
                DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
        }
 
        dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
 
        host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
                                   host->dma_dir);
 
        for (i = 0; i < host->dma_len; i++) {
                unsigned int length = sg_dma_len(&data->sg[i]);
                host->sg_cpu[i].dcmd = dcmd | length;
                if (length & 31 && !(data->flags & MMC_DATA_READ))
                        host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
                if (data->flags & MMC_DATA_READ) {
                        host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
                        host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
                } else {
                        host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
                        host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
                }
                host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
                                        sizeof(struct pxa_dma_desc);
        }
        host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
        wmb();
 
        DDADR(host->dma) = host->sg_dma;
        DCSR(host->dma) = DCSR_RUN;
}
 
static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
        WARN_ON(host->cmd != NULL);
        host->cmd = cmd;
 
        if (cmd->flags & MMC_RSP_BUSY)
                cmdat |= CMDAT_BUSY;
 
#define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
        switch (RSP_TYPE(mmc_resp_type(cmd))) {
        case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
                cmdat |= CMDAT_RESP_SHORT;
                break;
        case RSP_TYPE(MMC_RSP_R3):
                cmdat |= CMDAT_RESP_R3;
                break;
        case RSP_TYPE(MMC_RSP_R2):
                cmdat |= CMDAT_RESP_R2;
                break;
        default:
                break;
        }
 
        writel(cmd->opcode, host->base + MMC_CMD);
        writel(cmd->arg >> 16, host->base + MMC_ARGH);
        writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
        writel(cmdat, host->base + MMC_CMDAT);
        writel(host->clkrt, host->base + MMC_CLKRT);
 
        writel(START_CLOCK, host->base + MMC_STRPCL);
 
        pxamci_enable_irq(host, END_CMD_RES);
}
 
static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
        host->mrq = NULL;
        host->cmd = NULL;
        host->data = NULL;
        mmc_request_done(host->mmc, mrq);
}
 
static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
        struct mmc_command *cmd = host->cmd;
        int i;
        u32 v;
 
        if (!cmd)
                return 0;
 
        host->cmd = NULL;
 
        /*
         * Did I mention this is Sick.  We always need to
         * discard the upper 8 bits of the first 16-bit word.
         */
        v = readl(host->base + MMC_RES) & 0xffff;
        for (i = 0; i < 4; i++) {
                u32 w1 = readl(host->base + MMC_RES) & 0xffff;
                u32 w2 = readl(host->base + MMC_RES) & 0xffff;
                cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
                v = w2;
        }
 
        if (stat & STAT_TIME_OUT_RESPONSE) {
                cmd->error = -ETIMEDOUT;
        } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
                /*
                 * workaround for erratum #42:
                 * Intel PXA27x Family Processor Specification Update Rev 001
                 * A bogus CRC error can appear if the msb of a 136 bit
                 * response is a one.
                 */
                if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
                        pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
                } else
#endif
                cmd->error = -EILSEQ;
        }
 
        pxamci_disable_irq(host, END_CMD_RES);
        if (host->data && !cmd->error) {
                pxamci_enable_irq(host, DATA_TRAN_DONE);
        } else {
                pxamci_finish_request(host, host->mrq);
        }
 
        return 1;
}
 
static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
        struct mmc_data *data = host->data;
 
        if (!data)
                return 0;
 
        DCSR(host->dma) = 0;
        dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
                     host->dma_dir);
 
        if (stat & STAT_READ_TIME_OUT)
                data->error = -ETIMEDOUT;
        else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
                data->error = -EILSEQ;
 
        /*
         * There appears to be a hardware design bug here.  There seems to
         * be no way to find out how much data was transferred to the card.
         * This means that if there was an error on any block, we mark all
         * data blocks as being in error.
         */
        if (!data->error)
                data->bytes_xfered = data->blocks * data->blksz;
        else
                data->bytes_xfered = 0;
 
        pxamci_disable_irq(host, DATA_TRAN_DONE);
 
        host->data = NULL;
        if (host->mrq->stop) {
                pxamci_stop_clock(host);
                pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
        } else {
                pxamci_finish_request(host, host->mrq);
        }
 
        return 1;
}
 
static irqreturn_t pxamci_irq(int irq, void *devid)
{
        struct pxamci_host *host = devid;
        unsigned int ireg;
        int handled = 0;
 
        ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
 
        if (ireg) {
                unsigned stat = readl(host->base + MMC_STAT);
 
                pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
 
                if (ireg & END_CMD_RES)
                        handled |= pxamci_cmd_done(host, stat);
                if (ireg & DATA_TRAN_DONE)
                        handled |= pxamci_data_done(host, stat);
                if (ireg & SDIO_INT) {
                        mmc_signal_sdio_irq(host->mmc);
                        handled = 1;
                }
        }
 
        return IRQ_RETVAL(handled);
}
 
static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
        struct pxamci_host *host = mmc_priv(mmc);
        unsigned int cmdat;
 
        WARN_ON(host->mrq != NULL);
 
        host->mrq = mrq;
 
        pxamci_stop_clock(host);
 
        cmdat = host->cmdat;
        host->cmdat &= ~CMDAT_INIT;
 
        if (mrq->data) {
                pxamci_setup_data(host, mrq->data);
 
                cmdat &= ~CMDAT_BUSY;
                cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
                if (mrq->data->flags & MMC_DATA_WRITE)
                        cmdat |= CMDAT_WRITE;
 
                if (mrq->data->flags & MMC_DATA_STREAM)
                        cmdat |= CMDAT_STREAM;
        }
 
        pxamci_start_cmd(host, mrq->cmd, cmdat);
}
 
static int pxamci_get_ro(struct mmc_host *mmc)
{
        struct pxamci_host *host = mmc_priv(mmc);
 
        if (host->pdata && host->pdata->get_ro)
                return host->pdata->get_ro(mmc_dev(mmc));
        /* Host doesn't support read only detection so assume writeable */
        return 0;
}
 
static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
        struct pxamci_host *host = mmc_priv(mmc);
 
        if (ios->clock) {
                unsigned long rate = host->clkrate;
                unsigned int clk = rate / ios->clock;
 
                if (host->clkrt == CLKRT_OFF)
                        clk_enable(host->clk);
 
                /*
                 * clk might result in a lower divisor than we
                 * desire.  check for that condition and adjust
                 * as appropriate.
                 */
                if (rate / clk > ios->clock)
                        clk <<= 1;
                host->clkrt = fls(clk) - 1;
 
                /*
                 * we write clkrt on the next command
                 */
        } else {
                pxamci_stop_clock(host);
                if (host->clkrt != CLKRT_OFF) {
                        host->clkrt = CLKRT_OFF;
                        clk_disable(host->clk);
                }
        }
 
        if (host->power_mode != ios->power_mode) {
                host->power_mode = ios->power_mode;
 
                if (host->pdata && host->pdata->setpower)
                        host->pdata->setpower(mmc_dev(mmc), ios->vdd);
 
                if (ios->power_mode == MMC_POWER_ON)
                        host->cmdat |= CMDAT_INIT;
        }
 
        if (ios->bus_width == MMC_BUS_WIDTH_4)
                host->cmdat |= CMDAT_SD_4DAT;
        else
                host->cmdat &= ~CMDAT_SD_4DAT;
 
        pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
                 host->clkrt, host->cmdat);
}
 
static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
{
        struct pxamci_host *pxa_host = mmc_priv(host);
 
        if (enable)
                pxamci_enable_irq(pxa_host, SDIO_INT);
        else
                pxamci_disable_irq(pxa_host, SDIO_INT);
}
 
static const struct mmc_host_ops pxamci_ops = {
        .request                = pxamci_request,
        .get_ro                 = pxamci_get_ro,
        .set_ios                = pxamci_set_ios,
        .enable_sdio_irq        = pxamci_enable_sdio_irq,
};
 
static void pxamci_dma_irq(int dma, void *devid)
{
        struct pxamci_host *host = devid;
        int dcsr = DCSR(dma);
        DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;
 
        if (dcsr & DCSR_ENDINTR) {
                writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
        } else {
                printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",
                       mmc_hostname(host->mmc), dma, dcsr);
                host->data->error = -EIO;
                pxamci_data_done(host, 0);
        }
}
 
static irqreturn_t pxamci_detect_irq(int irq, void *devid)
{
        struct pxamci_host *host = mmc_priv(devid);
 
        mmc_detect_change(devid, host->pdata->detect_delay);
        return IRQ_HANDLED;
}
 
static int pxamci_probe(struct platform_device *pdev)
{
        struct mmc_host *mmc;
        struct pxamci_host *host = NULL;
        struct resource *r;
        int ret, irq;
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        irq = platform_get_irq(pdev, 0);
        if (!r || irq < 0)
                return -ENXIO;
 
        r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
        if (!r)
                return -EBUSY;
 
        mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
        if (!mmc) {
                ret = -ENOMEM;
                goto out;
        }
 
        mmc->ops = &pxamci_ops;
 
        /*
         * We can do SG-DMA, but we don't because we never know how much
         * data we successfully wrote to the card.
         */
        mmc->max_phys_segs = NR_SG;
 
        /*
         * Our hardware DMA can handle a maximum of one page per SG entry.
         */
        mmc->max_seg_size = PAGE_SIZE;
 
        /*
         * Block length register is only 10 bits before PXA27x.
         */
        mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;
 
        /*
         * Block count register is 16 bits.
         */
        mmc->max_blk_count = 65535;
 
        host = mmc_priv(mmc);
        host->mmc = mmc;
        host->dma = -1;
        host->pdata = pdev->dev.platform_data;
        host->clkrt = CLKRT_OFF;
 
        host->clk = clk_get(&pdev->dev, "MMCCLK");
        if (IS_ERR(host->clk)) {
                ret = PTR_ERR(host->clk);
                host->clk = NULL;
                goto out;
        }
 
        host->clkrate = clk_get_rate(host->clk);
 
        /*
         * Calculate minimum clock rate, rounding up.
         */
        mmc->f_min = (host->clkrate + 63) / 64;
        mmc->f_max = host->clkrate;
 
        mmc->ocr_avail = host->pdata ?
                         host->pdata->ocr_mask :
                         MMC_VDD_32_33|MMC_VDD_33_34;
        mmc->caps = 0;
        host->cmdat = 0;
        if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
                mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
                host->cmdat |= CMDAT_SDIO_INT_EN;
        }
 
        host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
        if (!host->sg_cpu) {
                ret = -ENOMEM;
                goto out;
        }
 
        spin_lock_init(&host->lock);
        host->res = r;
        host->irq = irq;
        host->imask = MMC_I_MASK_ALL;
 
        host->base = ioremap(r->start, SZ_4K);
        if (!host->base) {
                ret = -ENOMEM;
                goto out;
        }
 
        /*
         * Ensure that the host controller is shut down, and setup
         * with our defaults.
         */
        pxamci_stop_clock(host);
        writel(0, host->base + MMC_SPI);
        writel(64, host->base + MMC_RESTO);
        writel(host->imask, host->base + MMC_I_MASK);
 
        host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
                                    pxamci_dma_irq, host);
        if (host->dma < 0) {
                ret = -EBUSY;
                goto out;
        }
 
        ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
        if (ret)
                goto out;
 
        platform_set_drvdata(pdev, mmc);
 
        if (host->pdata && host->pdata->init)
                host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
 
        mmc_add_host(mmc);
 
        return 0;
 
 out:
        if (host) {
                if (host->dma >= 0)
                        pxa_free_dma(host->dma);
                if (host->base)
                        iounmap(host->base);
                if (host->sg_cpu)
                        dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
                if (host->clk)
                        clk_put(host->clk);
        }
        if (mmc)
                mmc_free_host(mmc);
        release_resource(r);
        return ret;
}
 
static int pxamci_remove(struct platform_device *pdev)
{
        struct mmc_host *mmc = platform_get_drvdata(pdev);
 
        platform_set_drvdata(pdev, NULL);
 
        if (mmc) {
                struct pxamci_host *host = mmc_priv(mmc);
 
                if (host->pdata && host->pdata->exit)
                        host->pdata->exit(&pdev->dev, mmc);
 
                mmc_remove_host(mmc);
 
                pxamci_stop_clock(host);
                writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
                       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
                       host->base + MMC_I_MASK);
 
                DRCMRRXMMC = 0;
                DRCMRTXMMC = 0;
 
                free_irq(host->irq, host);
                pxa_free_dma(host->dma);
                iounmap(host->base);
                dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 
                clk_put(host->clk);
 
                release_resource(host->res);
 
                mmc_free_host(mmc);
        }
        return 0;
}
 
#ifdef CONFIG_PM
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
{
        struct mmc_host *mmc = platform_get_drvdata(dev);
        int ret = 0;
 
        if (mmc)
                ret = mmc_suspend_host(mmc, state);
 
        return ret;
}
 
static int pxamci_resume(struct platform_device *dev)
{
        struct mmc_host *mmc = platform_get_drvdata(dev);
        int ret = 0;
 
        if (mmc)
                ret = mmc_resume_host(mmc);
 
        return ret;
}
#else
#define pxamci_suspend  NULL
#define pxamci_resume   NULL
#endif
 
static struct platform_driver pxamci_driver = {
        .probe          = pxamci_probe,
        .remove         = pxamci_remove,
        .suspend        = pxamci_suspend,
        .resume         = pxamci_resume,
        .driver         = {
                .name   = DRIVER_NAME,
        },
};
 
static int __init pxamci_init(void)
{
        return platform_driver_register(&pxamci_driver);
}
 
static void __exit pxamci_exit(void)
{
        platform_driver_unregister(&pxamci_driver);
}
 
module_init(pxamci_init);
module_exit(pxamci_exit);
 
MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");

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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [mmc/] [host/] [pxamci.c] - Blame information for rev 78

Line No.	Rev	Author	Line
1	62	marcus.erl	`/*`
2			`* linux/drivers/mmc/host/pxa.c - PXA MMCI driver`
3			`*`
4			`* Copyright (C) 2003 Russell King, All Rights Reserved.`
5			`*`
6			`* This program is free software; you can redistribute it and/or modify`
7			`* it under the terms of the GNU General Public License version 2 as`
8			`* published by the Free Software Foundation.`
9			`*`
10			`* This hardware is really sick:`
11			`* - No way to clear interrupts.`
12			`* - Have to turn off the clock whenever we touch the device.`
13			`* - Doesn't tell you how many data blocks were transferred.`
14			`* Yuck!`
15			`*`
16			`* 1 and 3 byte data transfers not supported`
17			`* max block length up to 1023`
18			`*/`
19			`#include <linux/module.h>`
20			`#include <linux/init.h>`
21			`#include <linux/ioport.h>`
22			`#include <linux/platform_device.h>`
23			`#include <linux/delay.h>`
24			`#include <linux/interrupt.h>`
25			`#include <linux/dma-mapping.h>`
26			`#include <linux/clk.h>`
27			`#include <linux/err.h>`
28			`#include <linux/mmc/host.h>`
29
30			`#include <asm/dma.h>`
31			`#include <asm/io.h>`
32			`#include <asm/sizes.h>`
33
34			`#include <asm/arch/pxa-regs.h>`
35			`#include <asm/arch/mmc.h>`
36
37			`#include "pxamci.h"`
38
39			`#define DRIVER_NAME "pxa2xx-mci"`
40
41			`#define NR_SG 1`
42			`#define CLKRT_OFF (~0)`
43
44			`struct pxamci_host {`
45			`struct mmc_host *mmc;`
46			`spinlock_t lock;`
47			`struct resource *res;`
48			`void __iomem *base;`
49			`struct clk *clk;`
50			`unsigned long clkrate;`
51			`int irq;`
52			`int dma;`
53			`unsigned int clkrt;`
54			`unsigned int cmdat;`
55			`unsigned int imask;`
56			`unsigned int power_mode;`
57			`struct pxamci_platform_data *pdata;`
58
59			`struct mmc_request *mrq;`
60			`struct mmc_command *cmd;`
61			`struct mmc_data *data;`
62
63			`dma_addr_t sg_dma;`
64			`struct pxa_dma_desc *sg_cpu;`
65			`unsigned int dma_len;`
66
67			`unsigned int dma_dir;`
68			`};`
69
70			`static void pxamci_stop_clock(struct pxamci_host *host)`
71			`{`
72			`if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {`
73			`unsigned long timeout = 10000;`
74			`unsigned int v;`
75
76			`writel(STOP_CLOCK, host->base + MMC_STRPCL);`
77
78			`do {`
79			`v = readl(host->base + MMC_STAT);`
80			`if (!(v & STAT_CLK_EN))`
81			`break;`
82			`udelay(1);`
83			`} while (timeout--);`
84
85			`if (v & STAT_CLK_EN)`
86			`dev_err(mmc_dev(host->mmc), "unable to stop clock\n");`
87			`}`
88			`}`
89
90			`static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)`
91			`{`
92			`unsigned long flags;`
93
94			`spin_lock_irqsave(&host->lock, flags);`
95			`host->imask &= ~mask;`
96			`writel(host->imask, host->base + MMC_I_MASK);`
97			`spin_unlock_irqrestore(&host->lock, flags);`
98			`}`
99
100			`static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)`
101			`{`
102			`unsigned long flags;`
103
104			`spin_lock_irqsave(&host->lock, flags);`
105			`host->imask \|= mask;`
106			`writel(host->imask, host->base + MMC_I_MASK);`
107			`spin_unlock_irqrestore(&host->lock, flags);`
108			`}`
109
110			`static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)`
111			`{`
112			`unsigned int nob = data->blocks;`
113			`unsigned long long clks;`
114			`unsigned int timeout;`
115			`u32 dcmd;`
116			`int i;`
117
118			`host->data = data;`
119
120			`if (data->flags & MMC_DATA_STREAM)`
121			`nob = 0xffff;`
122
123			`writel(nob, host->base + MMC_NOB);`
124			`writel(data->blksz, host->base + MMC_BLKLEN);`
125
126			`clks = (unsigned long long)data->timeout_ns * host->clkrate;`
127			`do_div(clks, 1000000000UL);`
128			`timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);`
129			`writel((timeout + 255) / 256, host->base + MMC_RDTO);`
130
131			`if (data->flags & MMC_DATA_READ) {`
132			`host->dma_dir = DMA_FROM_DEVICE;`
133			`dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;`
134			`DRCMRTXMMC = 0;`
135			`DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;`
136			`} else {`
137			`host->dma_dir = DMA_TO_DEVICE;`
138			`dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;`
139			`DRCMRRXMMC = 0;`
140			`DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;`
141			`}`
142
143			`dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;`
144
145			`host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,`
146			`host->dma_dir);`
147
148			`for (i = 0; i < host->dma_len; i++) {`
149			`unsigned int length = sg_dma_len(&data->sg[i]);`
150			`host->sg_cpu[i].dcmd = dcmd \| length;`
151			`if (length & 31 && !(data->flags & MMC_DATA_READ))`
152			`host->sg_cpu[i].dcmd \|= DCMD_ENDIRQEN;`
153			`if (data->flags & MMC_DATA_READ) {`
154			`host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;`
155			`host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);`
156			`} else {`
157			`host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);`
158			`host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;`
159			`}`
160			`host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *`
161			`sizeof(struct pxa_dma_desc);`
162			`}`
163			`host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;`
164			`wmb();`
165
166			`DDADR(host->dma) = host->sg_dma;`
167			`DCSR(host->dma) = DCSR_RUN;`
168			`}`
169
170			`static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)`
171			`{`
172			`WARN_ON(host->cmd != NULL);`
173			`host->cmd = cmd;`
174
175			`if (cmd->flags & MMC_RSP_BUSY)`
176			`cmdat \|= CMDAT_BUSY;`
177
178			`#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY\|MMC_RSP_OPCODE))`
179			`switch (RSP_TYPE(mmc_resp_type(cmd))) {`
180			`case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */`
181			`cmdat \|= CMDAT_RESP_SHORT;`
182			`break;`
183			`case RSP_TYPE(MMC_RSP_R3):`
184			`cmdat \|= CMDAT_RESP_R3;`
185			`break;`
186			`case RSP_TYPE(MMC_RSP_R2):`
187			`cmdat \|= CMDAT_RESP_R2;`
188			`break;`
189			`default:`
190			`break;`
191			`}`
192
193			`writel(cmd->opcode, host->base + MMC_CMD);`
194			`writel(cmd->arg >> 16, host->base + MMC_ARGH);`
195			`writel(cmd->arg & 0xffff, host->base + MMC_ARGL);`
196			`writel(cmdat, host->base + MMC_CMDAT);`
197			`writel(host->clkrt, host->base + MMC_CLKRT);`
198
199			`writel(START_CLOCK, host->base + MMC_STRPCL);`
200
201			`pxamci_enable_irq(host, END_CMD_RES);`
202			`}`
203
204			`static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)`
205			`{`
206			`host->mrq = NULL;`
207			`host->cmd = NULL;`
208			`host->data = NULL;`
209			`mmc_request_done(host->mmc, mrq);`
210			`}`
211
212			`static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)`
213			`{`
214			`struct mmc_command *cmd = host->cmd;`
215			`int i;`
216			`u32 v;`
217
218			`if (!cmd)`
219			`return 0;`
220
221			`host->cmd = NULL;`
222
223			`/*`
224			`* Did I mention this is Sick. We always need to`
225			`* discard the upper 8 bits of the first 16-bit word.`
226			`*/`
227			`v = readl(host->base + MMC_RES) & 0xffff;`
228			`for (i = 0; i < 4; i++) {`
229			`u32 w1 = readl(host->base + MMC_RES) & 0xffff;`
230			`u32 w2 = readl(host->base + MMC_RES) & 0xffff;`
231			`cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;`
232			`v = w2;`
233			`}`
234
235			`if (stat & STAT_TIME_OUT_RESPONSE) {`
236			`cmd->error = -ETIMEDOUT;`
237			`} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {`
238			`#ifdef CONFIG_PXA27x`
239			`/*`
240			`* workaround for erratum #42:`
241			`* Intel PXA27x Family Processor Specification Update Rev 001`
242			`* A bogus CRC error can appear if the msb of a 136 bit`
243			`* response is a one.`
244			`*/`
245			`if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {`
246			`pr_debug("ignoring CRC from command %d - risky\n", cmd->opcode);`
247			`} else`
248			`#endif`
249			`cmd->error = -EILSEQ;`
250			`}`
251
252			`pxamci_disable_irq(host, END_CMD_RES);`
253			`if (host->data && !cmd->error) {`
254			`pxamci_enable_irq(host, DATA_TRAN_DONE);`
255			`} else {`
256			`pxamci_finish_request(host, host->mrq);`
257			`}`
258
259			`return 1;`
260			`}`
261
262			`static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)`
263			`{`
264			`struct mmc_data *data = host->data;`
265
266			`if (!data)`
267			`return 0;`
268
269			`DCSR(host->dma) = 0;`
270			`dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,`
271			`host->dma_dir);`
272
273			`if (stat & STAT_READ_TIME_OUT)`
274			`data->error = -ETIMEDOUT;`
275			`else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))`
276			`data->error = -EILSEQ;`
277
278			`/*`
279			`* There appears to be a hardware design bug here. There seems to`
280			`* be no way to find out how much data was transferred to the card.`
281			`* This means that if there was an error on any block, we mark all`
282			`* data blocks as being in error.`
283			`*/`
284			`if (!data->error)`
285			`data->bytes_xfered = data->blocks * data->blksz;`
286			`else`
287			`data->bytes_xfered = 0;`
288
289			`pxamci_disable_irq(host, DATA_TRAN_DONE);`
290
291			`host->data = NULL;`
292			`if (host->mrq->stop) {`
293			`pxamci_stop_clock(host);`
294			`pxamci_start_cmd(host, host->mrq->stop, host->cmdat);`
295			`} else {`
296			`pxamci_finish_request(host, host->mrq);`
297			`}`
298
299			`return 1;`
300			`}`
301
302			`static irqreturn_t pxamci_irq(int irq, void *devid)`
303			`{`
304			`struct pxamci_host *host = devid;`
305			`unsigned int ireg;`
306			`int handled = 0;`
307
308			`ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);`
309
310			`if (ireg) {`
311			`unsigned stat = readl(host->base + MMC_STAT);`
312
313			`pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);`
314
315			`if (ireg & END_CMD_RES)`
316			`handled \|= pxamci_cmd_done(host, stat);`
317			`if (ireg & DATA_TRAN_DONE)`
318			`handled \|= pxamci_data_done(host, stat);`
319			`if (ireg & SDIO_INT) {`
320			`mmc_signal_sdio_irq(host->mmc);`
321			`handled = 1;`
322			`}`
323			`}`
324
325			`return IRQ_RETVAL(handled);`
326			`}`
327
328			`static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)`
329			`{`
330			`struct pxamci_host *host = mmc_priv(mmc);`
331			`unsigned int cmdat;`
332
333			`WARN_ON(host->mrq != NULL);`
334
335			`host->mrq = mrq;`
336
337			`pxamci_stop_clock(host);`
338
339			`cmdat = host->cmdat;`
340			`host->cmdat &= ~CMDAT_INIT;`
341
342			`if (mrq->data) {`
343			`pxamci_setup_data(host, mrq->data);`
344
345			`cmdat &= ~CMDAT_BUSY;`
346			`cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;`
347			`if (mrq->data->flags & MMC_DATA_WRITE)`
348			`cmdat \|= CMDAT_WRITE;`
349
350			`if (mrq->data->flags & MMC_DATA_STREAM)`
351			`cmdat \|= CMDAT_STREAM;`
352			`}`
353
354			`pxamci_start_cmd(host, mrq->cmd, cmdat);`
355			`}`
356
357			`static int pxamci_get_ro(struct mmc_host *mmc)`
358			`{`
359			`struct pxamci_host *host = mmc_priv(mmc);`
360
361			`if (host->pdata && host->pdata->get_ro)`
362			`return host->pdata->get_ro(mmc_dev(mmc));`
363			`/* Host doesn't support read only detection so assume writeable */`
364			`return 0;`
365			`}`
366
367			`static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)`
368			`{`
369			`struct pxamci_host *host = mmc_priv(mmc);`
370
371			`if (ios->clock) {`
372			`unsigned long rate = host->clkrate;`
373			`unsigned int clk = rate / ios->clock;`
374
375			`if (host->clkrt == CLKRT_OFF)`
376			`clk_enable(host->clk);`
377
378			`/*`
379			`* clk might result in a lower divisor than we`
380			`* desire. check for that condition and adjust`
381			`* as appropriate.`
382			`*/`
383			`if (rate / clk > ios->clock)`
384			`clk <<= 1;`
385			`host->clkrt = fls(clk) - 1;`
386
387			`/*`
388			`* we write clkrt on the next command`
389			`*/`
390			`} else {`
391			`pxamci_stop_clock(host);`
392			`if (host->clkrt != CLKRT_OFF) {`
393			`host->clkrt = CLKRT_OFF;`
394			`clk_disable(host->clk);`
395			`}`
396			`}`
397
398			`if (host->power_mode != ios->power_mode) {`
399			`host->power_mode = ios->power_mode;`
400
401			`if (host->pdata && host->pdata->setpower)`
402			`host->pdata->setpower(mmc_dev(mmc), ios->vdd);`
403
404			`if (ios->power_mode == MMC_POWER_ON)`
405			`host->cmdat \|= CMDAT_INIT;`
406			`}`
407
408			`if (ios->bus_width == MMC_BUS_WIDTH_4)`
409			`host->cmdat \|= CMDAT_SD_4DAT;`
410			`else`
411			`host->cmdat &= ~CMDAT_SD_4DAT;`
412
413			`pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",`
414			`host->clkrt, host->cmdat);`
415			`}`
416
417			`static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)`
418			`{`
419			`struct pxamci_host *pxa_host = mmc_priv(host);`
420
421			`if (enable)`
422			`pxamci_enable_irq(pxa_host, SDIO_INT);`
423			`else`
424			`pxamci_disable_irq(pxa_host, SDIO_INT);`
425			`}`
426
427			`static const struct mmc_host_ops pxamci_ops = {`
428			`.request = pxamci_request,`
429			`.get_ro = pxamci_get_ro,`
430			`.set_ios = pxamci_set_ios,`
431			`.enable_sdio_irq = pxamci_enable_sdio_irq,`
432			`};`
433
434			`static void pxamci_dma_irq(int dma, void *devid)`
435			`{`
436			`struct pxamci_host *host = devid;`
437			`int dcsr = DCSR(dma);`
438			`DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;`
439
440			`if (dcsr & DCSR_ENDINTR) {`
441			`writel(BUF_PART_FULL, host->base + MMC_PRTBUF);`
442			`} else {`
443			`printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",`
444			`mmc_hostname(host->mmc), dma, dcsr);`
445			`host->data->error = -EIO;`
446			`pxamci_data_done(host, 0);`
447			`}`
448			`}`
449
450			`static irqreturn_t pxamci_detect_irq(int irq, void *devid)`
451			`{`
452			`struct pxamci_host *host = mmc_priv(devid);`
453
454			`mmc_detect_change(devid, host->pdata->detect_delay);`
455			`return IRQ_HANDLED;`
456			`}`
457
458			`static int pxamci_probe(struct platform_device *pdev)`
459			`{`
460			`struct mmc_host *mmc;`
461			`struct pxamci_host *host = NULL;`
462			`struct resource *r;`
463			`int ret, irq;`
464
465			`r = platform_get_resource(pdev, IORESOURCE_MEM, 0);`
466			`irq = platform_get_irq(pdev, 0);`
467			`if (!r \|\| irq < 0)`
468			`return -ENXIO;`
469
470			`r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);`
471			`if (!r)`
472			`return -EBUSY;`
473
474			`mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);`
475			`if (!mmc) {`
476			`ret = -ENOMEM;`
477			`goto out;`
478			`}`
479
480			`mmc->ops = &pxamci_ops;`
481
482			`/*`
483			`* We can do SG-DMA, but we don't because we never know how much`
484			`* data we successfully wrote to the card.`
485			`*/`
486			`mmc->max_phys_segs = NR_SG;`
487
488			`/*`
489			`* Our hardware DMA can handle a maximum of one page per SG entry.`
490			`*/`
491			`mmc->max_seg_size = PAGE_SIZE;`
492
493			`/*`
494			`* Block length register is only 10 bits before PXA27x.`
495			`*/`
496			`mmc->max_blk_size = (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) ? 1023 : 2048;`
497
498			`/*`
499			`* Block count register is 16 bits.`
500			`*/`
501			`mmc->max_blk_count = 65535;`
502
503			`host = mmc_priv(mmc);`
504			`host->mmc = mmc;`
505			`host->dma = -1;`
506			`host->pdata = pdev->dev.platform_data;`
507			`host->clkrt = CLKRT_OFF;`
508
509			`host->clk = clk_get(&pdev->dev, "MMCCLK");`
510			`if (IS_ERR(host->clk)) {`
511			`ret = PTR_ERR(host->clk);`
512			`host->clk = NULL;`
513			`goto out;`
514			`}`
515
516			`host->clkrate = clk_get_rate(host->clk);`
517
518			`/*`
519			`* Calculate minimum clock rate, rounding up.`
520			`*/`
521			`mmc->f_min = (host->clkrate + 63) / 64;`
522			`mmc->f_max = host->clkrate;`
523
524			`mmc->ocr_avail = host->pdata ?`
525			`host->pdata->ocr_mask :`
526			`MMC_VDD_32_33\|MMC_VDD_33_34;`
527			`mmc->caps = 0;`
528			`host->cmdat = 0;`
529			`if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {`
530			`mmc->caps \|= MMC_CAP_4_BIT_DATA \| MMC_CAP_SDIO_IRQ;`
531			`host->cmdat \|= CMDAT_SDIO_INT_EN;`
532			`}`
533
534			`host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);`
535			`if (!host->sg_cpu) {`
536			`ret = -ENOMEM;`
537			`goto out;`
538			`}`
539
540			`spin_lock_init(&host->lock);`
541			`host->res = r;`
542			`host->irq = irq;`
543			`host->imask = MMC_I_MASK_ALL;`
544
545			`host->base = ioremap(r->start, SZ_4K);`
546			`if (!host->base) {`
547			`ret = -ENOMEM;`
548			`goto out;`
549			`}`
550
551			`/*`
552			`* Ensure that the host controller is shut down, and setup`
553			`* with our defaults.`
554			`*/`
555			`pxamci_stop_clock(host);`
556			`writel(0, host->base + MMC_SPI);`
557			`writel(64, host->base + MMC_RESTO);`
558			`writel(host->imask, host->base + MMC_I_MASK);`
559
560			`host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,`
561			`pxamci_dma_irq, host);`
562			`if (host->dma < 0) {`
563			`ret = -EBUSY;`
564			`goto out;`
565			`}`
566
567			`ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);`
568			`if (ret)`
569			`goto out;`
570
571			`platform_set_drvdata(pdev, mmc);`
572
573			`if (host->pdata && host->pdata->init)`
574			`host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);`
575
576			`mmc_add_host(mmc);`
577
578			`return 0;`
579
580			`out:`
581			`if (host) {`
582			`if (host->dma >= 0)`
583			`pxa_free_dma(host->dma);`
584			`if (host->base)`
585			`iounmap(host->base);`
586			`if (host->sg_cpu)`
587			`dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);`
588			`if (host->clk)`
589			`clk_put(host->clk);`
590			`}`
591			`if (mmc)`
592			`mmc_free_host(mmc);`
593			`release_resource(r);`
594			`return ret;`
595			`}`
596
597			`static int pxamci_remove(struct platform_device *pdev)`
598			`{`
599			`struct mmc_host *mmc = platform_get_drvdata(pdev);`
600
601			`platform_set_drvdata(pdev, NULL);`
602
603			`if (mmc) {`
604			`struct pxamci_host *host = mmc_priv(mmc);`
605
606			`if (host->pdata && host->pdata->exit)`
607			`host->pdata->exit(&pdev->dev, mmc);`
608
609			`mmc_remove_host(mmc);`
610
611			`pxamci_stop_clock(host);`
612			`writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|`
613			`END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,`
614			`host->base + MMC_I_MASK);`
615
616			`DRCMRRXMMC = 0;`
617			`DRCMRTXMMC = 0;`
618
619			`free_irq(host->irq, host);`
620			`pxa_free_dma(host->dma);`
621			`iounmap(host->base);`
622			`dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);`
623
624			`clk_put(host->clk);`
625
626			`release_resource(host->res);`
627
628			`mmc_free_host(mmc);`
629			`}`
630			`return 0;`
631			`}`
632
633			`#ifdef CONFIG_PM`
634			`static int pxamci_suspend(struct platform_device *dev, pm_message_t state)`
635			`{`
636			`struct mmc_host *mmc = platform_get_drvdata(dev);`
637			`int ret = 0;`
638
639			`if (mmc)`
640			`ret = mmc_suspend_host(mmc, state);`
641
642			`return ret;`
643			`}`
644
645			`static int pxamci_resume(struct platform_device *dev)`
646			`{`
647			`struct mmc_host *mmc = platform_get_drvdata(dev);`
648			`int ret = 0;`
649
650			`if (mmc)`
651			`ret = mmc_resume_host(mmc);`
652
653			`return ret;`
654			`}`
655			`#else`
656			`#define pxamci_suspend NULL`
657			`#define pxamci_resume NULL`
658			`#endif`
659
660			`static struct platform_driver pxamci_driver = {`
661			`.probe = pxamci_probe,`
662			`.remove = pxamci_remove,`
663			`.suspend = pxamci_suspend,`
664			`.resume = pxamci_resume,`
665			`.driver = {`
666			`.name = DRIVER_NAME,`
667			`},`
668			`};`
669
670			`static int __init pxamci_init(void)`
671			`{`
672			`return platform_driver_register(&pxamci_driver);`
673			`}`
674
675			`static void __exit pxamci_exit(void)`
676			`{`
677			`platform_driver_unregister(&pxamci_driver);`
678			`}`
679
680			`module_init(pxamci_init);`
681			`module_exit(pxamci_exit);`
682
683			`MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");`
684			`MODULE_LICENSE("GPL");`