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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [mmc/] [host/] [pxamci.c] - Blame information for rev 82

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/*
 *  linux/drivers/mmc/host/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *      1 and 3 byte data transfers not supported
 *      max block length up to 1023
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mmc/host.h>
 
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/sizes.h>
 
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>
 
#include "pxamci.h"
 
#define DRIVER_NAME     "pxa2xx-mci"
 
#define NR_SG   1
#define CLKRT_OFF       (~0)
 
struct pxamci_host {
        struct mmc_host         *mmc;
        spinlock_t              lock;
        struct resource         *res;
        void __iomem            *base;
        struct clk              *clk;
        unsigned long           clkrate;
        int                     irq;
        int                     dma;
        unsigned int            clkrt;
        unsigned int            cmdat;
        unsigned int            imask;
        unsigned int            power_mode;
        struct pxamci_platform_data *pdata;
 
        struct mmc_request      *mrq;
        struct mmc_command      *cmd;
        struct mmc_data         *data;
 
        dma_addr_t              sg_dma;
        struct pxa_dma_desc     *sg_cpu;
        unsigned int            dma_len;
 
        unsigned int            dma_dir;
};
 
static void pxamci_stop_clock(struct pxamci_host *host)
{
        if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
                unsigned long timeout = 10000;
                unsigned int v;
 
                writel(STOP_CLOCK, host->base + MMC_STRPCL);
 
                do {
                        v = readl(host->base + MMC_STAT);
                        if (!(v & STAT_CLK_EN))
                                break;
                        udelay(1);
                } while (timeout--);
 
                if (v & STAT_CLK_EN)
                        dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
        }
}
 
static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
        host->imask &= ~mask;
        writel(host->imask, host->base + MMC_I_MASK);
 
        spin_unlock_irqrestore(&host->lock, flags);
}
 
static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
        host->imask |= mask;
        writel(host->imask, host->base + MMC_I_MASK);
        spin_unlock_irqrestore(&host->lock, flags);
}
 
static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
        unsigned int nob = data->blocks;
        unsigned long long clks;
        unsigned int timeout;
        u32 dcmd;
        int i;
 
        host->data = data;
 
        if (data->flags & MMC_DATA_STREAM)
                nob = 0xffff;
 
        writel(nob, host->base + MMC_NOB);
        writel(data->blksz, host->base + MMC_BLKLEN);
 
        clks = (unsigned long long)data->timeout_ns * host->clkrate;
        do_div(clks, 1000000000UL);
        timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
        writel((timeout + 255) / 256, host->base + MMC_RDTO);
 
        if (data->flags & MMC_DATA_READ) {
                host->dma_dir = DMA_FROM_DEVICE;
                dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
                DRCMRTXMMC = 0;
                DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
        } else {
                host->dma_dir = DMA_TO_DEVICE;
                dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
                DRCMRRXMMC = 0;
                DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
        }
 
        dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
 
        host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
                                   host->dma_dir);
 
        for (i = 0; i < host->dma_len; i++) {
                unsigned int length = sg_dma_len(&data->sg[i]);
                host->sg_cpu[i].dcmd = dcmd | length;
                if (length & 31 && !(data->flags & MMC_DATA_READ))
                        host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
                if (data->flags & MMC_DATA_READ) {
                        host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
                        host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
                } else {
                        host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
                        host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
                }
                host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
                                        sizeof(struct pxa_dma_desc);
        }
        host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
        wmb();
 
        DDADR(host->dma) = host->sg_dma;
        DCSR(host->dma) = DCSR_RUN;
}
 
static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
        WARN_ON(host->cmd != NULL);
        host->cmd = cmd;
 
        if (cmd->flags & MMC_RSP_BUSY)
                cmdat |= CMDAT_BUSY;
 
#define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
        switch (RSP_TYPE(mmc_resp_type(cmd))) {
        case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
                cmdat |= CMDAT_RESP_SHORT;
                break;
        case RSP_TYPE(MMC_RSP_R3):
                cmdat |= CMDAT_RESP_R3;
                break;
        case RSP_TYPE(MMC_RSP_R2):
                cmdat |= CMDAT_RESP_R2;
                break;
        default:
                break;
        }
 
        writel(cmd->opcode, host->base + MMC_CMD);
        writel(cmd->arg >> 16, host->base + MMC_ARGH);
        writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
        writel(cmdat, host->base + MMC_CMDAT);
        writel(host->clkrt, host->base + MMC_CLKRT);
 
        writel(START_CLOCK, host->base + MMC_STRPCL);
 
        pxamci_enable_irq(host, END_CMD_RES);
}
 
static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
        host->mrq = NULL;
        host->cmd = NULL;
        host->data = NULL;
        mmc_request_done(host->mmc, mrq);
}
 
static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
        struct mmc_command *cmd = host->cmd;
        int i;
        u32 v;
 
        if (!cmd)
                return 0;
 
        host->cmd = NULL;
 
        /*
         * Did I mention this is Sick.  We always need to
         * discard the upper 8 bits of the first 16-bit word.
         */
        v = readl(host->base + MMC_RES) & 0xffff;
        for (i = 0; i < 4; i++) {
                u32 w1 = readl(host->base + MMC_RES) & 0xffff;
                u32 w2 = readl(host->base + MMC_RES) & 0xffff;
                cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
                v = w2;
        }
 
        if (stat & STAT_TIME_OUT_RESPONSE) {
                cmd->error = -ETIMEDOUT;
        } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
                /*
                 * workaround for erratum #42:
                 * Intel PXA27x Family Processor Specification Update Rev 001
                 * A bogus CRC error can appear if the msb of a 136 bit
                 * response is a one.
                 */
                if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
                        pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
                } else
#endif
                cmd->error = -EILSEQ;
        }
 
        pxamci_disable_irq(host, END_CMD_RES);
        if (host->data && !cmd->error) {
                pxamci_enable_irq(host, DATA_TRAN_DONE);
        } else {
                pxamci_finish_request(host, host->mrq);
        }
 
        return 1;
}
 
static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
        struct mmc_data *data = host->data;
 
        if (!data)
                return 0;
 
        DCSR(host->dma) = 0;
        dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
                     host->dma_dir);
 
        if (stat & STAT_READ_TIME_OUT)
                data->error = -ETIMEDOUT;
        else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
                data->error = -EILSEQ;
 
        /*
         * There appears to be a hardware design bug here.  There seems to
         * be no way to find out how much data was transferred to the card.
         * This means that if there was an error on any block, we mark all
         * data blocks as being in error.
         */
        if (!data->error)
                data->bytes_xfered = data->blocks * data->blksz;
        else
                data->bytes_xfered = 0;
 
        pxamci_disable_irq(host, DATA_TRAN_DONE);
 
        host->data = NULL;
        if (host->mrq->stop) {
                pxamci_stop_clock(host);
                pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
        } else {
                pxamci_finish_request(host, host->mrq);
        }
 
        return 1;
}
 
static irqreturn_t pxamci_irq(int irq, void *devid)
{
        struct pxamci_host *host = devid;
        unsigned int ireg;
        int handled = 0;
 
        ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
 
        if (ireg) {
                unsigned stat = readl(host->base + MMC_STAT);
 
                pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
 
                if (ireg & END_CMD_RES)
                        handled |= pxamci_cmd_done(host, stat);
                if (ireg & DATA_TRAN_DONE)
                        handled |= pxamci_data_done(host, stat);
                if (ireg & SDIO_INT) {
                        mmc_signal_sdio_irq(host->mmc);
                        handled = 1;
                }
        }
 
        return IRQ_RETVAL(handled);
}
 
static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
        struct pxamci_host *host = mmc_priv(mmc);
        unsigned int cmdat;
 
        WARN_ON(host->mrq != NULL);
 
        host->mrq = mrq;
 
        pxamci_stop_clock(host);
 
        cmdat = host->cmdat;
        host->cmdat &= ~CMDAT_INIT;
 
        if (mrq->data) {
                pxamci_setup_data(host, mrq->data);
 
                cmdat &= ~CMDAT_BUSY;
                cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
                if (mrq->data->flags & MMC_DATA_WRITE)
                        cmdat |= CMDAT_WRITE;
 
                if (mrq->data->flags & MMC_DATA_STREAM)
                        cmdat |= CMDAT_STREAM;
        }
 
        pxamci_start_cmd(host, mrq->cmd, cmdat);
}
 
static int pxamci_get_ro(struct mmc_host *mmc)
{
        struct pxamci_host *host = mmc_priv(mmc);
 
        if (host->pdata && host->pdata->get_ro)
                return host->pdata->get_ro(mmc_dev(mmc));
        /* Host doesn't support read only detection so assume writeable */
        return 0;
}
 
static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
        struct pxamci_host *host = mmc_priv(mmc);
 
        if (ios->clock) {
                unsigned long rate = host->clkrate;
                unsigned int clk = rate / ios->clock;
 
                if (host->clkrt == CLKRT_OFF)
                        clk_enable(host->clk);
 
                /*
                 * clk might result in a lower divisor than we
                 * desire.  check for that condition and adjust
                 * as appropriate.
                 */
                if (rate / clk > ios->clock)
                        clk <<= 1;
                host->clkrt = fls(clk) - 1;
 
                /*
                 * we write clkrt on the next command
                 */
        } else {
                pxamci_stop_clock(host);
                if (host->clkrt != CLKRT_OFF) {
                        host->clkrt = CLKRT_OFF;
                        clk_disable(host->clk);
                }
        }
 
        if (host->power_mode != ios->power_mode) {
                host->power_mode = ios->power_mode;
 
                if (host->pdata && host->pdata->setpower)
                        host->pdata->setpower(mmc_dev(mmc), ios->vdd);
 
                if (ios->power_mode == MMC_POWER_ON)
                        host->cmdat |= CMDAT_INIT;
        }
 
        if (ios->bus_width == MMC_BUS_WIDTH_4)
                host->cmdat |= CMDAT_SD_4DAT;
        else
                host->cmdat &= ~CMDAT_SD_4DAT;
 
        pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
                 host->clkrt, host->cmdat);
}
 
static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
{
        struct pxamci_host *pxa_host = mmc_priv(host);
 
        if (enable)
                pxamci_enable_irq(pxa_host, SDIO_INT);
        else
                pxamci_disable_irq(pxa_host, SDIO_INT);
}
 
static const struct mmc_host_ops pxamci_ops = {
        .request                = pxamci_request,
        .get_ro                 = pxamci_get_ro,
        .set_ios                = pxamci_set_ios,
        .enable_sdio_irq        = pxamci_enable_sdio_irq,
};
 
static void pxamci_dma_irq(int dma, void *devid)
{
        struct pxamci_host *host = devid;
        int dcsr = DCSR(dma);
        DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;
 
        if (dcsr & DCSR_ENDINTR) {
                writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
        } else {
                printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",
                       mmc_hostname(host->mmc), dma, dcsr);
                host->data->error = -EIO;
                pxamci_data_done(host, 0);
        }
}
 
static irqreturn_t pxamci_detect_irq(int irq, void *devid)
{
        struct pxamci_host *host = mmc_priv(devid);
 
        mmc_detect_change(devid, host->pdata->detect_delay);
        return IRQ_HANDLED;
}
 
static int pxamci_probe(struct platform_device *pdev)
{
        struct mmc_host *mmc;
        struct pxamci_host *host = NULL;
        struct resource *r;
        int ret, irq;
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        irq = platform_get_irq(pdev, 0);
        if (!r || irq < 0)
                return -ENXIO;
 
        r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
        if (!r)
                return -EBUSY;
 
        mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
        if (!mmc) {
                ret = -ENOMEM;
                goto out;
        }
 
        mmc->ops = &pxamci_ops;
 
        /*
         * We can do SG-DMA, but we don't because we never know how much
         * data we successfully wrote to the card.
         */
        mmc->max_phys_segs = NR_SG;
 
        /*
         * Our hardware DMA can handle a maximum of one page per SG entry.
         */
        mmc->max_seg_size = PAGE_SIZE;
 
        /*
         * Block length register is only 10 bits before PXA27x.
         */
        mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;
 
        /*
         * Block count register is 16 bits.
         */
        mmc->max_blk_count = 65535;
 
        host = mmc_priv(mmc);
        host->mmc = mmc;
        host->dma = -1;
        host->pdata = pdev->dev.platform_data;
        host->clkrt = CLKRT_OFF;
 
        host->clk = clk_get(&pdev->dev, "MMCCLK");
        if (IS_ERR(host->clk)) {
                ret = PTR_ERR(host->clk);
                host->clk = NULL;
                goto out;
        }
 
        host->clkrate = clk_get_rate(host->clk);
 
        /*
         * Calculate minimum clock rate, rounding up.
         */
        mmc->f_min = (host->clkrate + 63) / 64;
        mmc->f_max = host->clkrate;
 
        mmc->ocr_avail = host->pdata ?
                         host->pdata->ocr_mask :
                         MMC_VDD_32_33|MMC_VDD_33_34;
        mmc->caps = 0;
        host->cmdat = 0;
        if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
                mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
                host->cmdat |= CMDAT_SDIO_INT_EN;
        }
 
        host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
        if (!host->sg_cpu) {
                ret = -ENOMEM;
                goto out;
        }
 
        spin_lock_init(&host->lock);
        host->res = r;
        host->irq = irq;
        host->imask = MMC_I_MASK_ALL;
 
        host->base = ioremap(r->start, SZ_4K);
        if (!host->base) {
                ret = -ENOMEM;
                goto out;
        }
 
        /*
         * Ensure that the host controller is shut down, and setup
         * with our defaults.
         */
        pxamci_stop_clock(host);
        writel(0, host->base + MMC_SPI);
        writel(64, host->base + MMC_RESTO);
        writel(host->imask, host->base + MMC_I_MASK);
 
        host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
                                    pxamci_dma_irq, host);
        if (host->dma < 0) {
                ret = -EBUSY;
                goto out;
        }
 
        ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
        if (ret)
                goto out;
 
        platform_set_drvdata(pdev, mmc);
 
        if (host->pdata && host->pdata->init)
                host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
 
        mmc_add_host(mmc);
 
        return 0;
 
 out:
        if (host) {
                if (host->dma >= 0)
                        pxa_free_dma(host->dma);
                if (host->base)
                        iounmap(host->base);
                if (host->sg_cpu)
                        dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
                if (host->clk)
                        clk_put(host->clk);
        }
        if (mmc)
                mmc_free_host(mmc);
        release_resource(r);
        return ret;
}
 
static int pxamci_remove(struct platform_device *pdev)
{
        struct mmc_host *mmc = platform_get_drvdata(pdev);
 
        platform_set_drvdata(pdev, NULL);
 
        if (mmc) {
                struct pxamci_host *host = mmc_priv(mmc);
 
                if (host->pdata && host->pdata->exit)
                        host->pdata->exit(&pdev->dev, mmc);
 
                mmc_remove_host(mmc);
 
                pxamci_stop_clock(host);
                writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
                       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
                       host->base + MMC_I_MASK);
 
                DRCMRRXMMC = 0;
                DRCMRTXMMC = 0;
 
                free_irq(host->irq, host);
                pxa_free_dma(host->dma);
                iounmap(host->base);
                dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 
                clk_put(host->clk);
 
                release_resource(host->res);
 
                mmc_free_host(mmc);
        }
        return 0;
}
 
#ifdef CONFIG_PM
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
{
        struct mmc_host *mmc = platform_get_drvdata(dev);
        int ret = 0;
 
        if (mmc)
                ret = mmc_suspend_host(mmc, state);
 
        return ret;
}
 
static int pxamci_resume(struct platform_device *dev)
{
        struct mmc_host *mmc = platform_get_drvdata(dev);
        int ret = 0;
 
        if (mmc)
                ret = mmc_resume_host(mmc);
 
        return ret;
}
#else
#define pxamci_suspend  NULL
#define pxamci_resume   NULL
#endif
 
static struct platform_driver pxamci_driver = {
        .probe          = pxamci_probe,
        .remove         = pxamci_remove,
        .suspend        = pxamci_suspend,
        .resume         = pxamci_resume,
        .driver         = {
                .name   = DRIVER_NAME,
        },
};
 
static int __init pxamci_init(void)
{
        return platform_driver_register(&pxamci_driver);
}
 
static void __exit pxamci_exit(void)
{
        platform_driver_unregister(&pxamci_driver);
}
 
module_init(pxamci_init);
module_exit(pxamci_exit);
 
MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");

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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [mmc/] [host/] [pxamci.c] - Blame information for rev 82

Line No.	Rev	Author	Line
1	62	marcus.erl	`/*`
2			`* linux/drivers/mmc/host/pxa.c - PXA MMCI driver`
3			`*`
4			`* Copyright (C) 2003 Russell King, All Rights Reserved.`
5			`*`
6			`* This program is free software; you can redistribute it and/or modify`
7			`* it under the terms of the GNU General Public License version 2 as`
8			`* published by the Free Software Foundation.`
9			`*`
10			`* This hardware is really sick:`
11			`* - No way to clear interrupts.`
12			`* - Have to turn off the clock whenever we touch the device.`
13			`* - Doesn't tell you how many data blocks were transferred.`
14			`* Yuck!`
15			`*`
16			`* 1 and 3 byte data transfers not supported`
17			`* max block length up to 1023`
18			`*/`
19			`#include <linux/module.h>`
20			`#include <linux/init.h>`
21			`#include <linux/ioport.h>`
22			`#include <linux/platform_device.h>`
23			`#include <linux/delay.h>`
24			`#include <linux/interrupt.h>`
25			`#include <linux/dma-mapping.h>`
26			`#include <linux/clk.h>`
27			`#include <linux/err.h>`
28			`#include <linux/mmc/host.h>`
29
30			`#include <asm/dma.h>`
31			`#include <asm/io.h>`
32			`#include <asm/sizes.h>`
33
34			`#include <asm/arch/pxa-regs.h>`
35			`#include <asm/arch/mmc.h>`
36
37			`#include "pxamci.h"`
38
39			`#define DRIVER_NAME "pxa2xx-mci"`
40
41			`#define NR_SG 1`
42			`#define CLKRT_OFF (~0)`
43
44			`struct pxamci_host {`
45			`struct mmc_host *mmc;`
46			`spinlock_t lock;`
47			`struct resource *res;`
48			`void __iomem *base;`
49			`struct clk *clk;`
50			`unsigned long clkrate;`
51			`int irq;`
52			`int dma;`
53			`unsigned int clkrt;`
54			`unsigned int cmdat;`
55			`unsigned int imask;`
56			`unsigned int power_mode;`
57			`struct pxamci_platform_data *pdata;`
58
59			`struct mmc_request *mrq;`
60			`struct mmc_command *cmd;`
61			`struct mmc_data *data;`
62
63			`dma_addr_t sg_dma;`
64			`struct pxa_dma_desc *sg_cpu;`
65			`unsigned int dma_len;`
66
67			`unsigned int dma_dir;`
68			`};`
69
70			`static void pxamci_stop_clock(struct pxamci_host *host)`
71			`{`
72			`if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {`
73			`unsigned long timeout = 10000;`
74			`unsigned int v;`
75
76			`writel(STOP_CLOCK, host->base + MMC_STRPCL);`
77
78			`do {`
79			`v = readl(host->base + MMC_STAT);`
80			`if (!(v & STAT_CLK_EN))`
81			`break;`
82			`udelay(1);`
83			`} while (timeout--);`
84
85			`if (v & STAT_CLK_EN)`
86			`dev_err(mmc_dev(host->mmc), "unable to stop clock\n");`
87			`}`
88			`}`
89
90			`static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)`
91			`{`
92			`unsigned long flags;`
93
94			`spin_lock_irqsave(&host->lock, flags);`
95			`host->imask &= ~mask;`
96			`writel(host->imask, host->base + MMC_I_MASK);`
97	82	tac2
98	62	marcus.erl	`spin_unlock_irqrestore(&host->lock, flags);`
99			`}`
100
101			`static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)`
102			`{`
103			`unsigned long flags;`
104
105			`spin_lock_irqsave(&host->lock, flags);`
106			`host->imask \|= mask;`
107			`writel(host->imask, host->base + MMC_I_MASK);`
108			`spin_unlock_irqrestore(&host->lock, flags);`
109			`}`
110
111			`static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)`
112			`{`
113			`unsigned int nob = data->blocks;`
114			`unsigned long long clks;`
115			`unsigned int timeout;`
116			`u32 dcmd;`
117			`int i;`
118
119			`host->data = data;`
120
121			`if (data->flags & MMC_DATA_STREAM)`
122			`nob = 0xffff;`
123
124			`writel(nob, host->base + MMC_NOB);`
125			`writel(data->blksz, host->base + MMC_BLKLEN);`
126
127			`clks = (unsigned long long)data->timeout_ns * host->clkrate;`
128			`do_div(clks, 1000000000UL);`
129			`timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);`
130			`writel((timeout + 255) / 256, host->base + MMC_RDTO);`
131
132			`if (data->flags & MMC_DATA_READ) {`
133			`host->dma_dir = DMA_FROM_DEVICE;`
134			`dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;`
135			`DRCMRTXMMC = 0;`
136			`DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;`
137			`} else {`
138			`host->dma_dir = DMA_TO_DEVICE;`
139			`dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;`
140			`DRCMRRXMMC = 0;`
141			`DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;`
142			`}`
143
144			`dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;`
145
146			`host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,`
147			`host->dma_dir);`
148
149			`for (i = 0; i < host->dma_len; i++) {`
150			`unsigned int length = sg_dma_len(&data->sg[i]);`
151			`host->sg_cpu[i].dcmd = dcmd \| length;`
152			`if (length & 31 && !(data->flags & MMC_DATA_READ))`
153			`host->sg_cpu[i].dcmd \|= DCMD_ENDIRQEN;`
154			`if (data->flags & MMC_DATA_READ) {`
155			`host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;`
156			`host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);`
157			`} else {`
158			`host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);`
159			`host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;`
160			`}`
161			`host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *`
162			`sizeof(struct pxa_dma_desc);`
163			`}`
164			`host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;`
165			`wmb();`
166
167			`DDADR(host->dma) = host->sg_dma;`
168			`DCSR(host->dma) = DCSR_RUN;`
169			`}`
170
171			`static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)`
172			`{`
173			`WARN_ON(host->cmd != NULL);`
174			`host->cmd = cmd;`
175
176			`if (cmd->flags & MMC_RSP_BUSY)`
177			`cmdat \|= CMDAT_BUSY;`
178
179			`#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY\|MMC_RSP_OPCODE))`
180			`switch (RSP_TYPE(mmc_resp_type(cmd))) {`
181			`case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */`
182			`cmdat \|= CMDAT_RESP_SHORT;`
183			`break;`
184			`case RSP_TYPE(MMC_RSP_R3):`
185			`cmdat \|= CMDAT_RESP_R3;`
186			`break;`
187			`case RSP_TYPE(MMC_RSP_R2):`
188			`cmdat \|= CMDAT_RESP_R2;`
189			`break;`
190			`default:`
191			`break;`
192			`}`
193
194			`writel(cmd->opcode, host->base + MMC_CMD);`
195			`writel(cmd->arg >> 16, host->base + MMC_ARGH);`
196			`writel(cmd->arg & 0xffff, host->base + MMC_ARGL);`
197			`writel(cmdat, host->base + MMC_CMDAT);`
198			`writel(host->clkrt, host->base + MMC_CLKRT);`
199
200			`writel(START_CLOCK, host->base + MMC_STRPCL);`
201
202			`pxamci_enable_irq(host, END_CMD_RES);`
203			`}`
204
205			`static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)`
206			`{`
207			`host->mrq = NULL;`
208			`host->cmd = NULL;`
209			`host->data = NULL;`
210			`mmc_request_done(host->mmc, mrq);`
211			`}`
212
213			`static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)`
214			`{`
215			`struct mmc_command *cmd = host->cmd;`
216			`int i;`
217			`u32 v;`
218
219			`if (!cmd)`
220			`return 0;`
221
222			`host->cmd = NULL;`
223
224			`/*`
225			`* Did I mention this is Sick. We always need to`
226			`* discard the upper 8 bits of the first 16-bit word.`
227			`*/`
228			`v = readl(host->base + MMC_RES) & 0xffff;`
229			`for (i = 0; i < 4; i++) {`
230			`u32 w1 = readl(host->base + MMC_RES) & 0xffff;`
231			`u32 w2 = readl(host->base + MMC_RES) & 0xffff;`
232			`cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;`
233			`v = w2;`
234			`}`
235
236			`if (stat & STAT_TIME_OUT_RESPONSE) {`
237			`cmd->error = -ETIMEDOUT;`
238			`} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {`
239			`#ifdef CONFIG_PXA27x`
240			`/*`
241			`* workaround for erratum #42:`
242			`* Intel PXA27x Family Processor Specification Update Rev 001`
243			`* A bogus CRC error can appear if the msb of a 136 bit`
244			`* response is a one.`
245			`*/`
246			`if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {`
247			`pr_debug("ignoring CRC from command %d - risky\n", cmd->opcode);`
248			`} else`
249			`#endif`
250			`cmd->error = -EILSEQ;`
251			`}`
252
253			`pxamci_disable_irq(host, END_CMD_RES);`
254			`if (host->data && !cmd->error) {`
255			`pxamci_enable_irq(host, DATA_TRAN_DONE);`
256			`} else {`
257			`pxamci_finish_request(host, host->mrq);`
258			`}`
259
260			`return 1;`
261			`}`
262
263			`static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)`
264			`{`
265			`struct mmc_data *data = host->data;`
266
267			`if (!data)`
268			`return 0;`
269
270			`DCSR(host->dma) = 0;`
271			`dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,`
272			`host->dma_dir);`
273
274			`if (stat & STAT_READ_TIME_OUT)`
275			`data->error = -ETIMEDOUT;`
276			`else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))`
277			`data->error = -EILSEQ;`
278
279			`/*`
280			`* There appears to be a hardware design bug here. There seems to`
281			`* be no way to find out how much data was transferred to the card.`
282			`* This means that if there was an error on any block, we mark all`
283			`* data blocks as being in error.`
284			`*/`
285			`if (!data->error)`
286			`data->bytes_xfered = data->blocks * data->blksz;`
287			`else`
288			`data->bytes_xfered = 0;`
289
290			`pxamci_disable_irq(host, DATA_TRAN_DONE);`
291
292			`host->data = NULL;`
293			`if (host->mrq->stop) {`
294			`pxamci_stop_clock(host);`
295			`pxamci_start_cmd(host, host->mrq->stop, host->cmdat);`
296			`} else {`
297			`pxamci_finish_request(host, host->mrq);`
298			`}`
299
300			`return 1;`
301			`}`
302
303			`static irqreturn_t pxamci_irq(int irq, void *devid)`
304			`{`
305			`struct pxamci_host *host = devid;`
306			`unsigned int ireg;`
307			`int handled = 0;`
308
309			`ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);`
310
311			`if (ireg) {`
312			`unsigned stat = readl(host->base + MMC_STAT);`
313
314			`pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);`
315
316			`if (ireg & END_CMD_RES)`
317			`handled \|= pxamci_cmd_done(host, stat);`
318			`if (ireg & DATA_TRAN_DONE)`
319			`handled \|= pxamci_data_done(host, stat);`
320			`if (ireg & SDIO_INT) {`
321			`mmc_signal_sdio_irq(host->mmc);`
322			`handled = 1;`
323			`}`
324			`}`
325
326			`return IRQ_RETVAL(handled);`
327			`}`
328
329			`static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)`
330			`{`
331			`struct pxamci_host *host = mmc_priv(mmc);`
332			`unsigned int cmdat;`
333
334			`WARN_ON(host->mrq != NULL);`
335
336			`host->mrq = mrq;`
337
338			`pxamci_stop_clock(host);`
339
340			`cmdat = host->cmdat;`
341			`host->cmdat &= ~CMDAT_INIT;`
342
343			`if (mrq->data) {`
344			`pxamci_setup_data(host, mrq->data);`
345
346			`cmdat &= ~CMDAT_BUSY;`
347			`cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;`
348			`if (mrq->data->flags & MMC_DATA_WRITE)`
349			`cmdat \|= CMDAT_WRITE;`
350
351			`if (mrq->data->flags & MMC_DATA_STREAM)`
352			`cmdat \|= CMDAT_STREAM;`
353			`}`
354
355			`pxamci_start_cmd(host, mrq->cmd, cmdat);`
356			`}`
357
358			`static int pxamci_get_ro(struct mmc_host *mmc)`
359			`{`
360			`struct pxamci_host *host = mmc_priv(mmc);`
361
362			`if (host->pdata && host->pdata->get_ro)`
363			`return host->pdata->get_ro(mmc_dev(mmc));`
364			`/* Host doesn't support read only detection so assume writeable */`
365			`return 0;`
366			`}`
367
368			`static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)`
369			`{`
370			`struct pxamci_host *host = mmc_priv(mmc);`
371
372			`if (ios->clock) {`
373			`unsigned long rate = host->clkrate;`
374			`unsigned int clk = rate / ios->clock;`
375
376			`if (host->clkrt == CLKRT_OFF)`
377			`clk_enable(host->clk);`
378
379			`/*`
380			`* clk might result in a lower divisor than we`
381			`* desire. check for that condition and adjust`
382			`* as appropriate.`
383			`*/`
384			`if (rate / clk > ios->clock)`
385			`clk <<= 1;`
386			`host->clkrt = fls(clk) - 1;`
387
388			`/*`
389			`* we write clkrt on the next command`
390			`*/`
391			`} else {`
392			`pxamci_stop_clock(host);`
393			`if (host->clkrt != CLKRT_OFF) {`
394			`host->clkrt = CLKRT_OFF;`
395			`clk_disable(host->clk);`
396			`}`
397			`}`
398
399			`if (host->power_mode != ios->power_mode) {`
400			`host->power_mode = ios->power_mode;`
401
402			`if (host->pdata && host->pdata->setpower)`
403			`host->pdata->setpower(mmc_dev(mmc), ios->vdd);`
404
405			`if (ios->power_mode == MMC_POWER_ON)`
406			`host->cmdat \|= CMDAT_INIT;`
407			`}`
408
409			`if (ios->bus_width == MMC_BUS_WIDTH_4)`
410			`host->cmdat \|= CMDAT_SD_4DAT;`
411			`else`
412			`host->cmdat &= ~CMDAT_SD_4DAT;`
413
414			`pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",`
415			`host->clkrt, host->cmdat);`
416			`}`
417
418			`static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)`
419			`{`
420			`struct pxamci_host *pxa_host = mmc_priv(host);`
421
422			`if (enable)`
423			`pxamci_enable_irq(pxa_host, SDIO_INT);`
424			`else`
425			`pxamci_disable_irq(pxa_host, SDIO_INT);`
426			`}`
427
428			`static const struct mmc_host_ops pxamci_ops = {`
429			`.request = pxamci_request,`
430			`.get_ro = pxamci_get_ro,`
431			`.set_ios = pxamci_set_ios,`
432			`.enable_sdio_irq = pxamci_enable_sdio_irq,`
433			`};`
434
435			`static void pxamci_dma_irq(int dma, void *devid)`
436			`{`
437			`struct pxamci_host *host = devid;`
438			`int dcsr = DCSR(dma);`
439			`DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;`
440
441			`if (dcsr & DCSR_ENDINTR) {`
442			`writel(BUF_PART_FULL, host->base + MMC_PRTBUF);`
443			`} else {`
444			`printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",`
445			`mmc_hostname(host->mmc), dma, dcsr);`
446			`host->data->error = -EIO;`
447			`pxamci_data_done(host, 0);`
448			`}`
449			`}`
450
451			`static irqreturn_t pxamci_detect_irq(int irq, void *devid)`
452			`{`
453			`struct pxamci_host *host = mmc_priv(devid);`
454
455			`mmc_detect_change(devid, host->pdata->detect_delay);`
456			`return IRQ_HANDLED;`
457			`}`
458
459			`static int pxamci_probe(struct platform_device *pdev)`
460			`{`
461			`struct mmc_host *mmc;`
462			`struct pxamci_host *host = NULL;`
463			`struct resource *r;`
464			`int ret, irq;`
465
466			`r = platform_get_resource(pdev, IORESOURCE_MEM, 0);`
467			`irq = platform_get_irq(pdev, 0);`
468			`if (!r \|\| irq < 0)`
469			`return -ENXIO;`
470
471			`r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);`
472			`if (!r)`
473			`return -EBUSY;`
474
475			`mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);`
476			`if (!mmc) {`
477			`ret = -ENOMEM;`
478			`goto out;`
479			`}`
480
481			`mmc->ops = &pxamci_ops;`
482
483			`/*`
484			`* We can do SG-DMA, but we don't because we never know how much`
485			`* data we successfully wrote to the card.`
486			`*/`
487			`mmc->max_phys_segs = NR_SG;`
488
489			`/*`
490			`* Our hardware DMA can handle a maximum of one page per SG entry.`
491			`*/`
492			`mmc->max_seg_size = PAGE_SIZE;`
493
494			`/*`
495			`* Block length register is only 10 bits before PXA27x.`
496			`*/`
497			`mmc->max_blk_size = (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) ? 1023 : 2048;`
498
499			`/*`
500			`* Block count register is 16 bits.`
501			`*/`
502			`mmc->max_blk_count = 65535;`
503
504			`host = mmc_priv(mmc);`
505			`host->mmc = mmc;`
506			`host->dma = -1;`
507			`host->pdata = pdev->dev.platform_data;`
508			`host->clkrt = CLKRT_OFF;`
509
510			`host->clk = clk_get(&pdev->dev, "MMCCLK");`
511			`if (IS_ERR(host->clk)) {`
512			`ret = PTR_ERR(host->clk);`
513			`host->clk = NULL;`
514			`goto out;`
515			`}`
516
517			`host->clkrate = clk_get_rate(host->clk);`
518
519			`/*`
520			`* Calculate minimum clock rate, rounding up.`
521			`*/`
522			`mmc->f_min = (host->clkrate + 63) / 64;`
523			`mmc->f_max = host->clkrate;`
524
525			`mmc->ocr_avail = host->pdata ?`
526			`host->pdata->ocr_mask :`
527			`MMC_VDD_32_33\|MMC_VDD_33_34;`
528			`mmc->caps = 0;`
529			`host->cmdat = 0;`
530			`if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {`
531			`mmc->caps \|= MMC_CAP_4_BIT_DATA \| MMC_CAP_SDIO_IRQ;`
532			`host->cmdat \|= CMDAT_SDIO_INT_EN;`
533			`}`
534
535			`host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);`
536			`if (!host->sg_cpu) {`
537			`ret = -ENOMEM;`
538			`goto out;`
539			`}`
540
541			`spin_lock_init(&host->lock);`
542			`host->res = r;`
543			`host->irq = irq;`
544			`host->imask = MMC_I_MASK_ALL;`
545
546			`host->base = ioremap(r->start, SZ_4K);`
547			`if (!host->base) {`
548			`ret = -ENOMEM;`
549			`goto out;`
550			`}`
551
552			`/*`
553			`* Ensure that the host controller is shut down, and setup`
554			`* with our defaults.`
555			`*/`
556			`pxamci_stop_clock(host);`
557			`writel(0, host->base + MMC_SPI);`
558			`writel(64, host->base + MMC_RESTO);`
559			`writel(host->imask, host->base + MMC_I_MASK);`
560
561			`host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,`
562			`pxamci_dma_irq, host);`
563			`if (host->dma < 0) {`
564			`ret = -EBUSY;`
565			`goto out;`
566			`}`
567
568			`ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);`
569			`if (ret)`
570			`goto out;`
571
572			`platform_set_drvdata(pdev, mmc);`
573
574			`if (host->pdata && host->pdata->init)`
575			`host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);`
576
577			`mmc_add_host(mmc);`
578
579			`return 0;`
580
581			`out:`
582			`if (host) {`
583			`if (host->dma >= 0)`
584			`pxa_free_dma(host->dma);`
585			`if (host->base)`
586			`iounmap(host->base);`
587			`if (host->sg_cpu)`
588			`dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);`
589			`if (host->clk)`
590			`clk_put(host->clk);`
591			`}`
592			`if (mmc)`
593			`mmc_free_host(mmc);`
594			`release_resource(r);`
595			`return ret;`
596			`}`
597
598			`static int pxamci_remove(struct platform_device *pdev)`
599			`{`
600			`struct mmc_host *mmc = platform_get_drvdata(pdev);`
601
602			`platform_set_drvdata(pdev, NULL);`
603
604			`if (mmc) {`
605			`struct pxamci_host *host = mmc_priv(mmc);`
606
607			`if (host->pdata && host->pdata->exit)`
608			`host->pdata->exit(&pdev->dev, mmc);`
609
610			`mmc_remove_host(mmc);`
611
612			`pxamci_stop_clock(host);`
613			`writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|`
614			`END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,`
615			`host->base + MMC_I_MASK);`
616
617			`DRCMRRXMMC = 0;`
618			`DRCMRTXMMC = 0;`
619
620			`free_irq(host->irq, host);`
621			`pxa_free_dma(host->dma);`
622			`iounmap(host->base);`
623			`dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);`
624
625			`clk_put(host->clk);`
626
627			`release_resource(host->res);`
628
629			`mmc_free_host(mmc);`
630			`}`
631			`return 0;`
632			`}`
633
634			`#ifdef CONFIG_PM`
635			`static int pxamci_suspend(struct platform_device *dev, pm_message_t state)`
636			`{`
637			`struct mmc_host *mmc = platform_get_drvdata(dev);`
638			`int ret = 0;`
639
640			`if (mmc)`
641			`ret = mmc_suspend_host(mmc, state);`
642
643			`return ret;`
644			`}`
645
646			`static int pxamci_resume(struct platform_device *dev)`
647			`{`
648			`struct mmc_host *mmc = platform_get_drvdata(dev);`
649			`int ret = 0;`
650
651			`if (mmc)`
652			`ret = mmc_resume_host(mmc);`
653
654			`return ret;`
655			`}`
656			`#else`
657			`#define pxamci_suspend NULL`
658			`#define pxamci_resume NULL`
659			`#endif`
660
661			`static struct platform_driver pxamci_driver = {`
662			`.probe = pxamci_probe,`
663			`.remove = pxamci_remove,`
664			`.suspend = pxamci_suspend,`
665			`.resume = pxamci_resume,`
666			`.driver = {`
667			`.name = DRIVER_NAME,`
668			`},`
669			`};`
670
671			`static int __init pxamci_init(void)`
672			`{`
673			`return platform_driver_register(&pxamci_driver);`
674			`}`
675
676			`static void __exit pxamci_exit(void)`
677			`{`
678			`platform_driver_unregister(&pxamci_driver);`
679			`}`
680
681			`module_init(pxamci_init);`
682			`module_exit(pxamci_exit);`
683
684			`MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");`
685			`MODULE_LICENSE("GPL");`