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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [mmc/] [host/] [sdhci.c] - Blame information for rev 78

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1 62 marcus.erl
/*
2
 *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3
 *
4
 *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
5
 *
6
 * This program is free software; you can redistribute it and/or modify
7
 * it under the terms of the GNU General Public License as published by
8
 * the Free Software Foundation; either version 2 of the License, or (at
9
 * your option) any later version.
10
 *
11
 * Thanks to the following companies for their support:
12
 *
13
 *     - JMicron (hardware and technical support)
14
 */
15
 
16
#include <linux/delay.h>
17
#include <linux/highmem.h>
18
#include <linux/pci.h>
19
#include <linux/dma-mapping.h>
20
#include <linux/scatterlist.h>
21
 
22
#include <linux/mmc/host.h>
23
 
24
#include "sdhci.h"
25
 
26
#define DRIVER_NAME "sdhci"
27
 
28
#define DBG(f, x...) \
29
        pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
30
 
31
static unsigned int debug_quirks = 0;
32
 
33
/*
34
 * Different quirks to handle when the hardware deviates from a strict
35
 * interpretation of the SDHCI specification.
36
 */
37
 
38
/* Controller doesn't honor resets unless we touch the clock register */
39
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
40
/* Controller has bad caps bits, but really supports DMA */
41
#define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
42
/* Controller doesn't like some resets when there is no card inserted. */
43
#define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
44
/* Controller doesn't like clearing the power reg before a change */
45
#define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
46
/* Controller has flaky internal state so reset it on each ios change */
47
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
48
/* Controller has an unusable DMA engine */
49
#define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
50
/* Controller can only DMA from 32-bit aligned addresses */
51
#define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<6)
52
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
53
#define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<7)
54
/* Controller needs to be reset after each request to stay stable */
55
#define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<8)
56
 
57
static const struct pci_device_id pci_ids[] __devinitdata = {
58
        {
59
                .vendor         = PCI_VENDOR_ID_RICOH,
60
                .device         = PCI_DEVICE_ID_RICOH_R5C822,
61
                .subvendor      = PCI_VENDOR_ID_IBM,
62
                .subdevice      = PCI_ANY_ID,
63
                .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
64
                                  SDHCI_QUIRK_FORCE_DMA,
65
        },
66
 
67
        {
68
                .vendor         = PCI_VENDOR_ID_RICOH,
69
                .device         = PCI_DEVICE_ID_RICOH_R5C822,
70
                .subvendor      = PCI_ANY_ID,
71
                .subdevice      = PCI_ANY_ID,
72
                .driver_data    = SDHCI_QUIRK_FORCE_DMA |
73
                                  SDHCI_QUIRK_NO_CARD_NO_RESET,
74
        },
75
 
76
        {
77
                .vendor         = PCI_VENDOR_ID_TI,
78
                .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
79
                .subvendor      = PCI_ANY_ID,
80
                .subdevice      = PCI_ANY_ID,
81
                .driver_data    = SDHCI_QUIRK_FORCE_DMA,
82
        },
83
 
84
        {
85
                .vendor         = PCI_VENDOR_ID_ENE,
86
                .device         = PCI_DEVICE_ID_ENE_CB712_SD,
87
                .subvendor      = PCI_ANY_ID,
88
                .subdevice      = PCI_ANY_ID,
89
                .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
90
                                  SDHCI_QUIRK_BROKEN_DMA,
91
        },
92
 
93
        {
94
                .vendor         = PCI_VENDOR_ID_ENE,
95
                .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
96
                .subvendor      = PCI_ANY_ID,
97
                .subdevice      = PCI_ANY_ID,
98
                .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
99
                                  SDHCI_QUIRK_BROKEN_DMA,
100
        },
101
 
102
        {
103
                .vendor         = PCI_VENDOR_ID_ENE,
104
                .device         = PCI_DEVICE_ID_ENE_CB714_SD,
105
                .subvendor      = PCI_ANY_ID,
106
                .subdevice      = PCI_ANY_ID,
107
                .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
108
                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
109
        },
110
 
111
        {
112
                .vendor         = PCI_VENDOR_ID_ENE,
113
                .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
114
                .subvendor      = PCI_ANY_ID,
115
                .subdevice      = PCI_ANY_ID,
116
                .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
117
                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
118
        },
119
 
120
        {
121
                .vendor         = PCI_VENDOR_ID_JMICRON,
122
                .device         = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
123
                .subvendor      = PCI_ANY_ID,
124
                .subdevice      = PCI_ANY_ID,
125
                .driver_data    = SDHCI_QUIRK_32BIT_DMA_ADDR |
126
                                  SDHCI_QUIRK_32BIT_DMA_SIZE |
127
                                  SDHCI_QUIRK_RESET_AFTER_REQUEST,
128
        },
129
 
130
        {       /* Generic SD host controller */
131
                PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
132
        },
133
 
134
        { /* end: all zeroes */ },
135
};
136
 
137
MODULE_DEVICE_TABLE(pci, pci_ids);
138
 
139
static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
140
static void sdhci_finish_data(struct sdhci_host *);
141
 
142
static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
143
static void sdhci_finish_command(struct sdhci_host *);
144
 
145
static void sdhci_dumpregs(struct sdhci_host *host)
146
{
147
        printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
148
 
149
        printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
150
                readl(host->ioaddr + SDHCI_DMA_ADDRESS),
151
                readw(host->ioaddr + SDHCI_HOST_VERSION));
152
        printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
153
                readw(host->ioaddr + SDHCI_BLOCK_SIZE),
154
                readw(host->ioaddr + SDHCI_BLOCK_COUNT));
155
        printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
156
                readl(host->ioaddr + SDHCI_ARGUMENT),
157
                readw(host->ioaddr + SDHCI_TRANSFER_MODE));
158
        printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
159
                readl(host->ioaddr + SDHCI_PRESENT_STATE),
160
                readb(host->ioaddr + SDHCI_HOST_CONTROL));
161
        printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
162
                readb(host->ioaddr + SDHCI_POWER_CONTROL),
163
                readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
164
        printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
165
                readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
166
                readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
167
        printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
168
                readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
169
                readl(host->ioaddr + SDHCI_INT_STATUS));
170
        printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
171
                readl(host->ioaddr + SDHCI_INT_ENABLE),
172
                readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
173
        printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
174
                readw(host->ioaddr + SDHCI_ACMD12_ERR),
175
                readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
176
        printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
177
                readl(host->ioaddr + SDHCI_CAPABILITIES),
178
                readl(host->ioaddr + SDHCI_MAX_CURRENT));
179
 
180
        printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
181
}
182
 
183
/*****************************************************************************\
184
 *                                                                           *
185
 * Low level functions                                                       *
186
 *                                                                           *
187
\*****************************************************************************/
188
 
189
static void sdhci_reset(struct sdhci_host *host, u8 mask)
190
{
191
        unsigned long timeout;
192
 
193
        if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
194
                if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
195
                        SDHCI_CARD_PRESENT))
196
                        return;
197
        }
198
 
199
        writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
200
 
201
        if (mask & SDHCI_RESET_ALL)
202
                host->clock = 0;
203
 
204
        /* Wait max 100 ms */
205
        timeout = 100;
206
 
207
        /* hw clears the bit when it's done */
208
        while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
209
                if (timeout == 0) {
210
                        printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
211
                                mmc_hostname(host->mmc), (int)mask);
212
                        sdhci_dumpregs(host);
213
                        return;
214
                }
215
                timeout--;
216
                mdelay(1);
217
        }
218
}
219
 
220
static void sdhci_init(struct sdhci_host *host)
221
{
222
        u32 intmask;
223
 
224
        sdhci_reset(host, SDHCI_RESET_ALL);
225
 
226
        intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227
                SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
228
                SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
229
                SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
230
                SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
231
                SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
232
 
233
        writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
234
        writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
235
}
236
 
237
static void sdhci_activate_led(struct sdhci_host *host)
238
{
239
        u8 ctrl;
240
 
241
        ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
242
        ctrl |= SDHCI_CTRL_LED;
243
        writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
244
}
245
 
246
static void sdhci_deactivate_led(struct sdhci_host *host)
247
{
248
        u8 ctrl;
249
 
250
        ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
251
        ctrl &= ~SDHCI_CTRL_LED;
252
        writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
253
}
254
 
255
/*****************************************************************************\
256
 *                                                                           *
257
 * Core functions                                                            *
258
 *                                                                           *
259
\*****************************************************************************/
260
 
261
static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
262
{
263
        return sg_virt(host->cur_sg);
264
}
265
 
266
static inline int sdhci_next_sg(struct sdhci_host* host)
267
{
268
        /*
269
         * Skip to next SG entry.
270
         */
271
        host->cur_sg++;
272
        host->num_sg--;
273
 
274
        /*
275
         * Any entries left?
276
         */
277
        if (host->num_sg > 0) {
278
                host->offset = 0;
279
                host->remain = host->cur_sg->length;
280
        }
281
 
282
        return host->num_sg;
283
}
284
 
285
static void sdhci_read_block_pio(struct sdhci_host *host)
286
{
287
        int blksize, chunk_remain;
288
        u32 data;
289
        char *buffer;
290
        int size;
291
 
292
        DBG("PIO reading\n");
293
 
294
        blksize = host->data->blksz;
295
        chunk_remain = 0;
296
        data = 0;
297
 
298
        buffer = sdhci_sg_to_buffer(host) + host->offset;
299
 
300
        while (blksize) {
301
                if (chunk_remain == 0) {
302
                        data = readl(host->ioaddr + SDHCI_BUFFER);
303
                        chunk_remain = min(blksize, 4);
304
                }
305
 
306
                size = min(host->remain, chunk_remain);
307
 
308
                chunk_remain -= size;
309
                blksize -= size;
310
                host->offset += size;
311
                host->remain -= size;
312
 
313
                while (size) {
314
                        *buffer = data & 0xFF;
315
                        buffer++;
316
                        data >>= 8;
317
                        size--;
318
                }
319
 
320
                if (host->remain == 0) {
321
                        if (sdhci_next_sg(host) == 0) {
322
                                BUG_ON(blksize != 0);
323
                                return;
324
                        }
325
                        buffer = sdhci_sg_to_buffer(host);
326
                }
327
        }
328
}
329
 
330
static void sdhci_write_block_pio(struct sdhci_host *host)
331
{
332
        int blksize, chunk_remain;
333
        u32 data;
334
        char *buffer;
335
        int bytes, size;
336
 
337
        DBG("PIO writing\n");
338
 
339
        blksize = host->data->blksz;
340
        chunk_remain = 4;
341
        data = 0;
342
 
343
        bytes = 0;
344
        buffer = sdhci_sg_to_buffer(host) + host->offset;
345
 
346
        while (blksize) {
347
                size = min(host->remain, chunk_remain);
348
 
349
                chunk_remain -= size;
350
                blksize -= size;
351
                host->offset += size;
352
                host->remain -= size;
353
 
354
                while (size) {
355
                        data >>= 8;
356
                        data |= (u32)*buffer << 24;
357
                        buffer++;
358
                        size--;
359
                }
360
 
361
                if (chunk_remain == 0) {
362
                        writel(data, host->ioaddr + SDHCI_BUFFER);
363
                        chunk_remain = min(blksize, 4);
364
                }
365
 
366
                if (host->remain == 0) {
367
                        if (sdhci_next_sg(host) == 0) {
368
                                BUG_ON(blksize != 0);
369
                                return;
370
                        }
371
                        buffer = sdhci_sg_to_buffer(host);
372
                }
373
        }
374
}
375
 
376
static void sdhci_transfer_pio(struct sdhci_host *host)
377
{
378
        u32 mask;
379
 
380
        BUG_ON(!host->data);
381
 
382
        if (host->num_sg == 0)
383
                return;
384
 
385
        if (host->data->flags & MMC_DATA_READ)
386
                mask = SDHCI_DATA_AVAILABLE;
387
        else
388
                mask = SDHCI_SPACE_AVAILABLE;
389
 
390
        while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
391
                if (host->data->flags & MMC_DATA_READ)
392
                        sdhci_read_block_pio(host);
393
                else
394
                        sdhci_write_block_pio(host);
395
 
396
                if (host->num_sg == 0)
397
                        break;
398
        }
399
 
400
        DBG("PIO transfer complete.\n");
401
}
402
 
403
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
404
{
405
        u8 count;
406
        unsigned target_timeout, current_timeout;
407
 
408
        WARN_ON(host->data);
409
 
410
        if (data == NULL)
411
                return;
412
 
413
        /* Sanity checks */
414
        BUG_ON(data->blksz * data->blocks > 524288);
415
        BUG_ON(data->blksz > host->mmc->max_blk_size);
416
        BUG_ON(data->blocks > 65535);
417
 
418
        host->data = data;
419
        host->data_early = 0;
420
 
421
        /* timeout in us */
422
        target_timeout = data->timeout_ns / 1000 +
423
                data->timeout_clks / host->clock;
424
 
425
        /*
426
         * Figure out needed cycles.
427
         * We do this in steps in order to fit inside a 32 bit int.
428
         * The first step is the minimum timeout, which will have a
429
         * minimum resolution of 6 bits:
430
         * (1) 2^13*1000 > 2^22,
431
         * (2) host->timeout_clk < 2^16
432
         *     =>
433
         *     (1) / (2) > 2^6
434
         */
435
        count = 0;
436
        current_timeout = (1 << 13) * 1000 / host->timeout_clk;
437
        while (current_timeout < target_timeout) {
438
                count++;
439
                current_timeout <<= 1;
440
                if (count >= 0xF)
441
                        break;
442
        }
443
 
444
        if (count >= 0xF) {
445
                printk(KERN_WARNING "%s: Too large timeout requested!\n",
446
                        mmc_hostname(host->mmc));
447
                count = 0xE;
448
        }
449
 
450
        writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
451
 
452
        if (host->flags & SDHCI_USE_DMA)
453
                host->flags |= SDHCI_REQ_USE_DMA;
454
 
455
        if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
456
                (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
457
                ((data->blksz * data->blocks) & 0x3))) {
458
                DBG("Reverting to PIO because of transfer size (%d)\n",
459
                        data->blksz * data->blocks);
460
                host->flags &= ~SDHCI_REQ_USE_DMA;
461
        }
462
 
463
        /*
464
         * The assumption here being that alignment is the same after
465
         * translation to device address space.
466
         */
467
        if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
468
                (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
469
                (data->sg->offset & 0x3))) {
470
                DBG("Reverting to PIO because of bad alignment\n");
471
                host->flags &= ~SDHCI_REQ_USE_DMA;
472
        }
473
 
474
        if (host->flags & SDHCI_REQ_USE_DMA) {
475
                int count;
476
 
477
                count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
478
                        (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
479
                BUG_ON(count != 1);
480
 
481
                writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
482
        } else {
483
                host->cur_sg = data->sg;
484
                host->num_sg = data->sg_len;
485
 
486
                host->offset = 0;
487
                host->remain = host->cur_sg->length;
488
        }
489
 
490
        /* We do not handle DMA boundaries, so set it to max (512 KiB) */
491
        writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
492
                host->ioaddr + SDHCI_BLOCK_SIZE);
493
        writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
494
}
495
 
496
static void sdhci_set_transfer_mode(struct sdhci_host *host,
497
        struct mmc_data *data)
498
{
499
        u16 mode;
500
 
501
        if (data == NULL)
502
                return;
503
 
504
        WARN_ON(!host->data);
505
 
506
        mode = SDHCI_TRNS_BLK_CNT_EN;
507
        if (data->blocks > 1)
508
                mode |= SDHCI_TRNS_MULTI;
509
        if (data->flags & MMC_DATA_READ)
510
                mode |= SDHCI_TRNS_READ;
511
        if (host->flags & SDHCI_REQ_USE_DMA)
512
                mode |= SDHCI_TRNS_DMA;
513
 
514
        writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
515
}
516
 
517
static void sdhci_finish_data(struct sdhci_host *host)
518
{
519
        struct mmc_data *data;
520
        u16 blocks;
521
 
522
        BUG_ON(!host->data);
523
 
524
        data = host->data;
525
        host->data = NULL;
526
 
527
        if (host->flags & SDHCI_REQ_USE_DMA) {
528
                pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
529
                        (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
530
        }
531
 
532
        /*
533
         * Controller doesn't count down when in single block mode.
534
         */
535
        if (data->blocks == 1)
536
                blocks = (data->error == 0) ? 0 : 1;
537
        else
538
                blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
539
        data->bytes_xfered = data->blksz * (data->blocks - blocks);
540
 
541
        if (!data->error && blocks) {
542
                printk(KERN_ERR "%s: Controller signalled completion even "
543
                        "though there were blocks left.\n",
544
                        mmc_hostname(host->mmc));
545
                data->error = -EIO;
546
        }
547
 
548
        if (data->stop) {
549
                /*
550
                 * The controller needs a reset of internal state machines
551
                 * upon error conditions.
552
                 */
553
                if (data->error) {
554
                        sdhci_reset(host, SDHCI_RESET_CMD);
555
                        sdhci_reset(host, SDHCI_RESET_DATA);
556
                }
557
 
558
                sdhci_send_command(host, data->stop);
559
        } else
560
                tasklet_schedule(&host->finish_tasklet);
561
}
562
 
563
static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
564
{
565
        int flags;
566
        u32 mask;
567
        unsigned long timeout;
568
 
569
        WARN_ON(host->cmd);
570
 
571
        /* Wait max 10 ms */
572
        timeout = 10;
573
 
574
        mask = SDHCI_CMD_INHIBIT;
575
        if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
576
                mask |= SDHCI_DATA_INHIBIT;
577
 
578
        /* We shouldn't wait for data inihibit for stop commands, even
579
           though they might use busy signaling */
580
        if (host->mrq->data && (cmd == host->mrq->data->stop))
581
                mask &= ~SDHCI_DATA_INHIBIT;
582
 
583
        while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
584
                if (timeout == 0) {
585
                        printk(KERN_ERR "%s: Controller never released "
586
                                "inhibit bit(s).\n", mmc_hostname(host->mmc));
587
                        sdhci_dumpregs(host);
588
                        cmd->error = -EIO;
589
                        tasklet_schedule(&host->finish_tasklet);
590
                        return;
591
                }
592
                timeout--;
593
                mdelay(1);
594
        }
595
 
596
        mod_timer(&host->timer, jiffies + 10 * HZ);
597
 
598
        host->cmd = cmd;
599
 
600
        sdhci_prepare_data(host, cmd->data);
601
 
602
        writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
603
 
604
        sdhci_set_transfer_mode(host, cmd->data);
605
 
606
        if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
607
                printk(KERN_ERR "%s: Unsupported response type!\n",
608
                        mmc_hostname(host->mmc));
609
                cmd->error = -EINVAL;
610
                tasklet_schedule(&host->finish_tasklet);
611
                return;
612
        }
613
 
614
        if (!(cmd->flags & MMC_RSP_PRESENT))
615
                flags = SDHCI_CMD_RESP_NONE;
616
        else if (cmd->flags & MMC_RSP_136)
617
                flags = SDHCI_CMD_RESP_LONG;
618
        else if (cmd->flags & MMC_RSP_BUSY)
619
                flags = SDHCI_CMD_RESP_SHORT_BUSY;
620
        else
621
                flags = SDHCI_CMD_RESP_SHORT;
622
 
623
        if (cmd->flags & MMC_RSP_CRC)
624
                flags |= SDHCI_CMD_CRC;
625
        if (cmd->flags & MMC_RSP_OPCODE)
626
                flags |= SDHCI_CMD_INDEX;
627
        if (cmd->data)
628
                flags |= SDHCI_CMD_DATA;
629
 
630
        writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
631
                host->ioaddr + SDHCI_COMMAND);
632
}
633
 
634
static void sdhci_finish_command(struct sdhci_host *host)
635
{
636
        int i;
637
 
638
        BUG_ON(host->cmd == NULL);
639
 
640
        if (host->cmd->flags & MMC_RSP_PRESENT) {
641
                if (host->cmd->flags & MMC_RSP_136) {
642
                        /* CRC is stripped so we need to do some shifting. */
643
                        for (i = 0;i < 4;i++) {
644
                                host->cmd->resp[i] = readl(host->ioaddr +
645
                                        SDHCI_RESPONSE + (3-i)*4) << 8;
646
                                if (i != 3)
647
                                        host->cmd->resp[i] |=
648
                                                readb(host->ioaddr +
649
                                                SDHCI_RESPONSE + (3-i)*4-1);
650
                        }
651
                } else {
652
                        host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
653
                }
654
        }
655
 
656
        host->cmd->error = 0;
657
 
658
        if (host->data && host->data_early)
659
                sdhci_finish_data(host);
660
 
661
        if (!host->cmd->data)
662
                tasklet_schedule(&host->finish_tasklet);
663
 
664
        host->cmd = NULL;
665
}
666
 
667
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
668
{
669
        int div;
670
        u16 clk;
671
        unsigned long timeout;
672
 
673
        if (clock == host->clock)
674
                return;
675
 
676
        writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
677
 
678
        if (clock == 0)
679
                goto out;
680
 
681
        for (div = 1;div < 256;div *= 2) {
682
                if ((host->max_clk / div) <= clock)
683
                        break;
684
        }
685
        div >>= 1;
686
 
687
        clk = div << SDHCI_DIVIDER_SHIFT;
688
        clk |= SDHCI_CLOCK_INT_EN;
689
        writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
690
 
691
        /* Wait max 10 ms */
692
        timeout = 10;
693
        while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
694
                & SDHCI_CLOCK_INT_STABLE)) {
695
                if (timeout == 0) {
696
                        printk(KERN_ERR "%s: Internal clock never "
697
                                "stabilised.\n", mmc_hostname(host->mmc));
698
                        sdhci_dumpregs(host);
699
                        return;
700
                }
701
                timeout--;
702
                mdelay(1);
703
        }
704
 
705
        clk |= SDHCI_CLOCK_CARD_EN;
706
        writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
707
 
708
out:
709
        host->clock = clock;
710
}
711
 
712
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
713
{
714
        u8 pwr;
715
 
716
        if (host->power == power)
717
                return;
718
 
719
        if (power == (unsigned short)-1) {
720
                writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
721
                goto out;
722
        }
723
 
724
        /*
725
         * Spec says that we should clear the power reg before setting
726
         * a new value. Some controllers don't seem to like this though.
727
         */
728
        if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
729
                writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
730
 
731
        pwr = SDHCI_POWER_ON;
732
 
733
        switch (1 << power) {
734
        case MMC_VDD_165_195:
735
                pwr |= SDHCI_POWER_180;
736
                break;
737
        case MMC_VDD_29_30:
738
        case MMC_VDD_30_31:
739
                pwr |= SDHCI_POWER_300;
740
                break;
741
        case MMC_VDD_32_33:
742
        case MMC_VDD_33_34:
743
                pwr |= SDHCI_POWER_330;
744
                break;
745
        default:
746
                BUG();
747
        }
748
 
749
        writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
750
 
751
out:
752
        host->power = power;
753
}
754
 
755
/*****************************************************************************\
756
 *                                                                           *
757
 * MMC callbacks                                                             *
758
 *                                                                           *
759
\*****************************************************************************/
760
 
761
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
762
{
763
        struct sdhci_host *host;
764
        unsigned long flags;
765
 
766
        host = mmc_priv(mmc);
767
 
768
        spin_lock_irqsave(&host->lock, flags);
769
 
770
        WARN_ON(host->mrq != NULL);
771
 
772
        sdhci_activate_led(host);
773
 
774
        host->mrq = mrq;
775
 
776
        if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
777
                host->mrq->cmd->error = -ENOMEDIUM;
778
                tasklet_schedule(&host->finish_tasklet);
779
        } else
780
                sdhci_send_command(host, mrq->cmd);
781
 
782
        mmiowb();
783
        spin_unlock_irqrestore(&host->lock, flags);
784
}
785
 
786
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
787
{
788
        struct sdhci_host *host;
789
        unsigned long flags;
790
        u8 ctrl;
791
 
792
        host = mmc_priv(mmc);
793
 
794
        spin_lock_irqsave(&host->lock, flags);
795
 
796
        /*
797
         * Reset the chip on each power off.
798
         * Should clear out any weird states.
799
         */
800
        if (ios->power_mode == MMC_POWER_OFF) {
801
                writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
802
                sdhci_init(host);
803
        }
804
 
805
        sdhci_set_clock(host, ios->clock);
806
 
807
        if (ios->power_mode == MMC_POWER_OFF)
808
                sdhci_set_power(host, -1);
809
        else
810
                sdhci_set_power(host, ios->vdd);
811
 
812
        ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
813
 
814
        if (ios->bus_width == MMC_BUS_WIDTH_4)
815
                ctrl |= SDHCI_CTRL_4BITBUS;
816
        else
817
                ctrl &= ~SDHCI_CTRL_4BITBUS;
818
 
819
        if (ios->timing == MMC_TIMING_SD_HS)
820
                ctrl |= SDHCI_CTRL_HISPD;
821
        else
822
                ctrl &= ~SDHCI_CTRL_HISPD;
823
 
824
        writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
825
 
826
        /*
827
         * Some (ENE) controllers go apeshit on some ios operation,
828
         * signalling timeout and CRC errors even on CMD0. Resetting
829
         * it on each ios seems to solve the problem.
830
         */
831
        if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
832
                sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
833
 
834
        mmiowb();
835
        spin_unlock_irqrestore(&host->lock, flags);
836
}
837
 
838
static int sdhci_get_ro(struct mmc_host *mmc)
839
{
840
        struct sdhci_host *host;
841
        unsigned long flags;
842
        int present;
843
 
844
        host = mmc_priv(mmc);
845
 
846
        spin_lock_irqsave(&host->lock, flags);
847
 
848
        present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
849
 
850
        spin_unlock_irqrestore(&host->lock, flags);
851
 
852
        return !(present & SDHCI_WRITE_PROTECT);
853
}
854
 
855
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
856
{
857
        struct sdhci_host *host;
858
        unsigned long flags;
859
        u32 ier;
860
 
861
        host = mmc_priv(mmc);
862
 
863
        spin_lock_irqsave(&host->lock, flags);
864
 
865
        ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
866
 
867
        ier &= ~SDHCI_INT_CARD_INT;
868
        if (enable)
869
                ier |= SDHCI_INT_CARD_INT;
870
 
871
        writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
872
        writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
873
 
874
        mmiowb();
875
 
876
        spin_unlock_irqrestore(&host->lock, flags);
877
}
878
 
879
static const struct mmc_host_ops sdhci_ops = {
880
        .request        = sdhci_request,
881
        .set_ios        = sdhci_set_ios,
882
        .get_ro         = sdhci_get_ro,
883
        .enable_sdio_irq = sdhci_enable_sdio_irq,
884
};
885
 
886
/*****************************************************************************\
887
 *                                                                           *
888
 * Tasklets                                                                  *
889
 *                                                                           *
890
\*****************************************************************************/
891
 
892
static void sdhci_tasklet_card(unsigned long param)
893
{
894
        struct sdhci_host *host;
895
        unsigned long flags;
896
 
897
        host = (struct sdhci_host*)param;
898
 
899
        spin_lock_irqsave(&host->lock, flags);
900
 
901
        if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
902
                if (host->mrq) {
903
                        printk(KERN_ERR "%s: Card removed during transfer!\n",
904
                                mmc_hostname(host->mmc));
905
                        printk(KERN_ERR "%s: Resetting controller.\n",
906
                                mmc_hostname(host->mmc));
907
 
908
                        sdhci_reset(host, SDHCI_RESET_CMD);
909
                        sdhci_reset(host, SDHCI_RESET_DATA);
910
 
911
                        host->mrq->cmd->error = -ENOMEDIUM;
912
                        tasklet_schedule(&host->finish_tasklet);
913
                }
914
        }
915
 
916
        spin_unlock_irqrestore(&host->lock, flags);
917
 
918
        mmc_detect_change(host->mmc, msecs_to_jiffies(500));
919
}
920
 
921
static void sdhci_tasklet_finish(unsigned long param)
922
{
923
        struct sdhci_host *host;
924
        unsigned long flags;
925
        struct mmc_request *mrq;
926
 
927
        host = (struct sdhci_host*)param;
928
 
929
        spin_lock_irqsave(&host->lock, flags);
930
 
931
        del_timer(&host->timer);
932
 
933
        mrq = host->mrq;
934
 
935
        /*
936
         * The controller needs a reset of internal state machines
937
         * upon error conditions.
938
         */
939
        if (mrq->cmd->error ||
940
                (mrq->data && (mrq->data->error ||
941
                (mrq->data->stop && mrq->data->stop->error))) ||
942
                (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
943
 
944
                /* Some controllers need this kick or reset won't work here */
945
                if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
946
                        unsigned int clock;
947
 
948
                        /* This is to force an update */
949
                        clock = host->clock;
950
                        host->clock = 0;
951
                        sdhci_set_clock(host, clock);
952
                }
953
 
954
                /* Spec says we should do both at the same time, but Ricoh
955
                   controllers do not like that. */
956
                sdhci_reset(host, SDHCI_RESET_CMD);
957
                sdhci_reset(host, SDHCI_RESET_DATA);
958
        }
959
 
960
        host->mrq = NULL;
961
        host->cmd = NULL;
962
        host->data = NULL;
963
 
964
        sdhci_deactivate_led(host);
965
 
966
        mmiowb();
967
        spin_unlock_irqrestore(&host->lock, flags);
968
 
969
        mmc_request_done(host->mmc, mrq);
970
}
971
 
972
static void sdhci_timeout_timer(unsigned long data)
973
{
974
        struct sdhci_host *host;
975
        unsigned long flags;
976
 
977
        host = (struct sdhci_host*)data;
978
 
979
        spin_lock_irqsave(&host->lock, flags);
980
 
981
        if (host->mrq) {
982
                printk(KERN_ERR "%s: Timeout waiting for hardware "
983
                        "interrupt.\n", mmc_hostname(host->mmc));
984
                sdhci_dumpregs(host);
985
 
986
                if (host->data) {
987
                        host->data->error = -ETIMEDOUT;
988
                        sdhci_finish_data(host);
989
                } else {
990
                        if (host->cmd)
991
                                host->cmd->error = -ETIMEDOUT;
992
                        else
993
                                host->mrq->cmd->error = -ETIMEDOUT;
994
 
995
                        tasklet_schedule(&host->finish_tasklet);
996
                }
997
        }
998
 
999
        mmiowb();
1000
        spin_unlock_irqrestore(&host->lock, flags);
1001
}
1002
 
1003
/*****************************************************************************\
1004
 *                                                                           *
1005
 * Interrupt handling                                                        *
1006
 *                                                                           *
1007
\*****************************************************************************/
1008
 
1009
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1010
{
1011
        BUG_ON(intmask == 0);
1012
 
1013
        if (!host->cmd) {
1014
                printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1015
                        "though no command operation was in progress.\n",
1016
                        mmc_hostname(host->mmc), (unsigned)intmask);
1017
                sdhci_dumpregs(host);
1018
                return;
1019
        }
1020
 
1021
        if (intmask & SDHCI_INT_TIMEOUT)
1022
                host->cmd->error = -ETIMEDOUT;
1023
        else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1024
                        SDHCI_INT_INDEX))
1025
                host->cmd->error = -EILSEQ;
1026
 
1027
        if (host->cmd->error)
1028
                tasklet_schedule(&host->finish_tasklet);
1029
        else if (intmask & SDHCI_INT_RESPONSE)
1030
                sdhci_finish_command(host);
1031
}
1032
 
1033
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1034
{
1035
        BUG_ON(intmask == 0);
1036
 
1037
        if (!host->data) {
1038
                /*
1039
                 * A data end interrupt is sent together with the response
1040
                 * for the stop command.
1041
                 */
1042
                if (intmask & SDHCI_INT_DATA_END)
1043
                        return;
1044
 
1045
                printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1046
                        "though no data operation was in progress.\n",
1047
                        mmc_hostname(host->mmc), (unsigned)intmask);
1048
                sdhci_dumpregs(host);
1049
 
1050
                return;
1051
        }
1052
 
1053
        if (intmask & SDHCI_INT_DATA_TIMEOUT)
1054
                host->data->error = -ETIMEDOUT;
1055
        else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1056
                host->data->error = -EILSEQ;
1057
 
1058
        if (host->data->error)
1059
                sdhci_finish_data(host);
1060
        else {
1061
                if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1062
                        sdhci_transfer_pio(host);
1063
 
1064
                /*
1065
                 * We currently don't do anything fancy with DMA
1066
                 * boundaries, but as we can't disable the feature
1067
                 * we need to at least restart the transfer.
1068
                 */
1069
                if (intmask & SDHCI_INT_DMA_END)
1070
                        writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1071
                                host->ioaddr + SDHCI_DMA_ADDRESS);
1072
 
1073
                if (intmask & SDHCI_INT_DATA_END) {
1074
                        if (host->cmd) {
1075
                                /*
1076
                                 * Data managed to finish before the
1077
                                 * command completed. Make sure we do
1078
                                 * things in the proper order.
1079
                                 */
1080
                                host->data_early = 1;
1081
                        } else {
1082
                                sdhci_finish_data(host);
1083
                        }
1084
                }
1085
        }
1086
}
1087
 
1088
static irqreturn_t sdhci_irq(int irq, void *dev_id)
1089
{
1090
        irqreturn_t result;
1091
        struct sdhci_host* host = dev_id;
1092
        u32 intmask;
1093
        int cardint = 0;
1094
 
1095
        spin_lock(&host->lock);
1096
 
1097
        intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1098
 
1099
        if (!intmask || intmask == 0xffffffff) {
1100
                result = IRQ_NONE;
1101
                goto out;
1102
        }
1103
 
1104
        DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1105
 
1106
        if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1107
                writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1108
                        host->ioaddr + SDHCI_INT_STATUS);
1109
                tasklet_schedule(&host->card_tasklet);
1110
        }
1111
 
1112
        intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1113
 
1114
        if (intmask & SDHCI_INT_CMD_MASK) {
1115
                writel(intmask & SDHCI_INT_CMD_MASK,
1116
                        host->ioaddr + SDHCI_INT_STATUS);
1117
                sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1118
        }
1119
 
1120
        if (intmask & SDHCI_INT_DATA_MASK) {
1121
                writel(intmask & SDHCI_INT_DATA_MASK,
1122
                        host->ioaddr + SDHCI_INT_STATUS);
1123
                sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1124
        }
1125
 
1126
        intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1127
 
1128
        intmask &= ~SDHCI_INT_ERROR;
1129
 
1130
        if (intmask & SDHCI_INT_BUS_POWER) {
1131
                printk(KERN_ERR "%s: Card is consuming too much power!\n",
1132
                        mmc_hostname(host->mmc));
1133
                writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1134
        }
1135
 
1136
        intmask &= ~SDHCI_INT_BUS_POWER;
1137
 
1138
        if (intmask & SDHCI_INT_CARD_INT)
1139
                cardint = 1;
1140
 
1141
        intmask &= ~SDHCI_INT_CARD_INT;
1142
 
1143
        if (intmask) {
1144
                printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1145
                        mmc_hostname(host->mmc), intmask);
1146
                sdhci_dumpregs(host);
1147
 
1148
                writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1149
        }
1150
 
1151
        result = IRQ_HANDLED;
1152
 
1153
        mmiowb();
1154
out:
1155
        spin_unlock(&host->lock);
1156
 
1157
        /*
1158
         * We have to delay this as it calls back into the driver.
1159
         */
1160
        if (cardint)
1161
                mmc_signal_sdio_irq(host->mmc);
1162
 
1163
        return result;
1164
}
1165
 
1166
/*****************************************************************************\
1167
 *                                                                           *
1168
 * Suspend/resume                                                            *
1169
 *                                                                           *
1170
\*****************************************************************************/
1171
 
1172
#ifdef CONFIG_PM
1173
 
1174
static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1175
{
1176
        struct sdhci_chip *chip;
1177
        int i, ret;
1178
 
1179
        chip = pci_get_drvdata(pdev);
1180
        if (!chip)
1181
                return 0;
1182
 
1183
        DBG("Suspending...\n");
1184
 
1185
        for (i = 0;i < chip->num_slots;i++) {
1186
                if (!chip->hosts[i])
1187
                        continue;
1188
                ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1189
                if (ret) {
1190
                        for (i--;i >= 0;i--)
1191
                                mmc_resume_host(chip->hosts[i]->mmc);
1192
                        return ret;
1193
                }
1194
        }
1195
 
1196
        pci_save_state(pdev);
1197
        pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1198
 
1199
        for (i = 0;i < chip->num_slots;i++) {
1200
                if (!chip->hosts[i])
1201
                        continue;
1202
                free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1203
        }
1204
 
1205
        pci_disable_device(pdev);
1206
        pci_set_power_state(pdev, pci_choose_state(pdev, state));
1207
 
1208
        return 0;
1209
}
1210
 
1211
static int sdhci_resume (struct pci_dev *pdev)
1212
{
1213
        struct sdhci_chip *chip;
1214
        int i, ret;
1215
 
1216
        chip = pci_get_drvdata(pdev);
1217
        if (!chip)
1218
                return 0;
1219
 
1220
        DBG("Resuming...\n");
1221
 
1222
        pci_set_power_state(pdev, PCI_D0);
1223
        pci_restore_state(pdev);
1224
        ret = pci_enable_device(pdev);
1225
        if (ret)
1226
                return ret;
1227
 
1228
        for (i = 0;i < chip->num_slots;i++) {
1229
                if (!chip->hosts[i])
1230
                        continue;
1231
                if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1232
                        pci_set_master(pdev);
1233
                ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1234
                        IRQF_SHARED, chip->hosts[i]->slot_descr,
1235
                        chip->hosts[i]);
1236
                if (ret)
1237
                        return ret;
1238
                sdhci_init(chip->hosts[i]);
1239
                mmiowb();
1240
                ret = mmc_resume_host(chip->hosts[i]->mmc);
1241
                if (ret)
1242
                        return ret;
1243
        }
1244
 
1245
        return 0;
1246
}
1247
 
1248
#else /* CONFIG_PM */
1249
 
1250
#define sdhci_suspend NULL
1251
#define sdhci_resume NULL
1252
 
1253
#endif /* CONFIG_PM */
1254
 
1255
/*****************************************************************************\
1256
 *                                                                           *
1257
 * Device probing/removal                                                    *
1258
 *                                                                           *
1259
\*****************************************************************************/
1260
 
1261
static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1262
{
1263
        int ret;
1264
        unsigned int version;
1265
        struct sdhci_chip *chip;
1266
        struct mmc_host *mmc;
1267
        struct sdhci_host *host;
1268
 
1269
        u8 first_bar;
1270
        unsigned int caps;
1271
 
1272
        chip = pci_get_drvdata(pdev);
1273
        BUG_ON(!chip);
1274
 
1275
        ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1276
        if (ret)
1277
                return ret;
1278
 
1279
        first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1280
 
1281
        if (first_bar > 5) {
1282
                printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1283
                return -ENODEV;
1284
        }
1285
 
1286
        if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1287
                printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1288
                return -ENODEV;
1289
        }
1290
 
1291
        if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1292
                printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1293
                        "You may experience problems.\n");
1294
        }
1295
 
1296
        if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1297
                printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1298
                return -ENODEV;
1299
        }
1300
 
1301
        if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1302
                printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1303
                return -ENODEV;
1304
        }
1305
 
1306
        mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1307
        if (!mmc)
1308
                return -ENOMEM;
1309
 
1310
        host = mmc_priv(mmc);
1311
        host->mmc = mmc;
1312
 
1313
        host->chip = chip;
1314
        chip->hosts[slot] = host;
1315
 
1316
        host->bar = first_bar + slot;
1317
 
1318
        host->addr = pci_resource_start(pdev, host->bar);
1319
        host->irq = pdev->irq;
1320
 
1321
        DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1322
 
1323
        snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1324
 
1325
        ret = pci_request_region(pdev, host->bar, host->slot_descr);
1326
        if (ret)
1327
                goto free;
1328
 
1329
        host->ioaddr = ioremap_nocache(host->addr,
1330
                pci_resource_len(pdev, host->bar));
1331
        if (!host->ioaddr) {
1332
                ret = -ENOMEM;
1333
                goto release;
1334
        }
1335
 
1336
        sdhci_reset(host, SDHCI_RESET_ALL);
1337
 
1338
        version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1339
        version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1340
        if (version > 1) {
1341
                printk(KERN_ERR "%s: Unknown controller version (%d). "
1342
                        "You may experience problems.\n", host->slot_descr,
1343
                        version);
1344
        }
1345
 
1346
        caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1347
 
1348
        if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1349
                host->flags |= SDHCI_USE_DMA;
1350
        else if (!(caps & SDHCI_CAN_DO_DMA))
1351
                DBG("Controller doesn't have DMA capability\n");
1352
        else
1353
                host->flags |= SDHCI_USE_DMA;
1354
 
1355
        if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1356
                (host->flags & SDHCI_USE_DMA)) {
1357
                DBG("Disabling DMA as it is marked broken\n");
1358
                host->flags &= ~SDHCI_USE_DMA;
1359
        }
1360
 
1361
        if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1362
                (host->flags & SDHCI_USE_DMA)) {
1363
                printk(KERN_WARNING "%s: Will use DMA "
1364
                        "mode even though HW doesn't fully "
1365
                        "claim to support it.\n", host->slot_descr);
1366
        }
1367
 
1368
        if (host->flags & SDHCI_USE_DMA) {
1369
                if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1370
                        printk(KERN_WARNING "%s: No suitable DMA available. "
1371
                                "Falling back to PIO.\n", host->slot_descr);
1372
                        host->flags &= ~SDHCI_USE_DMA;
1373
                }
1374
        }
1375
 
1376
        if (host->flags & SDHCI_USE_DMA)
1377
                pci_set_master(pdev);
1378
        else /* XXX: Hack to get MMC layer to avoid highmem */
1379
                pdev->dma_mask = 0;
1380
 
1381
        host->max_clk =
1382
                (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1383
        if (host->max_clk == 0) {
1384
                printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1385
                        "frequency.\n", host->slot_descr);
1386
                ret = -ENODEV;
1387
                goto unmap;
1388
        }
1389
        host->max_clk *= 1000000;
1390
 
1391
        host->timeout_clk =
1392
                (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1393
        if (host->timeout_clk == 0) {
1394
                printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1395
                        "frequency.\n", host->slot_descr);
1396
                ret = -ENODEV;
1397
                goto unmap;
1398
        }
1399
        if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1400
                host->timeout_clk *= 1000;
1401
 
1402
        /*
1403
         * Set host parameters.
1404
         */
1405
        mmc->ops = &sdhci_ops;
1406
        mmc->f_min = host->max_clk / 256;
1407
        mmc->f_max = host->max_clk;
1408
        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1409
 
1410
        if (caps & SDHCI_CAN_DO_HISPD)
1411
                mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1412
 
1413
        mmc->ocr_avail = 0;
1414
        if (caps & SDHCI_CAN_VDD_330)
1415
                mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1416
        if (caps & SDHCI_CAN_VDD_300)
1417
                mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1418
        if (caps & SDHCI_CAN_VDD_180)
1419
                mmc->ocr_avail |= MMC_VDD_165_195;
1420
 
1421
        if (mmc->ocr_avail == 0) {
1422
                printk(KERN_ERR "%s: Hardware doesn't report any "
1423
                        "support voltages.\n", host->slot_descr);
1424
                ret = -ENODEV;
1425
                goto unmap;
1426
        }
1427
 
1428
        spin_lock_init(&host->lock);
1429
 
1430
        /*
1431
         * Maximum number of segments. Hardware cannot do scatter lists.
1432
         */
1433
        if (host->flags & SDHCI_USE_DMA)
1434
                mmc->max_hw_segs = 1;
1435
        else
1436
                mmc->max_hw_segs = 16;
1437
        mmc->max_phys_segs = 16;
1438
 
1439
        /*
1440
         * Maximum number of sectors in one transfer. Limited by DMA boundary
1441
         * size (512KiB).
1442
         */
1443
        mmc->max_req_size = 524288;
1444
 
1445
        /*
1446
         * Maximum segment size. Could be one segment with the maximum number
1447
         * of bytes.
1448
         */
1449
        mmc->max_seg_size = mmc->max_req_size;
1450
 
1451
        /*
1452
         * Maximum block size. This varies from controller to controller and
1453
         * is specified in the capabilities register.
1454
         */
1455
        mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1456
        if (mmc->max_blk_size >= 3) {
1457
                printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1458
                        host->slot_descr);
1459
                mmc->max_blk_size = 512;
1460
        } else
1461
                mmc->max_blk_size = 512 << mmc->max_blk_size;
1462
 
1463
        /*
1464
         * Maximum block count.
1465
         */
1466
        mmc->max_blk_count = 65535;
1467
 
1468
        /*
1469
         * Init tasklets.
1470
         */
1471
        tasklet_init(&host->card_tasklet,
1472
                sdhci_tasklet_card, (unsigned long)host);
1473
        tasklet_init(&host->finish_tasklet,
1474
                sdhci_tasklet_finish, (unsigned long)host);
1475
 
1476
        setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1477
 
1478
        ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1479
                host->slot_descr, host);
1480
        if (ret)
1481
                goto untasklet;
1482
 
1483
        sdhci_init(host);
1484
 
1485
#ifdef CONFIG_MMC_DEBUG
1486
        sdhci_dumpregs(host);
1487
#endif
1488
 
1489
        mmiowb();
1490
 
1491
        mmc_add_host(mmc);
1492
 
1493
        printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1494
                host->addr, host->irq,
1495
                (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1496
 
1497
        return 0;
1498
 
1499
untasklet:
1500
        tasklet_kill(&host->card_tasklet);
1501
        tasklet_kill(&host->finish_tasklet);
1502
unmap:
1503
        iounmap(host->ioaddr);
1504
release:
1505
        pci_release_region(pdev, host->bar);
1506
free:
1507
        mmc_free_host(mmc);
1508
 
1509
        return ret;
1510
}
1511
 
1512
static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1513
{
1514
        struct sdhci_chip *chip;
1515
        struct mmc_host *mmc;
1516
        struct sdhci_host *host;
1517
 
1518
        chip = pci_get_drvdata(pdev);
1519
        host = chip->hosts[slot];
1520
        mmc = host->mmc;
1521
 
1522
        chip->hosts[slot] = NULL;
1523
 
1524
        mmc_remove_host(mmc);
1525
 
1526
        sdhci_reset(host, SDHCI_RESET_ALL);
1527
 
1528
        free_irq(host->irq, host);
1529
 
1530
        del_timer_sync(&host->timer);
1531
 
1532
        tasklet_kill(&host->card_tasklet);
1533
        tasklet_kill(&host->finish_tasklet);
1534
 
1535
        iounmap(host->ioaddr);
1536
 
1537
        pci_release_region(pdev, host->bar);
1538
 
1539
        mmc_free_host(mmc);
1540
}
1541
 
1542
static int __devinit sdhci_probe(struct pci_dev *pdev,
1543
        const struct pci_device_id *ent)
1544
{
1545
        int ret, i;
1546
        u8 slots, rev;
1547
        struct sdhci_chip *chip;
1548
 
1549
        BUG_ON(pdev == NULL);
1550
        BUG_ON(ent == NULL);
1551
 
1552
        pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1553
 
1554
        printk(KERN_INFO DRIVER_NAME
1555
                ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1556
                pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1557
                (int)rev);
1558
 
1559
        ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1560
        if (ret)
1561
                return ret;
1562
 
1563
        slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1564
        DBG("found %d slot(s)\n", slots);
1565
        if (slots == 0)
1566
                return -ENODEV;
1567
 
1568
        ret = pci_enable_device(pdev);
1569
        if (ret)
1570
                return ret;
1571
 
1572
        chip = kzalloc(sizeof(struct sdhci_chip) +
1573
                sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1574
        if (!chip) {
1575
                ret = -ENOMEM;
1576
                goto err;
1577
        }
1578
 
1579
        chip->pdev = pdev;
1580
        chip->quirks = ent->driver_data;
1581
 
1582
        if (debug_quirks)
1583
                chip->quirks = debug_quirks;
1584
 
1585
        chip->num_slots = slots;
1586
        pci_set_drvdata(pdev, chip);
1587
 
1588
        for (i = 0;i < slots;i++) {
1589
                ret = sdhci_probe_slot(pdev, i);
1590
                if (ret) {
1591
                        for (i--;i >= 0;i--)
1592
                                sdhci_remove_slot(pdev, i);
1593
                        goto free;
1594
                }
1595
        }
1596
 
1597
        return 0;
1598
 
1599
free:
1600
        pci_set_drvdata(pdev, NULL);
1601
        kfree(chip);
1602
 
1603
err:
1604
        pci_disable_device(pdev);
1605
        return ret;
1606
}
1607
 
1608
static void __devexit sdhci_remove(struct pci_dev *pdev)
1609
{
1610
        int i;
1611
        struct sdhci_chip *chip;
1612
 
1613
        chip = pci_get_drvdata(pdev);
1614
 
1615
        if (chip) {
1616
                for (i = 0;i < chip->num_slots;i++)
1617
                        sdhci_remove_slot(pdev, i);
1618
 
1619
                pci_set_drvdata(pdev, NULL);
1620
 
1621
                kfree(chip);
1622
        }
1623
 
1624
        pci_disable_device(pdev);
1625
}
1626
 
1627
static struct pci_driver sdhci_driver = {
1628
        .name =         DRIVER_NAME,
1629
        .id_table =     pci_ids,
1630
        .probe =        sdhci_probe,
1631
        .remove =       __devexit_p(sdhci_remove),
1632
        .suspend =      sdhci_suspend,
1633
        .resume =       sdhci_resume,
1634
};
1635
 
1636
/*****************************************************************************\
1637
 *                                                                           *
1638
 * Driver init/exit                                                          *
1639
 *                                                                           *
1640
\*****************************************************************************/
1641
 
1642
static int __init sdhci_drv_init(void)
1643
{
1644
        printk(KERN_INFO DRIVER_NAME
1645
                ": Secure Digital Host Controller Interface driver\n");
1646
        printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1647
 
1648
        return pci_register_driver(&sdhci_driver);
1649
}
1650
 
1651
static void __exit sdhci_drv_exit(void)
1652
{
1653
        DBG("Exiting\n");
1654
 
1655
        pci_unregister_driver(&sdhci_driver);
1656
}
1657
 
1658
module_init(sdhci_drv_init);
1659
module_exit(sdhci_drv_exit);
1660
 
1661
module_param(debug_quirks, uint, 0444);
1662
 
1663
MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1664
MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1665
MODULE_LICENSE("GPL");
1666
 
1667
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");

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