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/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */

/*

        Written 1996-1999 by Donald Becker.

        This software may be used and distributed according to the terms

        of the GNU General Public License, incorporated herein by reference.

        This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.

        Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597

        and the EtherLink XL 3c900 and 3c905 cards.

        Problem reports and questions should be directed to

        vortex@scyld.com

        The author may be reached as becker@scyld.com, or C/O

        Scyld Computing Corporation

        410 Severn Ave., Suite 210

        Annapolis MD 21403

*/

/*

 * FIXME: This driver _could_ support MTU changing, but doesn't.  See Don's hamachi.c implementation

 * as well as other drivers

 *

 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k

 * due to dead code elimination.  There will be some performance benefits from this due to

 * elimination of all the tests and reduced cache footprint.

 */

#define DRV_NAME        "3c59x"

/* A few values that may be tweaked. */

/* Keep the ring sizes a power of two for efficiency. */

#define TX_RING_SIZE    16

#define RX_RING_SIZE    32

#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/

/* "Knobs" that adjust features and parameters. */

/* Set the copy breakpoint for the copy-only-tiny-frames scheme.

   Setting to > 1512 effectively disables this feature. */

#ifndef __arm__

static int rx_copybreak = 200;

#else

/* ARM systems perform better by disregarding the bus-master

   transfer capability of these cards. -- rmk */

static int rx_copybreak = 1513;

#endif

/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */

static const int mtu = 1500;

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

static int max_interrupt_work = 32;

/* Tx timeout interval (millisecs) */

static int watchdog = 5000;

/* Allow aggregation of Tx interrupts.  Saves CPU load at the cost

 * of possible Tx stalls if the system is blocking interrupts

 * somewhere else.  Undefine this to disable.

 */

#define tx_interrupt_mitigation 1

/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */

#define vortex_debug debug

#ifdef VORTEX_DEBUG

static int vortex_debug = VORTEX_DEBUG;

#else

static int vortex_debug = 1;

#endif

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/string.h>

#include <linux/timer.h>

#include <linux/errno.h>

#include <linux/in.h>

#include <linux/ioport.h>

#include <linux/slab.h>

#include <linux/interrupt.h>

#include <linux/pci.h>

#include <linux/mii.h>

#include <linux/init.h>

#include <linux/netdevice.h>

#include <linux/etherdevice.h>

#include <linux/skbuff.h>

#include <linux/ethtool.h>

#include <linux/highmem.h>

#include <linux/eisa.h>

#include <linux/bitops.h>

#include <linux/jiffies.h>

#include <asm/irq.h>                    /* For NR_IRQS only. */

#include <asm/io.h>

#include <asm/uaccess.h>

/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.

   This is only in the support-all-kernels source code. */

#define RUN_AT(x) (jiffies + (x))

#include <linux/delay.h>

static char version[] __devinitdata =

DRV_NAME ": Donald Becker and others.\n";

MODULE_AUTHOR("Donald Becker <becker@scyld.com>");

MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");

MODULE_LICENSE("GPL");

/* Operational parameter that usually are not changed. */

/* The Vortex size is twice that of the original EtherLinkIII series: the

   runtime register window, window 1, is now always mapped in.

   The Boomerang size is twice as large as the Vortex -- it has additional

   bus master control registers. */

#define VORTEX_TOTAL_SIZE 0x20

#define BOOMERANG_TOTAL_SIZE 0x40

/* Set iff a MII transceiver on any interface requires mdio preamble.

   This only set with the original DP83840 on older 3c905 boards, so the extra

   code size of a per-interface flag is not worthwhile. */

static char mii_preamble_required;

#define PFX DRV_NAME ": "

/*

                                Theory of Operation

I. Board Compatibility

This device driver is designed for the 3Com FastEtherLink and FastEtherLink

XL, 3Com's PCI to 10/100baseT adapters.  It also works with the 10Mbs

versions of the FastEtherLink cards.  The supported product IDs are

  3c590, 3c592, 3c595, 3c597, 3c900, 3c905

The related ISA 3c515 is supported with a separate driver, 3c515.c, included

with the kernel source or available from

    cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html

II. Board-specific settings

PCI bus devices are configured by the system at boot time, so no jumpers

need to be set on the board.  The system BIOS should be set to assign the

PCI INTA signal to an otherwise unused system IRQ line.

The EEPROM settings for media type and forced-full-duplex are observed.

The EEPROM media type should be left at the default "autoselect" unless using

10base2 or AUI connections which cannot be reliably detected.

III. Driver operation

The 3c59x series use an interface that's very similar to the previous 3c5x9

series.  The primary interface is two programmed-I/O FIFOs, with an

alternate single-contiguous-region bus-master transfer (see next).

The 3c900 "Boomerang" series uses a full-bus-master interface with separate

lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,

DEC Tulip and Intel Speedo3.  The first chip version retains a compatible

programmed-I/O interface that has been removed in 'B' and subsequent board

revisions.

One extension that is advertised in a very large font is that the adapters

are capable of being bus masters.  On the Vortex chip this capability was

only for a single contiguous region making it far less useful than the full

bus master capability.  There is a significant performance impact of taking

an extra interrupt or polling for the completion of each transfer, as well

as difficulty sharing the single transfer engine between the transmit and

receive threads.  Using DMA transfers is a win only with large blocks or

with the flawed versions of the Intel Orion motherboard PCI controller.

The Boomerang chip's full-bus-master interface is useful, and has the

currently-unused advantages over other similar chips that queued transmit

packets may be reordered and receive buffer groups are associated with a

single frame.

With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.

Rather than a fixed intermediate receive buffer, this scheme allocates

full-sized skbuffs as receive buffers.  The value RX_COPYBREAK is used as

the copying breakpoint: it is chosen to trade-off the memory wasted by

passing the full-sized skbuff to the queue layer for all frames vs. the

copying cost of copying a frame to a correctly-sized skbuff.

IIIC. Synchronization

The driver runs as two independent, single-threaded flows of control.  One

is the send-packet routine, which enforces single-threaded use by the

dev->tbusy flag.  The other thread is the interrupt handler, which is single

threaded by the hardware and other software.

IV. Notes

Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development

3c590, 3c595, and 3c900 boards.

The name "Vortex" is the internal 3Com project name for the PCI ASIC, and

the EISA version is called "Demon".  According to Terry these names come

from rides at the local amusement park.

The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!

This driver only supports ethernet packets because of the skbuff allocation

limit of 4K.

*/

/* This table drives the PCI probe routines.  It's mostly boilerplate in all

   of the drivers, and will likely be provided by some future kernel.

*/

enum pci_flags_bit {

        PCI_USES_MASTER=4,

};

enum {  IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,

        EEPROM_8BIT=0x10,       /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */

        HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,

        INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,

        EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,

        EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };

enum vortex_chips {

        CH_3C590 = 0,

        CH_3C592,

        CH_3C597,

        CH_3C595_1,

        CH_3C595_2,

        CH_3C595_3,

        CH_3C900_1,

        CH_3C900_2,

        CH_3C900_3,

        CH_3C900_4,

        CH_3C900_5,

        CH_3C900B_FL,

        CH_3C905_1,

        CH_3C905_2,

        CH_3C905B_1,

        CH_3C905B_2,

        CH_3C905B_FX,

        CH_3C905C,

        CH_3C9202,

        CH_3C980,

        CH_3C9805,

        CH_3CSOHO100_TX,

        CH_3C555,

        CH_3C556,

        CH_3C556B,

        CH_3C575,

        CH_3C575_1,

        CH_3CCFE575,

        CH_3CCFE575CT,

        CH_3CCFE656,

        CH_3CCFEM656,

        CH_3CCFEM656_1,

        CH_3C450,

        CH_3C920,

        CH_3C982A,

        CH_3C982B,

        CH_905BT4,

        CH_920B_EMB_WNM,

};

/* note: this array directly indexed by above enums, and MUST

 * be kept in sync with both the enums above, and the PCI device

 * table below

 */

static struct vortex_chip_info {

        const char *name;

        int flags;

        int drv_flags;

        int io_size;

} vortex_info_tbl[] __devinitdata = {

        {"3c590 Vortex 10Mbps",

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c592 EISA 10Mbps Demon/Vortex",                                      /* AKPM: from Don's 3c59x_cb.c 0.49H */

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c597 EISA Fast Demon/Vortex",                                        /* AKPM: from Don's 3c59x_cb.c 0.49H */

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c595 Vortex 100baseTx",

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c595 Vortex 100baseT4",

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c595 Vortex 100base-MII",

         PCI_USES_MASTER, IS_VORTEX, 32, },

        {"3c900 Boomerang 10baseT",

         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

        {"3c900 Boomerang 10Mbps Combo",

         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

        {"3c900 Cyclone 10Mbps TPO",                                            /* AKPM: from Don's 0.99M */

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c900 Cyclone 10Mbps Combo",

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c900 Cyclone 10Mbps TPC",                                            /* AKPM: from Don's 0.99M */

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c900B-FL Cyclone 10base-FL",

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c905 Boomerang 100baseTx",

         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

        {"3c905 Boomerang 100baseT4",

         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

        {"3c905B Cyclone 100baseTx",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

        {"3c905B Cyclone 10/100/BNC",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

        {"3c905B-FX Cyclone 100baseFx",

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c905C Tornado",

        PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

        {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",

         PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },

        {"3c980 Cyclone",

         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

        {"3c980C Python-T",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

        {"3cSOHO100-TX Hurricane",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

        {"3c555 Laptop Hurricane",

         PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },

        {"3c556 Laptop Tornado",

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|

                                                                        HAS_HWCKSM, 128, },

        {"3c556B Laptop Hurricane",

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|

                                        WNO_XCVR_PWR|HAS_HWCKSM, 128, },

        {"3c575 [Megahertz] 10/100 LAN  CardBus",

        PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

        {"3c575 Boomerang CardBus",

         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

        {"3CCFE575BT Cyclone CardBus",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|

                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },

        {"3CCFE575CT Tornado CardBus",

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },

        {"3CCFE656 Cyclone CardBus",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },

        {"3CCFEM656B Cyclone+Winmodem CardBus",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },

        {"3CXFEM656C Tornado+Winmodem CardBus",                 /* From pcmcia-cs-3.1.5 */

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },

        {"3c450 HomePNA Tornado",                                               /* AKPM: from Don's 0.99Q */

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

        {"3c920 Tornado",

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

        {"3c982 Hydra Dual Port A",

         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },

        {"3c982 Hydra Dual Port B",

         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },

        {"3c905B-T4",

         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

        {"3c920B-EMB-WNM Tornado",

         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

        {NULL,}, /* NULL terminated list. */

};

static struct pci_device_id vortex_pci_tbl[] = {

        { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },

        { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },

        { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },

        { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },

        { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },

        { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },

        { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },

        { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },

        { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },

        { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },

        { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },

        { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },

        { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },

        { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },

        { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },

        { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },

        { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },

        { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },

        { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },

        { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },

        { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },

        { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },

        { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },

        { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },

        { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },

        { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },

        { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },

        { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },

        { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },

        { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },

        { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },

        { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },

        { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },

        { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },

        { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },

        { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },

        { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },

        { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },

        {0,}                                             /* 0 terminated list. */

};

MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);

/* Operational definitions.

   These are not used by other compilation units and thus are not

   exported in a ".h" file.

   First the windows.  There are eight register windows, with the command

   and status registers available in each.

   */

#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)

#define EL3_CMD 0x0e

#define EL3_STATUS 0x0e

/* The top five bits written to EL3_CMD are a command, the lower

   11 bits are the parameter, if applicable.

   Note that 11 parameters bits was fine for ethernet, but the new chip

   can handle FDDI length frames (~4500 octets) and now parameters count

   32-bit 'Dwords' rather than octets. */

enum vortex_cmd {

        TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,

        RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,

        UpStall = 6<<11, UpUnstall = (6<<11)+1,

        DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,

        RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,

        FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,

        SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,

        SetTxThreshold = 18<<11, SetTxStart = 19<<11,

        StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,

        StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};

/* The SetRxFilter command accepts the following classes: */

enum RxFilter {

        RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };

/* Bits in the general status register. */

enum vortex_status {

        IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,

        TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,

        IntReq = 0x0040, StatsFull = 0x0080,

        DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,

        DMAInProgress = 1<<11,                  /* DMA controller is still busy.*/

        CmdInProgress = 1<<12,                  /* EL3_CMD is still busy.*/

};

/* Register window 1 offsets, the window used in normal operation.

   On the Vortex this window is always mapped at offsets 0x10-0x1f. */

enum Window1 {

        TX_FIFO = 0x10,  RX_FIFO = 0x10,  RxErrors = 0x14,

        RxStatus = 0x18,  Timer=0x1A, TxStatus = 0x1B,

        TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */

};

enum Window0 {

        Wn0EepromCmd = 10,              /* Window 0: EEPROM command register. */

        Wn0EepromData = 12,             /* Window 0: EEPROM results register. */

        IntrStatus=0x0E,                /* Valid in all windows. */

};

enum Win0_EEPROM_bits {

        EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,

        EEPROM_EWENB = 0x30,            /* Enable erasing/writing for 10 msec. */

        EEPROM_EWDIS = 0x00,            /* Disable EWENB before 10 msec timeout. */

};

/* EEPROM locations. */

enum eeprom_offset {

        PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,

        EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,

        NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,

        DriverTune=13, Checksum=15};

enum Window2 {                  /* Window 2. */

        Wn2_ResetOptions=12,

};

enum Window3 {                  /* Window 3: MAC/config bits. */

        Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,

};

#define BFEXT(value, offset, bitcount)  \

    ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))

#define BFINS(lhs, rhs, offset, bitcount)                                       \

        (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   \

        (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))

#define RAM_SIZE(v)             BFEXT(v, 0, 3)

#define RAM_WIDTH(v)    BFEXT(v, 3, 1)

#define RAM_SPEED(v)    BFEXT(v, 4, 2)

#define ROM_SIZE(v)             BFEXT(v, 6, 2)

#define RAM_SPLIT(v)    BFEXT(v, 16, 2)

#define XCVR(v)                 BFEXT(v, 20, 4)

#define AUTOSELECT(v)   BFEXT(v, 24, 1)

enum Window4 {          /* Window 4: Xcvr/media bits. */

        Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,

};

enum Win4_Media_bits {

        Media_SQE = 0x0008,             /* Enable SQE error counting for AUI. */

        Media_10TP = 0x00C0,    /* Enable link beat and jabber for 10baseT. */

        Media_Lnk = 0x0080,             /* Enable just link beat for 100TX/100FX. */

        Media_LnkBeat = 0x0800,

};

enum Window7 {                                  /* Window 7: Bus Master control. */

        Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,

        Wn7_MasterStatus = 12,

};

/* Boomerang bus master control registers. */

enum MasterCtrl {

        PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,

        TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,

};

/* The Rx and Tx descriptor lists.

   Caution Alpha hackers: these types are 32 bits!  Note also the 8 byte

   alignment contraint on tx_ring[] and rx_ring[]. */

#define LAST_FRAG       0x80000000                      /* Last Addr/Len pair in descriptor. */

#define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */

struct boom_rx_desc {

        __le32 next;                                    /* Last entry points to 0.   */

        __le32 status;

        __le32 addr;                                    /* Up to 63 addr/len pairs possible. */

        __le32 length;                                  /* Set LAST_FRAG to indicate last pair. */

};

/* Values for the Rx status entry. */

enum rx_desc_status {

        RxDComplete=0x00008000, RxDError=0x4000,

        /* See boomerang_rx() for actual error bits */

        IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,

        IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,

};

#ifdef MAX_SKB_FRAGS

#define DO_ZEROCOPY 1

#else

#define DO_ZEROCOPY 0

#endif

struct boom_tx_desc {

        __le32 next;                                    /* Last entry points to 0.   */

        __le32 status;                                  /* bits 0:12 length, others see below.  */

#if DO_ZEROCOPY

        struct {

                __le32 addr;

                __le32 length;

        } frag[1+MAX_SKB_FRAGS];

#else

                __le32 addr;

                __le32 length;

#endif

};

/* Values for the Tx status entry. */

enum tx_desc_status {

        CRCDisable=0x2000, TxDComplete=0x8000,

        AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,

        TxIntrUploaded=0x80000000,              /* IRQ when in FIFO, but maybe not sent. */

};

/* Chip features we care about in vp->capabilities, read from the EEPROM. */

enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };

struct vortex_extra_stats {

        unsigned long tx_deferred;

        unsigned long tx_max_collisions;

        unsigned long tx_multiple_collisions;

        unsigned long tx_single_collisions;

        unsigned long rx_bad_ssd;

};

struct vortex_private {

        /* The Rx and Tx rings should be quad-word-aligned. */

        struct boom_rx_desc* rx_ring;

        struct boom_tx_desc* tx_ring;

        dma_addr_t rx_ring_dma;

        dma_addr_t tx_ring_dma;

        /* The addresses of transmit- and receive-in-place skbuffs. */

        struct sk_buff* rx_skbuff[RX_RING_SIZE];

        struct sk_buff* tx_skbuff[TX_RING_SIZE];

        unsigned int cur_rx, cur_tx;            /* The next free ring entry */

        unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */

        struct net_device_stats stats;          /* Generic stats */

        struct vortex_extra_stats xstats;       /* NIC-specific extra stats */

        struct sk_buff *tx_skb;                         /* Packet being eaten by bus master ctrl.  */

        dma_addr_t tx_skb_dma;                          /* Allocated DMA address for bus master ctrl DMA.   */

        /* PCI configuration space information. */

        struct device *gendev;

        void __iomem *ioaddr;                   /* IO address space */

        void __iomem *cb_fn_base;               /* CardBus function status addr space. */

        /* Some values here only for performance evaluation and path-coverage */

        int rx_nocopy, rx_copy, queued_packet, rx_csumhits;

        int card_idx;

        /* The remainder are related to chip state, mostly media selection. */

        struct timer_list timer;                        /* Media selection timer. */

        struct timer_list rx_oom_timer;         /* Rx skb allocation retry timer */

        int options;                                            /* User-settable misc. driver options. */

        unsigned int media_override:4,          /* Passed-in media type. */

                default_media:4,                                /* Read from the EEPROM/Wn3_Config. */

                full_duplex:1, autoselect:1,

                bus_master:1,                                   /* Vortex can only do a fragment bus-m. */

                full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang  */

                flow_ctrl:1,                                    /* Use 802.3x flow control (PAUSE only) */

                partner_flow_ctrl:1,                    /* Partner supports flow control */

                has_nway:1,

                enable_wol:1,                                   /* Wake-on-LAN is enabled */

                pm_state_valid:1,                               /* pci_dev->saved_config_space has sane contents */

                open:1,

                medialock:1,

                must_free_region:1,                             /* Flag: if zero, Cardbus owns the I/O region */

                large_frames:1;                 /* accept large frames */

        int drv_flags;

        u16 status_enable;

        u16 intr_enable;

        u16 available_media;                            /* From Wn3_Options. */

        u16 capabilities, info1, info2;         /* Various, from EEPROM. */

        u16 advertising;                                        /* NWay media advertisement */

        unsigned char phys[2];                          /* MII device addresses. */

        u16 deferred;                                           /* Resend these interrupts when we

                                                                                 * bale from the ISR */

        u16 io_size;                                            /* Size of PCI region (for release_region) */

        spinlock_t lock;                                        /* Serialise access to device & its vortex_private */

        struct mii_if_info mii;                         /* MII lib hooks/info */

};

#ifdef CONFIG_PCI