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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [net/] [arm/] [am79c961a.h] - Blame information for rev 62

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Line No. Rev Author Line
1 62 marcus.erl
/*
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 * linux/drivers/net/arm/am79c961a.h
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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 */
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#ifndef _LINUX_am79c961a_H
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#define _LINUX_am79c961a_H
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/* use 0 for production, 1 for verification, >2 for debug. debug flags: */
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#define DEBUG_TX         2
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#define DEBUG_RX         4
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#define DEBUG_INT        8
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#define DEBUG_IC        16
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#ifndef NET_DEBUG
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#define NET_DEBUG       0
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#endif
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#define NET_UID         0
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#define NET_RDP         0x10
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#define NET_RAP         0x12
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#define NET_RESET       0x14
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#define NET_IDP         0x16
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/*
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 * RAP registers
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 */
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#define CSR0            0
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#define CSR0_INIT       0x0001
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#define CSR0_STRT       0x0002
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#define CSR0_STOP       0x0004
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#define CSR0_TDMD       0x0008
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#define CSR0_TXON       0x0010
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#define CSR0_RXON       0x0020
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#define CSR0_IENA       0x0040
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#define CSR0_INTR       0x0080
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#define CSR0_IDON       0x0100
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#define CSR0_TINT       0x0200
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#define CSR0_RINT       0x0400
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#define CSR0_MERR       0x0800
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#define CSR0_MISS       0x1000
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#define CSR0_CERR       0x2000
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#define CSR0_BABL       0x4000
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#define CSR0_ERR        0x8000
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#define CSR3            3
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#define CSR3_EMBA       0x0008
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#define CSR3_DXMT2PD    0x0010
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#define CSR3_LAPPEN     0x0020
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#define CSR3_DXSUFLO    0x0040
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#define CSR3_IDONM      0x0100
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#define CSR3_TINTM      0x0200
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#define CSR3_RINTM      0x0400
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#define CSR3_MERRM      0x0800
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#define CSR3_MISSM      0x1000
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#define CSR3_BABLM      0x4000
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#define CSR3_MASKALL    0x5F00
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#define CSR4            4
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#define CSR4_JABM       0x0001
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#define CSR4_JAB        0x0002
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#define CSR4_TXSTRTM    0x0004
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#define CSR4_TXSTRT     0x0008
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#define CSR4_RCVCCOM    0x0010
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#define CSR4_RCVCCO     0x0020
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#define CSR4_MFCOM      0x0100
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#define CSR4_MFCO       0x0200
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#define CSR4_ASTRP_RCV  0x0400
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#define CSR4_APAD_XMIT  0x0800
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#define CTRL1           5
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#define CTRL1_SPND      0x0001
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#define LADRL           8
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#define LADRM1          9
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#define LADRM2          10
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#define LADRH           11
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#define PADRL           12
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#define PADRM           13
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#define PADRH           14
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#define MODE            15
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#define MODE_DISRX      0x0001
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#define MODE_DISTX      0x0002
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#define MODE_LOOP       0x0004
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#define MODE_DTCRC      0x0008
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#define MODE_COLL       0x0010
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#define MODE_DRETRY     0x0020
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#define MODE_INTLOOP    0x0040
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#define MODE_PORT_AUI   0x0000
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#define MODE_PORT_10BT  0x0080
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#define MODE_DRXPA      0x2000
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#define MODE_DRXBA      0x4000
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#define MODE_PROMISC    0x8000
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#define BASERXL         24
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#define BASERXH         25
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#define BASETXL         30
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#define BASETXH         31
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#define POLLINT         47
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#define SIZERXR         76
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#define SIZETXR         78
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#define CSR_MFC         112
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#define RMD_ENP         0x0100
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#define RMD_STP         0x0200
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#define RMD_CRC         0x0800
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#define RMD_FRAM        0x2000
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#define RMD_ERR         0x4000
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#define RMD_OWN         0x8000
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#define TMD_ENP         0x0100
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#define TMD_STP         0x0200
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#define TMD_MORE        0x1000
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#define TMD_ERR         0x4000
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#define TMD_OWN         0x8000
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#define TST_RTRY        0x0400
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#define TST_LCAR        0x0800
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#define TST_LCOL        0x1000
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#define TST_UFLO        0x4000
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#define TST_BUFF        0x8000
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#define ISALED0         0x0004
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#define ISALED0_LNKST   0x8000
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struct dev_priv {
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    struct net_device_stats stats;
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    unsigned long       rxbuffer[RX_BUFFERS];
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    unsigned long       txbuffer[TX_BUFFERS];
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    unsigned char       txhead;
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    unsigned char       txtail;
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    unsigned char       rxhead;
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    unsigned char       rxtail;
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    unsigned long       rxhdr;
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    unsigned long       txhdr;
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    spinlock_t          chip_lock;
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    struct timer_list   timer;
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};
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#endif

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