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marcus.erl |
/*
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* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
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* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
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* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* There are a lot of defines in here that are unused and/or have cryptic
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* names. Please leave them alone, as they're the closest thing we have
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* to a spec from Attansic at present. *ahem* -- CHS
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*/
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#ifndef _ATL1_HW_H_
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#define _ATL1_HW_H_
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#include <linux/types.h>
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#include <linux/mii.h>
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struct atl1_adapter;
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struct atl1_hw;
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/* function prototypes needed by multiple files */
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s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
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s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
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s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
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s32 atl1_read_mac_addr(struct atl1_hw *hw);
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s32 atl1_init_hw(struct atl1_hw *hw);
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s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
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s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
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u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
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void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
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s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
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void atl1_set_mac_addr(struct atl1_hw *hw);
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s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
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s32 atl1_reset_hw(struct atl1_hw *hw);
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void atl1_check_options(struct atl1_adapter *adapter);
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/* register definitions */
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#define REG_PCIE_CAP_LIST 0x58
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#define REG_VPD_CAP 0x6C
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#define VPD_CAP_ID_MASK 0xff
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#define VPD_CAP_ID_SHIFT 0
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#define VPD_CAP_NEXT_PTR_MASK 0xFF
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#define VPD_CAP_NEXT_PTR_SHIFT 8
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#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
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#define VPD_CAP_VPD_ADDR_SHIFT 16
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#define VPD_CAP_VPD_FLAG 0x80000000
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#define REG_VPD_DATA 0x70
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#define REG_SPI_FLASH_CTRL 0x200
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#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
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#define SPI_FLASH_CTRL_STS_WEN 0x2
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#define SPI_FLASH_CTRL_STS_WPEN 0x80
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#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
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#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
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#define SPI_FLASH_CTRL_INS_MASK 0x7
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#define SPI_FLASH_CTRL_INS_SHIFT 8
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#define SPI_FLASH_CTRL_START 0x800
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#define SPI_FLASH_CTRL_EN_VPD 0x2000
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#define SPI_FLASH_CTRL_LDSTART 0x8000
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#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
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#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
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#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
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#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
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#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
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#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
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#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
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#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
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#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
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#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
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#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
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#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
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#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
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#define REG_SPI_ADDR 0x204
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#define REG_SPI_DATA 0x208
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#define REG_SPI_FLASH_CONFIG 0x20C
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#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
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#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
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#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
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#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
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#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
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#define REG_SPI_FLASH_OP_PROGRAM 0x210
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#define REG_SPI_FLASH_OP_SC_ERASE 0x211
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#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
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#define REG_SPI_FLASH_OP_RDID 0x213
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#define REG_SPI_FLASH_OP_WREN 0x214
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#define REG_SPI_FLASH_OP_RDSR 0x215
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#define REG_SPI_FLASH_OP_WRSR 0x216
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#define REG_SPI_FLASH_OP_READ 0x217
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#define REG_TWSI_CTRL 0x218
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#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
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#define TWSI_CTRL_LD_OFFSET_SHIFT 0
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#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
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#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
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#define TWSI_CTRL_SW_LDSTART 0x800
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#define TWSI_CTRL_HW_LDSTART 0x1000
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#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
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#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
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#define TWSI_CTRL_LD_EXIST 0x400000
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#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
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#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
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#define TWSI_CTRL_FREQ_SEL_100K 0
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#define TWSI_CTRL_FREQ_SEL_200K 1
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#define TWSI_CTRL_FREQ_SEL_300K 2
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#define TWSI_CTRL_FREQ_SEL_400K 3
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#define TWSI_CTRL_SMB_SLV_ADDR
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#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
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#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
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#define REG_PCIE_DEV_MISC_CTRL 0x21C
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#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
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#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
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#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
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#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
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#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
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/* Selene Master Control Register */
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#define REG_MASTER_CTRL 0x1400
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#define MASTER_CTRL_SOFT_RST 0x1
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#define MASTER_CTRL_MTIMER_EN 0x2
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#define MASTER_CTRL_ITIMER_EN 0x4
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#define MASTER_CTRL_MANUAL_INT 0x8
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#define MASTER_CTRL_REV_NUM_SHIFT 16
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#define MASTER_CTRL_REV_NUM_MASK 0xff
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#define MASTER_CTRL_DEV_ID_SHIFT 24
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#define MASTER_CTRL_DEV_ID_MASK 0xff
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/* Timer Initial Value Register */
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#define REG_MANUAL_TIMER_INIT 0x1404
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/* IRQ ModeratorTimer Initial Value Register */
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#define REG_IRQ_MODU_TIMER_INIT 0x1408
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#define REG_GPHY_ENABLE 0x140C
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/* IRQ Anti-Lost Timer Initial Value Register */
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#define REG_CMBDISDMA_TIMER 0x140E
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/* Block IDLE Status Register */
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#define REG_IDLE_STATUS 0x1410
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#define IDLE_STATUS_RXMAC 1
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#define IDLE_STATUS_TXMAC 2
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#define IDLE_STATUS_RXQ 4
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#define IDLE_STATUS_TXQ 8
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#define IDLE_STATUS_DMAR 0x10
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#define IDLE_STATUS_DMAW 0x20
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#define IDLE_STATUS_SMB 0x40
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#define IDLE_STATUS_CMB 0x80
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/* MDIO Control Register */
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#define REG_MDIO_CTRL 0x1414
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#define MDIO_DATA_MASK 0xffff
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#define MDIO_DATA_SHIFT 0
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#define MDIO_REG_ADDR_MASK 0x1f
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#define MDIO_REG_ADDR_SHIFT 16
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#define MDIO_RW 0x200000
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#define MDIO_SUP_PREAMBLE 0x400000
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#define MDIO_START 0x800000
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#define MDIO_CLK_SEL_SHIFT 24
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#define MDIO_CLK_25_4 0
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#define MDIO_CLK_25_6 2
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#define MDIO_CLK_25_8 3
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#define MDIO_CLK_25_10 4
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#define MDIO_CLK_25_14 5
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#define MDIO_CLK_25_20 6
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#define MDIO_CLK_25_28 7
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#define MDIO_BUSY 0x8000000
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#define MDIO_WAIT_TIMES 30
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/* MII PHY Status Register */
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#define REG_PHY_STATUS 0x1418
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/* BIST Control and Status Register0 (for the Packet Memory) */
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#define REG_BIST0_CTRL 0x141c
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#define BIST0_NOW 0x1
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#define BIST0_SRAM_FAIL 0x2
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#define BIST0_FUSE_FLAG 0x4
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#define REG_BIST1_CTRL 0x1420
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#define BIST1_NOW 0x1
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#define BIST1_SRAM_FAIL 0x2
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#define BIST1_FUSE_FLAG 0x4
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/* MAC Control Register */
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#define REG_MAC_CTRL 0x1480
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#define MAC_CTRL_TX_EN 1
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#define MAC_CTRL_RX_EN 2
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#define MAC_CTRL_TX_FLOW 4
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#define MAC_CTRL_RX_FLOW 8
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#define MAC_CTRL_LOOPBACK 0x10
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#define MAC_CTRL_DUPLX 0x20
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#define MAC_CTRL_ADD_CRC 0x40
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#define MAC_CTRL_PAD 0x80
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#define MAC_CTRL_LENCHK 0x100
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#define MAC_CTRL_HUGE_EN 0x200
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#define MAC_CTRL_PRMLEN_SHIFT 10
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#define MAC_CTRL_PRMLEN_MASK 0xf
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#define MAC_CTRL_RMV_VLAN 0x4000
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#define MAC_CTRL_PROMIS_EN 0x8000
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#define MAC_CTRL_TX_PAUSE 0x10000
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#define MAC_CTRL_SCNT 0x20000
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#define MAC_CTRL_SRST_TX 0x40000
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#define MAC_CTRL_TX_SIMURST 0x80000
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#define MAC_CTRL_SPEED_SHIFT 20
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#define MAC_CTRL_SPEED_MASK 0x300000
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#define MAC_CTRL_SPEED_1000 2
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#define MAC_CTRL_SPEED_10_100 1
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#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
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#define MAC_CTRL_TX_HUGE 0x800000
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#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
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#define MAC_CTRL_MC_ALL_EN 0x2000000
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#define MAC_CTRL_BC_EN 0x4000000
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#define MAC_CTRL_DBG 0x8000000
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/* MAC IPG/IFG Control Register */
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#define REG_MAC_IPG_IFG 0x1484
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#define MAC_IPG_IFG_IPGT_SHIFT 0
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#define MAC_IPG_IFG_IPGT_MASK 0x7f
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#define MAC_IPG_IFG_MIFG_SHIFT 8
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#define MAC_IPG_IFG_MIFG_MASK 0xff
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#define MAC_IPG_IFG_IPGR1_SHIFT 16
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#define MAC_IPG_IFG_IPGR1_MASK 0x7f
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#define MAC_IPG_IFG_IPGR2_SHIFT 24
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#define MAC_IPG_IFG_IPGR2_MASK 0x7f
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/* MAC STATION ADDRESS */
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#define REG_MAC_STA_ADDR 0x1488
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/* Hash table for multicast address */
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#define REG_RX_HASH_TABLE 0x1490
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/* MAC Half-Duplex Control Register */
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254 |
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#define REG_MAC_HALF_DUPLX_CTRL 0x1498
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#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
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#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
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#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
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#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
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#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
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260 |
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#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
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261 |
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#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
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262 |
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#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
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#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
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264 |
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#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
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265 |
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#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
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266 |
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#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
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267 |
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268 |
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/* Maximum Frame Length Control Register */
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269 |
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#define REG_MTU 0x149c
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270 |
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271 |
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/* Wake-On-Lan control register */
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272 |
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#define REG_WOL_CTRL 0x14a0
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273 |
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#define WOL_PATTERN_EN 0x00000001
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274 |
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#define WOL_PATTERN_PME_EN 0x00000002
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275 |
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#define WOL_MAGIC_EN 0x00000004
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276 |
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#define WOL_MAGIC_PME_EN 0x00000008
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277 |
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#define WOL_LINK_CHG_EN 0x00000010
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278 |
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#define WOL_LINK_CHG_PME_EN 0x00000020
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279 |
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#define WOL_PATTERN_ST 0x00000100
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280 |
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#define WOL_MAGIC_ST 0x00000200
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281 |
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#define WOL_LINKCHG_ST 0x00000400
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282 |
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#define WOL_CLK_SWITCH_EN 0x00008000
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283 |
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#define WOL_PT0_EN 0x00010000
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284 |
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#define WOL_PT1_EN 0x00020000
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285 |
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#define WOL_PT2_EN 0x00040000
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286 |
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#define WOL_PT3_EN 0x00080000
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287 |
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#define WOL_PT4_EN 0x00100000
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288 |
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#define WOL_PT5_EN 0x00200000
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289 |
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#define WOL_PT6_EN 0x00400000
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290 |
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291 |
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/* WOL Length ( 2 DWORD ) */
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292 |
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#define REG_WOL_PATTERN_LEN 0x14a4
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293 |
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#define WOL_PT_LEN_MASK 0x7f
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294 |
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#define WOL_PT0_LEN_SHIFT 0
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295 |
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#define WOL_PT1_LEN_SHIFT 8
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296 |
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#define WOL_PT2_LEN_SHIFT 16
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297 |
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#define WOL_PT3_LEN_SHIFT 24
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298 |
|
|
#define WOL_PT4_LEN_SHIFT 0
|
299 |
|
|
#define WOL_PT5_LEN_SHIFT 8
|
300 |
|
|
#define WOL_PT6_LEN_SHIFT 16
|
301 |
|
|
|
302 |
|
|
/* Internal SRAM Partition Register */
|
303 |
|
|
#define REG_SRAM_RFD_ADDR 0x1500
|
304 |
|
|
#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
|
305 |
|
|
#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
|
306 |
|
|
#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
|
307 |
|
|
#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
|
308 |
|
|
#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
|
309 |
|
|
#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
|
310 |
|
|
#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
|
311 |
|
|
#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
|
312 |
|
|
#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
|
313 |
|
|
#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
|
314 |
|
|
#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
|
315 |
|
|
#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
|
316 |
|
|
#define SRAM_TCPH_ADDR_MASK 0x0fff
|
317 |
|
|
#define SRAM_TCPH_ADDR_SHIFT 0
|
318 |
|
|
#define SRAM_PATH_ADDR_MASK 0x0fff
|
319 |
|
|
#define SRAM_PATH_ADDR_SHIFT 16
|
320 |
|
|
|
321 |
|
|
/* Load Ptr Register */
|
322 |
|
|
#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
|
323 |
|
|
|
324 |
|
|
/* Descriptor Control register */
|
325 |
|
|
#define REG_DESC_BASE_ADDR_HI 0x1540
|
326 |
|
|
#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
|
327 |
|
|
#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
|
328 |
|
|
#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
|
329 |
|
|
#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
|
330 |
|
|
#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
|
331 |
|
|
#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
|
332 |
|
|
#define DESC_RFD_RING_SIZE_MASK 0x7ff
|
333 |
|
|
#define DESC_RFD_RING_SIZE_SHIFT 0
|
334 |
|
|
#define DESC_RRD_RING_SIZE_MASK 0x7ff
|
335 |
|
|
#define DESC_RRD_RING_SIZE_SHIFT 16
|
336 |
|
|
#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
|
337 |
|
|
#define DESC_TPD_RING_SIZE_MASK 0x3ff
|
338 |
|
|
#define DESC_TPD_RING_SIZE_SHIFT 0
|
339 |
|
|
|
340 |
|
|
/* TXQ Control Register */
|
341 |
|
|
#define REG_TXQ_CTRL 0x1580
|
342 |
|
|
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
|
343 |
|
|
#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
|
344 |
|
|
#define TXQ_CTRL_EN 0x20
|
345 |
|
|
#define TXQ_CTRL_ENH_MODE 0x40
|
346 |
|
|
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
|
347 |
|
|
#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
|
348 |
|
|
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
|
349 |
|
|
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
|
350 |
|
|
|
351 |
|
|
/* Jumbo packet Threshold for task offload */
|
352 |
|
|
#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
|
353 |
|
|
#define TX_JUMBO_TASK_TH_MASK 0x7ff
|
354 |
|
|
#define TX_JUMBO_TASK_TH_SHIFT 0
|
355 |
|
|
#define TX_TPD_MIN_IPG_MASK 0x1f
|
356 |
|
|
#define TX_TPD_MIN_IPG_SHIFT 16
|
357 |
|
|
|
358 |
|
|
/* RXQ Control Register */
|
359 |
|
|
#define REG_RXQ_CTRL 0x15a0
|
360 |
|
|
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
|
361 |
|
|
#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
|
362 |
|
|
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
|
363 |
|
|
#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
|
364 |
|
|
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
|
365 |
|
|
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
|
366 |
|
|
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
|
367 |
|
|
#define RXQ_CTRL_EN 0x80000000
|
368 |
|
|
|
369 |
|
|
/* Rx jumbo packet threshold and rrd retirement timer */
|
370 |
|
|
#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
|
371 |
|
|
#define RXQ_JMBOSZ_TH_MASK 0x7ff
|
372 |
|
|
#define RXQ_JMBOSZ_TH_SHIFT 0
|
373 |
|
|
#define RXQ_JMBO_LKAH_MASK 0xf
|
374 |
|
|
#define RXQ_JMBO_LKAH_SHIFT 11
|
375 |
|
|
#define RXQ_RRD_TIMER_MASK 0xffff
|
376 |
|
|
#define RXQ_RRD_TIMER_SHIFT 16
|
377 |
|
|
|
378 |
|
|
/* RFD flow control register */
|
379 |
|
|
#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
|
380 |
|
|
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
|
381 |
|
|
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
|
382 |
|
|
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
|
383 |
|
|
#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
|
384 |
|
|
|
385 |
|
|
/* RRD flow control register */
|
386 |
|
|
#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
|
387 |
|
|
#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
|
388 |
|
|
#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
|
389 |
|
|
#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
|
390 |
|
|
#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
|
391 |
|
|
|
392 |
|
|
/* DMA Engine Control Register */
|
393 |
|
|
#define REG_DMA_CTRL 0x15c0
|
394 |
|
|
#define DMA_CTRL_DMAR_IN_ORDER 0x1
|
395 |
|
|
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
|
396 |
|
|
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
|
397 |
|
|
#define DMA_CTRL_RCB_VALUE 0x8
|
398 |
|
|
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
|
399 |
|
|
#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
|
400 |
|
|
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
|
401 |
|
|
#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
|
402 |
|
|
#define DMA_CTRL_DMAR_EN 0x400
|
403 |
|
|
#define DMA_CTRL_DMAW_EN 0x800
|
404 |
|
|
|
405 |
|
|
/* CMB/SMB Control Register */
|
406 |
|
|
#define REG_CSMB_CTRL 0x15d0
|
407 |
|
|
#define CSMB_CTRL_CMB_NOW 1
|
408 |
|
|
#define CSMB_CTRL_SMB_NOW 2
|
409 |
|
|
#define CSMB_CTRL_CMB_EN 4
|
410 |
|
|
#define CSMB_CTRL_SMB_EN 8
|
411 |
|
|
|
412 |
|
|
/* CMB DMA Write Threshold Register */
|
413 |
|
|
#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
|
414 |
|
|
#define CMB_RRD_TH_SHIFT 0
|
415 |
|
|
#define CMB_RRD_TH_MASK 0x7ff
|
416 |
|
|
#define CMB_TPD_TH_SHIFT 16
|
417 |
|
|
#define CMB_TPD_TH_MASK 0x7ff
|
418 |
|
|
|
419 |
|
|
/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
|
420 |
|
|
#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
|
421 |
|
|
#define CMB_RX_TM_SHIFT 0
|
422 |
|
|
#define CMB_RX_TM_MASK 0xffff
|
423 |
|
|
#define CMB_TX_TM_SHIFT 16
|
424 |
|
|
#define CMB_TX_TM_MASK 0xffff
|
425 |
|
|
|
426 |
|
|
/* Number of packet received since last CMB write */
|
427 |
|
|
#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
|
428 |
|
|
|
429 |
|
|
/* Number of packet transmitted since last CMB write */
|
430 |
|
|
#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
|
431 |
|
|
|
432 |
|
|
/* SMB auto DMA timer register */
|
433 |
|
|
#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
|
434 |
|
|
|
435 |
|
|
/* Mailbox Register */
|
436 |
|
|
#define REG_MAILBOX 0x15f0
|
437 |
|
|
#define MB_RFD_PROD_INDX_SHIFT 0
|
438 |
|
|
#define MB_RFD_PROD_INDX_MASK 0x7ff
|
439 |
|
|
#define MB_RRD_CONS_INDX_SHIFT 11
|
440 |
|
|
#define MB_RRD_CONS_INDX_MASK 0x7ff
|
441 |
|
|
#define MB_TPD_PROD_INDX_SHIFT 22
|
442 |
|
|
#define MB_TPD_PROD_INDX_MASK 0x3ff
|
443 |
|
|
|
444 |
|
|
/* Interrupt Status Register */
|
445 |
|
|
#define REG_ISR 0x1600
|
446 |
|
|
#define ISR_SMB 1
|
447 |
|
|
#define ISR_TIMER 2
|
448 |
|
|
#define ISR_MANUAL 4
|
449 |
|
|
#define ISR_RXF_OV 8
|
450 |
|
|
#define ISR_RFD_UNRUN 0x10
|
451 |
|
|
#define ISR_RRD_OV 0x20
|
452 |
|
|
#define ISR_TXF_UNRUN 0x40
|
453 |
|
|
#define ISR_LINK 0x80
|
454 |
|
|
#define ISR_HOST_RFD_UNRUN 0x100
|
455 |
|
|
#define ISR_HOST_RRD_OV 0x200
|
456 |
|
|
#define ISR_DMAR_TO_RST 0x400
|
457 |
|
|
#define ISR_DMAW_TO_RST 0x800
|
458 |
|
|
#define ISR_GPHY 0x1000
|
459 |
|
|
#define ISR_RX_PKT 0x10000
|
460 |
|
|
#define ISR_TX_PKT 0x20000
|
461 |
|
|
#define ISR_TX_DMA 0x40000
|
462 |
|
|
#define ISR_RX_DMA 0x80000
|
463 |
|
|
#define ISR_CMB_RX 0x100000
|
464 |
|
|
#define ISR_CMB_TX 0x200000
|
465 |
|
|
#define ISR_MAC_RX 0x400000
|
466 |
|
|
#define ISR_MAC_TX 0x800000
|
467 |
|
|
#define ISR_UR_DETECTED 0x1000000
|
468 |
|
|
#define ISR_FERR_DETECTED 0x2000000
|
469 |
|
|
#define ISR_NFERR_DETECTED 0x4000000
|
470 |
|
|
#define ISR_CERR_DETECTED 0x8000000
|
471 |
|
|
#define ISR_PHY_LINKDOWN 0x10000000
|
472 |
|
|
#define ISR_DIS_SMB 0x20000000
|
473 |
|
|
#define ISR_DIS_DMA 0x40000000
|
474 |
|
|
#define ISR_DIS_INT 0x80000000
|
475 |
|
|
|
476 |
|
|
/* Interrupt Mask Register */
|
477 |
|
|
#define REG_IMR 0x1604
|
478 |
|
|
|
479 |
|
|
/* Normal Interrupt mask */
|
480 |
|
|
#define IMR_NORMAL_MASK (\
|
481 |
|
|
ISR_SMB |\
|
482 |
|
|
ISR_GPHY |\
|
483 |
|
|
ISR_PHY_LINKDOWN|\
|
484 |
|
|
ISR_DMAR_TO_RST |\
|
485 |
|
|
ISR_DMAW_TO_RST |\
|
486 |
|
|
ISR_CMB_TX |\
|
487 |
|
|
ISR_CMB_RX )
|
488 |
|
|
|
489 |
|
|
/* Debug Interrupt Mask (enable all interrupt) */
|
490 |
|
|
#define IMR_DEBUG_MASK (\
|
491 |
|
|
ISR_SMB |\
|
492 |
|
|
ISR_TIMER |\
|
493 |
|
|
ISR_MANUAL |\
|
494 |
|
|
ISR_RXF_OV |\
|
495 |
|
|
ISR_RFD_UNRUN |\
|
496 |
|
|
ISR_RRD_OV |\
|
497 |
|
|
ISR_TXF_UNRUN |\
|
498 |
|
|
ISR_LINK |\
|
499 |
|
|
ISR_CMB_TX |\
|
500 |
|
|
ISR_CMB_RX |\
|
501 |
|
|
ISR_RX_PKT |\
|
502 |
|
|
ISR_TX_PKT |\
|
503 |
|
|
ISR_MAC_RX |\
|
504 |
|
|
ISR_MAC_TX )
|
505 |
|
|
|
506 |
|
|
/* Interrupt Status Register */
|
507 |
|
|
#define REG_RFD_RRD_IDX 0x1800
|
508 |
|
|
#define REG_TPD_IDX 0x1804
|
509 |
|
|
|
510 |
|
|
/* MII definition */
|
511 |
|
|
/* PHY Common Register */
|
512 |
|
|
#define MII_AT001_CR 0x09
|
513 |
|
|
#define MII_AT001_SR 0x0A
|
514 |
|
|
#define MII_AT001_ESR 0x0F
|
515 |
|
|
#define MII_AT001_PSCR 0x10
|
516 |
|
|
#define MII_AT001_PSSR 0x11
|
517 |
|
|
|
518 |
|
|
/* PHY Control Register */
|
519 |
|
|
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
520 |
|
|
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
|
521 |
|
|
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
522 |
|
|
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
523 |
|
|
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
|
524 |
|
|
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
525 |
|
|
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
526 |
|
|
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
527 |
|
|
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
528 |
|
|
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
529 |
|
|
#define MII_CR_SPEED_MASK 0x2040
|
530 |
|
|
#define MII_CR_SPEED_1000 0x0040
|
531 |
|
|
#define MII_CR_SPEED_100 0x2000
|
532 |
|
|
#define MII_CR_SPEED_10 0x0000
|
533 |
|
|
|
534 |
|
|
/* PHY Status Register */
|
535 |
|
|
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
|
536 |
|
|
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
|
537 |
|
|
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
538 |
|
|
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
|
539 |
|
|
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
|
540 |
|
|
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
541 |
|
|
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
|
542 |
|
|
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
|
543 |
|
|
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
|
544 |
|
|
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
|
545 |
|
|
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
|
546 |
|
|
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
|
547 |
|
|
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
|
548 |
|
|
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
|
549 |
|
|
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
|
550 |
|
|
|
551 |
|
|
/* Link partner ability register. */
|
552 |
|
|
#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
|
553 |
|
|
#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
554 |
|
|
#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
555 |
|
|
#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
556 |
|
|
#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
557 |
|
|
#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
|
558 |
|
|
#define MII_LPA_PAUSE 0x0400 /* PAUSE */
|
559 |
|
|
#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
|
560 |
|
|
#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
|
561 |
|
|
#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
|
562 |
|
|
#define MII_LPA_NPAGE 0x8000 /* Next page bit */
|
563 |
|
|
|
564 |
|
|
/* Autoneg Advertisement Register */
|
565 |
|
|
#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
|
566 |
|
|
#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
567 |
|
|
#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
568 |
|
|
#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
569 |
|
|
#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
570 |
|
|
#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
|
571 |
|
|
#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
|
572 |
|
|
#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
|
573 |
|
|
#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
|
574 |
|
|
#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
|
575 |
|
|
#define MII_AR_SPEED_MASK 0x01E0
|
576 |
|
|
#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
|
577 |
|
|
|
578 |
|
|
/* 1000BASE-T Control Register */
|
579 |
|
|
#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
|
580 |
|
|
#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
|
581 |
|
|
#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
|
582 |
|
|
#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
|
583 |
|
|
#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
|
584 |
|
|
#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
|
585 |
|
|
#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
|
586 |
|
|
#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
|
587 |
|
|
#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
|
588 |
|
|
#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
|
589 |
|
|
#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
|
590 |
|
|
#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
|
591 |
|
|
|
592 |
|
|
/* 1000BASE-T Status Register */
|
593 |
|
|
#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
|
594 |
|
|
#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
|
595 |
|
|
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
596 |
|
|
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
597 |
|
|
#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
|
598 |
|
|
#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
|
599 |
|
|
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
|
600 |
|
|
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
|
601 |
|
|
|
602 |
|
|
/* Extended Status Register */
|
603 |
|
|
#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
|
604 |
|
|
#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
|
605 |
|
|
#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
|
606 |
|
|
#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
|
607 |
|
|
|
608 |
|
|
/* AT001 PHY Specific Control Register */
|
609 |
|
|
#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
|
610 |
|
|
#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|
611 |
|
|
#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
|
612 |
|
|
#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
|
613 |
|
|
#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
|
614 |
|
|
#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
|
615 |
|
|
#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
616 |
|
|
#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
|
617 |
|
|
#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
|
618 |
|
|
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
|
619 |
|
|
#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
|
620 |
|
|
#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
|
621 |
|
|
#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
|
622 |
|
|
#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
623 |
|
|
#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
|
624 |
|
|
#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
|
625 |
|
|
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
|
626 |
|
|
|
627 |
|
|
/* AT001 PHY Specific Status Register */
|
628 |
|
|
#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
|
629 |
|
|
#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
|
630 |
|
|
#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
631 |
|
|
#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
|
632 |
|
|
#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
|
633 |
|
|
#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
634 |
|
|
|
635 |
|
|
/* PCI Command Register Bit Definitions */
|
636 |
|
|
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
|
637 |
|
|
#define CMD_IO_SPACE 0x0001
|
638 |
|
|
#define CMD_MEMORY_SPACE 0x0002
|
639 |
|
|
#define CMD_BUS_MASTER 0x0004
|
640 |
|
|
|
641 |
|
|
/* Wake Up Filter Control */
|
642 |
|
|
#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
643 |
|
|
#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
644 |
|
|
#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
645 |
|
|
#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
|
646 |
|
|
#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
647 |
|
|
|
648 |
|
|
/* Error Codes */
|
649 |
|
|
#define ATL1_SUCCESS 0
|
650 |
|
|
#define ATL1_ERR_EEPROM 1
|
651 |
|
|
#define ATL1_ERR_PHY 2
|
652 |
|
|
#define ATL1_ERR_CONFIG 3
|
653 |
|
|
#define ATL1_ERR_PARAM 4
|
654 |
|
|
#define ATL1_ERR_MAC_TYPE 5
|
655 |
|
|
#define ATL1_ERR_PHY_TYPE 6
|
656 |
|
|
#define ATL1_ERR_PHY_SPEED 7
|
657 |
|
|
#define ATL1_ERR_PHY_RES 8
|
658 |
|
|
|
659 |
|
|
#define SPEED_0 0xffff
|
660 |
|
|
#define SPEED_10 10
|
661 |
|
|
#define SPEED_100 100
|
662 |
|
|
#define SPEED_1000 1000
|
663 |
|
|
#define HALF_DUPLEX 1
|
664 |
|
|
#define FULL_DUPLEX 2
|
665 |
|
|
|
666 |
|
|
#define MEDIA_TYPE_AUTO_SENSOR 0
|
667 |
|
|
#define MEDIA_TYPE_1000M_FULL 1
|
668 |
|
|
#define MEDIA_TYPE_100M_FULL 2
|
669 |
|
|
#define MEDIA_TYPE_100M_HALF 3
|
670 |
|
|
#define MEDIA_TYPE_10M_FULL 4
|
671 |
|
|
#define MEDIA_TYPE_10M_HALF 5
|
672 |
|
|
|
673 |
|
|
#define ADVERTISE_10_HALF 0x0001
|
674 |
|
|
#define ADVERTISE_10_FULL 0x0002
|
675 |
|
|
#define ADVERTISE_100_HALF 0x0004
|
676 |
|
|
#define ADVERTISE_100_FULL 0x0008
|
677 |
|
|
#define ADVERTISE_1000_HALF 0x0010
|
678 |
|
|
#define ADVERTISE_1000_FULL 0x0020
|
679 |
|
|
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
|
680 |
|
|
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
|
681 |
|
|
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
|
682 |
|
|
|
683 |
|
|
#define MAX_JUMBO_FRAME_SIZE 0x2800
|
684 |
|
|
|
685 |
|
|
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
686 |
|
|
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
|
687 |
|
|
|
688 |
|
|
/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
|
689 |
|
|
#define EEPROM_SUM 0xBABA
|
690 |
|
|
|
691 |
|
|
#define ATL1_EEDUMP_LEN 48
|
692 |
|
|
|
693 |
|
|
/* Statistics counters collected by the MAC */
|
694 |
|
|
struct stats_msg_block {
|
695 |
|
|
/* rx */
|
696 |
|
|
u32 rx_ok; /* The number of good packet received. */
|
697 |
|
|
u32 rx_bcast; /* The number of good broadcast packet received. */
|
698 |
|
|
u32 rx_mcast; /* The number of good multicast packet received. */
|
699 |
|
|
u32 rx_pause; /* The number of Pause packet received. */
|
700 |
|
|
u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
|
701 |
|
|
u32 rx_fcs_err; /* The number of packets with bad FCS. */
|
702 |
|
|
u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
|
703 |
|
|
u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
|
704 |
|
|
u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
|
705 |
|
|
u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
|
706 |
|
|
u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
|
707 |
|
|
u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
|
708 |
|
|
u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
|
709 |
|
|
u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
|
710 |
|
|
u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
|
711 |
|
|
u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
|
712 |
|
|
u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
|
713 |
|
|
u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
|
714 |
|
|
u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
|
715 |
|
|
u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
|
716 |
|
|
u32 rx_align_err; /* Alignment Error */
|
717 |
|
|
u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
|
718 |
|
|
u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
|
719 |
|
|
u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
|
720 |
|
|
|
721 |
|
|
/* tx */
|
722 |
|
|
u32 tx_ok; /* The number of good packet transmitted. */
|
723 |
|
|
u32 tx_bcast; /* The number of good broadcast packet transmitted. */
|
724 |
|
|
u32 tx_mcast; /* The number of good multicast packet transmitted. */
|
725 |
|
|
u32 tx_pause; /* The number of Pause packet transmitted. */
|
726 |
|
|
u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
|
727 |
|
|
u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
|
728 |
|
|
u32 tx_defer; /* The number of packets transmitted that is deferred. */
|
729 |
|
|
u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
|
730 |
|
|
u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
|
731 |
|
|
u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
|
732 |
|
|
u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
|
733 |
|
|
u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
|
734 |
|
|
u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
|
735 |
|
|
u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
|
736 |
|
|
u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
|
737 |
|
|
u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
|
738 |
|
|
u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
|
739 |
|
|
u32 tx_late_col; /* The number of packets transmitted with late collisions. */
|
740 |
|
|
u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
|
741 |
|
|
u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
|
742 |
|
|
u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
|
743 |
|
|
u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
|
744 |
|
|
u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
|
745 |
|
|
u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
|
746 |
|
|
u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
|
747 |
|
|
u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
|
748 |
|
|
* Software should clear this bit as soon as retrieving the statistics information. */
|
749 |
|
|
};
|
750 |
|
|
|
751 |
|
|
/* Coalescing Message Block */
|
752 |
|
|
struct coals_msg_block {
|
753 |
|
|
u32 int_stats; /* interrupt status */
|
754 |
|
|
u16 rrd_prod_idx; /* TRD Producer Index. */
|
755 |
|
|
u16 rfd_cons_idx; /* RFD Consumer Index. */
|
756 |
|
|
u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
|
757 |
|
|
* Software supposes to clear this bit when CMB information is processed. */
|
758 |
|
|
u16 tpd_cons_idx; /* TPD Consumer Index. */
|
759 |
|
|
};
|
760 |
|
|
|
761 |
|
|
/* RRD descriptor */
|
762 |
|
|
struct rx_return_desc {
|
763 |
|
|
u8 num_buf; /* Number of RFD buffers used by the received packet */
|
764 |
|
|
u8 resved;
|
765 |
|
|
u16 buf_indx; /* RFD Index of the first buffer */
|
766 |
|
|
union {
|
767 |
|
|
u32 valid;
|
768 |
|
|
struct {
|
769 |
|
|
u16 rx_chksum;
|
770 |
|
|
u16 pkt_size;
|
771 |
|
|
} xsum_sz;
|
772 |
|
|
} xsz;
|
773 |
|
|
|
774 |
|
|
u16 pkt_flg; /* Packet flags */
|
775 |
|
|
u16 err_flg; /* Error flags */
|
776 |
|
|
u16 resved2;
|
777 |
|
|
u16 vlan_tag; /* VLAN TAG */
|
778 |
|
|
};
|
779 |
|
|
|
780 |
|
|
#define PACKET_FLAG_ETH_TYPE 0x0080
|
781 |
|
|
#define PACKET_FLAG_VLAN_INS 0x0100
|
782 |
|
|
#define PACKET_FLAG_ERR 0x0200
|
783 |
|
|
#define PACKET_FLAG_IPV4 0x0400
|
784 |
|
|
#define PACKET_FLAG_UDP 0x0800
|
785 |
|
|
#define PACKET_FLAG_TCP 0x1000
|
786 |
|
|
#define PACKET_FLAG_BCAST 0x2000
|
787 |
|
|
#define PACKET_FLAG_MCAST 0x4000
|
788 |
|
|
#define PACKET_FLAG_PAUSE 0x8000
|
789 |
|
|
|
790 |
|
|
#define ERR_FLAG_CRC 0x0001
|
791 |
|
|
#define ERR_FLAG_CODE 0x0002
|
792 |
|
|
#define ERR_FLAG_DRIBBLE 0x0004
|
793 |
|
|
#define ERR_FLAG_RUNT 0x0008
|
794 |
|
|
#define ERR_FLAG_OV 0x0010
|
795 |
|
|
#define ERR_FLAG_TRUNC 0x0020
|
796 |
|
|
#define ERR_FLAG_IP_CHKSUM 0x0040
|
797 |
|
|
#define ERR_FLAG_L4_CHKSUM 0x0080
|
798 |
|
|
#define ERR_FLAG_LEN 0x0100
|
799 |
|
|
#define ERR_FLAG_DES_ADDR 0x0200
|
800 |
|
|
|
801 |
|
|
/* RFD descriptor */
|
802 |
|
|
struct rx_free_desc {
|
803 |
|
|
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
804 |
|
|
__le16 buf_len; /* Size of the receive buffer in host memory, in byte */
|
805 |
|
|
u16 coalese; /* Update consumer index to host after the reception of this frame */
|
806 |
|
|
/* __attribute__ ((packed)) is required */
|
807 |
|
|
} __attribute__ ((packed));
|
808 |
|
|
|
809 |
|
|
/* tsopu defines */
|
810 |
|
|
#define TSO_PARAM_BUFLEN_MASK 0x3FFF
|
811 |
|
|
#define TSO_PARAM_BUFLEN_SHIFT 0
|
812 |
|
|
#define TSO_PARAM_DMAINT_MASK 0x0001
|
813 |
|
|
#define TSO_PARAM_DMAINT_SHIFT 14
|
814 |
|
|
#define TSO_PARAM_PKTNT_MASK 0x0001
|
815 |
|
|
#define TSO_PARAM_PKTINT_SHIFT 15
|
816 |
|
|
#define TSO_PARAM_VLANTAG_MASK 0xFFFF
|
817 |
|
|
#define TSO_PARAM_VLAN_SHIFT 16
|
818 |
|
|
|
819 |
|
|
/* tsopl defines */
|
820 |
|
|
#define TSO_PARAM_EOP_MASK 0x0001
|
821 |
|
|
#define TSO_PARAM_EOP_SHIFT 0
|
822 |
|
|
#define TSO_PARAM_COALESCE_MASK 0x0001
|
823 |
|
|
#define TSO_PARAM_COALESCE_SHIFT 1
|
824 |
|
|
#define TSO_PARAM_INSVLAG_MASK 0x0001
|
825 |
|
|
#define TSO_PARAM_INSVLAG_SHIFT 2
|
826 |
|
|
#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
|
827 |
|
|
#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
|
828 |
|
|
#define TSO_PARAM_SEGMENT_MASK 0x0001
|
829 |
|
|
#define TSO_PARAM_SEGMENT_SHIFT 4
|
830 |
|
|
#define TSO_PARAM_IPCKSUM_MASK 0x0001
|
831 |
|
|
#define TSO_PARAM_IPCKSUM_SHIFT 5
|
832 |
|
|
#define TSO_PARAM_TCPCKSUM_MASK 0x0001
|
833 |
|
|
#define TSO_PARAM_TCPCKSUM_SHIFT 6
|
834 |
|
|
#define TSO_PARAM_UDPCKSUM_MASK 0x0001
|
835 |
|
|
#define TSO_PARAM_UDPCKSUM_SHIFT 7
|
836 |
|
|
#define TSO_PARAM_VLANTAGGED_MASK 0x0001
|
837 |
|
|
#define TSO_PARAM_VLANTAGGED_SHIFT 8
|
838 |
|
|
#define TSO_PARAM_ETHTYPE_MASK 0x0001
|
839 |
|
|
#define TSO_PARAM_ETHTYPE_SHIFT 9
|
840 |
|
|
#define TSO_PARAM_IPHL_MASK 0x000F
|
841 |
|
|
#define TSO_PARAM_IPHL_SHIFT 10
|
842 |
|
|
#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
|
843 |
|
|
#define TSO_PARAM_TCPHDRLEN_SHIFT 14
|
844 |
|
|
#define TSO_PARAM_HDRFLAG_MASK 0x0001
|
845 |
|
|
#define TSO_PARAM_HDRFLAG_SHIFT 18
|
846 |
|
|
#define TSO_PARAM_MSS_MASK 0x1FFF
|
847 |
|
|
#define TSO_PARAM_MSS_SHIFT 19
|
848 |
|
|
|
849 |
|
|
/* csumpu defines */
|
850 |
|
|
#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
|
851 |
|
|
#define CSUM_PARAM_BUFLEN_SHIFT 0
|
852 |
|
|
#define CSUM_PARAM_DMAINT_MASK 0x0001
|
853 |
|
|
#define CSUM_PARAM_DMAINT_SHIFT 14
|
854 |
|
|
#define CSUM_PARAM_PKTINT_MASK 0x0001
|
855 |
|
|
#define CSUM_PARAM_PKTINT_SHIFT 15
|
856 |
|
|
#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
|
857 |
|
|
#define CSUM_PARAM_VALAN_SHIFT 16
|
858 |
|
|
|
859 |
|
|
/* csumpl defines*/
|
860 |
|
|
#define CSUM_PARAM_EOP_MASK 0x0001
|
861 |
|
|
#define CSUM_PARAM_EOP_SHIFT 0
|
862 |
|
|
#define CSUM_PARAM_COALESCE_MASK 0x0001
|
863 |
|
|
#define CSUM_PARAM_COALESCE_SHIFT 1
|
864 |
|
|
#define CSUM_PARAM_INSVLAG_MASK 0x0001
|
865 |
|
|
#define CSUM_PARAM_INSVLAG_SHIFT 2
|
866 |
|
|
#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
|
867 |
|
|
#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
|
868 |
|
|
#define CSUM_PARAM_SEGMENT_MASK 0x0001
|
869 |
|
|
#define CSUM_PARAM_SEGMENT_SHIFT 4
|
870 |
|
|
#define CSUM_PARAM_IPCKSUM_MASK 0x0001
|
871 |
|
|
#define CSUM_PARAM_IPCKSUM_SHIFT 5
|
872 |
|
|
#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
|
873 |
|
|
#define CSUM_PARAM_TCPCKSUM_SHIFT 6
|
874 |
|
|
#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
|
875 |
|
|
#define CSUM_PARAM_UDPCKSUM_SHIFT 7
|
876 |
|
|
#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
|
877 |
|
|
#define CSUM_PARAM_VLANTAGGED_SHIFT 8
|
878 |
|
|
#define CSUM_PARAM_ETHTYPE_MASK 0x0001
|
879 |
|
|
#define CSUM_PARAM_ETHTYPE_SHIFT 9
|
880 |
|
|
#define CSUM_PARAM_IPHL_MASK 0x000F
|
881 |
|
|
#define CSUM_PARAM_IPHL_SHIFT 10
|
882 |
|
|
#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
|
883 |
|
|
#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
|
884 |
|
|
#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
|
885 |
|
|
#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
|
886 |
|
|
|
887 |
|
|
/* TPD descriptor */
|
888 |
|
|
struct tso_param {
|
889 |
|
|
/* The order of these declarations is important -- don't change it */
|
890 |
|
|
u32 tsopu; /* tso_param upper word */
|
891 |
|
|
u32 tsopl; /* tso_param lower word */
|
892 |
|
|
};
|
893 |
|
|
|
894 |
|
|
struct csum_param {
|
895 |
|
|
/* The order of these declarations is important -- don't change it */
|
896 |
|
|
u32 csumpu; /* csum_param upper word */
|
897 |
|
|
u32 csumpl; /* csum_param lower word */
|
898 |
|
|
};
|
899 |
|
|
|
900 |
|
|
union tpd_descr {
|
901 |
|
|
u64 data;
|
902 |
|
|
struct csum_param csum;
|
903 |
|
|
struct tso_param tso;
|
904 |
|
|
};
|
905 |
|
|
|
906 |
|
|
struct tx_packet_desc {
|
907 |
|
|
__le64 buffer_addr;
|
908 |
|
|
union tpd_descr desc;
|
909 |
|
|
};
|
910 |
|
|
|
911 |
|
|
/* DMA Order Settings */
|
912 |
|
|
enum atl1_dma_order {
|
913 |
|
|
atl1_dma_ord_in = 1,
|
914 |
|
|
atl1_dma_ord_enh = 2,
|
915 |
|
|
atl1_dma_ord_out = 4
|
916 |
|
|
};
|
917 |
|
|
|
918 |
|
|
enum atl1_dma_rcb {
|
919 |
|
|
atl1_rcb_64 = 0,
|
920 |
|
|
atl1_rcb_128 = 1
|
921 |
|
|
};
|
922 |
|
|
|
923 |
|
|
enum atl1_dma_req_block {
|
924 |
|
|
atl1_dma_req_128 = 0,
|
925 |
|
|
atl1_dma_req_256 = 1,
|
926 |
|
|
atl1_dma_req_512 = 2,
|
927 |
|
|
atl1_dma_req_1024 = 3,
|
928 |
|
|
atl1_dma_req_2048 = 4,
|
929 |
|
|
atl1_dma_req_4096 = 5
|
930 |
|
|
};
|
931 |
|
|
|
932 |
|
|
struct atl1_spi_flash_dev {
|
933 |
|
|
const char *manu_name; /* manufacturer id */
|
934 |
|
|
/* op-code */
|
935 |
|
|
u8 cmd_wrsr;
|
936 |
|
|
u8 cmd_read;
|
937 |
|
|
u8 cmd_program;
|
938 |
|
|
u8 cmd_wren;
|
939 |
|
|
u8 cmd_wrdi;
|
940 |
|
|
u8 cmd_rdsr;
|
941 |
|
|
u8 cmd_rdid;
|
942 |
|
|
u8 cmd_sector_erase;
|
943 |
|
|
u8 cmd_chip_erase;
|
944 |
|
|
};
|
945 |
|
|
|
946 |
|
|
#endif /* _ATL1_HW_H_ */
|