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marcus.erl |
/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
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/*
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Copyright (c) 2001, 2002 by D-Link Corporation
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Written by Edward Peng.<edward_peng@dlink.com.tw>
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Created 03-May-2001, base on Linux' sundance.c.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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*/
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#ifndef __DL2K_H__
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#define __DL2K_H__
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/init.h>
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#include <linux/crc32.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/processor.h> /* Processor type for cache alignment. */
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#define TX_RING_SIZE 256
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#define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
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#define RX_RING_SIZE 256
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#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
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#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
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/* This driver was written to use PCI memory space, however x86-oriented
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hardware often uses I/O space accesses. */
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#ifndef MEM_MAPPING
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#undef readb
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#undef readw
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#undef readl
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#undef writeb
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#undef writew
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#undef writel
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#define readb inb
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#define readw inw
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#define readl inl
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#define writeb outb
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#define writew outw
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#define writel outl
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#endif
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/* Offsets to the device registers.
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Unlike software-only systems, device drivers interact with complex hardware.
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It's not useful to define symbolic names for every register bit in the
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device. The name can only partially document the semantics and make
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the driver longer and more difficult to read.
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In general, only the important configuration values or bits changed
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multiple times should be defined symbolically.
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*/
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enum dl2x_offsets {
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/* I/O register offsets */
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DMACtrl = 0x00,
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RxDMAStatus = 0x08,
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TFDListPtr0 = 0x10,
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TFDListPtr1 = 0x14,
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TxDMABurstThresh = 0x18,
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TxDMAUrgentThresh = 0x19,
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TxDMAPollPeriod = 0x1a,
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RFDListPtr0 = 0x1c,
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RFDListPtr1 = 0x20,
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RxDMABurstThresh = 0x24,
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RxDMAUrgentThresh = 0x25,
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RxDMAPollPeriod = 0x26,
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RxDMAIntCtrl = 0x28,
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DebugCtrl = 0x2c,
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ASICCtrl = 0x30,
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FifoCtrl = 0x38,
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RxEarlyThresh = 0x3a,
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FlowOffThresh = 0x3c,
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FlowOnThresh = 0x3e,
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TxStartThresh = 0x44,
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EepromData = 0x48,
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EepromCtrl = 0x4a,
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ExpromAddr = 0x4c,
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Exprodata = 0x50,
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WakeEvent = 0x51,
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CountDown = 0x54,
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IntStatusAck = 0x5a,
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IntEnable = 0x5c,
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IntStatus = 0x5e,
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TxStatus = 0x60,
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MACCtrl = 0x6c,
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VLANTag = 0x70,
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PhyCtrl = 0x76,
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StationAddr0 = 0x78,
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StationAddr1 = 0x7a,
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StationAddr2 = 0x7c,
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VLANId = 0x80,
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MaxFrameSize = 0x86,
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ReceiveMode = 0x88,
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HashTable0 = 0x8c,
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HashTable1 = 0x90,
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RmonStatMask = 0x98,
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StatMask = 0x9c,
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RxJumboFrames = 0xbc,
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TCPCheckSumErrors = 0xc0,
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IPCheckSumErrors = 0xc2,
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UDPCheckSumErrors = 0xc4,
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TxJumboFrames = 0xf4,
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/* Ethernet MIB statistic register offsets */
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OctetRcvOk = 0xa8,
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McstOctetRcvOk = 0xac,
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BcstOctetRcvOk = 0xb0,
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FramesRcvOk = 0xb4,
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McstFramesRcvdOk = 0xb8,
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BcstFramesRcvdOk = 0xbe,
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MacControlFramesRcvd = 0xc6,
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FrameTooLongErrors = 0xc8,
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InRangeLengthErrors = 0xca,
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FramesCheckSeqErrors = 0xcc,
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FramesLostRxErrors = 0xce,
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OctetXmtOk = 0xd0,
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McstOctetXmtOk = 0xd4,
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BcstOctetXmtOk = 0xd8,
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FramesXmtOk = 0xdc,
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McstFramesXmtdOk = 0xe0,
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FramesWDeferredXmt = 0xe4,
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LateCollisions = 0xe8,
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MultiColFrames = 0xec,
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SingleColFrames = 0xf0,
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BcstFramesXmtdOk = 0xf6,
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CarrierSenseErrors = 0xf8,
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MacControlFramesXmtd = 0xfa,
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FramesAbortXSColls = 0xfc,
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FramesWEXDeferal = 0xfe,
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/* RMON statistic register offsets */
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EtherStatsCollisions = 0x100,
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EtherStatsOctetsTransmit = 0x104,
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EtherStatsPktsTransmit = 0x108,
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EtherStatsPkts64OctetTransmit = 0x10c,
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EtherStats65to127OctetsTransmit = 0x110,
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EtherStatsPkts128to255OctetsTransmit = 0x114,
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EtherStatsPkts256to511OctetsTransmit = 0x118,
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EtherStatsPkts512to1023OctetsTransmit = 0x11c,
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EtherStatsPkts1024to1518OctetsTransmit = 0x120,
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EtherStatsCRCAlignErrors = 0x124,
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EtherStatsUndersizePkts = 0x128,
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EtherStatsFragments = 0x12c,
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EtherStatsJabbers = 0x130,
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EtherStatsOctets = 0x134,
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EtherStatsPkts = 0x138,
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EtherStats64Octets = 0x13c,
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EtherStatsPkts65to127Octets = 0x140,
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EtherStatsPkts128to255Octets = 0x144,
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EtherStatsPkts256to511Octets = 0x148,
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EtherStatsPkts512to1023Octets = 0x14c,
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EtherStatsPkts1024to1518Octets = 0x150,
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};
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/* Bits in the interrupt status/mask registers. */
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enum IntStatus_bits {
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InterruptStatus = 0x0001,
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HostError = 0x0002,
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MACCtrlFrame = 0x0008,
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TxComplete = 0x0004,
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RxComplete = 0x0010,
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RxEarly = 0x0020,
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IntRequested = 0x0040,
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UpdateStats = 0x0080,
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LinkEvent = 0x0100,
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TxDMAComplete = 0x0200,
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RxDMAComplete = 0x0400,
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RFDListEnd = 0x0800,
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RxDMAPriority = 0x1000,
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};
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/* Bits in the ReceiveMode register. */
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enum ReceiveMode_bits {
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ReceiveUnicast = 0x0001,
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ReceiveMulticast = 0x0002,
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ReceiveBroadcast = 0x0004,
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ReceiveAllFrames = 0x0008,
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ReceiveMulticastHash = 0x0010,
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ReceiveIPMulticast = 0x0020,
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ReceiveVLANMatch = 0x0100,
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ReceiveVLANHash = 0x0200,
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};
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/* Bits in MACCtrl. */
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enum MACCtrl_bits {
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DuplexSelect = 0x20,
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TxFlowControlEnable = 0x80,
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RxFlowControlEnable = 0x0100,
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RcvFCS = 0x200,
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AutoVLANtagging = 0x1000,
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AutoVLANuntagging = 0x2000,
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StatsEnable = 0x00200000,
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StatsDisable = 0x00400000,
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StatsEnabled = 0x00800000,
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TxEnable = 0x01000000,
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TxDisable = 0x02000000,
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TxEnabled = 0x04000000,
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RxEnable = 0x08000000,
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RxDisable = 0x10000000,
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RxEnabled = 0x20000000,
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};
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enum ASICCtrl_LoWord_bits {
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PhyMedia = 0x0080,
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};
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enum ASICCtrl_HiWord_bits {
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GlobalReset = 0x0001,
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RxReset = 0x0002,
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TxReset = 0x0004,
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DMAReset = 0x0008,
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FIFOReset = 0x0010,
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NetworkReset = 0x0020,
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HostReset = 0x0040,
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ResetBusy = 0x0400,
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};
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/* Transmit Frame Control bits */
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enum TFC_bits {
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DwordAlign = 0x00000000,
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WordAlignDisable = 0x00030000,
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WordAlign = 0x00020000,
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TCPChecksumEnable = 0x00040000,
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UDPChecksumEnable = 0x00080000,
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IPChecksumEnable = 0x00100000,
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FCSAppendDisable = 0x00200000,
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TxIndicate = 0x00400000,
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TxDMAIndicate = 0x00800000,
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FragCountShift = 24,
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VLANTagInsert = 0x0000000010000000,
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TFDDone = 0x80000000,
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VIDShift = 32,
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UsePriorityShift = 48,
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};
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/* Receive Frames Status bits */
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enum RFS_bits {
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RxFIFOOverrun = 0x00010000,
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RxRuntFrame = 0x00020000,
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RxAlignmentError = 0x00040000,
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RxFCSError = 0x00080000,
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RxOverSizedFrame = 0x00100000,
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RxLengthError = 0x00200000,
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VLANDetected = 0x00400000,
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TCPDetected = 0x00800000,
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TCPError = 0x01000000,
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UDPDetected = 0x02000000,
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UDPError = 0x04000000,
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IPDetected = 0x08000000,
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IPError = 0x10000000,
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FrameStart = 0x20000000,
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| 265 |
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FrameEnd = 0x40000000,
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| 266 |
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RFDDone = 0x80000000,
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TCIShift = 32,
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RFS_Errors = 0x003f0000,
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};
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#define MII_RESET_TIME_OUT 10000
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/* MII register */
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enum _mii_reg {
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MII_BMCR = 0,
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| 275 |
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MII_BMSR = 1,
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| 276 |
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MII_PHY_ID1 = 2,
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| 277 |
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MII_PHY_ID2 = 3,
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| 278 |
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MII_ANAR = 4,
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| 279 |
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MII_ANLPAR = 5,
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| 280 |
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MII_ANER = 6,
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| 281 |
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MII_ANNPT = 7,
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| 282 |
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MII_ANLPRNP = 8,
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| 283 |
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MII_MSCR = 9,
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| 284 |
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MII_MSSR = 10,
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| 285 |
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MII_ESR = 15,
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| 286 |
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MII_PHY_SCR = 16,
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| 287 |
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};
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| 288 |
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/* PCS register */
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| 289 |
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enum _pcs_reg {
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| 290 |
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PCS_BMCR = 0,
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| 291 |
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PCS_BMSR = 1,
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| 292 |
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PCS_ANAR = 4,
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| 293 |
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PCS_ANLPAR = 5,
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| 294 |
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PCS_ANER = 6,
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| 295 |
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PCS_ANNPT = 7,
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| 296 |
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PCS_ANLPRNP = 8,
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| 297 |
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PCS_ESR = 15,
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| 298 |
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};
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| 299 |
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| 300 |
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/* Basic Mode Control Register */
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| 301 |
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enum _mii_bmcr {
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| 302 |
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MII_BMCR_RESET = 0x8000,
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| 303 |
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MII_BMCR_LOOP_BACK = 0x4000,
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| 304 |
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MII_BMCR_SPEED_LSB = 0x2000,
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| 305 |
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MII_BMCR_AN_ENABLE = 0x1000,
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| 306 |
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MII_BMCR_POWER_DOWN = 0x0800,
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| 307 |
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MII_BMCR_ISOLATE = 0x0400,
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| 308 |
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MII_BMCR_RESTART_AN = 0x0200,
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| 309 |
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MII_BMCR_DUPLEX_MODE = 0x0100,
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| 310 |
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MII_BMCR_COL_TEST = 0x0080,
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| 311 |
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MII_BMCR_SPEED_MSB = 0x0040,
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| 312 |
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MII_BMCR_SPEED_RESERVED = 0x003f,
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| 313 |
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MII_BMCR_SPEED_10 = 0,
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| 314 |
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MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
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| 315 |
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MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
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| 316 |
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};
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| 317 |
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| 318 |
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/* Basic Mode Status Register */
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| 319 |
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enum _mii_bmsr {
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| 320 |
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MII_BMSR_100BT4 = 0x8000,
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| 321 |
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MII_BMSR_100BX_FD = 0x4000,
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| 322 |
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MII_BMSR_100BX_HD = 0x2000,
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| 323 |
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MII_BMSR_10BT_FD = 0x1000,
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| 324 |
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MII_BMSR_10BT_HD = 0x0800,
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| 325 |
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MII_BMSR_100BT2_FD = 0x0400,
|
| 326 |
|
|
MII_BMSR_100BT2_HD = 0x0200,
|
| 327 |
|
|
MII_BMSR_EXT_STATUS = 0x0100,
|
| 328 |
|
|
MII_BMSR_PREAMBLE_SUPP = 0x0040,
|
| 329 |
|
|
MII_BMSR_AN_COMPLETE = 0x0020,
|
| 330 |
|
|
MII_BMSR_REMOTE_FAULT = 0x0010,
|
| 331 |
|
|
MII_BMSR_AN_ABILITY = 0x0008,
|
| 332 |
|
|
MII_BMSR_LINK_STATUS = 0x0004,
|
| 333 |
|
|
MII_BMSR_JABBER_DETECT = 0x0002,
|
| 334 |
|
|
MII_BMSR_EXT_CAP = 0x0001,
|
| 335 |
|
|
};
|
| 336 |
|
|
|
| 337 |
|
|
/* ANAR */
|
| 338 |
|
|
enum _mii_anar {
|
| 339 |
|
|
MII_ANAR_NEXT_PAGE = 0x8000,
|
| 340 |
|
|
MII_ANAR_REMOTE_FAULT = 0x4000,
|
| 341 |
|
|
MII_ANAR_ASYMMETRIC = 0x0800,
|
| 342 |
|
|
MII_ANAR_PAUSE = 0x0400,
|
| 343 |
|
|
MII_ANAR_100BT4 = 0x0200,
|
| 344 |
|
|
MII_ANAR_100BX_FD = 0x0100,
|
| 345 |
|
|
MII_ANAR_100BX_HD = 0x0080,
|
| 346 |
|
|
MII_ANAR_10BT_FD = 0x0020,
|
| 347 |
|
|
MII_ANAR_10BT_HD = 0x0010,
|
| 348 |
|
|
MII_ANAR_SELECTOR = 0x001f,
|
| 349 |
|
|
MII_IEEE8023_CSMACD = 0x0001,
|
| 350 |
|
|
};
|
| 351 |
|
|
|
| 352 |
|
|
/* ANLPAR */
|
| 353 |
|
|
enum _mii_anlpar {
|
| 354 |
|
|
MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
|
| 355 |
|
|
MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
|
| 356 |
|
|
MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
|
| 357 |
|
|
MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
|
| 358 |
|
|
MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
|
| 359 |
|
|
MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
|
| 360 |
|
|
MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
|
| 361 |
|
|
MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
|
| 362 |
|
|
MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
|
| 363 |
|
|
MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
|
| 364 |
|
|
};
|
| 365 |
|
|
|
| 366 |
|
|
/* Auto-Negotiation Expansion Register */
|
| 367 |
|
|
enum _mii_aner {
|
| 368 |
|
|
MII_ANER_PAR_DETECT_FAULT = 0x0010,
|
| 369 |
|
|
MII_ANER_LP_NEXTPAGABLE = 0x0008,
|
| 370 |
|
|
MII_ANER_NETXTPAGABLE = 0x0004,
|
| 371 |
|
|
MII_ANER_PAGE_RECEIVED = 0x0002,
|
| 372 |
|
|
MII_ANER_LP_NEGOTIABLE = 0x0001,
|
| 373 |
|
|
};
|
| 374 |
|
|
|
| 375 |
|
|
/* MASTER-SLAVE Control Register */
|
| 376 |
|
|
enum _mii_mscr {
|
| 377 |
|
|
MII_MSCR_TEST_MODE = 0xe000,
|
| 378 |
|
|
MII_MSCR_CFG_ENABLE = 0x1000,
|
| 379 |
|
|
MII_MSCR_CFG_VALUE = 0x0800,
|
| 380 |
|
|
MII_MSCR_PORT_VALUE = 0x0400,
|
| 381 |
|
|
MII_MSCR_1000BT_FD = 0x0200,
|
| 382 |
|
|
MII_MSCR_1000BT_HD = 0X0100,
|
| 383 |
|
|
};
|
| 384 |
|
|
|
| 385 |
|
|
/* MASTER-SLAVE Status Register */
|
| 386 |
|
|
enum _mii_mssr {
|
| 387 |
|
|
MII_MSSR_CFG_FAULT = 0x8000,
|
| 388 |
|
|
MII_MSSR_CFG_RES = 0x4000,
|
| 389 |
|
|
MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
|
| 390 |
|
|
MII_MSSR_REMOTE_RCVR = 0x1000,
|
| 391 |
|
|
MII_MSSR_LP_1000BT_HD = 0x0800,
|
| 392 |
|
|
MII_MSSR_LP_1000BT_FD = 0x0400,
|
| 393 |
|
|
MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
|
| 394 |
|
|
};
|
| 395 |
|
|
|
| 396 |
|
|
/* IEEE Extened Status Register */
|
| 397 |
|
|
enum _mii_esr {
|
| 398 |
|
|
MII_ESR_1000BX_FD = 0x8000,
|
| 399 |
|
|
MII_ESR_1000BX_HD = 0x4000,
|
| 400 |
|
|
MII_ESR_1000BT_FD = 0x2000,
|
| 401 |
|
|
MII_ESR_1000BT_HD = 0x1000,
|
| 402 |
|
|
};
|
| 403 |
|
|
/* PHY Specific Control Register */
|
| 404 |
|
|
#if 0
|
| 405 |
|
|
typedef union t_MII_PHY_SCR {
|
| 406 |
|
|
u16 image;
|
| 407 |
|
|
struct {
|
| 408 |
|
|
u16 disable_jabber:1; // bit 0
|
| 409 |
|
|
u16 polarity_reversal:1; // bit 1
|
| 410 |
|
|
u16 SEQ_test:1; // bit 2
|
| 411 |
|
|
u16 _bit_3:1; // bit 3
|
| 412 |
|
|
u16 disable_CLK125:1; // bit 4
|
| 413 |
|
|
u16 mdi_crossover_mode:2; // bit 6:5
|
| 414 |
|
|
u16 enable_ext_dist:1; // bit 7
|
| 415 |
|
|
u16 _bit_8_9:2; // bit 9:8
|
| 416 |
|
|
u16 force_link:1; // bit 10
|
| 417 |
|
|
u16 assert_CRS:1; // bit 11
|
| 418 |
|
|
u16 rcv_fifo_depth:2; // bit 13:12
|
| 419 |
|
|
u16 xmit_fifo_depth:2; // bit 15:14
|
| 420 |
|
|
} bits;
|
| 421 |
|
|
} PHY_SCR_t, *PPHY_SCR_t;
|
| 422 |
|
|
#endif
|
| 423 |
|
|
|
| 424 |
|
|
typedef enum t_MII_ADMIN_STATUS {
|
| 425 |
|
|
adm_reset,
|
| 426 |
|
|
adm_operational,
|
| 427 |
|
|
adm_loopback,
|
| 428 |
|
|
adm_power_down,
|
| 429 |
|
|
adm_isolate
|
| 430 |
|
|
} MII_ADMIN_t, *PMII_ADMIN_t;
|
| 431 |
|
|
|
| 432 |
|
|
/* Physical Coding Sublayer Management (PCS) */
|
| 433 |
|
|
/* PCS control and status registers bitmap as the same as MII */
|
| 434 |
|
|
/* PCS Extended Status register bitmap as the same as MII */
|
| 435 |
|
|
/* PCS ANAR */
|
| 436 |
|
|
enum _pcs_anar {
|
| 437 |
|
|
PCS_ANAR_NEXT_PAGE = 0x8000,
|
| 438 |
|
|
PCS_ANAR_REMOTE_FAULT = 0x3000,
|
| 439 |
|
|
PCS_ANAR_ASYMMETRIC = 0x0100,
|
| 440 |
|
|
PCS_ANAR_PAUSE = 0x0080,
|
| 441 |
|
|
PCS_ANAR_HALF_DUPLEX = 0x0040,
|
| 442 |
|
|
PCS_ANAR_FULL_DUPLEX = 0x0020,
|
| 443 |
|
|
};
|
| 444 |
|
|
/* PCS ANLPAR */
|
| 445 |
|
|
enum _pcs_anlpar {
|
| 446 |
|
|
PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
|
| 447 |
|
|
PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
|
| 448 |
|
|
PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
|
| 449 |
|
|
PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
|
| 450 |
|
|
PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
|
| 451 |
|
|
PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
|
| 452 |
|
|
};
|
| 453 |
|
|
|
| 454 |
|
|
typedef struct t_SROM {
|
| 455 |
|
|
u16 config_param; /* 0x00 */
|
| 456 |
|
|
u16 asic_ctrl; /* 0x02 */
|
| 457 |
|
|
u16 sub_vendor_id; /* 0x04 */
|
| 458 |
|
|
u16 sub_system_id; /* 0x06 */
|
| 459 |
|
|
u16 reserved1[12]; /* 0x08-0x1f */
|
| 460 |
|
|
u8 mac_addr[6]; /* 0x20-0x25 */
|
| 461 |
|
|
u8 reserved2[10]; /* 0x26-0x2f */
|
| 462 |
|
|
u8 sib[204]; /* 0x30-0xfb */
|
| 463 |
|
|
u32 crc; /* 0xfc-0xff */
|
| 464 |
|
|
} SROM_t, *PSROM_t;
|
| 465 |
|
|
|
| 466 |
|
|
/* Ioctl custom data */
|
| 467 |
|
|
struct ioctl_data {
|
| 468 |
|
|
char signature[10];
|
| 469 |
|
|
int cmd;
|
| 470 |
|
|
int len;
|
| 471 |
|
|
char *data;
|
| 472 |
|
|
};
|
| 473 |
|
|
|
| 474 |
|
|
struct mii_data {
|
| 475 |
|
|
__u16 reserved;
|
| 476 |
|
|
__u16 reg_num;
|
| 477 |
|
|
__u16 in_value;
|
| 478 |
|
|
__u16 out_value;
|
| 479 |
|
|
};
|
| 480 |
|
|
|
| 481 |
|
|
/* The Rx and Tx buffer descriptors. */
|
| 482 |
|
|
struct netdev_desc {
|
| 483 |
|
|
__le64 next_desc;
|
| 484 |
|
|
__le64 status;
|
| 485 |
|
|
__le64 fraginfo;
|
| 486 |
|
|
};
|
| 487 |
|
|
|
| 488 |
|
|
#define PRIV_ALIGN 15 /* Required alignment mask */
|
| 489 |
|
|
/* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
|
| 490 |
|
|
within the structure. */
|
| 491 |
|
|
struct netdev_private {
|
| 492 |
|
|
/* Descriptor rings first for alignment. */
|
| 493 |
|
|
struct netdev_desc *rx_ring;
|
| 494 |
|
|
struct netdev_desc *tx_ring;
|
| 495 |
|
|
struct sk_buff *rx_skbuff[RX_RING_SIZE];
|
| 496 |
|
|
struct sk_buff *tx_skbuff[TX_RING_SIZE];
|
| 497 |
|
|
dma_addr_t tx_ring_dma;
|
| 498 |
|
|
dma_addr_t rx_ring_dma;
|
| 499 |
|
|
struct pci_dev *pdev;
|
| 500 |
|
|
spinlock_t tx_lock;
|
| 501 |
|
|
spinlock_t rx_lock;
|
| 502 |
|
|
struct net_device_stats stats;
|
| 503 |
|
|
unsigned int rx_buf_sz; /* Based on MTU+slack. */
|
| 504 |
|
|
unsigned int speed; /* Operating speed */
|
| 505 |
|
|
unsigned int vlan; /* VLAN Id */
|
| 506 |
|
|
unsigned int chip_id; /* PCI table chip id */
|
| 507 |
|
|
unsigned int rx_coalesce; /* Maximum frames each RxDMAComplete intr */
|
| 508 |
|
|
unsigned int rx_timeout; /* Wait time between RxDMAComplete intr */
|
| 509 |
|
|
unsigned int tx_coalesce; /* Maximum frames each tx interrupt */
|
| 510 |
|
|
unsigned int full_duplex:1; /* Full-duplex operation requested. */
|
| 511 |
|
|
unsigned int an_enable:2; /* Auto-Negotiated Enable */
|
| 512 |
|
|
unsigned int jumbo:1; /* Jumbo frame enable */
|
| 513 |
|
|
unsigned int coalesce:1; /* Rx coalescing enable */
|
| 514 |
|
|
unsigned int tx_flow:1; /* Tx flow control enable */
|
| 515 |
|
|
unsigned int rx_flow:1; /* Rx flow control enable */
|
| 516 |
|
|
unsigned int phy_media:1; /* 1: fiber, 0: copper */
|
| 517 |
|
|
unsigned int link_status:1; /* Current link status */
|
| 518 |
|
|
struct netdev_desc *last_tx; /* Last Tx descriptor used. */
|
| 519 |
|
|
unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
|
| 520 |
|
|
unsigned long cur_tx, old_tx;
|
| 521 |
|
|
struct timer_list timer;
|
| 522 |
|
|
int wake_polarity;
|
| 523 |
|
|
char name[256]; /* net device description */
|
| 524 |
|
|
u8 duplex_polarity;
|
| 525 |
|
|
u16 mcast_filter[4];
|
| 526 |
|
|
u16 advertising; /* NWay media advertisement */
|
| 527 |
|
|
u16 negotiate; /* Negotiated media */
|
| 528 |
|
|
int phy_addr; /* PHY addresses. */
|
| 529 |
|
|
};
|
| 530 |
|
|
|
| 531 |
|
|
/* The station address location in the EEPROM. */
|
| 532 |
|
|
/* The struct pci_device_id consist of:
|
| 533 |
|
|
vendor, device Vendor and device ID to match (or PCI_ANY_ID)
|
| 534 |
|
|
subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID)
|
| 535 |
|
|
class Device class to match. The class_mask tells which bits
|
| 536 |
|
|
class_mask of the class are honored during the comparison.
|
| 537 |
|
|
driver_data Data private to the driver.
|
| 538 |
|
|
*/
|
| 539 |
|
|
|
| 540 |
|
|
static const struct pci_device_id rio_pci_tbl[] = {
|
| 541 |
|
|
{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
|
| 542 |
|
|
{0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
|
| 543 |
|
|
{ }
|
| 544 |
|
|
};
|
| 545 |
|
|
MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
|
| 546 |
|
|
#define TX_TIMEOUT (4*HZ)
|
| 547 |
|
|
#define PACKET_SIZE 1536
|
| 548 |
|
|
#define MAX_JUMBO 8000
|
| 549 |
|
|
#define RIO_IO_SIZE 340
|
| 550 |
|
|
#define DEFAULT_RXC 5
|
| 551 |
|
|
#define DEFAULT_RXT 750
|
| 552 |
|
|
#define DEFAULT_TXC 1
|
| 553 |
|
|
#define MAX_TXC 8
|
| 554 |
|
|
#endif /* __DL2K_H__ */
|
