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/* drivers/net/eepro100.c: An Intel i82557-559 Ethernet driver for Linux. */

/*

        Written 1996-1999 by Donald Becker.

        The driver also contains updates by different kernel developers

        (see incomplete list below).

        Current maintainer is Andrey V. Savochkin <saw@saw.sw.com.sg>.

        Please use this email address and linux-kernel mailing list for bug reports.

        This software may be used and distributed according to the terms

        of the GNU General Public License, incorporated herein by reference.

        This driver is for the Intel EtherExpress Pro100 (Speedo3) design.

        It should work with all i82557/558/559 boards.

        Version history:

        1998 Apr - 2000 Feb  Andrey V. Savochkin <saw@saw.sw.com.sg>

                Serious fixes for multicast filter list setting, TX timeout routine;

                RX ring refilling logic;  other stuff

        2000 Feb  Jeff Garzik <jgarzik@pobox.com>

                Convert to new PCI driver interface

        2000 Mar 24  Dragan Stancevic <visitor@valinux.com>

                Disabled FC and ER, to avoid lockups when when we get FCP interrupts.

        2000 Jul 17 Goutham Rao <goutham.rao@intel.com>

                PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary

        2000 Aug 31 David Mosberger <davidm@hpl.hp.com>

                rx_align support: enables rx DMA without causing unaligned accesses.

*/

static const char * const version =

"eepro100.c:v1.09j-t 9/29/99 Donald Becker\n"

"eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw@saw.sw.com.sg> and others\n";

/* A few user-configurable values that apply to all boards.

   First set is undocumented and spelled per Intel recommendations. */

static int congenb /* = 0 */; /* Enable congestion control in the DP83840. */

static int txfifo = 8;          /* Tx FIFO threshold in 4 byte units, 0-15 */

static int rxfifo = 8;          /* Rx FIFO threshold, default 32 bytes. */

/* Tx/Rx DMA burst length, 0-127, 0 == no preemption, tx==128 -> disabled. */

static int txdmacount = 128;

static int rxdmacount /* = 0 */;

#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) || defined(__mips__) || \

        defined(__arm__)

  /* align rx buffers to 2 bytes so that IP header is aligned */

# define rx_align(skb)          skb_reserve((skb), 2)

# define RxFD_ALIGNMENT         __attribute__ ((aligned (2), packed))

#else

# define rx_align(skb)

# define RxFD_ALIGNMENT

#endif

/* Set the copy breakpoint for the copy-only-tiny-buffer Rx method.

   Lower values use more memory, but are faster. */

static int rx_copybreak = 200;

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

static int max_interrupt_work = 20;

/* Maximum number of multicast addresses to filter (vs. rx-all-multicast) */

static int multicast_filter_limit = 64;

/* 'options' is used to pass a transceiver override or full-duplex flag

   e.g. "options=16" for FD, "options=32" for 100mbps-only. */

static int full_duplex[] = {-1, -1, -1, -1, -1, -1, -1, -1};

static int options[] = {-1, -1, -1, -1, -1, -1, -1, -1};

/* A few values that may be tweaked. */

/* The ring sizes should be a power of two for efficiency. */

#define TX_RING_SIZE    64

#define RX_RING_SIZE    64

/* How much slots multicast filter setup may take.

   Do not descrease without changing set_rx_mode() implementaion. */

#define TX_MULTICAST_SIZE   2

#define TX_MULTICAST_RESERV (TX_MULTICAST_SIZE*2)

/* Actual number of TX packets queued, must be

   <= TX_RING_SIZE-TX_MULTICAST_RESERV. */

#define TX_QUEUE_LIMIT  (TX_RING_SIZE-TX_MULTICAST_RESERV)

/* Hysteresis marking queue as no longer full. */

#define TX_QUEUE_UNFULL (TX_QUEUE_LIMIT-4)

/* Operational parameters that usually are not changed. */

/* Time in jiffies before concluding the transmitter is hung. */

#define TX_TIMEOUT              (2*HZ)

/* Size of an pre-allocated Rx buffer: <Ethernet MTU> + slack.*/

#define PKT_BUF_SZ              1536

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/string.h>

#include <linux/errno.h>

#include <linux/ioport.h>

#include <linux/slab.h>

#include <linux/interrupt.h>

#include <linux/timer.h>

#include <linux/pci.h>

#include <linux/spinlock.h>

#include <linux/init.h>

#include <linux/mii.h>

#include <linux/delay.h>

#include <linux/bitops.h>

#include <asm/io.h>

#include <asm/uaccess.h>

#include <asm/irq.h>

#include <linux/netdevice.h>

#include <linux/etherdevice.h>

#include <linux/rtnetlink.h>

#include <linux/skbuff.h>

#include <linux/ethtool.h>

static int use_io;

static int debug = -1;

#define DEBUG_DEFAULT           (NETIF_MSG_DRV          | \

                                 NETIF_MSG_HW           | \

                                 NETIF_MSG_RX_ERR       | \

                                 NETIF_MSG_TX_ERR)

#define DEBUG                   ((debug >= 0) ? (1<<debug)-1 : DEBUG_DEFAULT)

MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");

MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");

MODULE_LICENSE("GPL");

module_param(use_io, int, 0);

module_param(debug, int, 0);

module_param_array(options, int, NULL, 0);

module_param_array(full_duplex, int, NULL, 0);

module_param(congenb, int, 0);

module_param(txfifo, int, 0);

module_param(rxfifo, int, 0);

module_param(txdmacount, int, 0);

module_param(rxdmacount, int, 0);

module_param(rx_copybreak, int, 0);

module_param(max_interrupt_work, int, 0);

module_param(multicast_filter_limit, int, 0);

MODULE_PARM_DESC(debug, "debug level (0-6)");

MODULE_PARM_DESC(options, "Bits 0-3: transceiver type, bit 4: full duplex, bit 5: 100Mbps");

MODULE_PARM_DESC(full_duplex, "full duplex setting(s) (1)");

MODULE_PARM_DESC(congenb, "Enable congestion control (1)");

MODULE_PARM_DESC(txfifo, "Tx FIFO threshold in 4 byte units, (0-15)");

MODULE_PARM_DESC(rxfifo, "Rx FIFO threshold in 4 byte units, (0-15)");

MODULE_PARM_DESC(txdmacount, "Tx DMA burst length; 128 - disable (0-128)");

MODULE_PARM_DESC(rxdmacount, "Rx DMA burst length; 128 - disable (0-128)");

MODULE_PARM_DESC(rx_copybreak, "copy breakpoint for copy-only-tiny-frames");

MODULE_PARM_DESC(max_interrupt_work, "maximum events handled per interrupt");

MODULE_PARM_DESC(multicast_filter_limit, "maximum number of filtered multicast addresses");

#define RUN_AT(x) (jiffies + (x))

#define netdevice_start(dev)

#define netdevice_stop(dev)

#define netif_set_tx_timeout(dev, tf, tm) \

                                                                do { \

                                                                        (dev)->tx_timeout = (tf); \

                                                                        (dev)->watchdog_timeo = (tm); \

                                                                } while(0)

/*

                                Theory of Operation

I. Board Compatibility

This device driver is designed for the Intel i82557 "Speedo3" chip, Intel's

single-chip fast Ethernet controller for PCI, as used on the Intel

EtherExpress Pro 100 adapter.

II. Board-specific settings

PCI bus devices are configured by the system at boot time, so no jumpers

need to be set on the board.  The system BIOS should be set to assign the

PCI INTA signal to an otherwise unused system IRQ line.  While it's

possible to share PCI interrupt lines, it negatively impacts performance and

only recent kernels support it.

III. Driver operation

IIIA. General

The Speedo3 is very similar to other Intel network chips, that is to say

"apparently designed on a different planet".  This chips retains the complex

Rx and Tx descriptors and multiple buffers pointers as previous chips, but

also has simplified Tx and Rx buffer modes.  This driver uses the "flexible"

Tx mode, but in a simplified lower-overhead manner: it associates only a

single buffer descriptor with each frame descriptor.

Despite the extra space overhead in each receive skbuff, the driver must use

the simplified Rx buffer mode to assure that only a single data buffer is

associated with each RxFD. The driver implements this by reserving space

for the Rx descriptor at the head of each Rx skbuff.

The Speedo-3 has receive and command unit base addresses that are added to

almost all descriptor pointers.  The driver sets these to zero, so that all

pointer fields are absolute addresses.

The System Control Block (SCB) of some previous Intel chips exists on the

chip in both PCI I/O and memory space.  This driver uses the I/O space

registers, but might switch to memory mapped mode to better support non-x86

processors.

IIIB. Transmit structure

The driver must use the complex Tx command+descriptor mode in order to

have a indirect pointer to the skbuff data section.  Each Tx command block

(TxCB) is associated with two immediately appended Tx Buffer Descriptor

(TxBD).  A fixed ring of these TxCB+TxBD pairs are kept as part of the

speedo_private data structure for each adapter instance.

The newer i82558 explicitly supports this structure, and can read the two

TxBDs in the same PCI burst as the TxCB.

This ring structure is used for all normal transmit packets, but the

transmit packet descriptors aren't long enough for most non-Tx commands such

as CmdConfigure.  This is complicated by the possibility that the chip has

already loaded the link address in the previous descriptor.  So for these

commands we convert the next free descriptor on the ring to a NoOp, and point

that descriptor's link to the complex command.

An additional complexity of these non-transmit commands are that they may be

added asynchronous to the normal transmit queue, so we disable interrupts

whenever the Tx descriptor ring is manipulated.

A notable aspect of these special configure commands is that they do

work with the normal Tx ring entry scavenge method.  The Tx ring scavenge

is done at interrupt time using the 'dirty_tx' index, and checking for the

command-complete bit.  While the setup frames may have the NoOp command on the

Tx ring marked as complete, but not have completed the setup command, this

is not a problem.  The tx_ring entry can be still safely reused, as the

tx_skbuff[] entry is always empty for config_cmd and mc_setup frames.

Commands may have bits set e.g. CmdSuspend in the command word to either

suspend or stop the transmit/command unit.  This driver always flags the last

command with CmdSuspend, erases the CmdSuspend in the previous command, and

then issues a CU_RESUME.

Note: Watch out for the potential race condition here: imagine

        erasing the previous suspend

                the chip processes the previous command

                the chip processes the final command, and suspends

        doing the CU_RESUME

                the chip processes the next-yet-valid post-final-command.

So blindly sending a CU_RESUME is only safe if we do it immediately after

after erasing the previous CmdSuspend, without the possibility of an

intervening delay.  Thus the resume command is always within the

interrupts-disabled region.  This is a timing dependence, but handling this

condition in a timing-independent way would considerably complicate the code.

Note: In previous generation Intel chips, restarting the command unit was a

notoriously slow process.  This is presumably no longer true.

IIIC. Receive structure

Because of the bus-master support on the Speedo3 this driver uses the new

SKBUFF_RX_COPYBREAK scheme, rather than a fixed intermediate receive buffer.

This scheme allocates full-sized skbuffs as receive buffers.  The value

SKBUFF_RX_COPYBREAK is used as the copying breakpoint: it is chosen to

trade-off the memory wasted by passing the full-sized skbuff to the queue

layer for all frames vs. the copying cost of copying a frame to a

correctly-sized skbuff.

For small frames the copying cost is negligible (esp. considering that we

are pre-loading the cache with immediately useful header information), so we

allocate a new, minimally-sized skbuff.  For large frames the copying cost

is non-trivial, and the larger copy might flush the cache of useful data, so

we pass up the skbuff the packet was received into.

IV. Notes

Thanks to Steve Williams of Intel for arranging the non-disclosure agreement

that stated that I could disclose the information.  But I still resent

having to sign an Intel NDA when I'm helping Intel sell their own product!

*/

static int speedo_found1(struct pci_dev *pdev, void __iomem *ioaddr, int fnd_cnt, int acpi_idle_state);

/* Offsets to the various registers.

   All accesses need not be longword aligned. */

enum speedo_offsets {

        SCBStatus = 0, SCBCmd = 2,       /* Rx/Command Unit command and status. */

        SCBIntmask = 3,

        SCBPointer = 4,                         /* General purpose pointer. */

        SCBPort = 8,                            /* Misc. commands and operands.  */

        SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */

        SCBCtrlMDI = 16,                        /* MDI interface control. */

        SCBEarlyRx = 20,                        /* Early receive byte count. */

};

/* Commands that can be put in a command list entry. */

enum commands {

        CmdNOp = 0, CmdIASetup = 0x10000, CmdConfigure = 0x20000,

        CmdMulticastList = 0x30000, CmdTx = 0x40000, CmdTDR = 0x50000,

        CmdDump = 0x60000, CmdDiagnose = 0x70000,

        CmdSuspend = 0x40000000,        /* Suspend after completion. */

        CmdIntr = 0x20000000,           /* Interrupt after completion. */

        CmdTxFlex = 0x00080000,         /* Use "Flexible mode" for CmdTx command. */

};

/* Clear CmdSuspend (1<<30) avoiding interference with the card access to the

   status bits.  Previous driver versions used separate 16 bit fields for

   commands and statuses.  --SAW

 */

#if defined(__alpha__)

# define clear_suspend(cmd)  clear_bit(30, &(cmd)->cmd_status);

#else

# if defined(__LITTLE_ENDIAN)

#  define clear_suspend(cmd)  ((__u16 *)&(cmd)->cmd_status)[1] &= ~0x4000

# elif defined(__BIG_ENDIAN)

#  define clear_suspend(cmd)  ((__u16 *)&(cmd)->cmd_status)[1] &= ~0x0040

# else

#  error Unsupported byteorder

# endif

#endif

enum SCBCmdBits {

        SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,

        SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,

        SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,

        /* The rest are Rx and Tx commands. */

        CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,

        CUCmdBase=0x0060,       /* CU Base address (set to zero) . */

        CUDumpStats=0x0070, /* Dump then reset stats counters. */

        RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,

        RxResumeNoResources=0x0007,

};

enum SCBPort_cmds {

        PortReset=0, PortSelfTest=1, PortPartialReset=2, PortDump=3,

};

/* The Speedo3 Rx and Tx frame/buffer descriptors. */

struct descriptor {                         /* A generic descriptor. */

        volatile s32 cmd_status;        /* All command and status fields. */

        u32 link;                                   /* struct descriptor *  */

        unsigned char params[0];

};

/* The Speedo3 Rx and Tx buffer descriptors. */

struct RxFD {                                   /* Receive frame descriptor. */

        volatile s32 status;

        u32 link;                                       /* struct RxFD * */

        u32 rx_buf_addr;                        /* void * */

        u32 count;

} RxFD_ALIGNMENT;

/* Selected elements of the Tx/RxFD.status word. */

enum RxFD_bits {

        RxComplete=0x8000, RxOK=0x2000,

        RxErrCRC=0x0800, RxErrAlign=0x0400, RxErrTooBig=0x0200, RxErrSymbol=0x0010,

        RxEth2Type=0x0020, RxNoMatch=0x0004, RxNoIAMatch=0x0002,

        TxUnderrun=0x1000,  StatusComplete=0x8000,

};

#define CONFIG_DATA_SIZE 22

struct TxFD {                                   /* Transmit frame descriptor set. */

        s32 status;

        u32 link;                                       /* void * */

        u32 tx_desc_addr;                       /* Always points to the tx_buf_addr element. */

        s32 count;                                      /* # of TBD (=1), Tx start thresh., etc. */

        /* This constitutes two "TBD" entries -- we only use one. */

#define TX_DESCR_BUF_OFFSET 16

        u32 tx_buf_addr0;                       /* void *, frame to be transmitted.  */

        s32 tx_buf_size0;                       /* Length of Tx frame. */

        u32 tx_buf_addr1;                       /* void *, frame to be transmitted.  */

        s32 tx_buf_size1;                       /* Length of Tx frame. */

        /* the structure must have space for at least CONFIG_DATA_SIZE starting

         * from tx_desc_addr field */

};

/* Multicast filter setting block.  --SAW */

struct speedo_mc_block {

        struct speedo_mc_block *next;

        unsigned int tx;

        dma_addr_t frame_dma;

        unsigned int len;

        struct descriptor frame __attribute__ ((__aligned__(16)));

};

/* Elements of the dump_statistics block. This block must be lword aligned. */

struct speedo_stats {

        u32 tx_good_frames;

        u32 tx_coll16_errs;

        u32 tx_late_colls;

        u32 tx_underruns;

        u32 tx_lost_carrier;

        u32 tx_deferred;

        u32 tx_one_colls;

        u32 tx_multi_colls;

        u32 tx_total_colls;

        u32 rx_good_frames;

        u32 rx_crc_errs;

        u32 rx_align_errs;

        u32 rx_resource_errs;

        u32 rx_overrun_errs;

        u32 rx_colls_errs;

        u32 rx_runt_errs;

        u32 done_marker;

};

enum Rx_ring_state_bits {

        RrNoMem=1, RrPostponed=2, RrNoResources=4, RrOOMReported=8,

};

/* Do not change the position (alignment) of the first few elements!

   The later elements are grouped for cache locality.

   Unfortunately, all the positions have been shifted since there.

   A new re-alignment is required.  2000/03/06  SAW */

struct speedo_private {

    void __iomem *regs;

        struct TxFD     *tx_ring;               /* Commands (usually CmdTxPacket). */

        struct RxFD *rx_ringp[RX_RING_SIZE];    /* Rx descriptor, used as ring. */

        /* The addresses of a Tx/Rx-in-place packets/buffers. */

        struct sk_buff *tx_skbuff[TX_RING_SIZE];

        struct sk_buff *rx_skbuff[RX_RING_SIZE];

        /* Mapped addresses of the rings. */

        dma_addr_t tx_ring_dma;

#define TX_RING_ELEM_DMA(sp, n) ((sp)->tx_ring_dma + (n)*sizeof(struct TxFD))

        dma_addr_t rx_ring_dma[RX_RING_SIZE];

        struct descriptor *last_cmd;            /* Last command sent. */

        unsigned int cur_tx, dirty_tx;          /* The ring entries to be free()ed. */

        spinlock_t lock;                        /* Group with Tx control cache line. */

        u32 tx_threshold;                       /* The value for txdesc.count. */

        struct RxFD *last_rxf;                  /* Last filled RX buffer. */

        dma_addr_t last_rxf_dma;

        unsigned int cur_rx, dirty_rx;          /* The next free ring entry */

        long last_rx_time;                      /* Last Rx, in jiffies, to handle Rx hang. */

        struct net_device_stats stats;

        struct speedo_stats *lstats;

        dma_addr_t lstats_dma;

        int chip_id;

        struct pci_dev *pdev;

        struct timer_list timer;                /* Media selection timer. */

        struct speedo_mc_block *mc_setup_head;  /* Multicast setup frame list head. */

        struct speedo_mc_block *mc_setup_tail;  /* Multicast setup frame list tail. */

        long in_interrupt;                      /* Word-aligned dev->interrupt */

        unsigned char acpi_pwr;

        signed char rx_mode;                    /* Current PROMISC/ALLMULTI setting. */

        unsigned int tx_full:1;                 /* The Tx queue is full. */

        unsigned int flow_ctrl:1;               /* Use 802.3x flow control. */

        unsigned int rx_bug:1;                  /* Work around receiver hang errata. */

        unsigned char default_port:8;           /* Last dev->if_port value. */

        unsigned char rx_ring_state;            /* RX ring status flags. */

        unsigned short phy[2];                  /* PHY media interfaces available. */

        unsigned short partner;                 /* Link partner caps. */

        struct mii_if_info mii_if;              /* MII API hooks, info */

        u32 msg_enable;                         /* debug message level */

};

/* The parameters for a CmdConfigure operation.

   There are so many options that it would be difficult to document each bit.

   We mostly use the default or recommended settings. */

static const char i82557_config_cmd[CONFIG_DATA_SIZE] = {

        22, 0x08, 0, 0,  0, 0, 0x32, 0x03,  1, /* 1=Use MII  0=Use AUI */

        0, 0x2E, 0,  0x60, 0,

        0xf2, 0x48,   0, 0x40, 0xf2, 0x80,               /* 0x40=Force full-duplex */

        0x3f, 0x05, };

static const char i82558_config_cmd[CONFIG_DATA_SIZE] = {

        22, 0x08, 0, 1,  0, 0, 0x22, 0x03,  1, /* 1=Use MII  0=Use AUI */

        0, 0x2E, 0,  0x60, 0x08, 0x88,

        0x68, 0, 0x40, 0xf2, 0x84,               /* Disable FC */

        0x31, 0x05, };

/* PHY media interface chips. */

static const char * const phys[] = {

        "None", "i82553-A/B", "i82553-C", "i82503",

        "DP83840", "80c240", "80c24", "i82555",

        "unknown-8", "unknown-9", "DP83840A", "unknown-11",

        "unknown-12", "unknown-13", "unknown-14", "unknown-15", };

enum phy_chips { NonSuchPhy=0, I82553AB, I82553C, I82503, DP83840, S80C240,

                                         S80C24, I82555, DP83840A=10, };

static const char is_mii[] = { 0, 1, 1, 0, 1, 1, 0, 1 };

#define EE_READ_CMD             (6)

static int eepro100_init_one(struct pci_dev *pdev,

                const struct pci_device_id *ent);

static int do_eeprom_cmd(void __iomem *ioaddr, int cmd, int cmd_len);

static int mdio_read(struct net_device *dev, int phy_id, int location);

static void mdio_write(struct net_device *dev, int phy_id, int location, int value);

static int speedo_open(struct net_device *dev);

static void speedo_resume(struct net_device *dev);

static void speedo_timer(unsigned long data);

static void speedo_init_rx_ring(struct net_device *dev);

static void speedo_tx_timeout(struct net_device *dev);

static int speedo_start_xmit(struct sk_buff *skb, struct net_device *dev);

static void speedo_refill_rx_buffers(struct net_device *dev, int force);

static int speedo_rx(struct net_device *dev);

static void speedo_tx_buffer_gc(struct net_device *dev);

static irqreturn_t speedo_interrupt(int irq, void *dev_instance);

static int speedo_close(struct net_device *dev);

static struct net_device_stats *speedo_get_stats(struct net_device *dev);

static int speedo_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

static void set_rx_mode(struct net_device *dev);

static void speedo_show_state(struct net_device *dev);

static const struct ethtool_ops ethtool_ops;

#ifdef honor_default_port

/* Optional driver feature to allow forcing the transceiver setting.

   Not recommended. */

static int mii_ctrl[8] = { 0x3300, 0x3100, 0x0000, 0x0100,

                                                   0x2000, 0x2100, 0x0400, 0x3100};

#endif

/* How to wait for the command unit to accept a command.

   Typically this takes 0 ticks. */

static inline unsigned char wait_for_cmd_done(struct net_device *dev,

                                                                                                struct speedo_private *sp)

{

        int wait = 1000;

        void __iomem *cmd_ioaddr = sp->regs + SCBCmd;

        unsigned char r;

        do  {

                udelay(1);

                r = ioread8(cmd_ioaddr);

        } while(r && --wait >= 0);

        if (wait < 0)

                printk(KERN_ALERT "%s: wait_for_cmd_done timeout!\n", dev->name);

        return r;

}

static int __devinit eepro100_init_one (struct pci_dev *pdev,

                const struct pci_device_id *ent)

{

        void __iomem *ioaddr;

        int irq, pci_bar;

        int acpi_idle_state = 0, pm;

        static int cards_found /* = 0 */;

        unsigned long pci_base;

#ifndef MODULE

        /* when built-in, we only print version if device is found */

        static int did_version;

        if (did_version++ == 0)

                printk(version);

#endif

        /* save power state before pci_enable_device overwrites it */

        pm = pci_find_capability(pdev, PCI_CAP_ID_PM);

        if (pm) {

                u16 pwr_command;

                pci_read_config_word(pdev, pm + PCI_PM_CTRL, &pwr_command);

                acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;

        }

        if (pci_enable_device(pdev))

                goto err_out_free_mmio_region;

        pci_set_master(pdev);

        if (!request_region(pci_resource_start(pdev, 1),

                        pci_resource_len(pdev, 1), "eepro100")) {

                dev_err(&pdev->dev, "eepro100: cannot reserve I/O ports\n");

                goto err_out_none;

        }

        if (!request_mem_region(pci_resource_start(pdev, 0),

                        pci_resource_len(pdev, 0), "eepro100")) {

                dev_err(&pdev->dev, "eepro100: cannot reserve MMIO region\n");

                goto err_out_free_pio_region;

        }

        irq = pdev->irq;

        pci_bar = use_io ? 1 : 0;

        pci_base = pci_resource_start(pdev, pci_bar);

        if (DEBUG & NETIF_MSG_PROBE)

                printk("Found Intel i82557 PCI Speedo at %#lx, IRQ %d.\n",

                       pci_base, irq);

        ioaddr = pci_iomap(pdev, pci_bar, 0);

        if (!ioaddr) {

                dev_err(&pdev->dev, "eepro100: cannot remap IO\n");

                goto err_out_free_mmio_region;

        }

        if (speedo_found1(pdev, ioaddr, cards_found, acpi_idle_state) == 0)

                cards_found++;

        else

                goto err_out_iounmap;

        return 0;

err_out_iounmap: ;

        pci_iounmap(pdev, ioaddr);

err_out_free_mmio_region:

        release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));

err_out_free_pio_region:

        release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));

err_out_none:

        return -ENODEV;

}

#ifdef CONFIG_NET_POLL_CONTROLLER

/*

 * Polling 'interrupt' - used by things like netconsole to send skbs

 * without having to re-enable interrupts. It's not called while

 * the interrupt routine is executing.

 */

static void poll_speedo (struct net_device *dev)

{

        /* disable_irq is not very nice, but with the funny lockless design

           we have no other choice. */

        disable_irq(dev->irq);

        speedo_interrupt (dev->irq, dev);

        enable_irq(dev->irq);

}

#endif

static int __devinit speedo_found1(struct pci_dev *pdev,

                void __iomem *ioaddr, int card_idx, int acpi_idle_state)

{

        struct net_device *dev;

        struct speedo_private *sp;

        const char *product;

        int i, option;

        u16 eeprom[0x100];

        int size;

        void *tx_ring_space;

        dma_addr_t tx_ring_dma;

        DECLARE_MAC_BUF(mac);

        size = TX_RING_SIZE * sizeof(struct TxFD) + sizeof(struct speedo_stats);

        tx_ring_space = pci_alloc_consistent(pdev, size, &tx_ring_dma);

        if (tx_ring_space == NULL)

                return -1;

        dev = alloc_etherdev(sizeof(struct speedo_private));

        if (dev == NULL) {

                printk(KERN_ERR "eepro100: Could not allocate ethernet device.\n");

                pci_free_consistent(pdev, size, tx_ring_space, tx_ring_dma);

                return -1;

        }

        SET_NETDEV_DEV(dev, &pdev->dev);

        if (dev->mem_start > 0)

                option = dev->mem_start;

        else if (card_idx >= 0  &&  options[card_idx] >= 0)

                option = options[card_idx];

        else

                option = 0;

        rtnl_lock();

        if (dev_alloc_name(dev, dev->name) < 0)

                goto err_free_unlock;

        /* Read the station address EEPROM before doing the reset.

           Nominally his should even be done before accepting the device, but

           then we wouldn't have a device name with which to report the error.

           The size test is for 6 bit vs. 8 bit address serial EEPROMs.

        */

        {

                void __iomem *iobase;

                int read_cmd, ee_size;

                u16 sum;

                int j;

                /* Use IO only to avoid postponed writes and satisfy EEPROM timing

                   requirements. */

                iobase = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));

                if (!iobase)

                        goto err_free_unlock;

                if ((do_eeprom_cmd(iobase, EE_READ_CMD << 24, 27) & 0xffe0000)

                        == 0xffe0000) {

                        ee_size = 0x100;

                        read_cmd = EE_READ_CMD << 24;

                } else {

                        ee_size = 0x40;

                        read_cmd = EE_READ_CMD << 22;

                }

                for (j = 0, i = 0, sum = 0; i < ee_size; i++) {

                        u16 value = do_eeprom_cmd(iobase, read_cmd | (i << 16), 27);

                        eeprom[i] = value;

                        sum += value;

                        if (i < 3) {