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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [net/] [fec.h] - Blame information for rev 62

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1 62 marcus.erl 
/****************************************************************************/
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/*
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 *      fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
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 *                 processors.
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 *
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 *      (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
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 *      (C) Copyright 2000-2001, Lineo (www.lineo.com)
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 */
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/****************************************************************************/
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#ifndef FEC_H
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#define FEC_H
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/****************************************************************************/
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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    defined(CONFIG_M520x) || defined(CONFIG_M532x)
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/*
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 *      Just figures, Motorola would have to change the offsets for
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 *      registers in the same peripheral device on different models
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 *      of the ColdFire!
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 */
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typedef struct fec {
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        unsigned long   fec_reserved0;
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        unsigned long   fec_ievent;             /* Interrupt event reg */
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        unsigned long   fec_imask;              /* Interrupt mask reg */
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        unsigned long   fec_reserved1;
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        unsigned long   fec_r_des_active;       /* Receive descriptor reg */
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        unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
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        unsigned long   fec_reserved2[3];
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        unsigned long   fec_ecntrl;             /* Ethernet control reg */
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        unsigned long   fec_reserved3[6];
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        unsigned long   fec_mii_data;           /* MII manage frame reg */
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        unsigned long   fec_mii_speed;          /* MII speed control reg */
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        unsigned long   fec_reserved4[7];
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        unsigned long   fec_mib_ctrlstat;       /* MIB control/status reg */
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        unsigned long   fec_reserved5[7];
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        unsigned long   fec_r_cntrl;            /* Receive control reg */
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        unsigned long   fec_reserved6[15];
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        unsigned long   fec_x_cntrl;            /* Transmit Control reg */
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        unsigned long   fec_reserved7[7];
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        unsigned long   fec_addr_low;           /* Low 32bits MAC address */
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        unsigned long   fec_addr_high;          /* High 16bits MAC address */
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        unsigned long   fec_opd;                /* Opcode + Pause duration */
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        unsigned long   fec_reserved8[10];
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        unsigned long   fec_hash_table_high;    /* High 32bits hash table */
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        unsigned long   fec_hash_table_low;     /* Low 32bits hash table */
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        unsigned long   fec_grp_hash_table_high;/* High 32bits hash table */
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        unsigned long   fec_grp_hash_table_low; /* Low 32bits hash table */
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        unsigned long   fec_reserved9[7];
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        unsigned long   fec_x_wmrk;             /* FIFO transmit water mark */
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        unsigned long   fec_reserved10;
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        unsigned long   fec_r_bound;            /* FIFO receive bound reg */
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        unsigned long   fec_r_fstart;           /* FIFO receive start reg */
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        unsigned long   fec_reserved11[11];
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        unsigned long   fec_r_des_start;        /* Receive descriptor ring */
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        unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
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        unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
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} fec_t;
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#else
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/*
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 *      Define device register set address map.
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 */
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typedef struct fec {
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        unsigned long   fec_ecntrl;             /* Ethernet control reg */
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        unsigned long   fec_ievent;             /* Interrupt even reg */
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        unsigned long   fec_imask;              /* Interrupt mask reg */
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        unsigned long   fec_ivec;               /* Interrupt vec status reg */
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        unsigned long   fec_r_des_active;       /* Receive descriptor reg */
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        unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
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        unsigned long   fec_reserved1[10];
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        unsigned long   fec_mii_data;           /* MII manage frame reg */
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        unsigned long   fec_mii_speed;          /* MII speed control reg */
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        unsigned long   fec_reserved2[17];
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        unsigned long   fec_r_bound;            /* FIFO receive bound reg */
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        unsigned long   fec_r_fstart;           /* FIFO receive start reg */
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        unsigned long   fec_reserved3[4];
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        unsigned long   fec_x_wmrk;             /* FIFO transmit water mark */
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        unsigned long   fec_reserved4;
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        unsigned long   fec_x_fstart;           /* FIFO transmit start reg */
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        unsigned long   fec_reserved5[21];
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        unsigned long   fec_r_cntrl;            /* Receive control reg */
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        unsigned long   fec_max_frm_len;        /* Maximum frame length reg */
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        unsigned long   fec_reserved6[14];
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        unsigned long   fec_x_cntrl;            /* Transmit Control reg */
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        unsigned long   fec_reserved7[158];
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        unsigned long   fec_addr_low;           /* Low 32bits MAC address */
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        unsigned long   fec_addr_high;          /* High 16bits MAC address */
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        unsigned long   fec_hash_table_high;    /* High 32bits hash table */
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        unsigned long   fec_hash_table_low;     /* Low 32bits hash table */
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        unsigned long   fec_r_des_start;        /* Receive descriptor ring */
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        unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
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        unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
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        unsigned long   reserved8[9];
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        unsigned long   fec_fifo_ram[112];      /* FIFO RAM buffer */
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} fec_t;
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#endif /* CONFIG_M5272 */
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/*
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 *      Define the buffer descriptor structure.
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 */
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typedef struct bufdesc {
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        unsigned short  cbd_sc;                 /* Control and status info */
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        unsigned short  cbd_datlen;             /* Data length */
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        unsigned long   cbd_bufaddr;            /* Buffer address */
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} cbd_t;
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/*
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 *      The following definitions courtesy of commproc.h, which where
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 *      Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
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 */
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#define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
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#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
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#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
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#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
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#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
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#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
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#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
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#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
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#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
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#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
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#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
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#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
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#define BD_ENET_RX_WRAP         ((ushort)0x2000)
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#define BD_ENET_RX_INTR         ((ushort)0x1000)
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#define BD_ENET_RX_LAST         ((ushort)0x0800)
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#define BD_ENET_RX_FIRST        ((ushort)0x0400)
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#define BD_ENET_RX_MISS         ((ushort)0x0100)
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#define BD_ENET_RX_LG           ((ushort)0x0020)
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#define BD_ENET_RX_NO           ((ushort)0x0010)
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#define BD_ENET_RX_SH           ((ushort)0x0008)
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#define BD_ENET_RX_CR           ((ushort)0x0004)
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#define BD_ENET_RX_OV           ((ushort)0x0002)
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#define BD_ENET_RX_CL           ((ushort)0x0001)
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#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
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/* Buffer descriptor control/status used by Ethernet transmit.
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*/
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#define BD_ENET_TX_READY        ((ushort)0x8000)
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#define BD_ENET_TX_PAD          ((ushort)0x4000)
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#define BD_ENET_TX_WRAP         ((ushort)0x2000)
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#define BD_ENET_TX_INTR         ((ushort)0x1000)
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#define BD_ENET_TX_LAST         ((ushort)0x0800)
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#define BD_ENET_TX_TC           ((ushort)0x0400)
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#define BD_ENET_TX_DEF          ((ushort)0x0200)
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#define BD_ENET_TX_HB           ((ushort)0x0100)
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#define BD_ENET_TX_LC           ((ushort)0x0080)
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#define BD_ENET_TX_RL           ((ushort)0x0040)
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#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
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#define BD_ENET_TX_UN           ((ushort)0x0002)
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#define BD_ENET_TX_CSL          ((ushort)0x0001)
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#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
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/****************************************************************************/
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#endif /* FEC_H */

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