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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [net/] [irda/] [w83977af_ir.h] - Blame information for rev 62

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1 62 marcus.erl
/*********************************************************************
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 *
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 * Filename:      w83977af_ir.h
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 * Version:
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 * Description:
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 * Status:        Experimental.
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 * Author:        Paul VanderSpek
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 * Created at:    Thu Nov 19 13:55:34 1998
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 * Modified at:   Tue Jan 11 13:08:19 2000
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 * Modified by:   Dag Brattli <dagb@cs.uit.no>
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 *
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 *     Copyright (c) 1998-2000 Dag Brattli, All Rights Reserved.
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 *
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 *     This program is free software; you can redistribute it and/or
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 *     modify it under the terms of the GNU General Public License as
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 *     published by the Free Software Foundation; either version 2 of
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 *     the License, or (at your option) any later version.
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 *
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 *     Neither Dag Brattli nor University of Tromsø admit liability nor
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 *     provide warranty for any of this software. This material is
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 *     provided "AS-IS" and at no charge.
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 *
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 ********************************************************************/
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#ifndef W83977AF_IR_H
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#define W83977AF_IR_H
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#include <asm/io.h>
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#include <linux/types.h>
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/* Flags for configuration register CRF0 */
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#define ENBNKSEL        0x01
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#define APEDCRC         0x02
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#define TXW4C           0x04
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#define RXW4C           0x08
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/* Bank 0 */
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#define RBR             0x00 /* Receiver buffer register */
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#define TBR             0x00 /* Transmitter buffer register */
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#define ICR             0x01 /* Interrupt configuration register */
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#define ICR_ERBRI       0x01 /* Receiver buffer register interrupt */
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#define ICR_ETBREI      0x02 /* Transeiver empty interrupt */
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#define ICR_EUSRI       0x04//* IR status interrupt */
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#define ICR_EHSRI       0x04
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#define ICR_ETXURI      0x04 /* Tx underrun */
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#define ICR_EDMAI       0x10 /* DMA interrupt */
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#define ICR_ETXTHI      0x20 /* Transmitter threshold interrupt */
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#define ICR_EFSFI       0x40 /* Frame status FIFO interrupt */
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#define ICR_ETMRI       0x80 /* Timer interrupt */
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#define UFR             0x02 /* FIFO control register */
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#define UFR_EN_FIFO     0x01 /* Enable FIFO's */
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#define UFR_RXF_RST     0x02 /* Reset Rx FIFO */
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#define UFR_TXF_RST     0x04 /* Reset Tx FIFO */
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#define UFR_RXTL        0x80 /* Rx FIFO threshold (set to 16) */
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#define UFR_TXTL        0x20 /* Tx FIFO threshold (set to 17) */
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#define ISR             0x02 /* Interrupt status register */
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#define ISR_RXTH_I      0x01 /* Receive threshold interrupt */
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#define ISR_TXEMP_I     0x02 /* Transmitter empty interrupt */
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#define ISR_FEND_I      0x04
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#define ISR_DMA_I       0x10
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#define ISR_TXTH_I      0x20 /* Transmitter threshold interrupt */
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#define ISR_FSF_I       0x40
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#define ISR_TMR_I       0x80 /* Timer interrupt */
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#define UCR             0x03 /* Uart control register */
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#define UCR_DLS8        0x03 /* 8N1 */
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#define SSR             0x03 /* Sets select register */
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#define SET0            UCR_DLS8        /* Make sure we keep 8N1 */
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#define SET1            (0x80|UCR_DLS8) /* Make sure we keep 8N1 */
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#define SET2            0xE0
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#define SET3            0xE4
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#define SET4            0xE8
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#define SET5            0xEC
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#define SET6            0xF0
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#define SET7            0xF4
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#define HCR             0x04
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#define HCR_MODE_MASK   ~(0xD0)
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#define HCR_SIR         0x60
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#define HCR_MIR_576     0x20    
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#define HCR_MIR_1152    0x80
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#define HCR_FIR         0xA0
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#define HCR_EN_DMA      0x04
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#define HCR_EN_IRQ      0x08
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#define HCR_TX_WT       0x08
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#define USR             0x05 /* IR status register */
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#define USR_RDR         0x01 /* Receive data ready */
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#define USR_TSRE        0x40 /* Transmitter empty? */
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#define AUDR            0x07
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#define AUDR_SFEND      0x08 /* Set a frame end */
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#define AUDR_RXBSY      0x20 /* Rx busy */
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#define AUDR_UNDR       0x40 /* Transeiver underrun */
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/* Set 2 */
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#define ABLL            0x00 /* Advanced baud rate divisor latch (low byte) */
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#define ABHL            0x01 /* Advanced baud rate divisor latch (high byte) */
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#define ADCR1           0x02
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#define ADCR1_ADV_SL    0x01    
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#define ADCR1_D_CHSW    0x08    /* the specs are wrong. its bit 3, not 4 */
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#define ADCR1_DMA_F     0x02
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#define ADCR2           0x04
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#define ADCR2_TXFS32    0x01
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#define ADCR2_RXFS32    0x04
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#define RXFDTH          0x07
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/* Set 3 */
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#define AUID            0x00
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/* Set 4 */
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#define TMRL            0x00 /* Timer value register (low byte) */
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#define TMRH            0x01 /* Timer value register (high byte) */
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#define IR_MSL          0x02 /* Infrared mode select */
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#define IR_MSL_EN_TMR   0x01 /* Enable timer */
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#define TFRLL           0x04 /* Transmitter frame length (low byte) */
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#define TFRLH           0x05 /* Transmitter frame length (high byte) */
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#define RFRLL           0x06 /* Receiver frame length (low byte) */
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#define RFRLH           0x07 /* Receiver frame length (high byte) */
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/* Set 5 */
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#define FS_FO           0x05 /* Frame status FIFO */
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#define FS_FO_FSFDR     0x80 /* Frame status FIFO data ready */
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#define FS_FO_LST_FR    0x40 /* Frame lost */
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#define FS_FO_MX_LEX    0x10 /* Max frame len exceeded */
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#define FS_FO_PHY_ERR   0x08 /* Physical layer error */
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#define FS_FO_CRC_ERR   0x04 
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#define FS_FO_RX_OV     0x02 /* Receive overrun */
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#define FS_FO_FSF_OV    0x01 /* Frame status FIFO overrun */
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#define FS_FO_ERR_MSK   0x5f /* Error mask */
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#define RFLFL           0x06
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#define RFLFH           0x07
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/* Set 6 */
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#define IR_CFG2         0x00
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#define IR_CFG2_DIS_CRC 0x02
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/* Set 7 */
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#define IRM_CR          0x07 /* Infrared module control register */
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#define IRM_CR_IRX_MSL  0x40
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#define IRM_CR_AF_MNT   0x80 /* Automatic format */
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/* For storing entries in the status FIFO */
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struct st_fifo_entry {
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        int status;
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        int len;
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};
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struct st_fifo {
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        struct st_fifo_entry entries[10];
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        int head;
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        int tail;
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        int len;
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};
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/* Private data for each instance */
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struct w83977af_ir {
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        struct st_fifo st_fifo;
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        int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
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        int tx_len;          /* Number of frames in tx_buff */
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        struct net_device *netdev; /* Yes! we are some kind of netdevice */
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        struct net_device_stats stats;
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        struct irlap_cb    *irlap; /* The link layer we are binded to */
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        struct qos_info     qos;   /* QoS capabilities for this device */
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        chipio_t io;               /* IrDA controller information */
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        iobuff_t tx_buff;          /* Transmit buffer */
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        iobuff_t rx_buff;          /* Receive buffer */
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        dma_addr_t tx_buff_dma;
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        dma_addr_t rx_buff_dma;
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        /* Note : currently locking is *very* incomplete, but this
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         * will get you started. Check in nsc-ircc.c for a proper
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         * locking strategy. - Jean II */
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        spinlock_t lock;           /* For serializing operations */
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        __u32 new_speed;
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};
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static inline void switch_bank( int iobase, int set)
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{
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        outb(set, iobase+SSR);
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}
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#endif

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