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marcus.erl |
/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
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/*
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* Copyright 1996-1999 Thomas Bogendoerfer
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*
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* Derived from the lance driver written 1993,1994,1995 by Donald Becker.
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*
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* Copyright 1993 United States Government as represented by the
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* Director, National Security Agency.
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* This driver is for PCnet32 and PCnetPCI based ethercards
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*/
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/**************************************************************************
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* 23 Oct, 2000.
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* Fixed a few bugs, related to running the controller in 32bit mode.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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*************************************************************************/
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#define DRV_NAME "pcnet32"
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#ifdef CONFIG_PCNET32_NAPI
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#define DRV_VERSION "1.34-NAPI"
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#else
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#define DRV_VERSION "1.34"
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#endif
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#define DRV_RELDATE "14.Aug.2007"
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#define PFX DRV_NAME ": "
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static const char *const version =
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DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/crc32.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/moduleparam.h>
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#include <linux/bitops.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/irq.h>
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/*
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* PCI device identifiers for "new style" Linux PCI Device Drivers
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*/
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static struct pci_device_id pcnet32_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
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/*
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* Adapters that were sold with IBM's RS/6000 or pSeries hardware have
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* the incorrect vendor id.
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*/
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{ PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
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.class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
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{ } /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
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static int cards_found;
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/*
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* VLB I/O addresses
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*/
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static unsigned int pcnet32_portlist[] __initdata =
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{ 0x300, 0x320, 0x340, 0x360, 0 };
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static int pcnet32_debug = 0;
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static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
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static int pcnet32vlb; /* check for VLB cards ? */
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static struct net_device *pcnet32_dev;
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static int max_interrupt_work = 2;
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static int rx_copybreak = 200;
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#define PCNET32_PORT_AUI 0x00
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#define PCNET32_PORT_10BT 0x01
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#define PCNET32_PORT_GPSI 0x02
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#define PCNET32_PORT_MII 0x03
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#define PCNET32_PORT_PORTSEL 0x03
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#define PCNET32_PORT_ASEL 0x04
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#define PCNET32_PORT_100 0x40
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#define PCNET32_PORT_FD 0x80
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#define PCNET32_DMA_MASK 0xffffffff
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#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
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#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
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/*
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* table to translate option values from tulip
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* to internal options
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*/
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static const unsigned char options_mapping[] = {
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PCNET32_PORT_ASEL, /* 0 Auto-select */
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PCNET32_PORT_AUI, /* 1 BNC/AUI */
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PCNET32_PORT_AUI, /* 2 AUI/BNC */
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PCNET32_PORT_ASEL, /* 3 not supported */
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PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
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PCNET32_PORT_ASEL, /* 5 not supported */
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PCNET32_PORT_ASEL, /* 6 not supported */
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PCNET32_PORT_ASEL, /* 7 not supported */
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PCNET32_PORT_ASEL, /* 8 not supported */
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PCNET32_PORT_MII, /* 9 MII 10baseT */
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PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
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PCNET32_PORT_MII, /* 11 MII (autosel) */
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PCNET32_PORT_10BT, /* 12 10BaseT */
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PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
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/* 14 MII 100BaseTx-FD */
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PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
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PCNET32_PORT_ASEL /* 15 not supported */
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};
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static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
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"Loopback test (offline)"
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};
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#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
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#define PCNET32_NUM_REGS 136
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#define MAX_UNITS 8 /* More are supported, limit only on options */
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static int options[MAX_UNITS];
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static int full_duplex[MAX_UNITS];
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static int homepna[MAX_UNITS];
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/*
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* Theory of Operation
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*
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* This driver uses the same software structure as the normal lance
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* driver. So look for a verbose description in lance.c. The differences
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* to the normal lance driver is the use of the 32bit mode of PCnet32
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* and PCnetPCI chips. Because these chips are 32bit chips, there is no
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* 16MB limitation and we don't need bounce buffers.
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*/
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/*
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
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* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
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*/
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#ifndef PCNET32_LOG_TX_BUFFERS
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#define PCNET32_LOG_TX_BUFFERS 4
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#define PCNET32_LOG_RX_BUFFERS 5
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#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
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#define PCNET32_LOG_MAX_RX_BUFFERS 9
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#endif
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#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
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#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
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#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
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#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
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#define PKT_BUF_SZ 1544
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/* Offsets from base I/O address. */
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#define PCNET32_WIO_RDP 0x10
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#define PCNET32_WIO_RAP 0x12
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#define PCNET32_WIO_RESET 0x14
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#define PCNET32_WIO_BDP 0x16
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#define PCNET32_DWIO_RDP 0x10
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#define PCNET32_DWIO_RAP 0x14
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#define PCNET32_DWIO_RESET 0x18
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#define PCNET32_DWIO_BDP 0x1C
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#define PCNET32_TOTAL_SIZE 0x20
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#define CSR0 0
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#define CSR0_INIT 0x1
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#define CSR0_START 0x2
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#define CSR0_STOP 0x4
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#define CSR0_TXPOLL 0x8
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#define CSR0_INTEN 0x40
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#define CSR0_IDON 0x0100
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#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
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#define PCNET32_INIT_LOW 1
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#define PCNET32_INIT_HIGH 2
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#define CSR3 3
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#define CSR4 4
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#define CSR5 5
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#define CSR5_SUSPEND 0x0001
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#define CSR15 15
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#define PCNET32_MC_FILTER 8
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#define PCNET32_79C970A 0x2621
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/* The PCNET32 Rx and Tx ring descriptors. */
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struct pcnet32_rx_head {
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__le32 base;
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__le16 buf_length; /* two`s complement of length */
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__le16 status;
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__le32 msg_length;
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__le32 reserved;
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};
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struct pcnet32_tx_head {
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__le32 base;
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__le16 length; /* two`s complement of length */
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__le16 status;
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__le32 misc;
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__le32 reserved;
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};
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/* The PCNET32 32-Bit initialization block, described in databook. */
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struct pcnet32_init_block {
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__le16 mode;
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__le16 tlen_rlen;
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u8 phys_addr[6];
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__le16 reserved;
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__le32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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__le32 rx_ring;
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__le32 tx_ring;
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};
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/* PCnet32 access functions */
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struct pcnet32_access {
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u16 (*read_csr) (unsigned long, int);
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void (*write_csr) (unsigned long, int, u16);
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u16 (*read_bcr) (unsigned long, int);
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void (*write_bcr) (unsigned long, int, u16);
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u16 (*read_rap) (unsigned long);
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void (*write_rap) (unsigned long, u16);
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void (*reset) (unsigned long);
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};
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/*
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* The first field of pcnet32_private is read by the ethernet device
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* so the structure should be allocated using pci_alloc_consistent().
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*/
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struct pcnet32_private {
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struct pcnet32_init_block *init_block;
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/* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
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struct pcnet32_rx_head *rx_ring;
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struct pcnet32_tx_head *tx_ring;
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dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
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returned by pci_alloc_consistent */
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struct pci_dev *pci_dev;
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const char *name;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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struct sk_buff **tx_skbuff;
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struct sk_buff **rx_skbuff;
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dma_addr_t *tx_dma_addr;
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dma_addr_t *rx_dma_addr;
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struct pcnet32_access a;
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spinlock_t lock; /* Guard lock */
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unsigned int cur_rx, cur_tx; /* The next free ring entry */
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unsigned int rx_ring_size; /* current rx ring size */
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unsigned int tx_ring_size; /* current tx ring size */
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unsigned int rx_mod_mask; /* rx ring modular mask */
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unsigned int tx_mod_mask; /* tx ring modular mask */
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unsigned short rx_len_bits;
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unsigned short tx_len_bits;
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dma_addr_t rx_ring_dma_addr;
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dma_addr_t tx_ring_dma_addr;
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unsigned int dirty_rx, /* ring entries to be freed. */
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dirty_tx;
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struct net_device *dev;
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struct napi_struct napi;
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char tx_full;
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char phycount; /* number of phys found */
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int options;
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| 288 |
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unsigned int shared_irq:1, /* shared irq possible */
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dxsuflo:1, /* disable transmit stop on uflo */
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mii:1; /* mii port available */
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struct net_device *next;
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struct mii_if_info mii_if;
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struct timer_list watchdog_timer;
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struct timer_list blink_timer;
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u32 msg_enable; /* debug message level */
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| 297 |
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/* each bit indicates an available PHY */
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u32 phymask;
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unsigned short chip_version; /* which variant this is */
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};
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static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
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static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
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static int pcnet32_open(struct net_device *);
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static int pcnet32_init_ring(struct net_device *);
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static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
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static void pcnet32_tx_timeout(struct net_device *dev);
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static irqreturn_t pcnet32_interrupt(int, void *);
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static int pcnet32_close(struct net_device *);
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| 310 |
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static struct net_device_stats *pcnet32_get_stats(struct net_device *);
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static void pcnet32_load_multicast(struct net_device *dev);
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static void pcnet32_set_multicast_list(struct net_device *);
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static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
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static void pcnet32_watchdog(struct net_device *);
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| 315 |
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static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
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| 316 |
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static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
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| 317 |
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int val);
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| 318 |
|
|
static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
|
| 319 |
|
|
static void pcnet32_ethtool_test(struct net_device *dev,
|
| 320 |
|
|
struct ethtool_test *eth_test, u64 * data);
|
| 321 |
|
|
static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
|
| 322 |
|
|
static int pcnet32_phys_id(struct net_device *dev, u32 data);
|
| 323 |
|
|
static void pcnet32_led_blink_callback(struct net_device *dev);
|
| 324 |
|
|
static int pcnet32_get_regs_len(struct net_device *dev);
|
| 325 |
|
|
static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
| 326 |
|
|
void *ptr);
|
| 327 |
|
|
static void pcnet32_purge_tx_ring(struct net_device *dev);
|
| 328 |
|
|
static int pcnet32_alloc_ring(struct net_device *dev, char *name);
|
| 329 |
|
|
static void pcnet32_free_ring(struct net_device *dev);
|
| 330 |
|
|
static void pcnet32_check_media(struct net_device *dev, int verbose);
|
| 331 |
|
|
|
| 332 |
|
|
static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
|
| 333 |
|
|
{
|
| 334 |
|
|
outw(index, addr + PCNET32_WIO_RAP);
|
| 335 |
|
|
return inw(addr + PCNET32_WIO_RDP);
|
| 336 |
|
|
}
|
| 337 |
|
|
|
| 338 |
|
|
static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
|
| 339 |
|
|
{
|
| 340 |
|
|
outw(index, addr + PCNET32_WIO_RAP);
|
| 341 |
|
|
outw(val, addr + PCNET32_WIO_RDP);
|
| 342 |
|
|
}
|
| 343 |
|
|
|
| 344 |
|
|
static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
|
| 345 |
|
|
{
|
| 346 |
|
|
outw(index, addr + PCNET32_WIO_RAP);
|
| 347 |
|
|
return inw(addr + PCNET32_WIO_BDP);
|
| 348 |
|
|
}
|
| 349 |
|
|
|
| 350 |
|
|
static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
|
| 351 |
|
|
{
|
| 352 |
|
|
outw(index, addr + PCNET32_WIO_RAP);
|
| 353 |
|
|
outw(val, addr + PCNET32_WIO_BDP);
|
| 354 |
|
|
}
|
| 355 |
|
|
|
| 356 |
|
|
static u16 pcnet32_wio_read_rap(unsigned long addr)
|
| 357 |
|
|
{
|
| 358 |
|
|
return inw(addr + PCNET32_WIO_RAP);
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
|
| 362 |
|
|
{
|
| 363 |
|
|
outw(val, addr + PCNET32_WIO_RAP);
|
| 364 |
|
|
}
|
| 365 |
|
|
|
| 366 |
|
|
static void pcnet32_wio_reset(unsigned long addr)
|
| 367 |
|
|
{
|
| 368 |
|
|
inw(addr + PCNET32_WIO_RESET);
|
| 369 |
|
|
}
|
| 370 |
|
|
|
| 371 |
|
|
static int pcnet32_wio_check(unsigned long addr)
|
| 372 |
|
|
{
|
| 373 |
|
|
outw(88, addr + PCNET32_WIO_RAP);
|
| 374 |
|
|
return (inw(addr + PCNET32_WIO_RAP) == 88);
|
| 375 |
|
|
}
|
| 376 |
|
|
|
| 377 |
|
|
static struct pcnet32_access pcnet32_wio = {
|
| 378 |
|
|
.read_csr = pcnet32_wio_read_csr,
|
| 379 |
|
|
.write_csr = pcnet32_wio_write_csr,
|
| 380 |
|
|
.read_bcr = pcnet32_wio_read_bcr,
|
| 381 |
|
|
.write_bcr = pcnet32_wio_write_bcr,
|
| 382 |
|
|
.read_rap = pcnet32_wio_read_rap,
|
| 383 |
|
|
.write_rap = pcnet32_wio_write_rap,
|
| 384 |
|
|
.reset = pcnet32_wio_reset
|
| 385 |
|
|
};
|
| 386 |
|
|
|
| 387 |
|
|
static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
|
| 388 |
|
|
{
|
| 389 |
|
|
outl(index, addr + PCNET32_DWIO_RAP);
|
| 390 |
|
|
return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
|
| 391 |
|
|
}
|
| 392 |
|
|
|
| 393 |
|
|
static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
|
| 394 |
|
|
{
|
| 395 |
|
|
outl(index, addr + PCNET32_DWIO_RAP);
|
| 396 |
|
|
outl(val, addr + PCNET32_DWIO_RDP);
|
| 397 |
|
|
}
|
| 398 |
|
|
|
| 399 |
|
|
static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
|
| 400 |
|
|
{
|
| 401 |
|
|
outl(index, addr + PCNET32_DWIO_RAP);
|
| 402 |
|
|
return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
|
| 403 |
|
|
}
|
| 404 |
|
|
|
| 405 |
|
|
static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
|
| 406 |
|
|
{
|
| 407 |
|
|
outl(index, addr + PCNET32_DWIO_RAP);
|
| 408 |
|
|
outl(val, addr + PCNET32_DWIO_BDP);
|
| 409 |
|
|
}
|
| 410 |
|
|
|
| 411 |
|
|
static u16 pcnet32_dwio_read_rap(unsigned long addr)
|
| 412 |
|
|
{
|
| 413 |
|
|
return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
|
| 414 |
|
|
}
|
| 415 |
|
|
|
| 416 |
|
|
static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
|
| 417 |
|
|
{
|
| 418 |
|
|
outl(val, addr + PCNET32_DWIO_RAP);
|
| 419 |
|
|
}
|
| 420 |
|
|
|
| 421 |
|
|
static void pcnet32_dwio_reset(unsigned long addr)
|
| 422 |
|
|
{
|
| 423 |
|
|
inl(addr + PCNET32_DWIO_RESET);
|
| 424 |
|
|
}
|
| 425 |
|
|
|
| 426 |
|
|
static int pcnet32_dwio_check(unsigned long addr)
|
| 427 |
|
|
{
|
| 428 |
|
|
outl(88, addr + PCNET32_DWIO_RAP);
|
| 429 |
|
|
return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
|
| 430 |
|
|
}
|
| 431 |
|
|
|
| 432 |
|
|
static struct pcnet32_access pcnet32_dwio = {
|
| 433 |
|
|
.read_csr = pcnet32_dwio_read_csr,
|
| 434 |
|
|
.write_csr = pcnet32_dwio_write_csr,
|
| 435 |
|
|
.read_bcr = pcnet32_dwio_read_bcr,
|
| 436 |
|
|
.write_bcr = pcnet32_dwio_write_bcr,
|
| 437 |
|
|
.read_rap = pcnet32_dwio_read_rap,
|
| 438 |
|
|
.write_rap = pcnet32_dwio_write_rap,
|
| 439 |
|
|
.reset = pcnet32_dwio_reset
|
| 440 |
|
|
};
|
| 441 |
|
|
|
| 442 |
|
|
static void pcnet32_netif_stop(struct net_device *dev)
|
| 443 |
|
|
{
|
| 444 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 445 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 446 |
|
|
#endif
|
| 447 |
|
|
dev->trans_start = jiffies;
|
| 448 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 449 |
|
|
napi_disable(&lp->napi);
|
| 450 |
|
|
#endif
|
| 451 |
|
|
netif_tx_disable(dev);
|
| 452 |
|
|
}
|
| 453 |
|
|
|
| 454 |
|
|
static void pcnet32_netif_start(struct net_device *dev)
|
| 455 |
|
|
{
|
| 456 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 457 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 458 |
|
|
ulong ioaddr = dev->base_addr;
|
| 459 |
|
|
u16 val;
|
| 460 |
|
|
#endif
|
| 461 |
|
|
netif_wake_queue(dev);
|
| 462 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 463 |
|
|
val = lp->a.read_csr(ioaddr, CSR3);
|
| 464 |
|
|
val &= 0x00ff;
|
| 465 |
|
|
lp->a.write_csr(ioaddr, CSR3, val);
|
| 466 |
|
|
napi_enable(&lp->napi);
|
| 467 |
|
|
#endif
|
| 468 |
|
|
}
|
| 469 |
|
|
|
| 470 |
|
|
/*
|
| 471 |
|
|
* Allocate space for the new sized tx ring.
|
| 472 |
|
|
* Free old resources
|
| 473 |
|
|
* Save new resources.
|
| 474 |
|
|
* Any failure keeps old resources.
|
| 475 |
|
|
* Must be called with lp->lock held.
|
| 476 |
|
|
*/
|
| 477 |
|
|
static void pcnet32_realloc_tx_ring(struct net_device *dev,
|
| 478 |
|
|
struct pcnet32_private *lp,
|
| 479 |
|
|
unsigned int size)
|
| 480 |
|
|
{
|
| 481 |
|
|
dma_addr_t new_ring_dma_addr;
|
| 482 |
|
|
dma_addr_t *new_dma_addr_list;
|
| 483 |
|
|
struct pcnet32_tx_head *new_tx_ring;
|
| 484 |
|
|
struct sk_buff **new_skb_list;
|
| 485 |
|
|
|
| 486 |
|
|
pcnet32_purge_tx_ring(dev);
|
| 487 |
|
|
|
| 488 |
|
|
new_tx_ring = pci_alloc_consistent(lp->pci_dev,
|
| 489 |
|
|
sizeof(struct pcnet32_tx_head) *
|
| 490 |
|
|
(1 << size),
|
| 491 |
|
|
&new_ring_dma_addr);
|
| 492 |
|
|
if (new_tx_ring == NULL) {
|
| 493 |
|
|
if (netif_msg_drv(lp))
|
| 494 |
|
|
printk("\n" KERN_ERR
|
| 495 |
|
|
"%s: Consistent memory allocation failed.\n",
|
| 496 |
|
|
dev->name);
|
| 497 |
|
|
return;
|
| 498 |
|
|
}
|
| 499 |
|
|
memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
|
| 500 |
|
|
|
| 501 |
|
|
new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
|
| 502 |
|
|
GFP_ATOMIC);
|
| 503 |
|
|
if (!new_dma_addr_list) {
|
| 504 |
|
|
if (netif_msg_drv(lp))
|
| 505 |
|
|
printk("\n" KERN_ERR
|
| 506 |
|
|
"%s: Memory allocation failed.\n", dev->name);
|
| 507 |
|
|
goto free_new_tx_ring;
|
| 508 |
|
|
}
|
| 509 |
|
|
|
| 510 |
|
|
new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
|
| 511 |
|
|
GFP_ATOMIC);
|
| 512 |
|
|
if (!new_skb_list) {
|
| 513 |
|
|
if (netif_msg_drv(lp))
|
| 514 |
|
|
printk("\n" KERN_ERR
|
| 515 |
|
|
"%s: Memory allocation failed.\n", dev->name);
|
| 516 |
|
|
goto free_new_lists;
|
| 517 |
|
|
}
|
| 518 |
|
|
|
| 519 |
|
|
kfree(lp->tx_skbuff);
|
| 520 |
|
|
kfree(lp->tx_dma_addr);
|
| 521 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 522 |
|
|
sizeof(struct pcnet32_tx_head) *
|
| 523 |
|
|
lp->tx_ring_size, lp->tx_ring,
|
| 524 |
|
|
lp->tx_ring_dma_addr);
|
| 525 |
|
|
|
| 526 |
|
|
lp->tx_ring_size = (1 << size);
|
| 527 |
|
|
lp->tx_mod_mask = lp->tx_ring_size - 1;
|
| 528 |
|
|
lp->tx_len_bits = (size << 12);
|
| 529 |
|
|
lp->tx_ring = new_tx_ring;
|
| 530 |
|
|
lp->tx_ring_dma_addr = new_ring_dma_addr;
|
| 531 |
|
|
lp->tx_dma_addr = new_dma_addr_list;
|
| 532 |
|
|
lp->tx_skbuff = new_skb_list;
|
| 533 |
|
|
return;
|
| 534 |
|
|
|
| 535 |
|
|
free_new_lists:
|
| 536 |
|
|
kfree(new_dma_addr_list);
|
| 537 |
|
|
free_new_tx_ring:
|
| 538 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 539 |
|
|
sizeof(struct pcnet32_tx_head) *
|
| 540 |
|
|
(1 << size),
|
| 541 |
|
|
new_tx_ring,
|
| 542 |
|
|
new_ring_dma_addr);
|
| 543 |
|
|
return;
|
| 544 |
|
|
}
|
| 545 |
|
|
|
| 546 |
|
|
/*
|
| 547 |
|
|
* Allocate space for the new sized rx ring.
|
| 548 |
|
|
* Re-use old receive buffers.
|
| 549 |
|
|
* alloc extra buffers
|
| 550 |
|
|
* free unneeded buffers
|
| 551 |
|
|
* free unneeded buffers
|
| 552 |
|
|
* Save new resources.
|
| 553 |
|
|
* Any failure keeps old resources.
|
| 554 |
|
|
* Must be called with lp->lock held.
|
| 555 |
|
|
*/
|
| 556 |
|
|
static void pcnet32_realloc_rx_ring(struct net_device *dev,
|
| 557 |
|
|
struct pcnet32_private *lp,
|
| 558 |
|
|
unsigned int size)
|
| 559 |
|
|
{
|
| 560 |
|
|
dma_addr_t new_ring_dma_addr;
|
| 561 |
|
|
dma_addr_t *new_dma_addr_list;
|
| 562 |
|
|
struct pcnet32_rx_head *new_rx_ring;
|
| 563 |
|
|
struct sk_buff **new_skb_list;
|
| 564 |
|
|
int new, overlap;
|
| 565 |
|
|
|
| 566 |
|
|
new_rx_ring = pci_alloc_consistent(lp->pci_dev,
|
| 567 |
|
|
sizeof(struct pcnet32_rx_head) *
|
| 568 |
|
|
(1 << size),
|
| 569 |
|
|
&new_ring_dma_addr);
|
| 570 |
|
|
if (new_rx_ring == NULL) {
|
| 571 |
|
|
if (netif_msg_drv(lp))
|
| 572 |
|
|
printk("\n" KERN_ERR
|
| 573 |
|
|
"%s: Consistent memory allocation failed.\n",
|
| 574 |
|
|
dev->name);
|
| 575 |
|
|
return;
|
| 576 |
|
|
}
|
| 577 |
|
|
memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
|
| 578 |
|
|
|
| 579 |
|
|
new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
|
| 580 |
|
|
GFP_ATOMIC);
|
| 581 |
|
|
if (!new_dma_addr_list) {
|
| 582 |
|
|
if (netif_msg_drv(lp))
|
| 583 |
|
|
printk("\n" KERN_ERR
|
| 584 |
|
|
"%s: Memory allocation failed.\n", dev->name);
|
| 585 |
|
|
goto free_new_rx_ring;
|
| 586 |
|
|
}
|
| 587 |
|
|
|
| 588 |
|
|
new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
|
| 589 |
|
|
GFP_ATOMIC);
|
| 590 |
|
|
if (!new_skb_list) {
|
| 591 |
|
|
if (netif_msg_drv(lp))
|
| 592 |
|
|
printk("\n" KERN_ERR
|
| 593 |
|
|
"%s: Memory allocation failed.\n", dev->name);
|
| 594 |
|
|
goto free_new_lists;
|
| 595 |
|
|
}
|
| 596 |
|
|
|
| 597 |
|
|
/* first copy the current receive buffers */
|
| 598 |
|
|
overlap = min(size, lp->rx_ring_size);
|
| 599 |
|
|
for (new = 0; new < overlap; new++) {
|
| 600 |
|
|
new_rx_ring[new] = lp->rx_ring[new];
|
| 601 |
|
|
new_dma_addr_list[new] = lp->rx_dma_addr[new];
|
| 602 |
|
|
new_skb_list[new] = lp->rx_skbuff[new];
|
| 603 |
|
|
}
|
| 604 |
|
|
/* now allocate any new buffers needed */
|
| 605 |
|
|
for (; new < size; new++ ) {
|
| 606 |
|
|
struct sk_buff *rx_skbuff;
|
| 607 |
|
|
new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
|
| 608 |
|
|
if (!(rx_skbuff = new_skb_list[new])) {
|
| 609 |
|
|
/* keep the original lists and buffers */
|
| 610 |
|
|
if (netif_msg_drv(lp))
|
| 611 |
|
|
printk(KERN_ERR
|
| 612 |
|
|
"%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
|
| 613 |
|
|
dev->name);
|
| 614 |
|
|
goto free_all_new;
|
| 615 |
|
|
}
|
| 616 |
|
|
skb_reserve(rx_skbuff, 2);
|
| 617 |
|
|
|
| 618 |
|
|
new_dma_addr_list[new] =
|
| 619 |
|
|
pci_map_single(lp->pci_dev, rx_skbuff->data,
|
| 620 |
|
|
PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
|
| 621 |
|
|
new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
|
| 622 |
|
|
new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
|
| 623 |
|
|
new_rx_ring[new].status = cpu_to_le16(0x8000);
|
| 624 |
|
|
}
|
| 625 |
|
|
/* and free any unneeded buffers */
|
| 626 |
|
|
for (; new < lp->rx_ring_size; new++) {
|
| 627 |
|
|
if (lp->rx_skbuff[new]) {
|
| 628 |
|
|
pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
|
| 629 |
|
|
PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
|
| 630 |
|
|
dev_kfree_skb(lp->rx_skbuff[new]);
|
| 631 |
|
|
}
|
| 632 |
|
|
}
|
| 633 |
|
|
|
| 634 |
|
|
kfree(lp->rx_skbuff);
|
| 635 |
|
|
kfree(lp->rx_dma_addr);
|
| 636 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 637 |
|
|
sizeof(struct pcnet32_rx_head) *
|
| 638 |
|
|
lp->rx_ring_size, lp->rx_ring,
|
| 639 |
|
|
lp->rx_ring_dma_addr);
|
| 640 |
|
|
|
| 641 |
|
|
lp->rx_ring_size = (1 << size);
|
| 642 |
|
|
lp->rx_mod_mask = lp->rx_ring_size - 1;
|
| 643 |
|
|
lp->rx_len_bits = (size << 4);
|
| 644 |
|
|
lp->rx_ring = new_rx_ring;
|
| 645 |
|
|
lp->rx_ring_dma_addr = new_ring_dma_addr;
|
| 646 |
|
|
lp->rx_dma_addr = new_dma_addr_list;
|
| 647 |
|
|
lp->rx_skbuff = new_skb_list;
|
| 648 |
|
|
return;
|
| 649 |
|
|
|
| 650 |
|
|
free_all_new:
|
| 651 |
|
|
for (; --new >= lp->rx_ring_size; ) {
|
| 652 |
|
|
if (new_skb_list[new]) {
|
| 653 |
|
|
pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
|
| 654 |
|
|
PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
|
| 655 |
|
|
dev_kfree_skb(new_skb_list[new]);
|
| 656 |
|
|
}
|
| 657 |
|
|
}
|
| 658 |
|
|
kfree(new_skb_list);
|
| 659 |
|
|
free_new_lists:
|
| 660 |
|
|
kfree(new_dma_addr_list);
|
| 661 |
|
|
free_new_rx_ring:
|
| 662 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 663 |
|
|
sizeof(struct pcnet32_rx_head) *
|
| 664 |
|
|
(1 << size),
|
| 665 |
|
|
new_rx_ring,
|
| 666 |
|
|
new_ring_dma_addr);
|
| 667 |
|
|
return;
|
| 668 |
|
|
}
|
| 669 |
|
|
|
| 670 |
|
|
static void pcnet32_purge_rx_ring(struct net_device *dev)
|
| 671 |
|
|
{
|
| 672 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 673 |
|
|
int i;
|
| 674 |
|
|
|
| 675 |
|
|
/* free all allocated skbuffs */
|
| 676 |
|
|
for (i = 0; i < lp->rx_ring_size; i++) {
|
| 677 |
|
|
lp->rx_ring[i].status = 0; /* CPU owns buffer */
|
| 678 |
|
|
wmb(); /* Make sure adapter sees owner change */
|
| 679 |
|
|
if (lp->rx_skbuff[i]) {
|
| 680 |
|
|
pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
|
| 681 |
|
|
PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
|
| 682 |
|
|
dev_kfree_skb_any(lp->rx_skbuff[i]);
|
| 683 |
|
|
}
|
| 684 |
|
|
lp->rx_skbuff[i] = NULL;
|
| 685 |
|
|
lp->rx_dma_addr[i] = 0;
|
| 686 |
|
|
}
|
| 687 |
|
|
}
|
| 688 |
|
|
|
| 689 |
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
| 690 |
|
|
static void pcnet32_poll_controller(struct net_device *dev)
|
| 691 |
|
|
{
|
| 692 |
|
|
disable_irq(dev->irq);
|
| 693 |
|
|
pcnet32_interrupt(0, dev);
|
| 694 |
|
|
enable_irq(dev->irq);
|
| 695 |
|
|
}
|
| 696 |
|
|
#endif
|
| 697 |
|
|
|
| 698 |
|
|
static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
| 699 |
|
|
{
|
| 700 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 701 |
|
|
unsigned long flags;
|
| 702 |
|
|
int r = -EOPNOTSUPP;
|
| 703 |
|
|
|
| 704 |
|
|
if (lp->mii) {
|
| 705 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 706 |
|
|
mii_ethtool_gset(&lp->mii_if, cmd);
|
| 707 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 708 |
|
|
r = 0;
|
| 709 |
|
|
}
|
| 710 |
|
|
return r;
|
| 711 |
|
|
}
|
| 712 |
|
|
|
| 713 |
|
|
static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
| 714 |
|
|
{
|
| 715 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 716 |
|
|
unsigned long flags;
|
| 717 |
|
|
int r = -EOPNOTSUPP;
|
| 718 |
|
|
|
| 719 |
|
|
if (lp->mii) {
|
| 720 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 721 |
|
|
r = mii_ethtool_sset(&lp->mii_if, cmd);
|
| 722 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 723 |
|
|
}
|
| 724 |
|
|
return r;
|
| 725 |
|
|
}
|
| 726 |
|
|
|
| 727 |
|
|
static void pcnet32_get_drvinfo(struct net_device *dev,
|
| 728 |
|
|
struct ethtool_drvinfo *info)
|
| 729 |
|
|
{
|
| 730 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 731 |
|
|
|
| 732 |
|
|
strcpy(info->driver, DRV_NAME);
|
| 733 |
|
|
strcpy(info->version, DRV_VERSION);
|
| 734 |
|
|
if (lp->pci_dev)
|
| 735 |
|
|
strcpy(info->bus_info, pci_name(lp->pci_dev));
|
| 736 |
|
|
else
|
| 737 |
|
|
sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
|
| 738 |
|
|
}
|
| 739 |
|
|
|
| 740 |
|
|
static u32 pcnet32_get_link(struct net_device *dev)
|
| 741 |
|
|
{
|
| 742 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 743 |
|
|
unsigned long flags;
|
| 744 |
|
|
int r;
|
| 745 |
|
|
|
| 746 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 747 |
|
|
if (lp->mii) {
|
| 748 |
|
|
r = mii_link_ok(&lp->mii_if);
|
| 749 |
|
|
} else if (lp->chip_version >= PCNET32_79C970A) {
|
| 750 |
|
|
ulong ioaddr = dev->base_addr; /* card base I/O address */
|
| 751 |
|
|
r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
|
| 752 |
|
|
} else { /* can not detect link on really old chips */
|
| 753 |
|
|
r = 1;
|
| 754 |
|
|
}
|
| 755 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 756 |
|
|
|
| 757 |
|
|
return r;
|
| 758 |
|
|
}
|
| 759 |
|
|
|
| 760 |
|
|
static u32 pcnet32_get_msglevel(struct net_device *dev)
|
| 761 |
|
|
{
|
| 762 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 763 |
|
|
return lp->msg_enable;
|
| 764 |
|
|
}
|
| 765 |
|
|
|
| 766 |
|
|
static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
|
| 767 |
|
|
{
|
| 768 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 769 |
|
|
lp->msg_enable = value;
|
| 770 |
|
|
}
|
| 771 |
|
|
|
| 772 |
|
|
static int pcnet32_nway_reset(struct net_device *dev)
|
| 773 |
|
|
{
|
| 774 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 775 |
|
|
unsigned long flags;
|
| 776 |
|
|
int r = -EOPNOTSUPP;
|
| 777 |
|
|
|
| 778 |
|
|
if (lp->mii) {
|
| 779 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 780 |
|
|
r = mii_nway_restart(&lp->mii_if);
|
| 781 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 782 |
|
|
}
|
| 783 |
|
|
return r;
|
| 784 |
|
|
}
|
| 785 |
|
|
|
| 786 |
|
|
static void pcnet32_get_ringparam(struct net_device *dev,
|
| 787 |
|
|
struct ethtool_ringparam *ering)
|
| 788 |
|
|
{
|
| 789 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 790 |
|
|
|
| 791 |
|
|
ering->tx_max_pending = TX_MAX_RING_SIZE;
|
| 792 |
|
|
ering->tx_pending = lp->tx_ring_size;
|
| 793 |
|
|
ering->rx_max_pending = RX_MAX_RING_SIZE;
|
| 794 |
|
|
ering->rx_pending = lp->rx_ring_size;
|
| 795 |
|
|
}
|
| 796 |
|
|
|
| 797 |
|
|
static int pcnet32_set_ringparam(struct net_device *dev,
|
| 798 |
|
|
struct ethtool_ringparam *ering)
|
| 799 |
|
|
{
|
| 800 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 801 |
|
|
unsigned long flags;
|
| 802 |
|
|
unsigned int size;
|
| 803 |
|
|
ulong ioaddr = dev->base_addr;
|
| 804 |
|
|
int i;
|
| 805 |
|
|
|
| 806 |
|
|
if (ering->rx_mini_pending || ering->rx_jumbo_pending)
|
| 807 |
|
|
return -EINVAL;
|
| 808 |
|
|
|
| 809 |
|
|
if (netif_running(dev))
|
| 810 |
|
|
pcnet32_netif_stop(dev);
|
| 811 |
|
|
|
| 812 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 813 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
|
| 814 |
|
|
|
| 815 |
|
|
size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
|
| 816 |
|
|
|
| 817 |
|
|
/* set the minimum ring size to 4, to allow the loopback test to work
|
| 818 |
|
|
* unchanged.
|
| 819 |
|
|
*/
|
| 820 |
|
|
for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
|
| 821 |
|
|
if (size <= (1 << i))
|
| 822 |
|
|
break;
|
| 823 |
|
|
}
|
| 824 |
|
|
if ((1 << i) != lp->tx_ring_size)
|
| 825 |
|
|
pcnet32_realloc_tx_ring(dev, lp, i);
|
| 826 |
|
|
|
| 827 |
|
|
size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
|
| 828 |
|
|
for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
|
| 829 |
|
|
if (size <= (1 << i))
|
| 830 |
|
|
break;
|
| 831 |
|
|
}
|
| 832 |
|
|
if ((1 << i) != lp->rx_ring_size)
|
| 833 |
|
|
pcnet32_realloc_rx_ring(dev, lp, i);
|
| 834 |
|
|
|
| 835 |
|
|
lp->napi.weight = lp->rx_ring_size / 2;
|
| 836 |
|
|
|
| 837 |
|
|
if (netif_running(dev)) {
|
| 838 |
|
|
pcnet32_netif_start(dev);
|
| 839 |
|
|
pcnet32_restart(dev, CSR0_NORMAL);
|
| 840 |
|
|
}
|
| 841 |
|
|
|
| 842 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 843 |
|
|
|
| 844 |
|
|
if (netif_msg_drv(lp))
|
| 845 |
|
|
printk(KERN_INFO
|
| 846 |
|
|
"%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
|
| 847 |
|
|
lp->rx_ring_size, lp->tx_ring_size);
|
| 848 |
|
|
|
| 849 |
|
|
return 0;
|
| 850 |
|
|
}
|
| 851 |
|
|
|
| 852 |
|
|
static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
|
| 853 |
|
|
u8 * data)
|
| 854 |
|
|
{
|
| 855 |
|
|
memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
|
| 856 |
|
|
}
|
| 857 |
|
|
|
| 858 |
|
|
static int pcnet32_get_sset_count(struct net_device *dev, int sset)
|
| 859 |
|
|
{
|
| 860 |
|
|
switch (sset) {
|
| 861 |
|
|
case ETH_SS_TEST:
|
| 862 |
|
|
return PCNET32_TEST_LEN;
|
| 863 |
|
|
default:
|
| 864 |
|
|
return -EOPNOTSUPP;
|
| 865 |
|
|
}
|
| 866 |
|
|
}
|
| 867 |
|
|
|
| 868 |
|
|
static void pcnet32_ethtool_test(struct net_device *dev,
|
| 869 |
|
|
struct ethtool_test *test, u64 * data)
|
| 870 |
|
|
{
|
| 871 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 872 |
|
|
int rc;
|
| 873 |
|
|
|
| 874 |
|
|
if (test->flags == ETH_TEST_FL_OFFLINE) {
|
| 875 |
|
|
rc = pcnet32_loopback_test(dev, data);
|
| 876 |
|
|
if (rc) {
|
| 877 |
|
|
if (netif_msg_hw(lp))
|
| 878 |
|
|
printk(KERN_DEBUG "%s: Loopback test failed.\n",
|
| 879 |
|
|
dev->name);
|
| 880 |
|
|
test->flags |= ETH_TEST_FL_FAILED;
|
| 881 |
|
|
} else if (netif_msg_hw(lp))
|
| 882 |
|
|
printk(KERN_DEBUG "%s: Loopback test passed.\n",
|
| 883 |
|
|
dev->name);
|
| 884 |
|
|
} else if (netif_msg_hw(lp))
|
| 885 |
|
|
printk(KERN_DEBUG
|
| 886 |
|
|
"%s: No tests to run (specify 'Offline' on ethtool).",
|
| 887 |
|
|
dev->name);
|
| 888 |
|
|
} /* end pcnet32_ethtool_test */
|
| 889 |
|
|
|
| 890 |
|
|
static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
|
| 891 |
|
|
{
|
| 892 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 893 |
|
|
struct pcnet32_access *a = &lp->a; /* access to registers */
|
| 894 |
|
|
ulong ioaddr = dev->base_addr; /* card base I/O address */
|
| 895 |
|
|
struct sk_buff *skb; /* sk buff */
|
| 896 |
|
|
int x, i; /* counters */
|
| 897 |
|
|
int numbuffs = 4; /* number of TX/RX buffers and descs */
|
| 898 |
|
|
u16 status = 0x8300; /* TX ring status */
|
| 899 |
|
|
__le16 teststatus; /* test of ring status */
|
| 900 |
|
|
int rc; /* return code */
|
| 901 |
|
|
int size; /* size of packets */
|
| 902 |
|
|
unsigned char *packet; /* source packet data */
|
| 903 |
|
|
static const int data_len = 60; /* length of source packets */
|
| 904 |
|
|
unsigned long flags;
|
| 905 |
|
|
unsigned long ticks;
|
| 906 |
|
|
|
| 907 |
|
|
rc = 1; /* default to fail */
|
| 908 |
|
|
|
| 909 |
|
|
if (netif_running(dev))
|
| 910 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 911 |
|
|
pcnet32_netif_stop(dev);
|
| 912 |
|
|
#else
|
| 913 |
|
|
pcnet32_close(dev);
|
| 914 |
|
|
#endif
|
| 915 |
|
|
|
| 916 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 917 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
|
| 918 |
|
|
|
| 919 |
|
|
numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
|
| 920 |
|
|
|
| 921 |
|
|
/* Reset the PCNET32 */
|
| 922 |
|
|
lp->a.reset(ioaddr);
|
| 923 |
|
|
lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
|
| 924 |
|
|
|
| 925 |
|
|
/* switch pcnet32 to 32bit mode */
|
| 926 |
|
|
lp->a.write_bcr(ioaddr, 20, 2);
|
| 927 |
|
|
|
| 928 |
|
|
/* purge & init rings but don't actually restart */
|
| 929 |
|
|
pcnet32_restart(dev, 0x0000);
|
| 930 |
|
|
|
| 931 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
|
| 932 |
|
|
|
| 933 |
|
|
/* Initialize Transmit buffers. */
|
| 934 |
|
|
size = data_len + 15;
|
| 935 |
|
|
for (x = 0; x < numbuffs; x++) {
|
| 936 |
|
|
if (!(skb = dev_alloc_skb(size))) {
|
| 937 |
|
|
if (netif_msg_hw(lp))
|
| 938 |
|
|
printk(KERN_DEBUG
|
| 939 |
|
|
"%s: Cannot allocate skb at line: %d!\n",
|
| 940 |
|
|
dev->name, __LINE__);
|
| 941 |
|
|
goto clean_up;
|
| 942 |
|
|
} else {
|
| 943 |
|
|
packet = skb->data;
|
| 944 |
|
|
skb_put(skb, size); /* create space for data */
|
| 945 |
|
|
lp->tx_skbuff[x] = skb;
|
| 946 |
|
|
lp->tx_ring[x].length = cpu_to_le16(-skb->len);
|
| 947 |
|
|
lp->tx_ring[x].misc = 0;
|
| 948 |
|
|
|
| 949 |
|
|
/* put DA and SA into the skb */
|
| 950 |
|
|
for (i = 0; i < 6; i++)
|
| 951 |
|
|
*packet++ = dev->dev_addr[i];
|
| 952 |
|
|
for (i = 0; i < 6; i++)
|
| 953 |
|
|
*packet++ = dev->dev_addr[i];
|
| 954 |
|
|
/* type */
|
| 955 |
|
|
*packet++ = 0x08;
|
| 956 |
|
|
*packet++ = 0x06;
|
| 957 |
|
|
/* packet number */
|
| 958 |
|
|
*packet++ = x;
|
| 959 |
|
|
/* fill packet with data */
|
| 960 |
|
|
for (i = 0; i < data_len; i++)
|
| 961 |
|
|
*packet++ = i;
|
| 962 |
|
|
|
| 963 |
|
|
lp->tx_dma_addr[x] =
|
| 964 |
|
|
pci_map_single(lp->pci_dev, skb->data, skb->len,
|
| 965 |
|
|
PCI_DMA_TODEVICE);
|
| 966 |
|
|
lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
|
| 967 |
|
|
wmb(); /* Make sure owner changes after all others are visible */
|
| 968 |
|
|
lp->tx_ring[x].status = cpu_to_le16(status);
|
| 969 |
|
|
}
|
| 970 |
|
|
}
|
| 971 |
|
|
|
| 972 |
|
|
x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
|
| 973 |
|
|
a->write_bcr(ioaddr, 32, x | 0x0002);
|
| 974 |
|
|
|
| 975 |
|
|
/* set int loopback in CSR15 */
|
| 976 |
|
|
x = a->read_csr(ioaddr, CSR15) & 0xfffc;
|
| 977 |
|
|
lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
|
| 978 |
|
|
|
| 979 |
|
|
teststatus = cpu_to_le16(0x8000);
|
| 980 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
|
| 981 |
|
|
|
| 982 |
|
|
/* Check status of descriptors */
|
| 983 |
|
|
for (x = 0; x < numbuffs; x++) {
|
| 984 |
|
|
ticks = 0;
|
| 985 |
|
|
rmb();
|
| 986 |
|
|
while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
|
| 987 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 988 |
|
|
msleep(1);
|
| 989 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 990 |
|
|
rmb();
|
| 991 |
|
|
ticks++;
|
| 992 |
|
|
}
|
| 993 |
|
|
if (ticks == 200) {
|
| 994 |
|
|
if (netif_msg_hw(lp))
|
| 995 |
|
|
printk("%s: Desc %d failed to reset!\n",
|
| 996 |
|
|
dev->name, x);
|
| 997 |
|
|
break;
|
| 998 |
|
|
}
|
| 999 |
|
|
}
|
| 1000 |
|
|
|
| 1001 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
|
| 1002 |
|
|
wmb();
|
| 1003 |
|
|
if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
|
| 1004 |
|
|
printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
|
| 1005 |
|
|
|
| 1006 |
|
|
for (x = 0; x < numbuffs; x++) {
|
| 1007 |
|
|
printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
|
| 1008 |
|
|
skb = lp->rx_skbuff[x];
|
| 1009 |
|
|
for (i = 0; i < size; i++) {
|
| 1010 |
|
|
printk("%02x ", *(skb->data + i));
|
| 1011 |
|
|
}
|
| 1012 |
|
|
printk("\n");
|
| 1013 |
|
|
}
|
| 1014 |
|
|
}
|
| 1015 |
|
|
|
| 1016 |
|
|
x = 0;
|
| 1017 |
|
|
rc = 0;
|
| 1018 |
|
|
while (x < numbuffs && !rc) {
|
| 1019 |
|
|
skb = lp->rx_skbuff[x];
|
| 1020 |
|
|
packet = lp->tx_skbuff[x]->data;
|
| 1021 |
|
|
for (i = 0; i < size; i++) {
|
| 1022 |
|
|
if (*(skb->data + i) != packet[i]) {
|
| 1023 |
|
|
if (netif_msg_hw(lp))
|
| 1024 |
|
|
printk(KERN_DEBUG
|
| 1025 |
|
|
"%s: Error in compare! %2x - %02x %02x\n",
|
| 1026 |
|
|
dev->name, i, *(skb->data + i),
|
| 1027 |
|
|
packet[i]);
|
| 1028 |
|
|
rc = 1;
|
| 1029 |
|
|
break;
|
| 1030 |
|
|
}
|
| 1031 |
|
|
}
|
| 1032 |
|
|
x++;
|
| 1033 |
|
|
}
|
| 1034 |
|
|
|
| 1035 |
|
|
clean_up:
|
| 1036 |
|
|
*data1 = rc;
|
| 1037 |
|
|
pcnet32_purge_tx_ring(dev);
|
| 1038 |
|
|
|
| 1039 |
|
|
x = a->read_csr(ioaddr, CSR15);
|
| 1040 |
|
|
a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
|
| 1041 |
|
|
|
| 1042 |
|
|
x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
|
| 1043 |
|
|
a->write_bcr(ioaddr, 32, (x & ~0x0002));
|
| 1044 |
|
|
|
| 1045 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 1046 |
|
|
if (netif_running(dev)) {
|
| 1047 |
|
|
pcnet32_netif_start(dev);
|
| 1048 |
|
|
pcnet32_restart(dev, CSR0_NORMAL);
|
| 1049 |
|
|
} else {
|
| 1050 |
|
|
pcnet32_purge_rx_ring(dev);
|
| 1051 |
|
|
lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
|
| 1052 |
|
|
}
|
| 1053 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1054 |
|
|
#else
|
| 1055 |
|
|
if (netif_running(dev)) {
|
| 1056 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1057 |
|
|
pcnet32_open(dev);
|
| 1058 |
|
|
} else {
|
| 1059 |
|
|
pcnet32_purge_rx_ring(dev);
|
| 1060 |
|
|
lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
|
| 1061 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1062 |
|
|
}
|
| 1063 |
|
|
#endif
|
| 1064 |
|
|
|
| 1065 |
|
|
return (rc);
|
| 1066 |
|
|
} /* end pcnet32_loopback_test */
|
| 1067 |
|
|
|
| 1068 |
|
|
static void pcnet32_led_blink_callback(struct net_device *dev)
|
| 1069 |
|
|
{
|
| 1070 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1071 |
|
|
struct pcnet32_access *a = &lp->a;
|
| 1072 |
|
|
ulong ioaddr = dev->base_addr;
|
| 1073 |
|
|
unsigned long flags;
|
| 1074 |
|
|
int i;
|
| 1075 |
|
|
|
| 1076 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1077 |
|
|
for (i = 4; i < 8; i++) {
|
| 1078 |
|
|
a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
|
| 1079 |
|
|
}
|
| 1080 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1081 |
|
|
|
| 1082 |
|
|
mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
|
| 1083 |
|
|
}
|
| 1084 |
|
|
|
| 1085 |
|
|
static int pcnet32_phys_id(struct net_device *dev, u32 data)
|
| 1086 |
|
|
{
|
| 1087 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1088 |
|
|
struct pcnet32_access *a = &lp->a;
|
| 1089 |
|
|
ulong ioaddr = dev->base_addr;
|
| 1090 |
|
|
unsigned long flags;
|
| 1091 |
|
|
int i, regs[4];
|
| 1092 |
|
|
|
| 1093 |
|
|
if (!lp->blink_timer.function) {
|
| 1094 |
|
|
init_timer(&lp->blink_timer);
|
| 1095 |
|
|
lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
|
| 1096 |
|
|
lp->blink_timer.data = (unsigned long)dev;
|
| 1097 |
|
|
}
|
| 1098 |
|
|
|
| 1099 |
|
|
/* Save the current value of the bcrs */
|
| 1100 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1101 |
|
|
for (i = 4; i < 8; i++) {
|
| 1102 |
|
|
regs[i - 4] = a->read_bcr(ioaddr, i);
|
| 1103 |
|
|
}
|
| 1104 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1105 |
|
|
|
| 1106 |
|
|
mod_timer(&lp->blink_timer, jiffies);
|
| 1107 |
|
|
set_current_state(TASK_INTERRUPTIBLE);
|
| 1108 |
|
|
|
| 1109 |
|
|
/* AV: the limit here makes no sense whatsoever */
|
| 1110 |
|
|
if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
|
| 1111 |
|
|
data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
|
| 1112 |
|
|
|
| 1113 |
|
|
msleep_interruptible(data * 1000);
|
| 1114 |
|
|
del_timer_sync(&lp->blink_timer);
|
| 1115 |
|
|
|
| 1116 |
|
|
/* Restore the original value of the bcrs */
|
| 1117 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1118 |
|
|
for (i = 4; i < 8; i++) {
|
| 1119 |
|
|
a->write_bcr(ioaddr, i, regs[i - 4]);
|
| 1120 |
|
|
}
|
| 1121 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1122 |
|
|
|
| 1123 |
|
|
return 0;
|
| 1124 |
|
|
}
|
| 1125 |
|
|
|
| 1126 |
|
|
/*
|
| 1127 |
|
|
* lp->lock must be held.
|
| 1128 |
|
|
*/
|
| 1129 |
|
|
static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
|
| 1130 |
|
|
int can_sleep)
|
| 1131 |
|
|
{
|
| 1132 |
|
|
int csr5;
|
| 1133 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1134 |
|
|
struct pcnet32_access *a = &lp->a;
|
| 1135 |
|
|
ulong ioaddr = dev->base_addr;
|
| 1136 |
|
|
int ticks;
|
| 1137 |
|
|
|
| 1138 |
|
|
/* really old chips have to be stopped. */
|
| 1139 |
|
|
if (lp->chip_version < PCNET32_79C970A)
|
| 1140 |
|
|
return 0;
|
| 1141 |
|
|
|
| 1142 |
|
|
/* set SUSPEND (SPND) - CSR5 bit 0 */
|
| 1143 |
|
|
csr5 = a->read_csr(ioaddr, CSR5);
|
| 1144 |
|
|
a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
|
| 1145 |
|
|
|
| 1146 |
|
|
/* poll waiting for bit to be set */
|
| 1147 |
|
|
ticks = 0;
|
| 1148 |
|
|
while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
|
| 1149 |
|
|
spin_unlock_irqrestore(&lp->lock, *flags);
|
| 1150 |
|
|
if (can_sleep)
|
| 1151 |
|
|
msleep(1);
|
| 1152 |
|
|
else
|
| 1153 |
|
|
mdelay(1);
|
| 1154 |
|
|
spin_lock_irqsave(&lp->lock, *flags);
|
| 1155 |
|
|
ticks++;
|
| 1156 |
|
|
if (ticks > 200) {
|
| 1157 |
|
|
if (netif_msg_hw(lp))
|
| 1158 |
|
|
printk(KERN_DEBUG
|
| 1159 |
|
|
"%s: Error getting into suspend!\n",
|
| 1160 |
|
|
dev->name);
|
| 1161 |
|
|
return 0;
|
| 1162 |
|
|
}
|
| 1163 |
|
|
}
|
| 1164 |
|
|
return 1;
|
| 1165 |
|
|
}
|
| 1166 |
|
|
|
| 1167 |
|
|
/*
|
| 1168 |
|
|
* process one receive descriptor entry
|
| 1169 |
|
|
*/
|
| 1170 |
|
|
|
| 1171 |
|
|
static void pcnet32_rx_entry(struct net_device *dev,
|
| 1172 |
|
|
struct pcnet32_private *lp,
|
| 1173 |
|
|
struct pcnet32_rx_head *rxp,
|
| 1174 |
|
|
int entry)
|
| 1175 |
|
|
{
|
| 1176 |
|
|
int status = (short)le16_to_cpu(rxp->status) >> 8;
|
| 1177 |
|
|
int rx_in_place = 0;
|
| 1178 |
|
|
struct sk_buff *skb;
|
| 1179 |
|
|
short pkt_len;
|
| 1180 |
|
|
|
| 1181 |
|
|
if (status != 0x03) { /* There was an error. */
|
| 1182 |
|
|
/*
|
| 1183 |
|
|
* There is a tricky error noted by John Murphy,
|
| 1184 |
|
|
* <murf@perftech.com> to Russ Nelson: Even with full-sized
|
| 1185 |
|
|
* buffers it's possible for a jabber packet to use two
|
| 1186 |
|
|
* buffers, with only the last correctly noting the error.
|
| 1187 |
|
|
*/
|
| 1188 |
|
|
if (status & 0x01) /* Only count a general error at the */
|
| 1189 |
|
|
dev->stats.rx_errors++; /* end of a packet. */
|
| 1190 |
|
|
if (status & 0x20)
|
| 1191 |
|
|
dev->stats.rx_frame_errors++;
|
| 1192 |
|
|
if (status & 0x10)
|
| 1193 |
|
|
dev->stats.rx_over_errors++;
|
| 1194 |
|
|
if (status & 0x08)
|
| 1195 |
|
|
dev->stats.rx_crc_errors++;
|
| 1196 |
|
|
if (status & 0x04)
|
| 1197 |
|
|
dev->stats.rx_fifo_errors++;
|
| 1198 |
|
|
return;
|
| 1199 |
|
|
}
|
| 1200 |
|
|
|
| 1201 |
|
|
pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
|
| 1202 |
|
|
|
| 1203 |
|
|
/* Discard oversize frames. */
|
| 1204 |
|
|
if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
|
| 1205 |
|
|
if (netif_msg_drv(lp))
|
| 1206 |
|
|
printk(KERN_ERR "%s: Impossible packet size %d!\n",
|
| 1207 |
|
|
dev->name, pkt_len);
|
| 1208 |
|
|
dev->stats.rx_errors++;
|
| 1209 |
|
|
return;
|
| 1210 |
|
|
}
|
| 1211 |
|
|
if (pkt_len < 60) {
|
| 1212 |
|
|
if (netif_msg_rx_err(lp))
|
| 1213 |
|
|
printk(KERN_ERR "%s: Runt packet!\n", dev->name);
|
| 1214 |
|
|
dev->stats.rx_errors++;
|
| 1215 |
|
|
return;
|
| 1216 |
|
|
}
|
| 1217 |
|
|
|
| 1218 |
|
|
if (pkt_len > rx_copybreak) {
|
| 1219 |
|
|
struct sk_buff *newskb;
|
| 1220 |
|
|
|
| 1221 |
|
|
if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
|
| 1222 |
|
|
skb_reserve(newskb, 2);
|
| 1223 |
|
|
skb = lp->rx_skbuff[entry];
|
| 1224 |
|
|
pci_unmap_single(lp->pci_dev,
|
| 1225 |
|
|
lp->rx_dma_addr[entry],
|
| 1226 |
|
|
PKT_BUF_SZ - 2,
|
| 1227 |
|
|
PCI_DMA_FROMDEVICE);
|
| 1228 |
|
|
skb_put(skb, pkt_len);
|
| 1229 |
|
|
lp->rx_skbuff[entry] = newskb;
|
| 1230 |
|
|
lp->rx_dma_addr[entry] =
|
| 1231 |
|
|
pci_map_single(lp->pci_dev,
|
| 1232 |
|
|
newskb->data,
|
| 1233 |
|
|
PKT_BUF_SZ - 2,
|
| 1234 |
|
|
PCI_DMA_FROMDEVICE);
|
| 1235 |
|
|
rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
|
| 1236 |
|
|
rx_in_place = 1;
|
| 1237 |
|
|
} else
|
| 1238 |
|
|
skb = NULL;
|
| 1239 |
|
|
} else {
|
| 1240 |
|
|
skb = dev_alloc_skb(pkt_len + 2);
|
| 1241 |
|
|
}
|
| 1242 |
|
|
|
| 1243 |
|
|
if (skb == NULL) {
|
| 1244 |
|
|
if (netif_msg_drv(lp))
|
| 1245 |
|
|
printk(KERN_ERR
|
| 1246 |
|
|
"%s: Memory squeeze, dropping packet.\n",
|
| 1247 |
|
|
dev->name);
|
| 1248 |
|
|
dev->stats.rx_dropped++;
|
| 1249 |
|
|
return;
|
| 1250 |
|
|
}
|
| 1251 |
|
|
skb->dev = dev;
|
| 1252 |
|
|
if (!rx_in_place) {
|
| 1253 |
|
|
skb_reserve(skb, 2); /* 16 byte align */
|
| 1254 |
|
|
skb_put(skb, pkt_len); /* Make room */
|
| 1255 |
|
|
pci_dma_sync_single_for_cpu(lp->pci_dev,
|
| 1256 |
|
|
lp->rx_dma_addr[entry],
|
| 1257 |
|
|
pkt_len,
|
| 1258 |
|
|
PCI_DMA_FROMDEVICE);
|
| 1259 |
|
|
skb_copy_to_linear_data(skb,
|
| 1260 |
|
|
(unsigned char *)(lp->rx_skbuff[entry]->data),
|
| 1261 |
|
|
pkt_len);
|
| 1262 |
|
|
pci_dma_sync_single_for_device(lp->pci_dev,
|
| 1263 |
|
|
lp->rx_dma_addr[entry],
|
| 1264 |
|
|
pkt_len,
|
| 1265 |
|
|
PCI_DMA_FROMDEVICE);
|
| 1266 |
|
|
}
|
| 1267 |
|
|
dev->stats.rx_bytes += skb->len;
|
| 1268 |
|
|
skb->protocol = eth_type_trans(skb, dev);
|
| 1269 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 1270 |
|
|
netif_receive_skb(skb);
|
| 1271 |
|
|
#else
|
| 1272 |
|
|
netif_rx(skb);
|
| 1273 |
|
|
#endif
|
| 1274 |
|
|
dev->last_rx = jiffies;
|
| 1275 |
|
|
dev->stats.rx_packets++;
|
| 1276 |
|
|
return;
|
| 1277 |
|
|
}
|
| 1278 |
|
|
|
| 1279 |
|
|
static int pcnet32_rx(struct net_device *dev, int budget)
|
| 1280 |
|
|
{
|
| 1281 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1282 |
|
|
int entry = lp->cur_rx & lp->rx_mod_mask;
|
| 1283 |
|
|
struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
|
| 1284 |
|
|
int npackets = 0;
|
| 1285 |
|
|
|
| 1286 |
|
|
/* If we own the next entry, it's a new packet. Send it up. */
|
| 1287 |
|
|
while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
|
| 1288 |
|
|
pcnet32_rx_entry(dev, lp, rxp, entry);
|
| 1289 |
|
|
npackets += 1;
|
| 1290 |
|
|
/*
|
| 1291 |
|
|
* The docs say that the buffer length isn't touched, but Andrew
|
| 1292 |
|
|
* Boyd of QNX reports that some revs of the 79C965 clear it.
|
| 1293 |
|
|
*/
|
| 1294 |
|
|
rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
|
| 1295 |
|
|
wmb(); /* Make sure owner changes after others are visible */
|
| 1296 |
|
|
rxp->status = cpu_to_le16(0x8000);
|
| 1297 |
|
|
entry = (++lp->cur_rx) & lp->rx_mod_mask;
|
| 1298 |
|
|
rxp = &lp->rx_ring[entry];
|
| 1299 |
|
|
}
|
| 1300 |
|
|
|
| 1301 |
|
|
return npackets;
|
| 1302 |
|
|
}
|
| 1303 |
|
|
|
| 1304 |
|
|
static int pcnet32_tx(struct net_device *dev)
|
| 1305 |
|
|
{
|
| 1306 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1307 |
|
|
unsigned int dirty_tx = lp->dirty_tx;
|
| 1308 |
|
|
int delta;
|
| 1309 |
|
|
int must_restart = 0;
|
| 1310 |
|
|
|
| 1311 |
|
|
while (dirty_tx != lp->cur_tx) {
|
| 1312 |
|
|
int entry = dirty_tx & lp->tx_mod_mask;
|
| 1313 |
|
|
int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
|
| 1314 |
|
|
|
| 1315 |
|
|
if (status < 0)
|
| 1316 |
|
|
break; /* It still hasn't been Txed */
|
| 1317 |
|
|
|
| 1318 |
|
|
lp->tx_ring[entry].base = 0;
|
| 1319 |
|
|
|
| 1320 |
|
|
if (status & 0x4000) {
|
| 1321 |
|
|
/* There was a major error, log it. */
|
| 1322 |
|
|
int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
|
| 1323 |
|
|
dev->stats.tx_errors++;
|
| 1324 |
|
|
if (netif_msg_tx_err(lp))
|
| 1325 |
|
|
printk(KERN_ERR
|
| 1326 |
|
|
"%s: Tx error status=%04x err_status=%08x\n",
|
| 1327 |
|
|
dev->name, status,
|
| 1328 |
|
|
err_status);
|
| 1329 |
|
|
if (err_status & 0x04000000)
|
| 1330 |
|
|
dev->stats.tx_aborted_errors++;
|
| 1331 |
|
|
if (err_status & 0x08000000)
|
| 1332 |
|
|
dev->stats.tx_carrier_errors++;
|
| 1333 |
|
|
if (err_status & 0x10000000)
|
| 1334 |
|
|
dev->stats.tx_window_errors++;
|
| 1335 |
|
|
#ifndef DO_DXSUFLO
|
| 1336 |
|
|
if (err_status & 0x40000000) {
|
| 1337 |
|
|
dev->stats.tx_fifo_errors++;
|
| 1338 |
|
|
/* Ackk! On FIFO errors the Tx unit is turned off! */
|
| 1339 |
|
|
/* Remove this verbosity later! */
|
| 1340 |
|
|
if (netif_msg_tx_err(lp))
|
| 1341 |
|
|
printk(KERN_ERR
|
| 1342 |
|
|
"%s: Tx FIFO error!\n",
|
| 1343 |
|
|
dev->name);
|
| 1344 |
|
|
must_restart = 1;
|
| 1345 |
|
|
}
|
| 1346 |
|
|
#else
|
| 1347 |
|
|
if (err_status & 0x40000000) {
|
| 1348 |
|
|
dev->stats.tx_fifo_errors++;
|
| 1349 |
|
|
if (!lp->dxsuflo) { /* If controller doesn't recover ... */
|
| 1350 |
|
|
/* Ackk! On FIFO errors the Tx unit is turned off! */
|
| 1351 |
|
|
/* Remove this verbosity later! */
|
| 1352 |
|
|
if (netif_msg_tx_err(lp))
|
| 1353 |
|
|
printk(KERN_ERR
|
| 1354 |
|
|
"%s: Tx FIFO error!\n",
|
| 1355 |
|
|
dev->name);
|
| 1356 |
|
|
must_restart = 1;
|
| 1357 |
|
|
}
|
| 1358 |
|
|
}
|
| 1359 |
|
|
#endif
|
| 1360 |
|
|
} else {
|
| 1361 |
|
|
if (status & 0x1800)
|
| 1362 |
|
|
dev->stats.collisions++;
|
| 1363 |
|
|
dev->stats.tx_packets++;
|
| 1364 |
|
|
}
|
| 1365 |
|
|
|
| 1366 |
|
|
/* We must free the original skb */
|
| 1367 |
|
|
if (lp->tx_skbuff[entry]) {
|
| 1368 |
|
|
pci_unmap_single(lp->pci_dev,
|
| 1369 |
|
|
lp->tx_dma_addr[entry],
|
| 1370 |
|
|
lp->tx_skbuff[entry]->
|
| 1371 |
|
|
len, PCI_DMA_TODEVICE);
|
| 1372 |
|
|
dev_kfree_skb_any(lp->tx_skbuff[entry]);
|
| 1373 |
|
|
lp->tx_skbuff[entry] = NULL;
|
| 1374 |
|
|
lp->tx_dma_addr[entry] = 0;
|
| 1375 |
|
|
}
|
| 1376 |
|
|
dirty_tx++;
|
| 1377 |
|
|
}
|
| 1378 |
|
|
|
| 1379 |
|
|
delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
|
| 1380 |
|
|
if (delta > lp->tx_ring_size) {
|
| 1381 |
|
|
if (netif_msg_drv(lp))
|
| 1382 |
|
|
printk(KERN_ERR
|
| 1383 |
|
|
"%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
|
| 1384 |
|
|
dev->name, dirty_tx, lp->cur_tx,
|
| 1385 |
|
|
lp->tx_full);
|
| 1386 |
|
|
dirty_tx += lp->tx_ring_size;
|
| 1387 |
|
|
delta -= lp->tx_ring_size;
|
| 1388 |
|
|
}
|
| 1389 |
|
|
|
| 1390 |
|
|
if (lp->tx_full &&
|
| 1391 |
|
|
netif_queue_stopped(dev) &&
|
| 1392 |
|
|
delta < lp->tx_ring_size - 2) {
|
| 1393 |
|
|
/* The ring is no longer full, clear tbusy. */
|
| 1394 |
|
|
lp->tx_full = 0;
|
| 1395 |
|
|
netif_wake_queue(dev);
|
| 1396 |
|
|
}
|
| 1397 |
|
|
lp->dirty_tx = dirty_tx;
|
| 1398 |
|
|
|
| 1399 |
|
|
return must_restart;
|
| 1400 |
|
|
}
|
| 1401 |
|
|
|
| 1402 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 1403 |
|
|
static int pcnet32_poll(struct napi_struct *napi, int budget)
|
| 1404 |
|
|
{
|
| 1405 |
|
|
struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
|
| 1406 |
|
|
struct net_device *dev = lp->dev;
|
| 1407 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 1408 |
|
|
unsigned long flags;
|
| 1409 |
|
|
int work_done;
|
| 1410 |
|
|
u16 val;
|
| 1411 |
|
|
|
| 1412 |
|
|
work_done = pcnet32_rx(dev, budget);
|
| 1413 |
|
|
|
| 1414 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1415 |
|
|
if (pcnet32_tx(dev)) {
|
| 1416 |
|
|
/* reset the chip to clear the error condition, then restart */
|
| 1417 |
|
|
lp->a.reset(ioaddr);
|
| 1418 |
|
|
lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
|
| 1419 |
|
|
pcnet32_restart(dev, CSR0_START);
|
| 1420 |
|
|
netif_wake_queue(dev);
|
| 1421 |
|
|
}
|
| 1422 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1423 |
|
|
|
| 1424 |
|
|
if (work_done < budget) {
|
| 1425 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1426 |
|
|
|
| 1427 |
|
|
__netif_rx_complete(dev, napi);
|
| 1428 |
|
|
|
| 1429 |
|
|
/* clear interrupt masks */
|
| 1430 |
|
|
val = lp->a.read_csr(ioaddr, CSR3);
|
| 1431 |
|
|
val &= 0x00ff;
|
| 1432 |
|
|
lp->a.write_csr(ioaddr, CSR3, val);
|
| 1433 |
|
|
|
| 1434 |
|
|
/* Set interrupt enable. */
|
| 1435 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
|
| 1436 |
|
|
mmiowb();
|
| 1437 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1438 |
|
|
}
|
| 1439 |
|
|
return work_done;
|
| 1440 |
|
|
}
|
| 1441 |
|
|
#endif
|
| 1442 |
|
|
|
| 1443 |
|
|
#define PCNET32_REGS_PER_PHY 32
|
| 1444 |
|
|
#define PCNET32_MAX_PHYS 32
|
| 1445 |
|
|
static int pcnet32_get_regs_len(struct net_device *dev)
|
| 1446 |
|
|
{
|
| 1447 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1448 |
|
|
int j = lp->phycount * PCNET32_REGS_PER_PHY;
|
| 1449 |
|
|
|
| 1450 |
|
|
return ((PCNET32_NUM_REGS + j) * sizeof(u16));
|
| 1451 |
|
|
}
|
| 1452 |
|
|
|
| 1453 |
|
|
static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
| 1454 |
|
|
void *ptr)
|
| 1455 |
|
|
{
|
| 1456 |
|
|
int i, csr0;
|
| 1457 |
|
|
u16 *buff = ptr;
|
| 1458 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 1459 |
|
|
struct pcnet32_access *a = &lp->a;
|
| 1460 |
|
|
ulong ioaddr = dev->base_addr;
|
| 1461 |
|
|
unsigned long flags;
|
| 1462 |
|
|
|
| 1463 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 1464 |
|
|
|
| 1465 |
|
|
csr0 = a->read_csr(ioaddr, CSR0);
|
| 1466 |
|
|
if (!(csr0 & CSR0_STOP)) /* If not stopped */
|
| 1467 |
|
|
pcnet32_suspend(dev, &flags, 1);
|
| 1468 |
|
|
|
| 1469 |
|
|
/* read address PROM */
|
| 1470 |
|
|
for (i = 0; i < 16; i += 2)
|
| 1471 |
|
|
*buff++ = inw(ioaddr + i);
|
| 1472 |
|
|
|
| 1473 |
|
|
/* read control and status registers */
|
| 1474 |
|
|
for (i = 0; i < 90; i++) {
|
| 1475 |
|
|
*buff++ = a->read_csr(ioaddr, i);
|
| 1476 |
|
|
}
|
| 1477 |
|
|
|
| 1478 |
|
|
*buff++ = a->read_csr(ioaddr, 112);
|
| 1479 |
|
|
*buff++ = a->read_csr(ioaddr, 114);
|
| 1480 |
|
|
|
| 1481 |
|
|
/* read bus configuration registers */
|
| 1482 |
|
|
for (i = 0; i < 30; i++) {
|
| 1483 |
|
|
*buff++ = a->read_bcr(ioaddr, i);
|
| 1484 |
|
|
}
|
| 1485 |
|
|
*buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
|
| 1486 |
|
|
for (i = 31; i < 36; i++) {
|
| 1487 |
|
|
*buff++ = a->read_bcr(ioaddr, i);
|
| 1488 |
|
|
}
|
| 1489 |
|
|
|
| 1490 |
|
|
/* read mii phy registers */
|
| 1491 |
|
|
if (lp->mii) {
|
| 1492 |
|
|
int j;
|
| 1493 |
|
|
for (j = 0; j < PCNET32_MAX_PHYS; j++) {
|
| 1494 |
|
|
if (lp->phymask & (1 << j)) {
|
| 1495 |
|
|
for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
|
| 1496 |
|
|
lp->a.write_bcr(ioaddr, 33,
|
| 1497 |
|
|
(j << 5) | i);
|
| 1498 |
|
|
*buff++ = lp->a.read_bcr(ioaddr, 34);
|
| 1499 |
|
|
}
|
| 1500 |
|
|
}
|
| 1501 |
|
|
}
|
| 1502 |
|
|
}
|
| 1503 |
|
|
|
| 1504 |
|
|
if (!(csr0 & CSR0_STOP)) { /* If not stopped */
|
| 1505 |
|
|
int csr5;
|
| 1506 |
|
|
|
| 1507 |
|
|
/* clear SUSPEND (SPND) - CSR5 bit 0 */
|
| 1508 |
|
|
csr5 = a->read_csr(ioaddr, CSR5);
|
| 1509 |
|
|
a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
|
| 1510 |
|
|
}
|
| 1511 |
|
|
|
| 1512 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 1513 |
|
|
}
|
| 1514 |
|
|
|
| 1515 |
|
|
static const struct ethtool_ops pcnet32_ethtool_ops = {
|
| 1516 |
|
|
.get_settings = pcnet32_get_settings,
|
| 1517 |
|
|
.set_settings = pcnet32_set_settings,
|
| 1518 |
|
|
.get_drvinfo = pcnet32_get_drvinfo,
|
| 1519 |
|
|
.get_msglevel = pcnet32_get_msglevel,
|
| 1520 |
|
|
.set_msglevel = pcnet32_set_msglevel,
|
| 1521 |
|
|
.nway_reset = pcnet32_nway_reset,
|
| 1522 |
|
|
.get_link = pcnet32_get_link,
|
| 1523 |
|
|
.get_ringparam = pcnet32_get_ringparam,
|
| 1524 |
|
|
.set_ringparam = pcnet32_set_ringparam,
|
| 1525 |
|
|
.get_strings = pcnet32_get_strings,
|
| 1526 |
|
|
.self_test = pcnet32_ethtool_test,
|
| 1527 |
|
|
.phys_id = pcnet32_phys_id,
|
| 1528 |
|
|
.get_regs_len = pcnet32_get_regs_len,
|
| 1529 |
|
|
.get_regs = pcnet32_get_regs,
|
| 1530 |
|
|
.get_sset_count = pcnet32_get_sset_count,
|
| 1531 |
|
|
};
|
| 1532 |
|
|
|
| 1533 |
|
|
/* only probes for non-PCI devices, the rest are handled by
|
| 1534 |
|
|
* pci_register_driver via pcnet32_probe_pci */
|
| 1535 |
|
|
|
| 1536 |
|
|
static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
|
| 1537 |
|
|
{
|
| 1538 |
|
|
unsigned int *port, ioaddr;
|
| 1539 |
|
|
|
| 1540 |
|
|
/* search for PCnet32 VLB cards at known addresses */
|
| 1541 |
|
|
for (port = pcnet32_portlist; (ioaddr = *port); port++) {
|
| 1542 |
|
|
if (request_region
|
| 1543 |
|
|
(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
|
| 1544 |
|
|
/* check if there is really a pcnet chip on that ioaddr */
|
| 1545 |
|
|
if ((inb(ioaddr + 14) == 0x57)
|
| 1546 |
|
|
&& (inb(ioaddr + 15) == 0x57)) {
|
| 1547 |
|
|
pcnet32_probe1(ioaddr, 0, NULL);
|
| 1548 |
|
|
} else {
|
| 1549 |
|
|
release_region(ioaddr, PCNET32_TOTAL_SIZE);
|
| 1550 |
|
|
}
|
| 1551 |
|
|
}
|
| 1552 |
|
|
}
|
| 1553 |
|
|
}
|
| 1554 |
|
|
|
| 1555 |
|
|
static int __devinit
|
| 1556 |
|
|
pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
|
| 1557 |
|
|
{
|
| 1558 |
|
|
unsigned long ioaddr;
|
| 1559 |
|
|
int err;
|
| 1560 |
|
|
|
| 1561 |
|
|
err = pci_enable_device(pdev);
|
| 1562 |
|
|
if (err < 0) {
|
| 1563 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1564 |
|
|
printk(KERN_ERR PFX
|
| 1565 |
|
|
"failed to enable device -- err=%d\n", err);
|
| 1566 |
|
|
return err;
|
| 1567 |
|
|
}
|
| 1568 |
|
|
pci_set_master(pdev);
|
| 1569 |
|
|
|
| 1570 |
|
|
ioaddr = pci_resource_start(pdev, 0);
|
| 1571 |
|
|
if (!ioaddr) {
|
| 1572 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1573 |
|
|
printk(KERN_ERR PFX
|
| 1574 |
|
|
"card has no PCI IO resources, aborting\n");
|
| 1575 |
|
|
return -ENODEV;
|
| 1576 |
|
|
}
|
| 1577 |
|
|
|
| 1578 |
|
|
if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
|
| 1579 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1580 |
|
|
printk(KERN_ERR PFX
|
| 1581 |
|
|
"architecture does not support 32bit PCI busmaster DMA\n");
|
| 1582 |
|
|
return -ENODEV;
|
| 1583 |
|
|
}
|
| 1584 |
|
|
if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
|
| 1585 |
|
|
NULL) {
|
| 1586 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1587 |
|
|
printk(KERN_ERR PFX
|
| 1588 |
|
|
"io address range already allocated\n");
|
| 1589 |
|
|
return -EBUSY;
|
| 1590 |
|
|
}
|
| 1591 |
|
|
|
| 1592 |
|
|
err = pcnet32_probe1(ioaddr, 1, pdev);
|
| 1593 |
|
|
if (err < 0) {
|
| 1594 |
|
|
pci_disable_device(pdev);
|
| 1595 |
|
|
}
|
| 1596 |
|
|
return err;
|
| 1597 |
|
|
}
|
| 1598 |
|
|
|
| 1599 |
|
|
/* pcnet32_probe1
|
| 1600 |
|
|
* Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
|
| 1601 |
|
|
* pdev will be NULL when called from pcnet32_probe_vlbus.
|
| 1602 |
|
|
*/
|
| 1603 |
|
|
static int __devinit
|
| 1604 |
|
|
pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
| 1605 |
|
|
{
|
| 1606 |
|
|
struct pcnet32_private *lp;
|
| 1607 |
|
|
int i, media;
|
| 1608 |
|
|
int fdx, mii, fset, dxsuflo;
|
| 1609 |
|
|
int chip_version;
|
| 1610 |
|
|
char *chipname;
|
| 1611 |
|
|
struct net_device *dev;
|
| 1612 |
|
|
struct pcnet32_access *a = NULL;
|
| 1613 |
|
|
u8 promaddr[6];
|
| 1614 |
|
|
int ret = -ENODEV;
|
| 1615 |
|
|
|
| 1616 |
|
|
/* reset the chip */
|
| 1617 |
|
|
pcnet32_wio_reset(ioaddr);
|
| 1618 |
|
|
|
| 1619 |
|
|
/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
|
| 1620 |
|
|
if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
|
| 1621 |
|
|
a = &pcnet32_wio;
|
| 1622 |
|
|
} else {
|
| 1623 |
|
|
pcnet32_dwio_reset(ioaddr);
|
| 1624 |
|
|
if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
|
| 1625 |
|
|
&& pcnet32_dwio_check(ioaddr)) {
|
| 1626 |
|
|
a = &pcnet32_dwio;
|
| 1627 |
|
|
} else
|
| 1628 |
|
|
goto err_release_region;
|
| 1629 |
|
|
}
|
| 1630 |
|
|
|
| 1631 |
|
|
chip_version =
|
| 1632 |
|
|
a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
|
| 1633 |
|
|
if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
|
| 1634 |
|
|
printk(KERN_INFO " PCnet chip version is %#x.\n",
|
| 1635 |
|
|
chip_version);
|
| 1636 |
|
|
if ((chip_version & 0xfff) != 0x003) {
|
| 1637 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1638 |
|
|
printk(KERN_INFO PFX "Unsupported chip version.\n");
|
| 1639 |
|
|
goto err_release_region;
|
| 1640 |
|
|
}
|
| 1641 |
|
|
|
| 1642 |
|
|
/* initialize variables */
|
| 1643 |
|
|
fdx = mii = fset = dxsuflo = 0;
|
| 1644 |
|
|
chip_version = (chip_version >> 12) & 0xffff;
|
| 1645 |
|
|
|
| 1646 |
|
|
switch (chip_version) {
|
| 1647 |
|
|
case 0x2420:
|
| 1648 |
|
|
chipname = "PCnet/PCI 79C970"; /* PCI */
|
| 1649 |
|
|
break;
|
| 1650 |
|
|
case 0x2430:
|
| 1651 |
|
|
if (shared)
|
| 1652 |
|
|
chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
|
| 1653 |
|
|
else
|
| 1654 |
|
|
chipname = "PCnet/32 79C965"; /* 486/VL bus */
|
| 1655 |
|
|
break;
|
| 1656 |
|
|
case 0x2621:
|
| 1657 |
|
|
chipname = "PCnet/PCI II 79C970A"; /* PCI */
|
| 1658 |
|
|
fdx = 1;
|
| 1659 |
|
|
break;
|
| 1660 |
|
|
case 0x2623:
|
| 1661 |
|
|
chipname = "PCnet/FAST 79C971"; /* PCI */
|
| 1662 |
|
|
fdx = 1;
|
| 1663 |
|
|
mii = 1;
|
| 1664 |
|
|
fset = 1;
|
| 1665 |
|
|
break;
|
| 1666 |
|
|
case 0x2624:
|
| 1667 |
|
|
chipname = "PCnet/FAST+ 79C972"; /* PCI */
|
| 1668 |
|
|
fdx = 1;
|
| 1669 |
|
|
mii = 1;
|
| 1670 |
|
|
fset = 1;
|
| 1671 |
|
|
break;
|
| 1672 |
|
|
case 0x2625:
|
| 1673 |
|
|
chipname = "PCnet/FAST III 79C973"; /* PCI */
|
| 1674 |
|
|
fdx = 1;
|
| 1675 |
|
|
mii = 1;
|
| 1676 |
|
|
break;
|
| 1677 |
|
|
case 0x2626:
|
| 1678 |
|
|
chipname = "PCnet/Home 79C978"; /* PCI */
|
| 1679 |
|
|
fdx = 1;
|
| 1680 |
|
|
/*
|
| 1681 |
|
|
* This is based on specs published at www.amd.com. This section
|
| 1682 |
|
|
* assumes that a card with a 79C978 wants to go into standard
|
| 1683 |
|
|
* ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
|
| 1684 |
|
|
* and the module option homepna=1 can select this instead.
|
| 1685 |
|
|
*/
|
| 1686 |
|
|
media = a->read_bcr(ioaddr, 49);
|
| 1687 |
|
|
media &= ~3; /* default to 10Mb ethernet */
|
| 1688 |
|
|
if (cards_found < MAX_UNITS && homepna[cards_found])
|
| 1689 |
|
|
media |= 1; /* switch to home wiring mode */
|
| 1690 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1691 |
|
|
printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
|
| 1692 |
|
|
(media & 1) ? "1" : "10");
|
| 1693 |
|
|
a->write_bcr(ioaddr, 49, media);
|
| 1694 |
|
|
break;
|
| 1695 |
|
|
case 0x2627:
|
| 1696 |
|
|
chipname = "PCnet/FAST III 79C975"; /* PCI */
|
| 1697 |
|
|
fdx = 1;
|
| 1698 |
|
|
mii = 1;
|
| 1699 |
|
|
break;
|
| 1700 |
|
|
case 0x2628:
|
| 1701 |
|
|
chipname = "PCnet/PRO 79C976";
|
| 1702 |
|
|
fdx = 1;
|
| 1703 |
|
|
mii = 1;
|
| 1704 |
|
|
break;
|
| 1705 |
|
|
default:
|
| 1706 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1707 |
|
|
printk(KERN_INFO PFX
|
| 1708 |
|
|
"PCnet version %#x, no PCnet32 chip.\n",
|
| 1709 |
|
|
chip_version);
|
| 1710 |
|
|
goto err_release_region;
|
| 1711 |
|
|
}
|
| 1712 |
|
|
|
| 1713 |
|
|
/*
|
| 1714 |
|
|
* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
|
| 1715 |
|
|
* starting until the packet is loaded. Strike one for reliability, lose
|
| 1716 |
|
|
* one for latency - although on PCI this isnt a big loss. Older chips
|
| 1717 |
|
|
* have FIFO's smaller than a packet, so you can't do this.
|
| 1718 |
|
|
* Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
|
| 1719 |
|
|
*/
|
| 1720 |
|
|
|
| 1721 |
|
|
if (fset) {
|
| 1722 |
|
|
a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
|
| 1723 |
|
|
a->write_csr(ioaddr, 80,
|
| 1724 |
|
|
(a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
|
| 1725 |
|
|
dxsuflo = 1;
|
| 1726 |
|
|
}
|
| 1727 |
|
|
|
| 1728 |
|
|
dev = alloc_etherdev(sizeof(*lp));
|
| 1729 |
|
|
if (!dev) {
|
| 1730 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1731 |
|
|
printk(KERN_ERR PFX "Memory allocation failed.\n");
|
| 1732 |
|
|
ret = -ENOMEM;
|
| 1733 |
|
|
goto err_release_region;
|
| 1734 |
|
|
}
|
| 1735 |
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
| 1736 |
|
|
|
| 1737 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1738 |
|
|
printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
|
| 1739 |
|
|
|
| 1740 |
|
|
/* In most chips, after a chip reset, the ethernet address is read from the
|
| 1741 |
|
|
* station address PROM at the base address and programmed into the
|
| 1742 |
|
|
* "Physical Address Registers" CSR12-14.
|
| 1743 |
|
|
* As a precautionary measure, we read the PROM values and complain if
|
| 1744 |
|
|
* they disagree with the CSRs. If they miscompare, and the PROM addr
|
| 1745 |
|
|
* is valid, then the PROM addr is used.
|
| 1746 |
|
|
*/
|
| 1747 |
|
|
for (i = 0; i < 3; i++) {
|
| 1748 |
|
|
unsigned int val;
|
| 1749 |
|
|
val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
|
| 1750 |
|
|
/* There may be endianness issues here. */
|
| 1751 |
|
|
dev->dev_addr[2 * i] = val & 0x0ff;
|
| 1752 |
|
|
dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
|
| 1753 |
|
|
}
|
| 1754 |
|
|
|
| 1755 |
|
|
/* read PROM address and compare with CSR address */
|
| 1756 |
|
|
for (i = 0; i < 6; i++)
|
| 1757 |
|
|
promaddr[i] = inb(ioaddr + i);
|
| 1758 |
|
|
|
| 1759 |
|
|
if (memcmp(promaddr, dev->dev_addr, 6)
|
| 1760 |
|
|
|| !is_valid_ether_addr(dev->dev_addr)) {
|
| 1761 |
|
|
if (is_valid_ether_addr(promaddr)) {
|
| 1762 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE) {
|
| 1763 |
|
|
printk(" warning: CSR address invalid,\n");
|
| 1764 |
|
|
printk(KERN_INFO
|
| 1765 |
|
|
" using instead PROM address of");
|
| 1766 |
|
|
}
|
| 1767 |
|
|
memcpy(dev->dev_addr, promaddr, 6);
|
| 1768 |
|
|
}
|
| 1769 |
|
|
}
|
| 1770 |
|
|
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
|
| 1771 |
|
|
|
| 1772 |
|
|
/* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
|
| 1773 |
|
|
if (!is_valid_ether_addr(dev->perm_addr))
|
| 1774 |
|
|
memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
|
| 1775 |
|
|
|
| 1776 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE) {
|
| 1777 |
|
|
for (i = 0; i < 6; i++)
|
| 1778 |
|
|
printk(" %2.2x", dev->dev_addr[i]);
|
| 1779 |
|
|
|
| 1780 |
|
|
/* Version 0x2623 and 0x2624 */
|
| 1781 |
|
|
if (((chip_version + 1) & 0xfffe) == 0x2624) {
|
| 1782 |
|
|
i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
|
| 1783 |
|
|
printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
|
| 1784 |
|
|
switch (i >> 10) {
|
| 1785 |
|
|
case 0:
|
| 1786 |
|
|
printk(" 20 bytes,");
|
| 1787 |
|
|
break;
|
| 1788 |
|
|
case 1:
|
| 1789 |
|
|
printk(" 64 bytes,");
|
| 1790 |
|
|
break;
|
| 1791 |
|
|
case 2:
|
| 1792 |
|
|
printk(" 128 bytes,");
|
| 1793 |
|
|
break;
|
| 1794 |
|
|
case 3:
|
| 1795 |
|
|
printk("~220 bytes,");
|
| 1796 |
|
|
break;
|
| 1797 |
|
|
}
|
| 1798 |
|
|
i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
|
| 1799 |
|
|
printk(" BCR18(%x):", i & 0xffff);
|
| 1800 |
|
|
if (i & (1 << 5))
|
| 1801 |
|
|
printk("BurstWrEn ");
|
| 1802 |
|
|
if (i & (1 << 6))
|
| 1803 |
|
|
printk("BurstRdEn ");
|
| 1804 |
|
|
if (i & (1 << 7))
|
| 1805 |
|
|
printk("DWordIO ");
|
| 1806 |
|
|
if (i & (1 << 11))
|
| 1807 |
|
|
printk("NoUFlow ");
|
| 1808 |
|
|
i = a->read_bcr(ioaddr, 25);
|
| 1809 |
|
|
printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
|
| 1810 |
|
|
i = a->read_bcr(ioaddr, 26);
|
| 1811 |
|
|
printk(" SRAM_BND=0x%04x,", i << 8);
|
| 1812 |
|
|
i = a->read_bcr(ioaddr, 27);
|
| 1813 |
|
|
if (i & (1 << 14))
|
| 1814 |
|
|
printk("LowLatRx");
|
| 1815 |
|
|
}
|
| 1816 |
|
|
}
|
| 1817 |
|
|
|
| 1818 |
|
|
dev->base_addr = ioaddr;
|
| 1819 |
|
|
lp = netdev_priv(dev);
|
| 1820 |
|
|
/* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
|
| 1821 |
|
|
if ((lp->init_block =
|
| 1822 |
|
|
pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
|
| 1823 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1824 |
|
|
printk(KERN_ERR PFX
|
| 1825 |
|
|
"Consistent memory allocation failed.\n");
|
| 1826 |
|
|
ret = -ENOMEM;
|
| 1827 |
|
|
goto err_free_netdev;
|
| 1828 |
|
|
}
|
| 1829 |
|
|
lp->pci_dev = pdev;
|
| 1830 |
|
|
|
| 1831 |
|
|
lp->dev = dev;
|
| 1832 |
|
|
|
| 1833 |
|
|
spin_lock_init(&lp->lock);
|
| 1834 |
|
|
|
| 1835 |
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
| 1836 |
|
|
lp->name = chipname;
|
| 1837 |
|
|
lp->shared_irq = shared;
|
| 1838 |
|
|
lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
|
| 1839 |
|
|
lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
|
| 1840 |
|
|
lp->tx_mod_mask = lp->tx_ring_size - 1;
|
| 1841 |
|
|
lp->rx_mod_mask = lp->rx_ring_size - 1;
|
| 1842 |
|
|
lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
|
| 1843 |
|
|
lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
|
| 1844 |
|
|
lp->mii_if.full_duplex = fdx;
|
| 1845 |
|
|
lp->mii_if.phy_id_mask = 0x1f;
|
| 1846 |
|
|
lp->mii_if.reg_num_mask = 0x1f;
|
| 1847 |
|
|
lp->dxsuflo = dxsuflo;
|
| 1848 |
|
|
lp->mii = mii;
|
| 1849 |
|
|
lp->chip_version = chip_version;
|
| 1850 |
|
|
lp->msg_enable = pcnet32_debug;
|
| 1851 |
|
|
if ((cards_found >= MAX_UNITS)
|
| 1852 |
|
|
|| (options[cards_found] > sizeof(options_mapping)))
|
| 1853 |
|
|
lp->options = PCNET32_PORT_ASEL;
|
| 1854 |
|
|
else
|
| 1855 |
|
|
lp->options = options_mapping[options[cards_found]];
|
| 1856 |
|
|
lp->mii_if.dev = dev;
|
| 1857 |
|
|
lp->mii_if.mdio_read = mdio_read;
|
| 1858 |
|
|
lp->mii_if.mdio_write = mdio_write;
|
| 1859 |
|
|
|
| 1860 |
|
|
/* napi.weight is used in both the napi and non-napi cases */
|
| 1861 |
|
|
lp->napi.weight = lp->rx_ring_size / 2;
|
| 1862 |
|
|
|
| 1863 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 1864 |
|
|
netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
|
| 1865 |
|
|
#endif
|
| 1866 |
|
|
|
| 1867 |
|
|
if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
|
| 1868 |
|
|
((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
|
| 1869 |
|
|
lp->options |= PCNET32_PORT_FD;
|
| 1870 |
|
|
|
| 1871 |
|
|
if (!a) {
|
| 1872 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1873 |
|
|
printk(KERN_ERR PFX "No access methods\n");
|
| 1874 |
|
|
ret = -ENODEV;
|
| 1875 |
|
|
goto err_free_consistent;
|
| 1876 |
|
|
}
|
| 1877 |
|
|
lp->a = *a;
|
| 1878 |
|
|
|
| 1879 |
|
|
/* prior to register_netdev, dev->name is not yet correct */
|
| 1880 |
|
|
if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
|
| 1881 |
|
|
ret = -ENOMEM;
|
| 1882 |
|
|
goto err_free_ring;
|
| 1883 |
|
|
}
|
| 1884 |
|
|
/* detect special T1/E1 WAN card by checking for MAC address */
|
| 1885 |
|
|
if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
|
| 1886 |
|
|
&& dev->dev_addr[2] == 0x75)
|
| 1887 |
|
|
lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
|
| 1888 |
|
|
|
| 1889 |
|
|
lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
|
| 1890 |
|
|
lp->init_block->tlen_rlen =
|
| 1891 |
|
|
cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
|
| 1892 |
|
|
for (i = 0; i < 6; i++)
|
| 1893 |
|
|
lp->init_block->phys_addr[i] = dev->dev_addr[i];
|
| 1894 |
|
|
lp->init_block->filter[0] = 0x00000000;
|
| 1895 |
|
|
lp->init_block->filter[1] = 0x00000000;
|
| 1896 |
|
|
lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
|
| 1897 |
|
|
lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
|
| 1898 |
|
|
|
| 1899 |
|
|
/* switch pcnet32 to 32bit mode */
|
| 1900 |
|
|
a->write_bcr(ioaddr, 20, 2);
|
| 1901 |
|
|
|
| 1902 |
|
|
a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
|
| 1903 |
|
|
a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
|
| 1904 |
|
|
|
| 1905 |
|
|
if (pdev) { /* use the IRQ provided by PCI */
|
| 1906 |
|
|
dev->irq = pdev->irq;
|
| 1907 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1908 |
|
|
printk(" assigned IRQ %d.\n", dev->irq);
|
| 1909 |
|
|
} else {
|
| 1910 |
|
|
unsigned long irq_mask = probe_irq_on();
|
| 1911 |
|
|
|
| 1912 |
|
|
/*
|
| 1913 |
|
|
* To auto-IRQ we enable the initialization-done and DMA error
|
| 1914 |
|
|
* interrupts. For ISA boards we get a DMA error, but VLB and PCI
|
| 1915 |
|
|
* boards will work.
|
| 1916 |
|
|
*/
|
| 1917 |
|
|
/* Trigger an initialization just for the interrupt. */
|
| 1918 |
|
|
a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
|
| 1919 |
|
|
mdelay(1);
|
| 1920 |
|
|
|
| 1921 |
|
|
dev->irq = probe_irq_off(irq_mask);
|
| 1922 |
|
|
if (!dev->irq) {
|
| 1923 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1924 |
|
|
printk(", failed to detect IRQ line.\n");
|
| 1925 |
|
|
ret = -ENODEV;
|
| 1926 |
|
|
goto err_free_ring;
|
| 1927 |
|
|
}
|
| 1928 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1929 |
|
|
printk(", probed IRQ %d.\n", dev->irq);
|
| 1930 |
|
|
}
|
| 1931 |
|
|
|
| 1932 |
|
|
/* Set the mii phy_id so that we can query the link state */
|
| 1933 |
|
|
if (lp->mii) {
|
| 1934 |
|
|
/* lp->phycount and lp->phymask are set to 0 by memset above */
|
| 1935 |
|
|
|
| 1936 |
|
|
lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
|
| 1937 |
|
|
/* scan for PHYs */
|
| 1938 |
|
|
for (i = 0; i < PCNET32_MAX_PHYS; i++) {
|
| 1939 |
|
|
unsigned short id1, id2;
|
| 1940 |
|
|
|
| 1941 |
|
|
id1 = mdio_read(dev, i, MII_PHYSID1);
|
| 1942 |
|
|
if (id1 == 0xffff)
|
| 1943 |
|
|
continue;
|
| 1944 |
|
|
id2 = mdio_read(dev, i, MII_PHYSID2);
|
| 1945 |
|
|
if (id2 == 0xffff)
|
| 1946 |
|
|
continue;
|
| 1947 |
|
|
if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
|
| 1948 |
|
|
continue; /* 79C971 & 79C972 have phantom phy at id 31 */
|
| 1949 |
|
|
lp->phycount++;
|
| 1950 |
|
|
lp->phymask |= (1 << i);
|
| 1951 |
|
|
lp->mii_if.phy_id = i;
|
| 1952 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1953 |
|
|
printk(KERN_INFO PFX
|
| 1954 |
|
|
"Found PHY %04x:%04x at address %d.\n",
|
| 1955 |
|
|
id1, id2, i);
|
| 1956 |
|
|
}
|
| 1957 |
|
|
lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
|
| 1958 |
|
|
if (lp->phycount > 1) {
|
| 1959 |
|
|
lp->options |= PCNET32_PORT_MII;
|
| 1960 |
|
|
}
|
| 1961 |
|
|
}
|
| 1962 |
|
|
|
| 1963 |
|
|
init_timer(&lp->watchdog_timer);
|
| 1964 |
|
|
lp->watchdog_timer.data = (unsigned long)dev;
|
| 1965 |
|
|
lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
|
| 1966 |
|
|
|
| 1967 |
|
|
/* The PCNET32-specific entries in the device structure. */
|
| 1968 |
|
|
dev->open = &pcnet32_open;
|
| 1969 |
|
|
dev->hard_start_xmit = &pcnet32_start_xmit;
|
| 1970 |
|
|
dev->stop = &pcnet32_close;
|
| 1971 |
|
|
dev->get_stats = &pcnet32_get_stats;
|
| 1972 |
|
|
dev->set_multicast_list = &pcnet32_set_multicast_list;
|
| 1973 |
|
|
dev->do_ioctl = &pcnet32_ioctl;
|
| 1974 |
|
|
dev->ethtool_ops = &pcnet32_ethtool_ops;
|
| 1975 |
|
|
dev->tx_timeout = pcnet32_tx_timeout;
|
| 1976 |
|
|
dev->watchdog_timeo = (5 * HZ);
|
| 1977 |
|
|
|
| 1978 |
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
| 1979 |
|
|
dev->poll_controller = pcnet32_poll_controller;
|
| 1980 |
|
|
#endif
|
| 1981 |
|
|
|
| 1982 |
|
|
/* Fill in the generic fields of the device structure. */
|
| 1983 |
|
|
if (register_netdev(dev))
|
| 1984 |
|
|
goto err_free_ring;
|
| 1985 |
|
|
|
| 1986 |
|
|
if (pdev) {
|
| 1987 |
|
|
pci_set_drvdata(pdev, dev);
|
| 1988 |
|
|
} else {
|
| 1989 |
|
|
lp->next = pcnet32_dev;
|
| 1990 |
|
|
pcnet32_dev = dev;
|
| 1991 |
|
|
}
|
| 1992 |
|
|
|
| 1993 |
|
|
if (pcnet32_debug & NETIF_MSG_PROBE)
|
| 1994 |
|
|
printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
|
| 1995 |
|
|
cards_found++;
|
| 1996 |
|
|
|
| 1997 |
|
|
/* enable LED writes */
|
| 1998 |
|
|
a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
|
| 1999 |
|
|
|
| 2000 |
|
|
return 0;
|
| 2001 |
|
|
|
| 2002 |
|
|
err_free_ring:
|
| 2003 |
|
|
pcnet32_free_ring(dev);
|
| 2004 |
|
|
err_free_consistent:
|
| 2005 |
|
|
pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
|
| 2006 |
|
|
lp->init_block, lp->init_dma_addr);
|
| 2007 |
|
|
err_free_netdev:
|
| 2008 |
|
|
free_netdev(dev);
|
| 2009 |
|
|
err_release_region:
|
| 2010 |
|
|
release_region(ioaddr, PCNET32_TOTAL_SIZE);
|
| 2011 |
|
|
return ret;
|
| 2012 |
|
|
}
|
| 2013 |
|
|
|
| 2014 |
|
|
/* if any allocation fails, caller must also call pcnet32_free_ring */
|
| 2015 |
|
|
static int pcnet32_alloc_ring(struct net_device *dev, char *name)
|
| 2016 |
|
|
{
|
| 2017 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2018 |
|
|
|
| 2019 |
|
|
lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
|
| 2020 |
|
|
sizeof(struct pcnet32_tx_head) *
|
| 2021 |
|
|
lp->tx_ring_size,
|
| 2022 |
|
|
&lp->tx_ring_dma_addr);
|
| 2023 |
|
|
if (lp->tx_ring == NULL) {
|
| 2024 |
|
|
if (netif_msg_drv(lp))
|
| 2025 |
|
|
printk("\n" KERN_ERR PFX
|
| 2026 |
|
|
"%s: Consistent memory allocation failed.\n",
|
| 2027 |
|
|
name);
|
| 2028 |
|
|
return -ENOMEM;
|
| 2029 |
|
|
}
|
| 2030 |
|
|
|
| 2031 |
|
|
lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
|
| 2032 |
|
|
sizeof(struct pcnet32_rx_head) *
|
| 2033 |
|
|
lp->rx_ring_size,
|
| 2034 |
|
|
&lp->rx_ring_dma_addr);
|
| 2035 |
|
|
if (lp->rx_ring == NULL) {
|
| 2036 |
|
|
if (netif_msg_drv(lp))
|
| 2037 |
|
|
printk("\n" KERN_ERR PFX
|
| 2038 |
|
|
"%s: Consistent memory allocation failed.\n",
|
| 2039 |
|
|
name);
|
| 2040 |
|
|
return -ENOMEM;
|
| 2041 |
|
|
}
|
| 2042 |
|
|
|
| 2043 |
|
|
lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
|
| 2044 |
|
|
GFP_ATOMIC);
|
| 2045 |
|
|
if (!lp->tx_dma_addr) {
|
| 2046 |
|
|
if (netif_msg_drv(lp))
|
| 2047 |
|
|
printk("\n" KERN_ERR PFX
|
| 2048 |
|
|
"%s: Memory allocation failed.\n", name);
|
| 2049 |
|
|
return -ENOMEM;
|
| 2050 |
|
|
}
|
| 2051 |
|
|
|
| 2052 |
|
|
lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
|
| 2053 |
|
|
GFP_ATOMIC);
|
| 2054 |
|
|
if (!lp->rx_dma_addr) {
|
| 2055 |
|
|
if (netif_msg_drv(lp))
|
| 2056 |
|
|
printk("\n" KERN_ERR PFX
|
| 2057 |
|
|
"%s: Memory allocation failed.\n", name);
|
| 2058 |
|
|
return -ENOMEM;
|
| 2059 |
|
|
}
|
| 2060 |
|
|
|
| 2061 |
|
|
lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
|
| 2062 |
|
|
GFP_ATOMIC);
|
| 2063 |
|
|
if (!lp->tx_skbuff) {
|
| 2064 |
|
|
if (netif_msg_drv(lp))
|
| 2065 |
|
|
printk("\n" KERN_ERR PFX
|
| 2066 |
|
|
"%s: Memory allocation failed.\n", name);
|
| 2067 |
|
|
return -ENOMEM;
|
| 2068 |
|
|
}
|
| 2069 |
|
|
|
| 2070 |
|
|
lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
|
| 2071 |
|
|
GFP_ATOMIC);
|
| 2072 |
|
|
if (!lp->rx_skbuff) {
|
| 2073 |
|
|
if (netif_msg_drv(lp))
|
| 2074 |
|
|
printk("\n" KERN_ERR PFX
|
| 2075 |
|
|
"%s: Memory allocation failed.\n", name);
|
| 2076 |
|
|
return -ENOMEM;
|
| 2077 |
|
|
}
|
| 2078 |
|
|
|
| 2079 |
|
|
return 0;
|
| 2080 |
|
|
}
|
| 2081 |
|
|
|
| 2082 |
|
|
static void pcnet32_free_ring(struct net_device *dev)
|
| 2083 |
|
|
{
|
| 2084 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2085 |
|
|
|
| 2086 |
|
|
kfree(lp->tx_skbuff);
|
| 2087 |
|
|
lp->tx_skbuff = NULL;
|
| 2088 |
|
|
|
| 2089 |
|
|
kfree(lp->rx_skbuff);
|
| 2090 |
|
|
lp->rx_skbuff = NULL;
|
| 2091 |
|
|
|
| 2092 |
|
|
kfree(lp->tx_dma_addr);
|
| 2093 |
|
|
lp->tx_dma_addr = NULL;
|
| 2094 |
|
|
|
| 2095 |
|
|
kfree(lp->rx_dma_addr);
|
| 2096 |
|
|
lp->rx_dma_addr = NULL;
|
| 2097 |
|
|
|
| 2098 |
|
|
if (lp->tx_ring) {
|
| 2099 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 2100 |
|
|
sizeof(struct pcnet32_tx_head) *
|
| 2101 |
|
|
lp->tx_ring_size, lp->tx_ring,
|
| 2102 |
|
|
lp->tx_ring_dma_addr);
|
| 2103 |
|
|
lp->tx_ring = NULL;
|
| 2104 |
|
|
}
|
| 2105 |
|
|
|
| 2106 |
|
|
if (lp->rx_ring) {
|
| 2107 |
|
|
pci_free_consistent(lp->pci_dev,
|
| 2108 |
|
|
sizeof(struct pcnet32_rx_head) *
|
| 2109 |
|
|
lp->rx_ring_size, lp->rx_ring,
|
| 2110 |
|
|
lp->rx_ring_dma_addr);
|
| 2111 |
|
|
lp->rx_ring = NULL;
|
| 2112 |
|
|
}
|
| 2113 |
|
|
}
|
| 2114 |
|
|
|
| 2115 |
|
|
static int pcnet32_open(struct net_device *dev)
|
| 2116 |
|
|
{
|
| 2117 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2118 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2119 |
|
|
u16 val;
|
| 2120 |
|
|
int i;
|
| 2121 |
|
|
int rc;
|
| 2122 |
|
|
unsigned long flags;
|
| 2123 |
|
|
|
| 2124 |
|
|
if (request_irq(dev->irq, &pcnet32_interrupt,
|
| 2125 |
|
|
lp->shared_irq ? IRQF_SHARED : 0, dev->name,
|
| 2126 |
|
|
(void *)dev)) {
|
| 2127 |
|
|
return -EAGAIN;
|
| 2128 |
|
|
}
|
| 2129 |
|
|
|
| 2130 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2131 |
|
|
/* Check for a valid station address */
|
| 2132 |
|
|
if (!is_valid_ether_addr(dev->dev_addr)) {
|
| 2133 |
|
|
rc = -EINVAL;
|
| 2134 |
|
|
goto err_free_irq;
|
| 2135 |
|
|
}
|
| 2136 |
|
|
|
| 2137 |
|
|
/* Reset the PCNET32 */
|
| 2138 |
|
|
lp->a.reset(ioaddr);
|
| 2139 |
|
|
|
| 2140 |
|
|
/* switch pcnet32 to 32bit mode */
|
| 2141 |
|
|
lp->a.write_bcr(ioaddr, 20, 2);
|
| 2142 |
|
|
|
| 2143 |
|
|
if (netif_msg_ifup(lp))
|
| 2144 |
|
|
printk(KERN_DEBUG
|
| 2145 |
|
|
"%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
|
| 2146 |
|
|
dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
|
| 2147 |
|
|
(u32) (lp->rx_ring_dma_addr),
|
| 2148 |
|
|
(u32) (lp->init_dma_addr));
|
| 2149 |
|
|
|
| 2150 |
|
|
/* set/reset autoselect bit */
|
| 2151 |
|
|
val = lp->a.read_bcr(ioaddr, 2) & ~2;
|
| 2152 |
|
|
if (lp->options & PCNET32_PORT_ASEL)
|
| 2153 |
|
|
val |= 2;
|
| 2154 |
|
|
lp->a.write_bcr(ioaddr, 2, val);
|
| 2155 |
|
|
|
| 2156 |
|
|
/* handle full duplex setting */
|
| 2157 |
|
|
if (lp->mii_if.full_duplex) {
|
| 2158 |
|
|
val = lp->a.read_bcr(ioaddr, 9) & ~3;
|
| 2159 |
|
|
if (lp->options & PCNET32_PORT_FD) {
|
| 2160 |
|
|
val |= 1;
|
| 2161 |
|
|
if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
|
| 2162 |
|
|
val |= 2;
|
| 2163 |
|
|
} else if (lp->options & PCNET32_PORT_ASEL) {
|
| 2164 |
|
|
/* workaround of xSeries250, turn on for 79C975 only */
|
| 2165 |
|
|
if (lp->chip_version == 0x2627)
|
| 2166 |
|
|
val |= 3;
|
| 2167 |
|
|
}
|
| 2168 |
|
|
lp->a.write_bcr(ioaddr, 9, val);
|
| 2169 |
|
|
}
|
| 2170 |
|
|
|
| 2171 |
|
|
/* set/reset GPSI bit in test register */
|
| 2172 |
|
|
val = lp->a.read_csr(ioaddr, 124) & ~0x10;
|
| 2173 |
|
|
if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
|
| 2174 |
|
|
val |= 0x10;
|
| 2175 |
|
|
lp->a.write_csr(ioaddr, 124, val);
|
| 2176 |
|
|
|
| 2177 |
|
|
/* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
|
| 2178 |
|
|
if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
|
| 2179 |
|
|
(lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
|
| 2180 |
|
|
lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
|
| 2181 |
|
|
if (lp->options & PCNET32_PORT_ASEL) {
|
| 2182 |
|
|
lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
|
| 2183 |
|
|
if (netif_msg_link(lp))
|
| 2184 |
|
|
printk(KERN_DEBUG
|
| 2185 |
|
|
"%s: Setting 100Mb-Full Duplex.\n",
|
| 2186 |
|
|
dev->name);
|
| 2187 |
|
|
}
|
| 2188 |
|
|
}
|
| 2189 |
|
|
if (lp->phycount < 2) {
|
| 2190 |
|
|
/*
|
| 2191 |
|
|
* 24 Jun 2004 according AMD, in order to change the PHY,
|
| 2192 |
|
|
* DANAS (or DISPM for 79C976) must be set; then select the speed,
|
| 2193 |
|
|
* duplex, and/or enable auto negotiation, and clear DANAS
|
| 2194 |
|
|
*/
|
| 2195 |
|
|
if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
|
| 2196 |
|
|
lp->a.write_bcr(ioaddr, 32,
|
| 2197 |
|
|
lp->a.read_bcr(ioaddr, 32) | 0x0080);
|
| 2198 |
|
|
/* disable Auto Negotiation, set 10Mpbs, HD */
|
| 2199 |
|
|
val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
|
| 2200 |
|
|
if (lp->options & PCNET32_PORT_FD)
|
| 2201 |
|
|
val |= 0x10;
|
| 2202 |
|
|
if (lp->options & PCNET32_PORT_100)
|
| 2203 |
|
|
val |= 0x08;
|
| 2204 |
|
|
lp->a.write_bcr(ioaddr, 32, val);
|
| 2205 |
|
|
} else {
|
| 2206 |
|
|
if (lp->options & PCNET32_PORT_ASEL) {
|
| 2207 |
|
|
lp->a.write_bcr(ioaddr, 32,
|
| 2208 |
|
|
lp->a.read_bcr(ioaddr,
|
| 2209 |
|
|
32) | 0x0080);
|
| 2210 |
|
|
/* enable auto negotiate, setup, disable fd */
|
| 2211 |
|
|
val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
|
| 2212 |
|
|
val |= 0x20;
|
| 2213 |
|
|
lp->a.write_bcr(ioaddr, 32, val);
|
| 2214 |
|
|
}
|
| 2215 |
|
|
}
|
| 2216 |
|
|
} else {
|
| 2217 |
|
|
int first_phy = -1;
|
| 2218 |
|
|
u16 bmcr;
|
| 2219 |
|
|
u32 bcr9;
|
| 2220 |
|
|
struct ethtool_cmd ecmd;
|
| 2221 |
|
|
|
| 2222 |
|
|
/*
|
| 2223 |
|
|
* There is really no good other way to handle multiple PHYs
|
| 2224 |
|
|
* other than turning off all automatics
|
| 2225 |
|
|
*/
|
| 2226 |
|
|
val = lp->a.read_bcr(ioaddr, 2);
|
| 2227 |
|
|
lp->a.write_bcr(ioaddr, 2, val & ~2);
|
| 2228 |
|
|
val = lp->a.read_bcr(ioaddr, 32);
|
| 2229 |
|
|
lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
|
| 2230 |
|
|
|
| 2231 |
|
|
if (!(lp->options & PCNET32_PORT_ASEL)) {
|
| 2232 |
|
|
/* setup ecmd */
|
| 2233 |
|
|
ecmd.port = PORT_MII;
|
| 2234 |
|
|
ecmd.transceiver = XCVR_INTERNAL;
|
| 2235 |
|
|
ecmd.autoneg = AUTONEG_DISABLE;
|
| 2236 |
|
|
ecmd.speed =
|
| 2237 |
|
|
lp->
|
| 2238 |
|
|
options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
|
| 2239 |
|
|
bcr9 = lp->a.read_bcr(ioaddr, 9);
|
| 2240 |
|
|
|
| 2241 |
|
|
if (lp->options & PCNET32_PORT_FD) {
|
| 2242 |
|
|
ecmd.duplex = DUPLEX_FULL;
|
| 2243 |
|
|
bcr9 |= (1 << 0);
|
| 2244 |
|
|
} else {
|
| 2245 |
|
|
ecmd.duplex = DUPLEX_HALF;
|
| 2246 |
|
|
bcr9 |= ~(1 << 0);
|
| 2247 |
|
|
}
|
| 2248 |
|
|
lp->a.write_bcr(ioaddr, 9, bcr9);
|
| 2249 |
|
|
}
|
| 2250 |
|
|
|
| 2251 |
|
|
for (i = 0; i < PCNET32_MAX_PHYS; i++) {
|
| 2252 |
|
|
if (lp->phymask & (1 << i)) {
|
| 2253 |
|
|
/* isolate all but the first PHY */
|
| 2254 |
|
|
bmcr = mdio_read(dev, i, MII_BMCR);
|
| 2255 |
|
|
if (first_phy == -1) {
|
| 2256 |
|
|
first_phy = i;
|
| 2257 |
|
|
mdio_write(dev, i, MII_BMCR,
|
| 2258 |
|
|
bmcr & ~BMCR_ISOLATE);
|
| 2259 |
|
|
} else {
|
| 2260 |
|
|
mdio_write(dev, i, MII_BMCR,
|
| 2261 |
|
|
bmcr | BMCR_ISOLATE);
|
| 2262 |
|
|
}
|
| 2263 |
|
|
/* use mii_ethtool_sset to setup PHY */
|
| 2264 |
|
|
lp->mii_if.phy_id = i;
|
| 2265 |
|
|
ecmd.phy_address = i;
|
| 2266 |
|
|
if (lp->options & PCNET32_PORT_ASEL) {
|
| 2267 |
|
|
mii_ethtool_gset(&lp->mii_if, &ecmd);
|
| 2268 |
|
|
ecmd.autoneg = AUTONEG_ENABLE;
|
| 2269 |
|
|
}
|
| 2270 |
|
|
mii_ethtool_sset(&lp->mii_if, &ecmd);
|
| 2271 |
|
|
}
|
| 2272 |
|
|
}
|
| 2273 |
|
|
lp->mii_if.phy_id = first_phy;
|
| 2274 |
|
|
if (netif_msg_link(lp))
|
| 2275 |
|
|
printk(KERN_INFO "%s: Using PHY number %d.\n",
|
| 2276 |
|
|
dev->name, first_phy);
|
| 2277 |
|
|
}
|
| 2278 |
|
|
|
| 2279 |
|
|
#ifdef DO_DXSUFLO
|
| 2280 |
|
|
if (lp->dxsuflo) { /* Disable transmit stop on underflow */
|
| 2281 |
|
|
val = lp->a.read_csr(ioaddr, CSR3);
|
| 2282 |
|
|
val |= 0x40;
|
| 2283 |
|
|
lp->a.write_csr(ioaddr, CSR3, val);
|
| 2284 |
|
|
}
|
| 2285 |
|
|
#endif
|
| 2286 |
|
|
|
| 2287 |
|
|
lp->init_block->mode =
|
| 2288 |
|
|
cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
|
| 2289 |
|
|
pcnet32_load_multicast(dev);
|
| 2290 |
|
|
|
| 2291 |
|
|
if (pcnet32_init_ring(dev)) {
|
| 2292 |
|
|
rc = -ENOMEM;
|
| 2293 |
|
|
goto err_free_ring;
|
| 2294 |
|
|
}
|
| 2295 |
|
|
|
| 2296 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 2297 |
|
|
napi_enable(&lp->napi);
|
| 2298 |
|
|
#endif
|
| 2299 |
|
|
|
| 2300 |
|
|
/* Re-initialize the PCNET32, and start it when done. */
|
| 2301 |
|
|
lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
|
| 2302 |
|
|
lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
|
| 2303 |
|
|
|
| 2304 |
|
|
lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
|
| 2305 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
|
| 2306 |
|
|
|
| 2307 |
|
|
netif_start_queue(dev);
|
| 2308 |
|
|
|
| 2309 |
|
|
if (lp->chip_version >= PCNET32_79C970A) {
|
| 2310 |
|
|
/* Print the link status and start the watchdog */
|
| 2311 |
|
|
pcnet32_check_media(dev, 1);
|
| 2312 |
|
|
mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
|
| 2313 |
|
|
}
|
| 2314 |
|
|
|
| 2315 |
|
|
i = 0;
|
| 2316 |
|
|
while (i++ < 100)
|
| 2317 |
|
|
if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
|
| 2318 |
|
|
break;
|
| 2319 |
|
|
/*
|
| 2320 |
|
|
* We used to clear the InitDone bit, 0x0100, here but Mark Stockton
|
| 2321 |
|
|
* reports that doing so triggers a bug in the '974.
|
| 2322 |
|
|
*/
|
| 2323 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
|
| 2324 |
|
|
|
| 2325 |
|
|
if (netif_msg_ifup(lp))
|
| 2326 |
|
|
printk(KERN_DEBUG
|
| 2327 |
|
|
"%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
|
| 2328 |
|
|
dev->name, i,
|
| 2329 |
|
|
(u32) (lp->init_dma_addr),
|
| 2330 |
|
|
lp->a.read_csr(ioaddr, CSR0));
|
| 2331 |
|
|
|
| 2332 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2333 |
|
|
|
| 2334 |
|
|
return 0; /* Always succeed */
|
| 2335 |
|
|
|
| 2336 |
|
|
err_free_ring:
|
| 2337 |
|
|
/* free any allocated skbuffs */
|
| 2338 |
|
|
pcnet32_purge_rx_ring(dev);
|
| 2339 |
|
|
|
| 2340 |
|
|
/*
|
| 2341 |
|
|
* Switch back to 16bit mode to avoid problems with dumb
|
| 2342 |
|
|
* DOS packet driver after a warm reboot
|
| 2343 |
|
|
*/
|
| 2344 |
|
|
lp->a.write_bcr(ioaddr, 20, 4);
|
| 2345 |
|
|
|
| 2346 |
|
|
err_free_irq:
|
| 2347 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2348 |
|
|
free_irq(dev->irq, dev);
|
| 2349 |
|
|
return rc;
|
| 2350 |
|
|
}
|
| 2351 |
|
|
|
| 2352 |
|
|
/*
|
| 2353 |
|
|
* The LANCE has been halted for one reason or another (busmaster memory
|
| 2354 |
|
|
* arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
|
| 2355 |
|
|
* etc.). Modern LANCE variants always reload their ring-buffer
|
| 2356 |
|
|
* configuration when restarted, so we must reinitialize our ring
|
| 2357 |
|
|
* context before restarting. As part of this reinitialization,
|
| 2358 |
|
|
* find all packets still on the Tx ring and pretend that they had been
|
| 2359 |
|
|
* sent (in effect, drop the packets on the floor) - the higher-level
|
| 2360 |
|
|
* protocols will time out and retransmit. It'd be better to shuffle
|
| 2361 |
|
|
* these skbs to a temp list and then actually re-Tx them after
|
| 2362 |
|
|
* restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
|
| 2363 |
|
|
*/
|
| 2364 |
|
|
|
| 2365 |
|
|
static void pcnet32_purge_tx_ring(struct net_device *dev)
|
| 2366 |
|
|
{
|
| 2367 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2368 |
|
|
int i;
|
| 2369 |
|
|
|
| 2370 |
|
|
for (i = 0; i < lp->tx_ring_size; i++) {
|
| 2371 |
|
|
lp->tx_ring[i].status = 0; /* CPU owns buffer */
|
| 2372 |
|
|
wmb(); /* Make sure adapter sees owner change */
|
| 2373 |
|
|
if (lp->tx_skbuff[i]) {
|
| 2374 |
|
|
pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
|
| 2375 |
|
|
lp->tx_skbuff[i]->len,
|
| 2376 |
|
|
PCI_DMA_TODEVICE);
|
| 2377 |
|
|
dev_kfree_skb_any(lp->tx_skbuff[i]);
|
| 2378 |
|
|
}
|
| 2379 |
|
|
lp->tx_skbuff[i] = NULL;
|
| 2380 |
|
|
lp->tx_dma_addr[i] = 0;
|
| 2381 |
|
|
}
|
| 2382 |
|
|
}
|
| 2383 |
|
|
|
| 2384 |
|
|
/* Initialize the PCNET32 Rx and Tx rings. */
|
| 2385 |
|
|
static int pcnet32_init_ring(struct net_device *dev)
|
| 2386 |
|
|
{
|
| 2387 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2388 |
|
|
int i;
|
| 2389 |
|
|
|
| 2390 |
|
|
lp->tx_full = 0;
|
| 2391 |
|
|
lp->cur_rx = lp->cur_tx = 0;
|
| 2392 |
|
|
lp->dirty_rx = lp->dirty_tx = 0;
|
| 2393 |
|
|
|
| 2394 |
|
|
for (i = 0; i < lp->rx_ring_size; i++) {
|
| 2395 |
|
|
struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
|
| 2396 |
|
|
if (rx_skbuff == NULL) {
|
| 2397 |
|
|
if (!
|
| 2398 |
|
|
(rx_skbuff = lp->rx_skbuff[i] =
|
| 2399 |
|
|
dev_alloc_skb(PKT_BUF_SZ))) {
|
| 2400 |
|
|
/* there is not much, we can do at this point */
|
| 2401 |
|
|
if (netif_msg_drv(lp))
|
| 2402 |
|
|
printk(KERN_ERR
|
| 2403 |
|
|
"%s: pcnet32_init_ring dev_alloc_skb failed.\n",
|
| 2404 |
|
|
dev->name);
|
| 2405 |
|
|
return -1;
|
| 2406 |
|
|
}
|
| 2407 |
|
|
skb_reserve(rx_skbuff, 2);
|
| 2408 |
|
|
}
|
| 2409 |
|
|
|
| 2410 |
|
|
rmb();
|
| 2411 |
|
|
if (lp->rx_dma_addr[i] == 0)
|
| 2412 |
|
|
lp->rx_dma_addr[i] =
|
| 2413 |
|
|
pci_map_single(lp->pci_dev, rx_skbuff->data,
|
| 2414 |
|
|
PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
|
| 2415 |
|
|
lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
|
| 2416 |
|
|
lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
|
| 2417 |
|
|
wmb(); /* Make sure owner changes after all others are visible */
|
| 2418 |
|
|
lp->rx_ring[i].status = cpu_to_le16(0x8000);
|
| 2419 |
|
|
}
|
| 2420 |
|
|
/* The Tx buffer address is filled in as needed, but we do need to clear
|
| 2421 |
|
|
* the upper ownership bit. */
|
| 2422 |
|
|
for (i = 0; i < lp->tx_ring_size; i++) {
|
| 2423 |
|
|
lp->tx_ring[i].status = 0; /* CPU owns buffer */
|
| 2424 |
|
|
wmb(); /* Make sure adapter sees owner change */
|
| 2425 |
|
|
lp->tx_ring[i].base = 0;
|
| 2426 |
|
|
lp->tx_dma_addr[i] = 0;
|
| 2427 |
|
|
}
|
| 2428 |
|
|
|
| 2429 |
|
|
lp->init_block->tlen_rlen =
|
| 2430 |
|
|
cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
|
| 2431 |
|
|
for (i = 0; i < 6; i++)
|
| 2432 |
|
|
lp->init_block->phys_addr[i] = dev->dev_addr[i];
|
| 2433 |
|
|
lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
|
| 2434 |
|
|
lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
|
| 2435 |
|
|
wmb(); /* Make sure all changes are visible */
|
| 2436 |
|
|
return 0;
|
| 2437 |
|
|
}
|
| 2438 |
|
|
|
| 2439 |
|
|
/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
|
| 2440 |
|
|
* then flush the pending transmit operations, re-initialize the ring,
|
| 2441 |
|
|
* and tell the chip to initialize.
|
| 2442 |
|
|
*/
|
| 2443 |
|
|
static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
|
| 2444 |
|
|
{
|
| 2445 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2446 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2447 |
|
|
int i;
|
| 2448 |
|
|
|
| 2449 |
|
|
/* wait for stop */
|
| 2450 |
|
|
for (i = 0; i < 100; i++)
|
| 2451 |
|
|
if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
|
| 2452 |
|
|
break;
|
| 2453 |
|
|
|
| 2454 |
|
|
if (i >= 100 && netif_msg_drv(lp))
|
| 2455 |
|
|
printk(KERN_ERR
|
| 2456 |
|
|
"%s: pcnet32_restart timed out waiting for stop.\n",
|
| 2457 |
|
|
dev->name);
|
| 2458 |
|
|
|
| 2459 |
|
|
pcnet32_purge_tx_ring(dev);
|
| 2460 |
|
|
if (pcnet32_init_ring(dev))
|
| 2461 |
|
|
return;
|
| 2462 |
|
|
|
| 2463 |
|
|
/* ReInit Ring */
|
| 2464 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
|
| 2465 |
|
|
i = 0;
|
| 2466 |
|
|
while (i++ < 1000)
|
| 2467 |
|
|
if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
|
| 2468 |
|
|
break;
|
| 2469 |
|
|
|
| 2470 |
|
|
lp->a.write_csr(ioaddr, CSR0, csr0_bits);
|
| 2471 |
|
|
}
|
| 2472 |
|
|
|
| 2473 |
|
|
static void pcnet32_tx_timeout(struct net_device *dev)
|
| 2474 |
|
|
{
|
| 2475 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2476 |
|
|
unsigned long ioaddr = dev->base_addr, flags;
|
| 2477 |
|
|
|
| 2478 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2479 |
|
|
/* Transmitter timeout, serious problems. */
|
| 2480 |
|
|
if (pcnet32_debug & NETIF_MSG_DRV)
|
| 2481 |
|
|
printk(KERN_ERR
|
| 2482 |
|
|
"%s: transmit timed out, status %4.4x, resetting.\n",
|
| 2483 |
|
|
dev->name, lp->a.read_csr(ioaddr, CSR0));
|
| 2484 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
|
| 2485 |
|
|
dev->stats.tx_errors++;
|
| 2486 |
|
|
if (netif_msg_tx_err(lp)) {
|
| 2487 |
|
|
int i;
|
| 2488 |
|
|
printk(KERN_DEBUG
|
| 2489 |
|
|
" Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
|
| 2490 |
|
|
lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
|
| 2491 |
|
|
lp->cur_rx);
|
| 2492 |
|
|
for (i = 0; i < lp->rx_ring_size; i++)
|
| 2493 |
|
|
printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
|
| 2494 |
|
|
le32_to_cpu(lp->rx_ring[i].base),
|
| 2495 |
|
|
(-le16_to_cpu(lp->rx_ring[i].buf_length)) &
|
| 2496 |
|
|
0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
|
| 2497 |
|
|
le16_to_cpu(lp->rx_ring[i].status));
|
| 2498 |
|
|
for (i = 0; i < lp->tx_ring_size; i++)
|
| 2499 |
|
|
printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
|
| 2500 |
|
|
le32_to_cpu(lp->tx_ring[i].base),
|
| 2501 |
|
|
(-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
|
| 2502 |
|
|
le32_to_cpu(lp->tx_ring[i].misc),
|
| 2503 |
|
|
le16_to_cpu(lp->tx_ring[i].status));
|
| 2504 |
|
|
printk("\n");
|
| 2505 |
|
|
}
|
| 2506 |
|
|
pcnet32_restart(dev, CSR0_NORMAL);
|
| 2507 |
|
|
|
| 2508 |
|
|
dev->trans_start = jiffies;
|
| 2509 |
|
|
netif_wake_queue(dev);
|
| 2510 |
|
|
|
| 2511 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2512 |
|
|
}
|
| 2513 |
|
|
|
| 2514 |
|
|
static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
| 2515 |
|
|
{
|
| 2516 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2517 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2518 |
|
|
u16 status;
|
| 2519 |
|
|
int entry;
|
| 2520 |
|
|
unsigned long flags;
|
| 2521 |
|
|
|
| 2522 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2523 |
|
|
|
| 2524 |
|
|
if (netif_msg_tx_queued(lp)) {
|
| 2525 |
|
|
printk(KERN_DEBUG
|
| 2526 |
|
|
"%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
|
| 2527 |
|
|
dev->name, lp->a.read_csr(ioaddr, CSR0));
|
| 2528 |
|
|
}
|
| 2529 |
|
|
|
| 2530 |
|
|
/* Default status -- will not enable Successful-TxDone
|
| 2531 |
|
|
* interrupt when that option is available to us.
|
| 2532 |
|
|
*/
|
| 2533 |
|
|
status = 0x8300;
|
| 2534 |
|
|
|
| 2535 |
|
|
/* Fill in a Tx ring entry */
|
| 2536 |
|
|
|
| 2537 |
|
|
/* Mask to ring buffer boundary. */
|
| 2538 |
|
|
entry = lp->cur_tx & lp->tx_mod_mask;
|
| 2539 |
|
|
|
| 2540 |
|
|
/* Caution: the write order is important here, set the status
|
| 2541 |
|
|
* with the "ownership" bits last. */
|
| 2542 |
|
|
|
| 2543 |
|
|
lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
|
| 2544 |
|
|
|
| 2545 |
|
|
lp->tx_ring[entry].misc = 0x00000000;
|
| 2546 |
|
|
|
| 2547 |
|
|
lp->tx_skbuff[entry] = skb;
|
| 2548 |
|
|
lp->tx_dma_addr[entry] =
|
| 2549 |
|
|
pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
|
| 2550 |
|
|
lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
|
| 2551 |
|
|
wmb(); /* Make sure owner changes after all others are visible */
|
| 2552 |
|
|
lp->tx_ring[entry].status = cpu_to_le16(status);
|
| 2553 |
|
|
|
| 2554 |
|
|
lp->cur_tx++;
|
| 2555 |
|
|
dev->stats.tx_bytes += skb->len;
|
| 2556 |
|
|
|
| 2557 |
|
|
/* Trigger an immediate send poll. */
|
| 2558 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
|
| 2559 |
|
|
|
| 2560 |
|
|
dev->trans_start = jiffies;
|
| 2561 |
|
|
|
| 2562 |
|
|
if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
|
| 2563 |
|
|
lp->tx_full = 1;
|
| 2564 |
|
|
netif_stop_queue(dev);
|
| 2565 |
|
|
}
|
| 2566 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2567 |
|
|
return 0;
|
| 2568 |
|
|
}
|
| 2569 |
|
|
|
| 2570 |
|
|
/* The PCNET32 interrupt handler. */
|
| 2571 |
|
|
static irqreturn_t
|
| 2572 |
|
|
pcnet32_interrupt(int irq, void *dev_id)
|
| 2573 |
|
|
{
|
| 2574 |
|
|
struct net_device *dev = dev_id;
|
| 2575 |
|
|
struct pcnet32_private *lp;
|
| 2576 |
|
|
unsigned long ioaddr;
|
| 2577 |
|
|
u16 csr0;
|
| 2578 |
|
|
int boguscnt = max_interrupt_work;
|
| 2579 |
|
|
|
| 2580 |
|
|
ioaddr = dev->base_addr;
|
| 2581 |
|
|
lp = netdev_priv(dev);
|
| 2582 |
|
|
|
| 2583 |
|
|
spin_lock(&lp->lock);
|
| 2584 |
|
|
|
| 2585 |
|
|
csr0 = lp->a.read_csr(ioaddr, CSR0);
|
| 2586 |
|
|
while ((csr0 & 0x8f00) && --boguscnt >= 0) {
|
| 2587 |
|
|
if (csr0 == 0xffff) {
|
| 2588 |
|
|
break; /* PCMCIA remove happened */
|
| 2589 |
|
|
}
|
| 2590 |
|
|
/* Acknowledge all of the current interrupt sources ASAP. */
|
| 2591 |
|
|
lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
|
| 2592 |
|
|
|
| 2593 |
|
|
if (netif_msg_intr(lp))
|
| 2594 |
|
|
printk(KERN_DEBUG
|
| 2595 |
|
|
"%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
|
| 2596 |
|
|
dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
|
| 2597 |
|
|
|
| 2598 |
|
|
/* Log misc errors. */
|
| 2599 |
|
|
if (csr0 & 0x4000)
|
| 2600 |
|
|
dev->stats.tx_errors++; /* Tx babble. */
|
| 2601 |
|
|
if (csr0 & 0x1000) {
|
| 2602 |
|
|
/*
|
| 2603 |
|
|
* This happens when our receive ring is full. This
|
| 2604 |
|
|
* shouldn't be a problem as we will see normal rx
|
| 2605 |
|
|
* interrupts for the frames in the receive ring. But
|
| 2606 |
|
|
* there are some PCI chipsets (I can reproduce this
|
| 2607 |
|
|
* on SP3G with Intel saturn chipset) which have
|
| 2608 |
|
|
* sometimes problems and will fill up the receive
|
| 2609 |
|
|
* ring with error descriptors. In this situation we
|
| 2610 |
|
|
* don't get a rx interrupt, but a missed frame
|
| 2611 |
|
|
* interrupt sooner or later.
|
| 2612 |
|
|
*/
|
| 2613 |
|
|
dev->stats.rx_errors++; /* Missed a Rx frame. */
|
| 2614 |
|
|
}
|
| 2615 |
|
|
if (csr0 & 0x0800) {
|
| 2616 |
|
|
if (netif_msg_drv(lp))
|
| 2617 |
|
|
printk(KERN_ERR
|
| 2618 |
|
|
"%s: Bus master arbitration failure, status %4.4x.\n",
|
| 2619 |
|
|
dev->name, csr0);
|
| 2620 |
|
|
/* unlike for the lance, there is no restart needed */
|
| 2621 |
|
|
}
|
| 2622 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 2623 |
|
|
if (netif_rx_schedule_prep(dev, &lp->napi)) {
|
| 2624 |
|
|
u16 val;
|
| 2625 |
|
|
/* set interrupt masks */
|
| 2626 |
|
|
val = lp->a.read_csr(ioaddr, CSR3);
|
| 2627 |
|
|
val |= 0x5f00;
|
| 2628 |
|
|
lp->a.write_csr(ioaddr, CSR3, val);
|
| 2629 |
|
|
mmiowb();
|
| 2630 |
|
|
__netif_rx_schedule(dev, &lp->napi);
|
| 2631 |
|
|
break;
|
| 2632 |
|
|
}
|
| 2633 |
|
|
#else
|
| 2634 |
|
|
pcnet32_rx(dev, lp->napi.weight);
|
| 2635 |
|
|
if (pcnet32_tx(dev)) {
|
| 2636 |
|
|
/* reset the chip to clear the error condition, then restart */
|
| 2637 |
|
|
lp->a.reset(ioaddr);
|
| 2638 |
|
|
lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
|
| 2639 |
|
|
pcnet32_restart(dev, CSR0_START);
|
| 2640 |
|
|
netif_wake_queue(dev);
|
| 2641 |
|
|
}
|
| 2642 |
|
|
#endif
|
| 2643 |
|
|
csr0 = lp->a.read_csr(ioaddr, CSR0);
|
| 2644 |
|
|
}
|
| 2645 |
|
|
|
| 2646 |
|
|
#ifndef CONFIG_PCNET32_NAPI
|
| 2647 |
|
|
/* Set interrupt enable. */
|
| 2648 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
|
| 2649 |
|
|
#endif
|
| 2650 |
|
|
|
| 2651 |
|
|
if (netif_msg_intr(lp))
|
| 2652 |
|
|
printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
|
| 2653 |
|
|
dev->name, lp->a.read_csr(ioaddr, CSR0));
|
| 2654 |
|
|
|
| 2655 |
|
|
spin_unlock(&lp->lock);
|
| 2656 |
|
|
|
| 2657 |
|
|
return IRQ_HANDLED;
|
| 2658 |
|
|
}
|
| 2659 |
|
|
|
| 2660 |
|
|
static int pcnet32_close(struct net_device *dev)
|
| 2661 |
|
|
{
|
| 2662 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2663 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2664 |
|
|
unsigned long flags;
|
| 2665 |
|
|
|
| 2666 |
|
|
del_timer_sync(&lp->watchdog_timer);
|
| 2667 |
|
|
|
| 2668 |
|
|
netif_stop_queue(dev);
|
| 2669 |
|
|
#ifdef CONFIG_PCNET32_NAPI
|
| 2670 |
|
|
napi_disable(&lp->napi);
|
| 2671 |
|
|
#endif
|
| 2672 |
|
|
|
| 2673 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2674 |
|
|
|
| 2675 |
|
|
dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
|
| 2676 |
|
|
|
| 2677 |
|
|
if (netif_msg_ifdown(lp))
|
| 2678 |
|
|
printk(KERN_DEBUG
|
| 2679 |
|
|
"%s: Shutting down ethercard, status was %2.2x.\n",
|
| 2680 |
|
|
dev->name, lp->a.read_csr(ioaddr, CSR0));
|
| 2681 |
|
|
|
| 2682 |
|
|
/* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
|
| 2683 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
|
| 2684 |
|
|
|
| 2685 |
|
|
/*
|
| 2686 |
|
|
* Switch back to 16bit mode to avoid problems with dumb
|
| 2687 |
|
|
* DOS packet driver after a warm reboot
|
| 2688 |
|
|
*/
|
| 2689 |
|
|
lp->a.write_bcr(ioaddr, 20, 4);
|
| 2690 |
|
|
|
| 2691 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2692 |
|
|
|
| 2693 |
|
|
free_irq(dev->irq, dev);
|
| 2694 |
|
|
|
| 2695 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2696 |
|
|
|
| 2697 |
|
|
pcnet32_purge_rx_ring(dev);
|
| 2698 |
|
|
pcnet32_purge_tx_ring(dev);
|
| 2699 |
|
|
|
| 2700 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2701 |
|
|
|
| 2702 |
|
|
return 0;
|
| 2703 |
|
|
}
|
| 2704 |
|
|
|
| 2705 |
|
|
static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
|
| 2706 |
|
|
{
|
| 2707 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2708 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2709 |
|
|
unsigned long flags;
|
| 2710 |
|
|
|
| 2711 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2712 |
|
|
dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
|
| 2713 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2714 |
|
|
|
| 2715 |
|
|
return &dev->stats;
|
| 2716 |
|
|
}
|
| 2717 |
|
|
|
| 2718 |
|
|
/* taken from the sunlance driver, which it took from the depca driver */
|
| 2719 |
|
|
static void pcnet32_load_multicast(struct net_device *dev)
|
| 2720 |
|
|
{
|
| 2721 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2722 |
|
|
volatile struct pcnet32_init_block *ib = lp->init_block;
|
| 2723 |
|
|
volatile __le16 *mcast_table = (__le16 *)ib->filter;
|
| 2724 |
|
|
struct dev_mc_list *dmi = dev->mc_list;
|
| 2725 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2726 |
|
|
char *addrs;
|
| 2727 |
|
|
int i;
|
| 2728 |
|
|
u32 crc;
|
| 2729 |
|
|
|
| 2730 |
|
|
/* set all multicast bits */
|
| 2731 |
|
|
if (dev->flags & IFF_ALLMULTI) {
|
| 2732 |
|
|
ib->filter[0] = cpu_to_le32(~0U);
|
| 2733 |
|
|
ib->filter[1] = cpu_to_le32(~0U);
|
| 2734 |
|
|
lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
|
| 2735 |
|
|
lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
|
| 2736 |
|
|
lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
|
| 2737 |
|
|
lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
|
| 2738 |
|
|
return;
|
| 2739 |
|
|
}
|
| 2740 |
|
|
/* clear the multicast filter */
|
| 2741 |
|
|
ib->filter[0] = 0;
|
| 2742 |
|
|
ib->filter[1] = 0;
|
| 2743 |
|
|
|
| 2744 |
|
|
/* Add addresses */
|
| 2745 |
|
|
for (i = 0; i < dev->mc_count; i++) {
|
| 2746 |
|
|
addrs = dmi->dmi_addr;
|
| 2747 |
|
|
dmi = dmi->next;
|
| 2748 |
|
|
|
| 2749 |
|
|
/* multicast address? */
|
| 2750 |
|
|
if (!(*addrs & 1))
|
| 2751 |
|
|
continue;
|
| 2752 |
|
|
|
| 2753 |
|
|
crc = ether_crc_le(6, addrs);
|
| 2754 |
|
|
crc = crc >> 26;
|
| 2755 |
|
|
mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
|
| 2756 |
|
|
}
|
| 2757 |
|
|
for (i = 0; i < 4; i++)
|
| 2758 |
|
|
lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
|
| 2759 |
|
|
le16_to_cpu(mcast_table[i]));
|
| 2760 |
|
|
return;
|
| 2761 |
|
|
}
|
| 2762 |
|
|
|
| 2763 |
|
|
/*
|
| 2764 |
|
|
* Set or clear the multicast filter for this adaptor.
|
| 2765 |
|
|
*/
|
| 2766 |
|
|
static void pcnet32_set_multicast_list(struct net_device *dev)
|
| 2767 |
|
|
{
|
| 2768 |
|
|
unsigned long ioaddr = dev->base_addr, flags;
|
| 2769 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2770 |
|
|
int csr15, suspended;
|
| 2771 |
|
|
|
| 2772 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2773 |
|
|
suspended = pcnet32_suspend(dev, &flags, 0);
|
| 2774 |
|
|
csr15 = lp->a.read_csr(ioaddr, CSR15);
|
| 2775 |
|
|
if (dev->flags & IFF_PROMISC) {
|
| 2776 |
|
|
/* Log any net taps. */
|
| 2777 |
|
|
if (netif_msg_hw(lp))
|
| 2778 |
|
|
printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
|
| 2779 |
|
|
dev->name);
|
| 2780 |
|
|
lp->init_block->mode =
|
| 2781 |
|
|
cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
|
| 2782 |
|
|
7);
|
| 2783 |
|
|
lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
|
| 2784 |
|
|
} else {
|
| 2785 |
|
|
lp->init_block->mode =
|
| 2786 |
|
|
cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
|
| 2787 |
|
|
lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
|
| 2788 |
|
|
pcnet32_load_multicast(dev);
|
| 2789 |
|
|
}
|
| 2790 |
|
|
|
| 2791 |
|
|
if (suspended) {
|
| 2792 |
|
|
int csr5;
|
| 2793 |
|
|
/* clear SUSPEND (SPND) - CSR5 bit 0 */
|
| 2794 |
|
|
csr5 = lp->a.read_csr(ioaddr, CSR5);
|
| 2795 |
|
|
lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
|
| 2796 |
|
|
} else {
|
| 2797 |
|
|
lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
|
| 2798 |
|
|
pcnet32_restart(dev, CSR0_NORMAL);
|
| 2799 |
|
|
netif_wake_queue(dev);
|
| 2800 |
|
|
}
|
| 2801 |
|
|
|
| 2802 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2803 |
|
|
}
|
| 2804 |
|
|
|
| 2805 |
|
|
/* This routine assumes that the lp->lock is held */
|
| 2806 |
|
|
static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
|
| 2807 |
|
|
{
|
| 2808 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2809 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2810 |
|
|
u16 val_out;
|
| 2811 |
|
|
|
| 2812 |
|
|
if (!lp->mii)
|
| 2813 |
|
|
return 0;
|
| 2814 |
|
|
|
| 2815 |
|
|
lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
|
| 2816 |
|
|
val_out = lp->a.read_bcr(ioaddr, 34);
|
| 2817 |
|
|
|
| 2818 |
|
|
return val_out;
|
| 2819 |
|
|
}
|
| 2820 |
|
|
|
| 2821 |
|
|
/* This routine assumes that the lp->lock is held */
|
| 2822 |
|
|
static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
|
| 2823 |
|
|
{
|
| 2824 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2825 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 2826 |
|
|
|
| 2827 |
|
|
if (!lp->mii)
|
| 2828 |
|
|
return;
|
| 2829 |
|
|
|
| 2830 |
|
|
lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
|
| 2831 |
|
|
lp->a.write_bcr(ioaddr, 34, val);
|
| 2832 |
|
|
}
|
| 2833 |
|
|
|
| 2834 |
|
|
static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
| 2835 |
|
|
{
|
| 2836 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2837 |
|
|
int rc;
|
| 2838 |
|
|
unsigned long flags;
|
| 2839 |
|
|
|
| 2840 |
|
|
/* SIOC[GS]MIIxxx ioctls */
|
| 2841 |
|
|
if (lp->mii) {
|
| 2842 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2843 |
|
|
rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
|
| 2844 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2845 |
|
|
} else {
|
| 2846 |
|
|
rc = -EOPNOTSUPP;
|
| 2847 |
|
|
}
|
| 2848 |
|
|
|
| 2849 |
|
|
return rc;
|
| 2850 |
|
|
}
|
| 2851 |
|
|
|
| 2852 |
|
|
static int pcnet32_check_otherphy(struct net_device *dev)
|
| 2853 |
|
|
{
|
| 2854 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2855 |
|
|
struct mii_if_info mii = lp->mii_if;
|
| 2856 |
|
|
u16 bmcr;
|
| 2857 |
|
|
int i;
|
| 2858 |
|
|
|
| 2859 |
|
|
for (i = 0; i < PCNET32_MAX_PHYS; i++) {
|
| 2860 |
|
|
if (i == lp->mii_if.phy_id)
|
| 2861 |
|
|
continue; /* skip active phy */
|
| 2862 |
|
|
if (lp->phymask & (1 << i)) {
|
| 2863 |
|
|
mii.phy_id = i;
|
| 2864 |
|
|
if (mii_link_ok(&mii)) {
|
| 2865 |
|
|
/* found PHY with active link */
|
| 2866 |
|
|
if (netif_msg_link(lp))
|
| 2867 |
|
|
printk(KERN_INFO
|
| 2868 |
|
|
"%s: Using PHY number %d.\n",
|
| 2869 |
|
|
dev->name, i);
|
| 2870 |
|
|
|
| 2871 |
|
|
/* isolate inactive phy */
|
| 2872 |
|
|
bmcr =
|
| 2873 |
|
|
mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
|
| 2874 |
|
|
mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
|
| 2875 |
|
|
bmcr | BMCR_ISOLATE);
|
| 2876 |
|
|
|
| 2877 |
|
|
/* de-isolate new phy */
|
| 2878 |
|
|
bmcr = mdio_read(dev, i, MII_BMCR);
|
| 2879 |
|
|
mdio_write(dev, i, MII_BMCR,
|
| 2880 |
|
|
bmcr & ~BMCR_ISOLATE);
|
| 2881 |
|
|
|
| 2882 |
|
|
/* set new phy address */
|
| 2883 |
|
|
lp->mii_if.phy_id = i;
|
| 2884 |
|
|
return 1;
|
| 2885 |
|
|
}
|
| 2886 |
|
|
}
|
| 2887 |
|
|
}
|
| 2888 |
|
|
return 0;
|
| 2889 |
|
|
}
|
| 2890 |
|
|
|
| 2891 |
|
|
/*
|
| 2892 |
|
|
* Show the status of the media. Similar to mii_check_media however it
|
| 2893 |
|
|
* correctly shows the link speed for all (tested) pcnet32 variants.
|
| 2894 |
|
|
* Devices with no mii just report link state without speed.
|
| 2895 |
|
|
*
|
| 2896 |
|
|
* Caller is assumed to hold and release the lp->lock.
|
| 2897 |
|
|
*/
|
| 2898 |
|
|
|
| 2899 |
|
|
static void pcnet32_check_media(struct net_device *dev, int verbose)
|
| 2900 |
|
|
{
|
| 2901 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2902 |
|
|
int curr_link;
|
| 2903 |
|
|
int prev_link = netif_carrier_ok(dev) ? 1 : 0;
|
| 2904 |
|
|
u32 bcr9;
|
| 2905 |
|
|
|
| 2906 |
|
|
if (lp->mii) {
|
| 2907 |
|
|
curr_link = mii_link_ok(&lp->mii_if);
|
| 2908 |
|
|
} else {
|
| 2909 |
|
|
ulong ioaddr = dev->base_addr; /* card base I/O address */
|
| 2910 |
|
|
curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
|
| 2911 |
|
|
}
|
| 2912 |
|
|
if (!curr_link) {
|
| 2913 |
|
|
if (prev_link || verbose) {
|
| 2914 |
|
|
netif_carrier_off(dev);
|
| 2915 |
|
|
if (netif_msg_link(lp))
|
| 2916 |
|
|
printk(KERN_INFO "%s: link down\n", dev->name);
|
| 2917 |
|
|
}
|
| 2918 |
|
|
if (lp->phycount > 1) {
|
| 2919 |
|
|
curr_link = pcnet32_check_otherphy(dev);
|
| 2920 |
|
|
prev_link = 0;
|
| 2921 |
|
|
}
|
| 2922 |
|
|
} else if (verbose || !prev_link) {
|
| 2923 |
|
|
netif_carrier_on(dev);
|
| 2924 |
|
|
if (lp->mii) {
|
| 2925 |
|
|
if (netif_msg_link(lp)) {
|
| 2926 |
|
|
struct ethtool_cmd ecmd;
|
| 2927 |
|
|
mii_ethtool_gset(&lp->mii_if, &ecmd);
|
| 2928 |
|
|
printk(KERN_INFO
|
| 2929 |
|
|
"%s: link up, %sMbps, %s-duplex\n",
|
| 2930 |
|
|
dev->name,
|
| 2931 |
|
|
(ecmd.speed == SPEED_100) ? "100" : "10",
|
| 2932 |
|
|
(ecmd.duplex ==
|
| 2933 |
|
|
DUPLEX_FULL) ? "full" : "half");
|
| 2934 |
|
|
}
|
| 2935 |
|
|
bcr9 = lp->a.read_bcr(dev->base_addr, 9);
|
| 2936 |
|
|
if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
|
| 2937 |
|
|
if (lp->mii_if.full_duplex)
|
| 2938 |
|
|
bcr9 |= (1 << 0);
|
| 2939 |
|
|
else
|
| 2940 |
|
|
bcr9 &= ~(1 << 0);
|
| 2941 |
|
|
lp->a.write_bcr(dev->base_addr, 9, bcr9);
|
| 2942 |
|
|
}
|
| 2943 |
|
|
} else {
|
| 2944 |
|
|
if (netif_msg_link(lp))
|
| 2945 |
|
|
printk(KERN_INFO "%s: link up\n", dev->name);
|
| 2946 |
|
|
}
|
| 2947 |
|
|
}
|
| 2948 |
|
|
}
|
| 2949 |
|
|
|
| 2950 |
|
|
/*
|
| 2951 |
|
|
* Check for loss of link and link establishment.
|
| 2952 |
|
|
* Can not use mii_check_media because it does nothing if mode is forced.
|
| 2953 |
|
|
*/
|
| 2954 |
|
|
|
| 2955 |
|
|
static void pcnet32_watchdog(struct net_device *dev)
|
| 2956 |
|
|
{
|
| 2957 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 2958 |
|
|
unsigned long flags;
|
| 2959 |
|
|
|
| 2960 |
|
|
/* Print the link status if it has changed */
|
| 2961 |
|
|
spin_lock_irqsave(&lp->lock, flags);
|
| 2962 |
|
|
pcnet32_check_media(dev, 0);
|
| 2963 |
|
|
spin_unlock_irqrestore(&lp->lock, flags);
|
| 2964 |
|
|
|
| 2965 |
|
|
mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
|
| 2966 |
|
|
}
|
| 2967 |
|
|
|
| 2968 |
|
|
static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
|
| 2969 |
|
|
{
|
| 2970 |
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
| 2971 |
|
|
|
| 2972 |
|
|
if (netif_running(dev)) {
|
| 2973 |
|
|
netif_device_detach(dev);
|
| 2974 |
|
|
pcnet32_close(dev);
|
| 2975 |
|
|
}
|
| 2976 |
|
|
pci_save_state(pdev);
|
| 2977 |
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
| 2978 |
|
|
return 0;
|
| 2979 |
|
|
}
|
| 2980 |
|
|
|
| 2981 |
|
|
static int pcnet32_pm_resume(struct pci_dev *pdev)
|
| 2982 |
|
|
{
|
| 2983 |
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
| 2984 |
|
|
|
| 2985 |
|
|
pci_set_power_state(pdev, PCI_D0);
|
| 2986 |
|
|
pci_restore_state(pdev);
|
| 2987 |
|
|
|
| 2988 |
|
|
if (netif_running(dev)) {
|
| 2989 |
|
|
pcnet32_open(dev);
|
| 2990 |
|
|
netif_device_attach(dev);
|
| 2991 |
|
|
}
|
| 2992 |
|
|
return 0;
|
| 2993 |
|
|
}
|
| 2994 |
|
|
|
| 2995 |
|
|
static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
|
| 2996 |
|
|
{
|
| 2997 |
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
| 2998 |
|
|
|
| 2999 |
|
|
if (dev) {
|
| 3000 |
|
|
struct pcnet32_private *lp = netdev_priv(dev);
|
| 3001 |
|
|
|
| 3002 |
|
|
unregister_netdev(dev);
|
| 3003 |
|
|
pcnet32_free_ring(dev);
|
| 3004 |
|
|
release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
|
| 3005 |
|
|
pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
|
| 3006 |
|
|
lp->init_block, lp->init_dma_addr);
|
| 3007 |
|
|
free_netdev(dev);
|
| 3008 |
|
|
pci_disable_device(pdev);
|
| 3009 |
|
|
pci_set_drvdata(pdev, NULL);
|
| 3010 |
|
|
}
|
| 3011 |
|
|
}
|
| 3012 |
|
|
|
| 3013 |
|
|
static struct pci_driver pcnet32_driver = {
|
| 3014 |
|
|
.name = DRV_NAME,
|
| 3015 |
|
|
.probe = pcnet32_probe_pci,
|
| 3016 |
|
|
.remove = __devexit_p(pcnet32_remove_one),
|
| 3017 |
|
|
.id_table = pcnet32_pci_tbl,
|
| 3018 |
|
|
.suspend = pcnet32_pm_suspend,
|
| 3019 |
|
|
.resume = pcnet32_pm_resume,
|
| 3020 |
|
|
};
|
| 3021 |
|
|
|
| 3022 |
|
|
/* An additional parameter that may be passed in... */
|
| 3023 |
|
|
static int debug = -1;
|
| 3024 |
|
|
static int tx_start_pt = -1;
|
| 3025 |
|
|
static int pcnet32_have_pci;
|
| 3026 |
|
|
|
| 3027 |
|
|
module_param(debug, int, 0);
|
| 3028 |
|
|
MODULE_PARM_DESC(debug, DRV_NAME " debug level");
|
| 3029 |
|
|
module_param(max_interrupt_work, int, 0);
|
| 3030 |
|
|
MODULE_PARM_DESC(max_interrupt_work,
|
| 3031 |
|
|
DRV_NAME " maximum events handled per interrupt");
|
| 3032 |
|
|
module_param(rx_copybreak, int, 0);
|
| 3033 |
|
|
MODULE_PARM_DESC(rx_copybreak,
|
| 3034 |
|
|
DRV_NAME " copy breakpoint for copy-only-tiny-frames");
|
| 3035 |
|
|
module_param(tx_start_pt, int, 0);
|
| 3036 |
|
|
MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
|
| 3037 |
|
|
module_param(pcnet32vlb, int, 0);
|
| 3038 |
|
|
MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
|
| 3039 |
|
|
module_param_array(options, int, NULL, 0);
|
| 3040 |
|
|
MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
|
| 3041 |
|
|
module_param_array(full_duplex, int, NULL, 0);
|
| 3042 |
|
|
MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
|
| 3043 |
|
|
/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
|
| 3044 |
|
|
module_param_array(homepna, int, NULL, 0);
|
| 3045 |
|
|
MODULE_PARM_DESC(homepna,
|
| 3046 |
|
|
DRV_NAME
|
| 3047 |
|
|
" mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
|
| 3048 |
|
|
|
| 3049 |
|
|
MODULE_AUTHOR("Thomas Bogendoerfer");
|
| 3050 |
|
|
MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
|
| 3051 |
|
|
MODULE_LICENSE("GPL");
|
| 3052 |
|
|
|
| 3053 |
|
|
#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
|
| 3054 |
|
|
|
| 3055 |
|
|
static int __init pcnet32_init_module(void)
|
| 3056 |
|
|
{
|
| 3057 |
|
|
printk(KERN_INFO "%s", version);
|
| 3058 |
|
|
|
| 3059 |
|
|
pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
|
| 3060 |
|
|
|
| 3061 |
|
|
if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
|
| 3062 |
|
|
tx_start = tx_start_pt;
|
| 3063 |
|
|
|
| 3064 |
|
|
/* find the PCI devices */
|
| 3065 |
|
|
if (!pci_register_driver(&pcnet32_driver))
|
| 3066 |
|
|
pcnet32_have_pci = 1;
|
| 3067 |
|
|
|
| 3068 |
|
|
/* should we find any remaining VLbus devices ? */
|
| 3069 |
|
|
if (pcnet32vlb)
|
| 3070 |
|
|
pcnet32_probe_vlbus(pcnet32_portlist);
|
| 3071 |
|
|
|
| 3072 |
|
|
if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
|
| 3073 |
|
|
printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
|
| 3074 |
|
|
|
| 3075 |
|
|
return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
|
| 3076 |
|
|
}
|
| 3077 |
|
|
|
| 3078 |
|
|
static void __exit pcnet32_cleanup_module(void)
|
| 3079 |
|
|
{
|
| 3080 |
|
|
struct net_device *next_dev;
|
| 3081 |
|
|
|
| 3082 |
|
|
while (pcnet32_dev) {
|
| 3083 |
|
|
struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
|
| 3084 |
|
|
next_dev = lp->next;
|
| 3085 |
|
|
unregister_netdev(pcnet32_dev);
|
| 3086 |
|
|
pcnet32_free_ring(pcnet32_dev);
|
| 3087 |
|
|
release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
|
| 3088 |
|
|
pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
|
| 3089 |
|
|
lp->init_block, lp->init_dma_addr);
|
| 3090 |
|
|
free_netdev(pcnet32_dev);
|
| 3091 |
|
|
pcnet32_dev = next_dev;
|
| 3092 |
|
|
}
|
| 3093 |
|
|
|
| 3094 |
|
|
if (pcnet32_have_pci)
|
| 3095 |
|
|
pci_unregister_driver(&pcnet32_driver);
|
| 3096 |
|
|
}
|
| 3097 |
|
|
|
| 3098 |
|
|
module_init(pcnet32_init_module);
|
| 3099 |
|
|
module_exit(pcnet32_cleanup_module);
|
| 3100 |
|
|
|
| 3101 |
|
|
/*
|
| 3102 |
|
|
* Local variables:
|
| 3103 |
|
|
* c-indent-level: 4
|
| 3104 |
|
|
* tab-width: 8
|
| 3105 |
|
|
* End:
|
| 3106 |
|
|
*/
|
