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/*

 * QLogic QLA3xxx NIC HBA Driver

 * Copyright (c)  2003-2006 QLogic Corporation

 *

 * See LICENSE.qla3xxx for copyright and licensing details.

 */

#ifndef _QLA3XXX_H_

#define _QLA3XXX_H_

/*

 * IOCB Definitions...

 */

#pragma pack(1)

#define OPCODE_OB_MAC_IOCB_FN0          0x01

#define OPCODE_OB_MAC_IOCB_FN2          0x21

#define OPCODE_OB_TCP_IOCB_FN0          0x03

#define OPCODE_OB_TCP_IOCB_FN2          0x23

#define OPCODE_UPDATE_NCB_IOCB_FN0      0x00

#define OPCODE_UPDATE_NCB_IOCB_FN2      0x20

#define OPCODE_UPDATE_NCB_IOCB      0xF0

#define OPCODE_IB_MAC_IOCB          0xF9

#define OPCODE_IB_3032_MAC_IOCB     0x09

#define OPCODE_IB_IP_IOCB           0xFA

#define OPCODE_IB_3032_IP_IOCB      0x0A

#define OPCODE_IB_TCP_IOCB          0xFB

#define OPCODE_DUMP_PROTO_IOCB      0xFE

#define OPCODE_BUFFER_ALERT_IOCB    0xFB

#define OPCODE_FUNC_ID_MASK                 0x30

#define OUTBOUND_MAC_IOCB                   0x01        /* plus function bits */

#define OUTBOUND_TCP_IOCB                   0x03        /* plus function bits */

#define UPDATE_NCB_IOCB                     0x00        /* plus function bits */

#define FN0_MA_BITS_MASK    0x00

#define FN1_MA_BITS_MASK    0x80

struct ob_mac_iocb_req {

        u8 opcode;

        u8 flags;

#define OB_MAC_IOCB_REQ_MA  0xe0

#define OB_MAC_IOCB_REQ_F   0x10

#define OB_MAC_IOCB_REQ_X   0x08

#define OB_MAC_IOCB_REQ_D   0x02

#define OB_MAC_IOCB_REQ_I   0x01

        u8 flags1;

#define OB_3032MAC_IOCB_REQ_IC  0x04

#define OB_3032MAC_IOCB_REQ_TC  0x02

#define OB_3032MAC_IOCB_REQ_UC  0x01

        u8 reserved0;

        __le32 transaction_id;

        __le16 data_len;

        u8 ip_hdr_off;

        u8 ip_hdr_len;

        __le32 reserved1;

        __le32 reserved2;

        __le32 buf_addr0_low;

        __le32 buf_addr0_high;

        __le32 buf_0_len;

        __le32 buf_addr1_low;

        __le32 buf_addr1_high;

        __le32 buf_1_len;

        __le32 buf_addr2_low;

        __le32 buf_addr2_high;

        __le32 buf_2_len;

        __le32 reserved3;

        __le32 reserved4;

};

/*

 * The following constants define control bits for buffer

 * length fields for all IOCB's.

 */

#define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */

#define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */

#define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */

#define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */

struct ob_mac_iocb_rsp {

        u8 opcode;

        u8 flags;

#define OB_MAC_IOCB_RSP_P   0x08

#define OB_MAC_IOCB_RSP_L   0x04

#define OB_MAC_IOCB_RSP_S   0x02

#define OB_MAC_IOCB_RSP_I   0x01

        __le16 reserved0;

        __le32 transaction_id;

        __le32 reserved1;

        __le32 reserved2;

};

struct ib_mac_iocb_rsp {

        u8 opcode;

#define IB_MAC_IOCB_RSP_V   0x80

        u8 flags;

#define IB_MAC_IOCB_RSP_S   0x80

#define IB_MAC_IOCB_RSP_H1  0x40

#define IB_MAC_IOCB_RSP_H0  0x20

#define IB_MAC_IOCB_RSP_B   0x10

#define IB_MAC_IOCB_RSP_M   0x08

#define IB_MAC_IOCB_RSP_MA  0x07

        __le16 length;

        __le32 reserved;

        __le32 ial_low;

        __le32 ial_high;

};

struct ob_ip_iocb_req {

        u8 opcode;

        __le16 flags;

#define OB_IP_IOCB_REQ_O        0x100

#define OB_IP_IOCB_REQ_H        0x008

#define OB_IP_IOCB_REQ_U        0x004

#define OB_IP_IOCB_REQ_D        0x002

#define OB_IP_IOCB_REQ_I        0x001

        u8 reserved0;

        __le32 transaction_id;

        __le16 data_len;

        __le16 reserved1;

        __le32 hncb_ptr_low;

        __le32 hncb_ptr_high;

        __le32 buf_addr0_low;

        __le32 buf_addr0_high;

        __le32 buf_0_len;

        __le32 buf_addr1_low;

        __le32 buf_addr1_high;

        __le32 buf_1_len;

        __le32 buf_addr2_low;

        __le32 buf_addr2_high;

        __le32 buf_2_len;

        __le32 reserved2;

        __le32 reserved3;

};

/* defines for BufferLength fields above */

#define OB_IP_IOCB_REQ_E    0x80000000

#define OB_IP_IOCB_REQ_C    0x40000000

#define OB_IP_IOCB_REQ_L    0x20000000

#define OB_IP_IOCB_REQ_R    0x10000000

struct ob_ip_iocb_rsp {

        u8 opcode;

        u8 flags;

#define OB_MAC_IOCB_RSP_H       0x10

#define OB_MAC_IOCB_RSP_E       0x08

#define OB_MAC_IOCB_RSP_L       0x04

#define OB_MAC_IOCB_RSP_S       0x02

#define OB_MAC_IOCB_RSP_I       0x01

        __le16 reserved0;

        __le32 transaction_id;

        __le32 reserved1;

        __le32 reserved2;

};

struct ob_tcp_iocb_req {

        u8 opcode;

        u8 flags0;

#define OB_TCP_IOCB_REQ_P       0x80

#define OB_TCP_IOCB_REQ_CI      0x20

#define OB_TCP_IOCB_REQ_H       0x10

#define OB_TCP_IOCB_REQ_LN      0x08

#define OB_TCP_IOCB_REQ_K       0x04

#define OB_TCP_IOCB_REQ_D       0x02

#define OB_TCP_IOCB_REQ_I       0x01

        u8 flags1;

#define OB_TCP_IOCB_REQ_OSM     0x40

#define OB_TCP_IOCB_REQ_URG     0x20

#define OB_TCP_IOCB_REQ_ACK     0x10

#define OB_TCP_IOCB_REQ_PSH     0x08

#define OB_TCP_IOCB_REQ_RST     0x04

#define OB_TCP_IOCB_REQ_SYN     0x02

#define OB_TCP_IOCB_REQ_FIN     0x01

        u8 options_len;

#define OB_TCP_IOCB_REQ_OMASK   0xF0

#define OB_TCP_IOCB_REQ_SHIFT   4

        __le32 transaction_id;

        __le32 data_len;

        __le32 hncb_ptr_low;

        __le32 hncb_ptr_high;

        __le32 buf_addr0_low;

        __le32 buf_addr0_high;

        __le32 buf_0_len;

        __le32 buf_addr1_low;

        __le32 buf_addr1_high;

        __le32 buf_1_len;

        __le32 buf_addr2_low;

        __le32 buf_addr2_high;

        __le32 buf_2_len;

        __le32 time_stamp;

        __le32 reserved1;

};

struct ob_tcp_iocb_rsp {

        u8 opcode;

        u8 flags0;

#define OB_TCP_IOCB_RSP_C       0x20

#define OB_TCP_IOCB_RSP_H       0x10

#define OB_TCP_IOCB_RSP_LN      0x08

#define OB_TCP_IOCB_RSP_K       0x04

#define OB_TCP_IOCB_RSP_D       0x02

#define OB_TCP_IOCB_RSP_I       0x01

        u8 flags1;

#define OB_TCP_IOCB_RSP_E       0x10

#define OB_TCP_IOCB_RSP_W       0x08

#define OB_TCP_IOCB_RSP_P       0x04

#define OB_TCP_IOCB_RSP_T       0x02

#define OB_TCP_IOCB_RSP_F       0x01

        u8 state;

#define OB_TCP_IOCB_RSP_SMASK   0xF0

#define OB_TCP_IOCB_RSP_SHIFT   4

        __le32 transaction_id;

        __le32 local_ncb_ptr;

        __le32 reserved0;

};

struct ib_ip_iocb_rsp {

        u8 opcode;

#define IB_IP_IOCB_RSP_3032_V   0x80

#define IB_IP_IOCB_RSP_3032_O   0x40

#define IB_IP_IOCB_RSP_3032_I   0x20

#define IB_IP_IOCB_RSP_3032_R   0x10

        u8 flags;

#define IB_IP_IOCB_RSP_S        0x80

#define IB_IP_IOCB_RSP_H1       0x40

#define IB_IP_IOCB_RSP_H0       0x20

#define IB_IP_IOCB_RSP_B        0x10

#define IB_IP_IOCB_RSP_M        0x08

#define IB_IP_IOCB_RSP_MA       0x07

        __le16 length;

        __le16 checksum;

#define IB_IP_IOCB_RSP_3032_ICE         0x01

#define IB_IP_IOCB_RSP_3032_CE          0x02

#define IB_IP_IOCB_RSP_3032_NUC         0x04

#define IB_IP_IOCB_RSP_3032_UDP         0x08

#define IB_IP_IOCB_RSP_3032_TCP         0x10

#define IB_IP_IOCB_RSP_3032_IPE         0x20

        __le16 reserved;

#define IB_IP_IOCB_RSP_R        0x01

        __le32 ial_low;

        __le32 ial_high;

};

struct ib_tcp_iocb_rsp {

        u8 opcode;

        u8 flags;

#define IB_TCP_IOCB_RSP_P       0x80

#define IB_TCP_IOCB_RSP_T       0x40

#define IB_TCP_IOCB_RSP_D       0x20

#define IB_TCP_IOCB_RSP_N       0x10

#define IB_TCP_IOCB_RSP_IP      0x03

#define IB_TCP_FLAG_MASK        0xf0

#define IB_TCP_FLAG_IOCB_SYN    0x00

#define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)

        __le16 length;

        __le32 hncb_ref_num;

        __le32 ial_low;

        __le32 ial_high;

};

struct net_rsp_iocb {

        u8 opcode;

        u8 flags;

        __le16 reserved0;

        __le32 reserved[3];

};

#pragma pack()

/*

 * Register Definitions...

 */

#define PORT0_PHY_ADDRESS   0x1e00

#define PORT1_PHY_ADDRESS   0x1f00

#define ETHERNET_CRC_SIZE   4

#define MII_SCAN_REGISTER 0x00000001

#define PHY_ID_0_REG    2

#define PHY_ID_1_REG    3

#define PHY_OUI_1_MASK       0xfc00

#define PHY_MODEL_MASK       0x03f0

/*  Address for the Agere Phy */

#define MII_AGERE_ADDR_1  0x00001000

#define MII_AGERE_ADDR_2  0x00001100

/* 32-bit ispControlStatus */

enum {

        ISP_CONTROL_NP_MASK = 0x0003,

        ISP_CONTROL_NP_PCSR = 0x0000,

        ISP_CONTROL_NP_HMCR = 0x0001,

        ISP_CONTROL_NP_LRAMCR = 0x0002,

        ISP_CONTROL_NP_PSR = 0x0003,

        ISP_CONTROL_RI = 0x0008,

        ISP_CONTROL_CI = 0x0010,

        ISP_CONTROL_PI = 0x0020,

        ISP_CONTROL_IN = 0x0040,

        ISP_CONTROL_BE = 0x0080,

        ISP_CONTROL_FN_MASK = 0x0700,

        ISP_CONTROL_FN0_NET = 0x0400,

        ISP_CONTROL_FN0_SCSI = 0x0500,

        ISP_CONTROL_FN1_NET = 0x0600,

        ISP_CONTROL_FN1_SCSI = 0x0700,

        ISP_CONTROL_LINK_DN_0 = 0x0800,

        ISP_CONTROL_LINK_DN_1 = 0x1000,

        ISP_CONTROL_FSR = 0x2000,

        ISP_CONTROL_FE = 0x4000,

        ISP_CONTROL_SR = 0x8000,

};

/* 32-bit ispInterruptMaskReg */

enum {

        ISP_IMR_ENABLE_INT = 0x0004,

        ISP_IMR_DISABLE_RESET_INT = 0x0008,

        ISP_IMR_DISABLE_CMPL_INT = 0x0010,

        ISP_IMR_DISABLE_PROC_INT = 0x0020,

};

/* 32-bit serialPortInterfaceReg */

enum {

        ISP_SERIAL_PORT_IF_CLK = 0x0001,

        ISP_SERIAL_PORT_IF_CS = 0x0002,

        ISP_SERIAL_PORT_IF_D0 = 0x0004,

        ISP_SERIAL_PORT_IF_DI = 0x0008,

        ISP_NVRAM_MASK = (0x000F << 16),

        ISP_SERIAL_PORT_IF_WE = 0x0010,

        ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,

        ISP_SERIAL_PORT_IF_SCI = 0x0400,

        ISP_SERIAL_PORT_IF_SC0 = 0x0800,

        ISP_SERIAL_PORT_IF_SCE = 0x1000,

        ISP_SERIAL_PORT_IF_SDI = 0x2000,

        ISP_SERIAL_PORT_IF_SDO = 0x4000,

        ISP_SERIAL_PORT_IF_SDE = 0x8000,

        ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,

};

/* semaphoreReg */

enum {

        QL_RESOURCE_MASK_BASE_CODE = 0x7,

        QL_RESOURCE_BITS_BASE_CODE = 0x4,

        QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),

        QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),

        QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),

        QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),

        QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),

        QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),

        QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),

        QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),

        QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),

        QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),

};

 /*

  * QL3XXX memory-mapped registers

  * QL3XXX has 4 "pages" of registers, each page occupying

  * 256 bytes.  Each page has a "common" area at the start and then

  * page-specific registers after that.

  */

struct ql3xxx_common_registers {

        u32 MB0;                /* Offset 0x00 */

        u32 MB1;                /* Offset 0x04 */

        u32 MB2;                /* Offset 0x08 */

        u32 MB3;                /* Offset 0x0c */

        u32 MB4;                /* Offset 0x10 */

        u32 MB5;                /* Offset 0x14 */

        u32 MB6;                /* Offset 0x18 */

        u32 MB7;                /* Offset 0x1c */

        u32 flashBiosAddr;

        u32 flashBiosData;

        u32 ispControlStatus;

        u32 ispInterruptMaskReg;

        u32 serialPortInterfaceReg;

        u32 semaphoreReg;

        u32 reqQProducerIndex;

        u32 rspQConsumerIndex;

        u32 rxLargeQProducerIndex;

        u32 rxSmallQProducerIndex;

        u32 arcMadiCommand;

        u32 arcMadiData;

};

enum {

        EXT_HW_CONFIG_SP_MASK = 0x0006,

        EXT_HW_CONFIG_SP_NONE = 0x0000,

        EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,

        EXT_HW_CONFIG_SP_ECC = 0x0004,

        EXT_HW_CONFIG_SP_ECCx = 0x0006,

        EXT_HW_CONFIG_SIZE_MASK = 0x0060,

        EXT_HW_CONFIG_SIZE_128M = 0x0000,

        EXT_HW_CONFIG_SIZE_256M = 0x0020,

        EXT_HW_CONFIG_SIZE_512M = 0x0040,

        EXT_HW_CONFIG_SIZE_INVALID = 0x0060,

        EXT_HW_CONFIG_PD = 0x0080,

        EXT_HW_CONFIG_FW = 0x0200,

        EXT_HW_CONFIG_US = 0x0400,

        EXT_HW_CONFIG_DCS_MASK = 0x1800,

        EXT_HW_CONFIG_DCS_9MA = 0x0000,

        EXT_HW_CONFIG_DCS_15MA = 0x0800,

        EXT_HW_CONFIG_DCS_18MA = 0x1000,

        EXT_HW_CONFIG_DCS_24MA = 0x1800,

        EXT_HW_CONFIG_DDS_MASK = 0x6000,

        EXT_HW_CONFIG_DDS_9MA = 0x0000,

        EXT_HW_CONFIG_DDS_15MA = 0x2000,

        EXT_HW_CONFIG_DDS_18MA = 0x4000,

        EXT_HW_CONFIG_DDS_24MA = 0x6000,

};

/* InternalChipConfig */

enum {

        INTERNAL_CHIP_DM = 0x0001,

        INTERNAL_CHIP_SD = 0x0002,

        INTERNAL_CHIP_RAP_MASK = 0x000C,

        INTERNAL_CHIP_RAP_RR = 0x0000,

        INTERNAL_CHIP_RAP_NRM = 0x0004,

        INTERNAL_CHIP_RAP_ERM = 0x0008,

        INTERNAL_CHIP_RAP_ERMx = 0x000C,

        INTERNAL_CHIP_WE = 0x0010,

        INTERNAL_CHIP_EF = 0x0020,

        INTERNAL_CHIP_FR = 0x0040,

        INTERNAL_CHIP_FW = 0x0080,

        INTERNAL_CHIP_FI = 0x0100,

        INTERNAL_CHIP_FT = 0x0200,

};

/* portControl */

enum {

        PORT_CONTROL_DS = 0x0001,

        PORT_CONTROL_HH = 0x0002,

        PORT_CONTROL_EI = 0x0004,

        PORT_CONTROL_ET = 0x0008,

        PORT_CONTROL_EF = 0x0010,

        PORT_CONTROL_DRM = 0x0020,

        PORT_CONTROL_RLB = 0x0040,

        PORT_CONTROL_RCB = 0x0080,

        PORT_CONTROL_MAC = 0x0100,

        PORT_CONTROL_IPV = 0x0200,

        PORT_CONTROL_IFP = 0x0400,

        PORT_CONTROL_ITP = 0x0800,

        PORT_CONTROL_FI = 0x1000,

        PORT_CONTROL_DFP = 0x2000,

        PORT_CONTROL_OI = 0x4000,

        PORT_CONTROL_CC = 0x8000,

};

/* portStatus */

enum {

        PORT_STATUS_SM0 = 0x0001,

        PORT_STATUS_SM1 = 0x0002,

        PORT_STATUS_X = 0x0008,

        PORT_STATUS_DL = 0x0080,

        PORT_STATUS_IC = 0x0200,

        PORT_STATUS_MRC = 0x0400,

        PORT_STATUS_NL = 0x0800,

        PORT_STATUS_REV_ID_MASK = 0x7000,

        PORT_STATUS_REV_ID_1 = 0x1000,

        PORT_STATUS_REV_ID_2 = 0x2000,

        PORT_STATUS_REV_ID_3 = 0x3000,

        PORT_STATUS_64 = 0x8000,

        PORT_STATUS_UP0 = 0x10000,

        PORT_STATUS_AC0 = 0x20000,

        PORT_STATUS_AE0 = 0x40000,

        PORT_STATUS_UP1 = 0x100000,

        PORT_STATUS_AC1 = 0x200000,

        PORT_STATUS_AE1 = 0x400000,

        PORT_STATUS_F0_ENABLED = 0x1000000,

        PORT_STATUS_F1_ENABLED = 0x2000000,

        PORT_STATUS_F2_ENABLED = 0x4000000,

        PORT_STATUS_F3_ENABLED = 0x8000000,

};

/* macMIIMgmtControlReg */

enum {

        MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,

        MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,

        MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,

        MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,

        MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,

        MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,

        MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,

        MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,

        MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,

        MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,

};

/* macMIIMgmtControlReg */

enum {

        MAC_MII_CONTROL_RC = 0x0001,

        MAC_MII_CONTROL_SC = 0x0002,

        MAC_MII_CONTROL_AS = 0x0004,

        MAC_MII_CONTROL_NP = 0x0008,

        MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,

        MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,

        MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,

        MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,

        MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,

        MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,

        MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,

        MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,

        MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,

        MAC_MII_CONTROL_RM = 0x8000,

};

/* macMIIStatusReg */

enum {

        MAC_MII_STATUS_BSY = 0x0001,

        MAC_MII_STATUS_SC = 0x0002,

        MAC_MII_STATUS_NV = 0x0004,

};

enum {

        MAC_CONFIG_REG_PE = 0x0001,

        MAC_CONFIG_REG_TF = 0x0002,

        MAC_CONFIG_REG_RF = 0x0004,

        MAC_CONFIG_REG_FD = 0x0008,

        MAC_CONFIG_REG_GM = 0x0010,

        MAC_CONFIG_REG_LB = 0x0020,

        MAC_CONFIG_REG_SR = 0x8000,

};

enum {

        MAC_HALF_DUPLEX_REG_ED = 0x10000,

        MAC_HALF_DUPLEX_REG_NB = 0x20000,

        MAC_HALF_DUPLEX_REG_BNB = 0x40000,

        MAC_HALF_DUPLEX_REG_ALT = 0x80000,

};

enum {

        IP_ADDR_INDEX_REG_MASK = 0x000f,

        IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,

        IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,

        IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,

        IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,

        IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,

        IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,

        IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,

        IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,

        IP_ADDR_INDEX_REG_6 = 0x0008,

        IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,

        IP_ADDR_INDEX_REG_E = 0x0040,

};

enum {

        QL3032_PORT_CONTROL_DS = 0x0001,

        QL3032_PORT_CONTROL_HH = 0x0002,

        QL3032_PORT_CONTROL_EIv6 = 0x0004,

        QL3032_PORT_CONTROL_EIv4 = 0x0008,

        QL3032_PORT_CONTROL_ET = 0x0010,

        QL3032_PORT_CONTROL_EF = 0x0020,

        QL3032_PORT_CONTROL_DRM = 0x0040,

        QL3032_PORT_CONTROL_RLB = 0x0080,

        QL3032_PORT_CONTROL_RCB = 0x0100,

        QL3032_PORT_CONTROL_KIE = 0x0200,

};

enum {

        PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,

        PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,

        PROBE_MUX_ADDR_REG_PCICLK = 0x0040,

        PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,

        PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,

        PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,

        PROBE_MUX_ADDR_REG_UP = 0x4000,

        PROBE_MUX_ADDR_REG_RE = 0x8000,

};

enum {

        STATISTICS_INDEX_REG_MASK = 0x01ff,

        STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,

        STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,

        STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,

        STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,

        STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,

        STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,

        STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,

        STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,

        STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,

        STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,

        STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,

        STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,

        STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,

        STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,

        STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,

        STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,

        STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,

        STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,

        STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,

        STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,

        STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,

        STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,

        STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,

        STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,

        STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,

        STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,

        STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,

        STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,

        STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,

        STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,

        STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,

        STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,

        STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,

        STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,

        STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,

        STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,

        STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,

        STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,

        STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,

        STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,

        STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,

        STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,

        STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,

        STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,

        STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,

        STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,

        STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,

        STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,

        STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,

        STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,

        STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,

        STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,

};

enum {

        PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,

        PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,

        PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,

        PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,

        PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,

        PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,

        PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,

        PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,

        PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,

        PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,

        PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,

        PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,

        PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,

        PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,

        PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,

        PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,

        PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,

        PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,

        PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,

        PORT_FATAL_ERROR_STATUS_TA = 0x00080000,

        PORT_FATAL_ERROR_STATUS_MA = 0x00100000,

        PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,

        PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,

        PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,

        PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,

};

/*

 *  port control and status page - page 0

 */

struct ql3xxx_port_registers {

        struct ql3xxx_common_registers CommonRegs;

        u32 ExternalHWConfig;

        u32 InternalChipConfig;

        u32 portControl;

        u32 portStatus;

        u32 macAddrIndirectPtrReg;

        u32 macAddrDataReg;

        u32 macMIIMgmtControlReg;

        u32 macMIIMgmtAddrReg;

        u32 macMIIMgmtDataReg;

        u32 macMIIStatusReg;

        u32 mac0ConfigReg;

        u32 mac0IpgIfgReg;

        u32 mac0HalfDuplexReg;

        u32 mac0MaxFrameLengthReg;

        u32 mac0PauseThresholdReg;

        u32 mac1ConfigReg;

        u32 mac1IpgIfgReg;

        u32 mac1HalfDuplexReg;

        u32 mac1MaxFrameLengthReg;

        u32 mac1PauseThresholdReg;

        u32 ipAddrIndexReg;

        u32 ipAddrDataReg;

        u32 ipReassemblyTimeout;

        u32 tcpMaxWindow;

        u32 currentTcpTimestamp[2];

        u32 internalRamRWAddrReg;

        u32 internalRamWDataReg;

        u32 reclaimedBufferAddrRegLow;

        u32 reclaimedBufferAddrRegHigh;

        u32 tcpConfiguration;

        u32 functionControl;

        u32 fpgaRevID;

        u32 localRamAddr;

        u32 localRamDataAutoIncr;

        u32 localRamDataNonIncr;

        u32 gpOutput;

        u32 gpInput;

        u32 probeMuxAddr;

        u32 probeMuxData;

        u32 statisticsIndexReg;

        u32 statisticsReadDataRegAutoIncr;

        u32 statisticsReadDataRegNoIncr;

        u32 PortFatalErrStatus;

};

/*

 * port host memory config page - page 1

 */

struct ql3xxx_host_memory_registers {

        struct ql3xxx_common_registers CommonRegs;

        u32 reserved[12];

        /* Network Request Queue */

        u32 reqConsumerIndex;

        u32 reqConsumerIndexAddrLow;

        u32 reqConsumerIndexAddrHigh;

        u32 reqBaseAddrLow;

        u32 reqBaseAddrHigh;

        u32 reqLength;

        /* Network Completion Queue */

        u32 rspProducerIndex;

        u32 rspProducerIndexAddrLow;

        u32 rspProducerIndexAddrHigh;

        u32 rspBaseAddrLow;

        u32 rspBaseAddrHigh;

        u32 rspLength;

        /* RX Large Buffer Queue */

        u32 rxLargeQConsumerIndex;

        u32 rxLargeQBaseAddrLow;

        u32 rxLargeQBaseAddrHigh;