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marcus.erl |
/*
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* Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
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*
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* Author: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE UCC Gigabit Ethernet Driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/workqueue.h>
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#include <asm/of_platform.h>
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#include <asm/uaccess.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/immap_qe.h>
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#include <asm/qe.h>
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#include <asm/ucc.h>
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#include <asm/ucc_fast.h>
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#include "ucc_geth.h"
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#include "ucc_geth_mii.h"
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#undef DEBUG
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#define ugeth_printk(level, format, arg...) \
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printk(level format "\n", ## arg)
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#define ugeth_dbg(format, arg...) \
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ugeth_printk(KERN_DEBUG , format , ## arg)
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#define ugeth_err(format, arg...) \
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ugeth_printk(KERN_ERR , format , ## arg)
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#define ugeth_info(format, arg...) \
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ugeth_printk(KERN_INFO , format , ## arg)
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#define ugeth_warn(format, arg...) \
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ugeth_printk(KERN_WARNING , format , ## arg)
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#ifdef UGETH_VERBOSE_DEBUG
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#define ugeth_vdbg ugeth_dbg
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#else
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#define ugeth_vdbg(fmt, args...) do { } while (0)
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#endif /* UGETH_VERBOSE_DEBUG */
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#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
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void uec_set_ethtool_ops(struct net_device *netdev);
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static DEFINE_SPINLOCK(ugeth_lock);
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static struct {
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u32 msg_enable;
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} debug = { -1 };
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module_param_named(debug, debug.msg_enable, int, 0);
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MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
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static struct ucc_geth_info ugeth_primary_info = {
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.uf_info = {
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.bd_mem_part = MEM_PART_SYSTEM,
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.rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
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.max_rx_buf_length = 1536,
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/* adjusted at startup if max-speed 1000 */
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.urfs = UCC_GETH_URFS_INIT,
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.urfet = UCC_GETH_URFET_INIT,
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.urfset = UCC_GETH_URFSET_INIT,
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.utfs = UCC_GETH_UTFS_INIT,
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.utfet = UCC_GETH_UTFET_INIT,
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.utftt = UCC_GETH_UTFTT_INIT,
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.ufpt = 256,
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.mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
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.ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
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.tenc = UCC_FAST_TX_ENCODING_NRZ,
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.renc = UCC_FAST_RX_ENCODING_NRZ,
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.tcrc = UCC_FAST_16_BIT_CRC,
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.synl = UCC_FAST_SYNC_LEN_NOT_USED,
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},
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.numQueuesTx = 1,
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.numQueuesRx = 1,
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.extendedFilteringChainPointer = ((uint32_t) NULL),
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.typeorlen = 3072 /*1536 */ ,
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.nonBackToBackIfgPart1 = 0x40,
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.nonBackToBackIfgPart2 = 0x60,
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.miminumInterFrameGapEnforcement = 0x50,
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.backToBackInterFrameGap = 0x60,
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.mblinterval = 128,
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.nortsrbytetime = 5,
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.fracsiz = 1,
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.strictpriorityq = 0xff,
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.altBebTruncation = 0xa,
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.excessDefer = 1,
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.maxRetransmission = 0xf,
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.collisionWindow = 0x37,
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.receiveFlowControl = 1,
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.transmitFlowControl = 1,
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.maxGroupAddrInHash = 4,
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.maxIndAddrInHash = 4,
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.prel = 7,
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.maxFrameLength = 1518,
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.minFrameLength = 64,
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.maxD1Length = 1520,
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.maxD2Length = 1520,
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.vlantype = 0x8100,
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.ecamptr = ((uint32_t) NULL),
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.eventRegMask = UCCE_OTHER,
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.pausePeriod = 0xf000,
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.interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
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.bdRingLenTx = {
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN,
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TX_BD_RING_LEN},
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.bdRingLenRx = {
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN,
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RX_BD_RING_LEN},
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.numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
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.largestexternallookupkeysize =
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QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
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.statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
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UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
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UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
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.vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
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.vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
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.rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
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.aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
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.padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
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.numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
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.numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
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.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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};
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static struct ucc_geth_info ugeth_info[8];
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#ifdef DEBUG
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static void mem_disp(u8 *addr, int size)
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{
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u8 *i;
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int size16Aling = (size >> 4) << 4;
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int size4Aling = (size >> 2) << 2;
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int notAlign = 0;
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if (size % 16)
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notAlign = 1;
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for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
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printk("0x%08x: %08x %08x %08x %08x\r\n",
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(u32) i,
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*((u32 *) (i)),
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*((u32 *) (i + 4)),
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*((u32 *) (i + 8)), *((u32 *) (i + 12)));
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if (notAlign == 1)
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printk("0x%08x: ", (u32) i);
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for (; (u32) i < (u32) addr + size4Aling; i += 4)
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printk("%08x ", *((u32 *) (i)));
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for (; (u32) i < (u32) addr + size; i++)
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printk("%02x", *((u8 *) (i)));
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if (notAlign == 1)
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printk("\r\n");
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}
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#endif /* DEBUG */
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#ifdef CONFIG_UGETH_FILTERING
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static void enqueue(struct list_head *node, struct list_head *lh)
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{
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unsigned long flags;
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spin_lock_irqsave(&ugeth_lock, flags);
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list_add_tail(node, lh);
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spin_unlock_irqrestore(&ugeth_lock, flags);
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}
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#endif /* CONFIG_UGETH_FILTERING */
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static struct list_head *dequeue(struct list_head *lh)
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{
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unsigned long flags;
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spin_lock_irqsave(&ugeth_lock, flags);
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if (!list_empty(lh)) {
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struct list_head *node = lh->next;
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list_del(node);
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spin_unlock_irqrestore(&ugeth_lock, flags);
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return node;
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} else {
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spin_unlock_irqrestore(&ugeth_lock, flags);
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return NULL;
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}
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}
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| 219 |
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static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
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{
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struct sk_buff *skb = NULL;
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skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
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UCC_GETH_RX_DATA_BUF_ALIGNMENT);
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if (skb == NULL)
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return NULL;
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| 229 |
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/* We need the data buffer to be aligned properly. We will reserve
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* as many bytes as needed to align the data properly
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*/
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skb_reserve(skb,
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UCC_GETH_RX_DATA_BUF_ALIGNMENT -
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(((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
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1)));
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skb->dev = ugeth->dev;
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out_be32(&((struct qe_bd *)bd)->buf,
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dma_map_single(NULL,
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skb->data,
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ugeth->ug_info->uf_info.max_rx_buf_length +
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UCC_GETH_RX_DATA_BUF_ALIGNMENT,
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DMA_FROM_DEVICE));
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out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
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| 248 |
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return skb;
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}
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| 250 |
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| 251 |
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static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
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{
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u8 *bd;
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u32 bd_status;
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| 255 |
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struct sk_buff *skb;
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| 256 |
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int i;
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| 257 |
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| 258 |
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bd = ugeth->p_rx_bd_ring[rxQ];
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| 259 |
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i = 0;
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| 260 |
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| 261 |
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do {
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| 262 |
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bd_status = in_be32((u32*)bd);
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| 263 |
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skb = get_new_skb(ugeth, bd);
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| 264 |
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| 265 |
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if (!skb) /* If can not allocate data buffer,
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abort. Cleanup will be elsewhere */
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| 267 |
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return -ENOMEM;
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| 268 |
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| 269 |
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ugeth->rx_skbuff[rxQ][i] = skb;
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| 270 |
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| 271 |
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/* advance the BD pointer */
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bd += sizeof(struct qe_bd);
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i++;
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| 274 |
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} while (!(bd_status & R_W));
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| 275 |
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| 276 |
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return 0;
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| 277 |
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}
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| 278 |
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| 279 |
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static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
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| 280 |
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volatile u32 *p_start,
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| 281 |
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u8 num_entries,
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| 282 |
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u32 thread_size,
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| 283 |
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u32 thread_alignment,
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| 284 |
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enum qe_risc_allocation risc,
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| 285 |
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int skip_page_for_first_entry)
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| 286 |
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{
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| 287 |
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u32 init_enet_offset;
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| 288 |
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u8 i;
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| 289 |
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int snum;
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| 290 |
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| 291 |
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for (i = 0; i < num_entries; i++) {
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| 292 |
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if ((snum = qe_get_snum()) < 0) {
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| 293 |
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if (netif_msg_ifup(ugeth))
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| 294 |
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ugeth_err("fill_init_enet_entries: Can not get SNUM.");
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| 295 |
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return snum;
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| 296 |
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}
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| 297 |
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|
if ((i == 0) && skip_page_for_first_entry)
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| 298 |
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/* First entry of Rx does not have page */
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| 299 |
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init_enet_offset = 0;
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| 300 |
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else {
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| 301 |
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init_enet_offset =
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| 302 |
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qe_muram_alloc(thread_size, thread_alignment);
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| 303 |
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if (IS_ERR_VALUE(init_enet_offset)) {
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| 304 |
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if (netif_msg_ifup(ugeth))
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| 305 |
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ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
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| 306 |
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qe_put_snum((u8) snum);
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| 307 |
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return -ENOMEM;
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| 308 |
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}
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| 309 |
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}
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| 310 |
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*(p_start++) =
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| 311 |
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((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
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| 312 |
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| risc;
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| 313 |
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}
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| 314 |
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|
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| 315 |
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return 0;
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| 316 |
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}
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| 317 |
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|
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| 318 |
|
|
static int return_init_enet_entries(struct ucc_geth_private *ugeth,
|
| 319 |
|
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volatile u32 *p_start,
|
| 320 |
|
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u8 num_entries,
|
| 321 |
|
|
enum qe_risc_allocation risc,
|
| 322 |
|
|
int skip_page_for_first_entry)
|
| 323 |
|
|
{
|
| 324 |
|
|
u32 init_enet_offset;
|
| 325 |
|
|
u8 i;
|
| 326 |
|
|
int snum;
|
| 327 |
|
|
|
| 328 |
|
|
for (i = 0; i < num_entries; i++) {
|
| 329 |
|
|
/* Check that this entry was actually valid --
|
| 330 |
|
|
needed in case failed in allocations */
|
| 331 |
|
|
if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
|
| 332 |
|
|
snum =
|
| 333 |
|
|
(u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
|
| 334 |
|
|
ENET_INIT_PARAM_SNUM_SHIFT;
|
| 335 |
|
|
qe_put_snum((u8) snum);
|
| 336 |
|
|
if (!((i == 0) && skip_page_for_first_entry)) {
|
| 337 |
|
|
/* First entry of Rx does not have page */
|
| 338 |
|
|
init_enet_offset =
|
| 339 |
|
|
(in_be32(p_start) &
|
| 340 |
|
|
ENET_INIT_PARAM_PTR_MASK);
|
| 341 |
|
|
qe_muram_free(init_enet_offset);
|
| 342 |
|
|
}
|
| 343 |
|
|
*(p_start++) = 0; /* Just for cosmetics */
|
| 344 |
|
|
}
|
| 345 |
|
|
}
|
| 346 |
|
|
|
| 347 |
|
|
return 0;
|
| 348 |
|
|
}
|
| 349 |
|
|
|
| 350 |
|
|
#ifdef DEBUG
|
| 351 |
|
|
static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
|
| 352 |
|
|
volatile u32 *p_start,
|
| 353 |
|
|
u8 num_entries,
|
| 354 |
|
|
u32 thread_size,
|
| 355 |
|
|
enum qe_risc_allocation risc,
|
| 356 |
|
|
int skip_page_for_first_entry)
|
| 357 |
|
|
{
|
| 358 |
|
|
u32 init_enet_offset;
|
| 359 |
|
|
u8 i;
|
| 360 |
|
|
int snum;
|
| 361 |
|
|
|
| 362 |
|
|
for (i = 0; i < num_entries; i++) {
|
| 363 |
|
|
/* Check that this entry was actually valid --
|
| 364 |
|
|
needed in case failed in allocations */
|
| 365 |
|
|
if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
|
| 366 |
|
|
snum =
|
| 367 |
|
|
(u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
|
| 368 |
|
|
ENET_INIT_PARAM_SNUM_SHIFT;
|
| 369 |
|
|
qe_put_snum((u8) snum);
|
| 370 |
|
|
if (!((i == 0) && skip_page_for_first_entry)) {
|
| 371 |
|
|
/* First entry of Rx does not have page */
|
| 372 |
|
|
init_enet_offset =
|
| 373 |
|
|
(in_be32(p_start) &
|
| 374 |
|
|
ENET_INIT_PARAM_PTR_MASK);
|
| 375 |
|
|
ugeth_info("Init enet entry %d:", i);
|
| 376 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 377 |
|
|
(u32)
|
| 378 |
|
|
qe_muram_addr(init_enet_offset));
|
| 379 |
|
|
mem_disp(qe_muram_addr(init_enet_offset),
|
| 380 |
|
|
thread_size);
|
| 381 |
|
|
}
|
| 382 |
|
|
p_start++;
|
| 383 |
|
|
}
|
| 384 |
|
|
}
|
| 385 |
|
|
|
| 386 |
|
|
return 0;
|
| 387 |
|
|
}
|
| 388 |
|
|
#endif
|
| 389 |
|
|
|
| 390 |
|
|
#ifdef CONFIG_UGETH_FILTERING
|
| 391 |
|
|
static struct enet_addr_container *get_enet_addr_container(void)
|
| 392 |
|
|
{
|
| 393 |
|
|
struct enet_addr_container *enet_addr_cont;
|
| 394 |
|
|
|
| 395 |
|
|
/* allocate memory */
|
| 396 |
|
|
enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
|
| 397 |
|
|
if (!enet_addr_cont) {
|
| 398 |
|
|
ugeth_err("%s: No memory for enet_addr_container object.",
|
| 399 |
|
|
__FUNCTION__);
|
| 400 |
|
|
return NULL;
|
| 401 |
|
|
}
|
| 402 |
|
|
|
| 403 |
|
|
return enet_addr_cont;
|
| 404 |
|
|
}
|
| 405 |
|
|
#endif /* CONFIG_UGETH_FILTERING */
|
| 406 |
|
|
|
| 407 |
|
|
static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
|
| 408 |
|
|
{
|
| 409 |
|
|
kfree(enet_addr_cont);
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
|
| 413 |
|
|
{
|
| 414 |
|
|
out_be16(®[0], ((u16)mac[5] << 8) | mac[4]);
|
| 415 |
|
|
out_be16(®[1], ((u16)mac[3] << 8) | mac[2]);
|
| 416 |
|
|
out_be16(®[2], ((u16)mac[1] << 8) | mac[0]);
|
| 417 |
|
|
}
|
| 418 |
|
|
|
| 419 |
|
|
#ifdef CONFIG_UGETH_FILTERING
|
| 420 |
|
|
static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
|
| 421 |
|
|
u8 *p_enet_addr, u8 paddr_num)
|
| 422 |
|
|
{
|
| 423 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 424 |
|
|
|
| 425 |
|
|
if (!(paddr_num < NUM_OF_PADDRS)) {
|
| 426 |
|
|
ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
|
| 427 |
|
|
return -EINVAL;
|
| 428 |
|
|
}
|
| 429 |
|
|
|
| 430 |
|
|
p_82xx_addr_filt =
|
| 431 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
|
| 432 |
|
|
addressfiltering;
|
| 433 |
|
|
|
| 434 |
|
|
/* Ethernet frames are defined in Little Endian mode, */
|
| 435 |
|
|
/* therefore to insert the address we reverse the bytes. */
|
| 436 |
|
|
set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
|
| 437 |
|
|
return 0;
|
| 438 |
|
|
}
|
| 439 |
|
|
#endif /* CONFIG_UGETH_FILTERING */
|
| 440 |
|
|
|
| 441 |
|
|
static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
|
| 442 |
|
|
{
|
| 443 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 444 |
|
|
|
| 445 |
|
|
if (!(paddr_num < NUM_OF_PADDRS)) {
|
| 446 |
|
|
ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
|
| 447 |
|
|
return -EINVAL;
|
| 448 |
|
|
}
|
| 449 |
|
|
|
| 450 |
|
|
p_82xx_addr_filt =
|
| 451 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
|
| 452 |
|
|
addressfiltering;
|
| 453 |
|
|
|
| 454 |
|
|
/* Writing address ff.ff.ff.ff.ff.ff disables address
|
| 455 |
|
|
recognition for this register */
|
| 456 |
|
|
out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
|
| 457 |
|
|
out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
|
| 458 |
|
|
out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
|
| 459 |
|
|
|
| 460 |
|
|
return 0;
|
| 461 |
|
|
}
|
| 462 |
|
|
|
| 463 |
|
|
static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
|
| 464 |
|
|
u8 *p_enet_addr)
|
| 465 |
|
|
{
|
| 466 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 467 |
|
|
u32 cecr_subblock;
|
| 468 |
|
|
|
| 469 |
|
|
p_82xx_addr_filt =
|
| 470 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
|
| 471 |
|
|
addressfiltering;
|
| 472 |
|
|
|
| 473 |
|
|
cecr_subblock =
|
| 474 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
|
| 475 |
|
|
|
| 476 |
|
|
/* Ethernet frames are defined in Little Endian mode,
|
| 477 |
|
|
therefor to insert */
|
| 478 |
|
|
/* the address to the hash (Big Endian mode), we reverse the bytes.*/
|
| 479 |
|
|
|
| 480 |
|
|
set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
|
| 481 |
|
|
|
| 482 |
|
|
qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
|
| 483 |
|
|
QE_CR_PROTOCOL_ETHERNET, 0);
|
| 484 |
|
|
}
|
| 485 |
|
|
|
| 486 |
|
|
#ifdef CONFIG_UGETH_MAGIC_PACKET
|
| 487 |
|
|
static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
|
| 488 |
|
|
{
|
| 489 |
|
|
struct ucc_fast_private *uccf;
|
| 490 |
|
|
struct ucc_geth *ug_regs;
|
| 491 |
|
|
u32 maccfg2, uccm;
|
| 492 |
|
|
|
| 493 |
|
|
uccf = ugeth->uccf;
|
| 494 |
|
|
ug_regs = ugeth->ug_regs;
|
| 495 |
|
|
|
| 496 |
|
|
/* Enable interrupts for magic packet detection */
|
| 497 |
|
|
uccm = in_be32(uccf->p_uccm);
|
| 498 |
|
|
uccm |= UCCE_MPD;
|
| 499 |
|
|
out_be32(uccf->p_uccm, uccm);
|
| 500 |
|
|
|
| 501 |
|
|
/* Enable magic packet detection */
|
| 502 |
|
|
maccfg2 = in_be32(&ug_regs->maccfg2);
|
| 503 |
|
|
maccfg2 |= MACCFG2_MPE;
|
| 504 |
|
|
out_be32(&ug_regs->maccfg2, maccfg2);
|
| 505 |
|
|
}
|
| 506 |
|
|
|
| 507 |
|
|
static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
|
| 508 |
|
|
{
|
| 509 |
|
|
struct ucc_fast_private *uccf;
|
| 510 |
|
|
struct ucc_geth *ug_regs;
|
| 511 |
|
|
u32 maccfg2, uccm;
|
| 512 |
|
|
|
| 513 |
|
|
uccf = ugeth->uccf;
|
| 514 |
|
|
ug_regs = ugeth->ug_regs;
|
| 515 |
|
|
|
| 516 |
|
|
/* Disable interrupts for magic packet detection */
|
| 517 |
|
|
uccm = in_be32(uccf->p_uccm);
|
| 518 |
|
|
uccm &= ~UCCE_MPD;
|
| 519 |
|
|
out_be32(uccf->p_uccm, uccm);
|
| 520 |
|
|
|
| 521 |
|
|
/* Disable magic packet detection */
|
| 522 |
|
|
maccfg2 = in_be32(&ug_regs->maccfg2);
|
| 523 |
|
|
maccfg2 &= ~MACCFG2_MPE;
|
| 524 |
|
|
out_be32(&ug_regs->maccfg2, maccfg2);
|
| 525 |
|
|
}
|
| 526 |
|
|
#endif /* MAGIC_PACKET */
|
| 527 |
|
|
|
| 528 |
|
|
static inline int compare_addr(u8 **addr1, u8 **addr2)
|
| 529 |
|
|
{
|
| 530 |
|
|
return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
|
| 531 |
|
|
}
|
| 532 |
|
|
|
| 533 |
|
|
#ifdef DEBUG
|
| 534 |
|
|
static void get_statistics(struct ucc_geth_private *ugeth,
|
| 535 |
|
|
struct ucc_geth_tx_firmware_statistics *
|
| 536 |
|
|
tx_firmware_statistics,
|
| 537 |
|
|
struct ucc_geth_rx_firmware_statistics *
|
| 538 |
|
|
rx_firmware_statistics,
|
| 539 |
|
|
struct ucc_geth_hardware_statistics *hardware_statistics)
|
| 540 |
|
|
{
|
| 541 |
|
|
struct ucc_fast *uf_regs;
|
| 542 |
|
|
struct ucc_geth *ug_regs;
|
| 543 |
|
|
struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
|
| 544 |
|
|
struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
|
| 545 |
|
|
|
| 546 |
|
|
ug_regs = ugeth->ug_regs;
|
| 547 |
|
|
uf_regs = (struct ucc_fast *) ug_regs;
|
| 548 |
|
|
p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
|
| 549 |
|
|
p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
|
| 550 |
|
|
|
| 551 |
|
|
/* Tx firmware only if user handed pointer and driver actually
|
| 552 |
|
|
gathers Tx firmware statistics */
|
| 553 |
|
|
if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
|
| 554 |
|
|
tx_firmware_statistics->sicoltx =
|
| 555 |
|
|
in_be32(&p_tx_fw_statistics_pram->sicoltx);
|
| 556 |
|
|
tx_firmware_statistics->mulcoltx =
|
| 557 |
|
|
in_be32(&p_tx_fw_statistics_pram->mulcoltx);
|
| 558 |
|
|
tx_firmware_statistics->latecoltxfr =
|
| 559 |
|
|
in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
|
| 560 |
|
|
tx_firmware_statistics->frabortduecol =
|
| 561 |
|
|
in_be32(&p_tx_fw_statistics_pram->frabortduecol);
|
| 562 |
|
|
tx_firmware_statistics->frlostinmactxer =
|
| 563 |
|
|
in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
|
| 564 |
|
|
tx_firmware_statistics->carriersenseertx =
|
| 565 |
|
|
in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
|
| 566 |
|
|
tx_firmware_statistics->frtxok =
|
| 567 |
|
|
in_be32(&p_tx_fw_statistics_pram->frtxok);
|
| 568 |
|
|
tx_firmware_statistics->txfrexcessivedefer =
|
| 569 |
|
|
in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
|
| 570 |
|
|
tx_firmware_statistics->txpkts256 =
|
| 571 |
|
|
in_be32(&p_tx_fw_statistics_pram->txpkts256);
|
| 572 |
|
|
tx_firmware_statistics->txpkts512 =
|
| 573 |
|
|
in_be32(&p_tx_fw_statistics_pram->txpkts512);
|
| 574 |
|
|
tx_firmware_statistics->txpkts1024 =
|
| 575 |
|
|
in_be32(&p_tx_fw_statistics_pram->txpkts1024);
|
| 576 |
|
|
tx_firmware_statistics->txpktsjumbo =
|
| 577 |
|
|
in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
|
| 578 |
|
|
}
|
| 579 |
|
|
|
| 580 |
|
|
/* Rx firmware only if user handed pointer and driver actually
|
| 581 |
|
|
* gathers Rx firmware statistics */
|
| 582 |
|
|
if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
|
| 583 |
|
|
int i;
|
| 584 |
|
|
rx_firmware_statistics->frrxfcser =
|
| 585 |
|
|
in_be32(&p_rx_fw_statistics_pram->frrxfcser);
|
| 586 |
|
|
rx_firmware_statistics->fraligner =
|
| 587 |
|
|
in_be32(&p_rx_fw_statistics_pram->fraligner);
|
| 588 |
|
|
rx_firmware_statistics->inrangelenrxer =
|
| 589 |
|
|
in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
|
| 590 |
|
|
rx_firmware_statistics->outrangelenrxer =
|
| 591 |
|
|
in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
|
| 592 |
|
|
rx_firmware_statistics->frtoolong =
|
| 593 |
|
|
in_be32(&p_rx_fw_statistics_pram->frtoolong);
|
| 594 |
|
|
rx_firmware_statistics->runt =
|
| 595 |
|
|
in_be32(&p_rx_fw_statistics_pram->runt);
|
| 596 |
|
|
rx_firmware_statistics->verylongevent =
|
| 597 |
|
|
in_be32(&p_rx_fw_statistics_pram->verylongevent);
|
| 598 |
|
|
rx_firmware_statistics->symbolerror =
|
| 599 |
|
|
in_be32(&p_rx_fw_statistics_pram->symbolerror);
|
| 600 |
|
|
rx_firmware_statistics->dropbsy =
|
| 601 |
|
|
in_be32(&p_rx_fw_statistics_pram->dropbsy);
|
| 602 |
|
|
for (i = 0; i < 0x8; i++)
|
| 603 |
|
|
rx_firmware_statistics->res0[i] =
|
| 604 |
|
|
p_rx_fw_statistics_pram->res0[i];
|
| 605 |
|
|
rx_firmware_statistics->mismatchdrop =
|
| 606 |
|
|
in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
|
| 607 |
|
|
rx_firmware_statistics->underpkts =
|
| 608 |
|
|
in_be32(&p_rx_fw_statistics_pram->underpkts);
|
| 609 |
|
|
rx_firmware_statistics->pkts256 =
|
| 610 |
|
|
in_be32(&p_rx_fw_statistics_pram->pkts256);
|
| 611 |
|
|
rx_firmware_statistics->pkts512 =
|
| 612 |
|
|
in_be32(&p_rx_fw_statistics_pram->pkts512);
|
| 613 |
|
|
rx_firmware_statistics->pkts1024 =
|
| 614 |
|
|
in_be32(&p_rx_fw_statistics_pram->pkts1024);
|
| 615 |
|
|
rx_firmware_statistics->pktsjumbo =
|
| 616 |
|
|
in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
|
| 617 |
|
|
rx_firmware_statistics->frlossinmacer =
|
| 618 |
|
|
in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
|
| 619 |
|
|
rx_firmware_statistics->pausefr =
|
| 620 |
|
|
in_be32(&p_rx_fw_statistics_pram->pausefr);
|
| 621 |
|
|
for (i = 0; i < 0x4; i++)
|
| 622 |
|
|
rx_firmware_statistics->res1[i] =
|
| 623 |
|
|
p_rx_fw_statistics_pram->res1[i];
|
| 624 |
|
|
rx_firmware_statistics->removevlan =
|
| 625 |
|
|
in_be32(&p_rx_fw_statistics_pram->removevlan);
|
| 626 |
|
|
rx_firmware_statistics->replacevlan =
|
| 627 |
|
|
in_be32(&p_rx_fw_statistics_pram->replacevlan);
|
| 628 |
|
|
rx_firmware_statistics->insertvlan =
|
| 629 |
|
|
in_be32(&p_rx_fw_statistics_pram->insertvlan);
|
| 630 |
|
|
}
|
| 631 |
|
|
|
| 632 |
|
|
/* Hardware only if user handed pointer and driver actually
|
| 633 |
|
|
gathers hardware statistics */
|
| 634 |
|
|
if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
|
| 635 |
|
|
hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
|
| 636 |
|
|
hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
|
| 637 |
|
|
hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
|
| 638 |
|
|
hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
|
| 639 |
|
|
hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
|
| 640 |
|
|
hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
|
| 641 |
|
|
hardware_statistics->txok = in_be32(&ug_regs->txok);
|
| 642 |
|
|
hardware_statistics->txcf = in_be16(&ug_regs->txcf);
|
| 643 |
|
|
hardware_statistics->tmca = in_be32(&ug_regs->tmca);
|
| 644 |
|
|
hardware_statistics->tbca = in_be32(&ug_regs->tbca);
|
| 645 |
|
|
hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
|
| 646 |
|
|
hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
|
| 647 |
|
|
hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
|
| 648 |
|
|
hardware_statistics->rmca = in_be32(&ug_regs->rmca);
|
| 649 |
|
|
hardware_statistics->rbca = in_be32(&ug_regs->rbca);
|
| 650 |
|
|
}
|
| 651 |
|
|
}
|
| 652 |
|
|
|
| 653 |
|
|
static void dump_bds(struct ucc_geth_private *ugeth)
|
| 654 |
|
|
{
|
| 655 |
|
|
int i;
|
| 656 |
|
|
int length;
|
| 657 |
|
|
|
| 658 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
|
| 659 |
|
|
if (ugeth->p_tx_bd_ring[i]) {
|
| 660 |
|
|
length =
|
| 661 |
|
|
(ugeth->ug_info->bdRingLenTx[i] *
|
| 662 |
|
|
sizeof(struct qe_bd));
|
| 663 |
|
|
ugeth_info("TX BDs[%d]", i);
|
| 664 |
|
|
mem_disp(ugeth->p_tx_bd_ring[i], length);
|
| 665 |
|
|
}
|
| 666 |
|
|
}
|
| 667 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
|
| 668 |
|
|
if (ugeth->p_rx_bd_ring[i]) {
|
| 669 |
|
|
length =
|
| 670 |
|
|
(ugeth->ug_info->bdRingLenRx[i] *
|
| 671 |
|
|
sizeof(struct qe_bd));
|
| 672 |
|
|
ugeth_info("RX BDs[%d]", i);
|
| 673 |
|
|
mem_disp(ugeth->p_rx_bd_ring[i], length);
|
| 674 |
|
|
}
|
| 675 |
|
|
}
|
| 676 |
|
|
}
|
| 677 |
|
|
|
| 678 |
|
|
static void dump_regs(struct ucc_geth_private *ugeth)
|
| 679 |
|
|
{
|
| 680 |
|
|
int i;
|
| 681 |
|
|
|
| 682 |
|
|
ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
|
| 683 |
|
|
ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
|
| 684 |
|
|
|
| 685 |
|
|
ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
|
| 686 |
|
|
(u32) & ugeth->ug_regs->maccfg1,
|
| 687 |
|
|
in_be32(&ugeth->ug_regs->maccfg1));
|
| 688 |
|
|
ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
|
| 689 |
|
|
(u32) & ugeth->ug_regs->maccfg2,
|
| 690 |
|
|
in_be32(&ugeth->ug_regs->maccfg2));
|
| 691 |
|
|
ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
|
| 692 |
|
|
(u32) & ugeth->ug_regs->ipgifg,
|
| 693 |
|
|
in_be32(&ugeth->ug_regs->ipgifg));
|
| 694 |
|
|
ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
|
| 695 |
|
|
(u32) & ugeth->ug_regs->hafdup,
|
| 696 |
|
|
in_be32(&ugeth->ug_regs->hafdup));
|
| 697 |
|
|
ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
|
| 698 |
|
|
(u32) & ugeth->ug_regs->ifctl,
|
| 699 |
|
|
in_be32(&ugeth->ug_regs->ifctl));
|
| 700 |
|
|
ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
|
| 701 |
|
|
(u32) & ugeth->ug_regs->ifstat,
|
| 702 |
|
|
in_be32(&ugeth->ug_regs->ifstat));
|
| 703 |
|
|
ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
|
| 704 |
|
|
(u32) & ugeth->ug_regs->macstnaddr1,
|
| 705 |
|
|
in_be32(&ugeth->ug_regs->macstnaddr1));
|
| 706 |
|
|
ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
|
| 707 |
|
|
(u32) & ugeth->ug_regs->macstnaddr2,
|
| 708 |
|
|
in_be32(&ugeth->ug_regs->macstnaddr2));
|
| 709 |
|
|
ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
|
| 710 |
|
|
(u32) & ugeth->ug_regs->uempr,
|
| 711 |
|
|
in_be32(&ugeth->ug_regs->uempr));
|
| 712 |
|
|
ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
|
| 713 |
|
|
(u32) & ugeth->ug_regs->utbipar,
|
| 714 |
|
|
in_be32(&ugeth->ug_regs->utbipar));
|
| 715 |
|
|
ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
|
| 716 |
|
|
(u32) & ugeth->ug_regs->uescr,
|
| 717 |
|
|
in_be16(&ugeth->ug_regs->uescr));
|
| 718 |
|
|
ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
|
| 719 |
|
|
(u32) & ugeth->ug_regs->tx64,
|
| 720 |
|
|
in_be32(&ugeth->ug_regs->tx64));
|
| 721 |
|
|
ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
|
| 722 |
|
|
(u32) & ugeth->ug_regs->tx127,
|
| 723 |
|
|
in_be32(&ugeth->ug_regs->tx127));
|
| 724 |
|
|
ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
|
| 725 |
|
|
(u32) & ugeth->ug_regs->tx255,
|
| 726 |
|
|
in_be32(&ugeth->ug_regs->tx255));
|
| 727 |
|
|
ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
|
| 728 |
|
|
(u32) & ugeth->ug_regs->rx64,
|
| 729 |
|
|
in_be32(&ugeth->ug_regs->rx64));
|
| 730 |
|
|
ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
|
| 731 |
|
|
(u32) & ugeth->ug_regs->rx127,
|
| 732 |
|
|
in_be32(&ugeth->ug_regs->rx127));
|
| 733 |
|
|
ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
|
| 734 |
|
|
(u32) & ugeth->ug_regs->rx255,
|
| 735 |
|
|
in_be32(&ugeth->ug_regs->rx255));
|
| 736 |
|
|
ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
|
| 737 |
|
|
(u32) & ugeth->ug_regs->txok,
|
| 738 |
|
|
in_be32(&ugeth->ug_regs->txok));
|
| 739 |
|
|
ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
|
| 740 |
|
|
(u32) & ugeth->ug_regs->txcf,
|
| 741 |
|
|
in_be16(&ugeth->ug_regs->txcf));
|
| 742 |
|
|
ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
|
| 743 |
|
|
(u32) & ugeth->ug_regs->tmca,
|
| 744 |
|
|
in_be32(&ugeth->ug_regs->tmca));
|
| 745 |
|
|
ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
|
| 746 |
|
|
(u32) & ugeth->ug_regs->tbca,
|
| 747 |
|
|
in_be32(&ugeth->ug_regs->tbca));
|
| 748 |
|
|
ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
|
| 749 |
|
|
(u32) & ugeth->ug_regs->rxfok,
|
| 750 |
|
|
in_be32(&ugeth->ug_regs->rxfok));
|
| 751 |
|
|
ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
|
| 752 |
|
|
(u32) & ugeth->ug_regs->rxbok,
|
| 753 |
|
|
in_be32(&ugeth->ug_regs->rxbok));
|
| 754 |
|
|
ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
|
| 755 |
|
|
(u32) & ugeth->ug_regs->rbyt,
|
| 756 |
|
|
in_be32(&ugeth->ug_regs->rbyt));
|
| 757 |
|
|
ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
|
| 758 |
|
|
(u32) & ugeth->ug_regs->rmca,
|
| 759 |
|
|
in_be32(&ugeth->ug_regs->rmca));
|
| 760 |
|
|
ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
|
| 761 |
|
|
(u32) & ugeth->ug_regs->rbca,
|
| 762 |
|
|
in_be32(&ugeth->ug_regs->rbca));
|
| 763 |
|
|
ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
|
| 764 |
|
|
(u32) & ugeth->ug_regs->scar,
|
| 765 |
|
|
in_be32(&ugeth->ug_regs->scar));
|
| 766 |
|
|
ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
|
| 767 |
|
|
(u32) & ugeth->ug_regs->scam,
|
| 768 |
|
|
in_be32(&ugeth->ug_regs->scam));
|
| 769 |
|
|
|
| 770 |
|
|
if (ugeth->p_thread_data_tx) {
|
| 771 |
|
|
int numThreadsTxNumerical;
|
| 772 |
|
|
switch (ugeth->ug_info->numThreadsTx) {
|
| 773 |
|
|
case UCC_GETH_NUM_OF_THREADS_1:
|
| 774 |
|
|
numThreadsTxNumerical = 1;
|
| 775 |
|
|
break;
|
| 776 |
|
|
case UCC_GETH_NUM_OF_THREADS_2:
|
| 777 |
|
|
numThreadsTxNumerical = 2;
|
| 778 |
|
|
break;
|
| 779 |
|
|
case UCC_GETH_NUM_OF_THREADS_4:
|
| 780 |
|
|
numThreadsTxNumerical = 4;
|
| 781 |
|
|
break;
|
| 782 |
|
|
case UCC_GETH_NUM_OF_THREADS_6:
|
| 783 |
|
|
numThreadsTxNumerical = 6;
|
| 784 |
|
|
break;
|
| 785 |
|
|
case UCC_GETH_NUM_OF_THREADS_8:
|
| 786 |
|
|
numThreadsTxNumerical = 8;
|
| 787 |
|
|
break;
|
| 788 |
|
|
default:
|
| 789 |
|
|
numThreadsTxNumerical = 0;
|
| 790 |
|
|
break;
|
| 791 |
|
|
}
|
| 792 |
|
|
|
| 793 |
|
|
ugeth_info("Thread data TXs:");
|
| 794 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 795 |
|
|
(u32) ugeth->p_thread_data_tx);
|
| 796 |
|
|
for (i = 0; i < numThreadsTxNumerical; i++) {
|
| 797 |
|
|
ugeth_info("Thread data TX[%d]:", i);
|
| 798 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 799 |
|
|
(u32) & ugeth->p_thread_data_tx[i]);
|
| 800 |
|
|
mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
|
| 801 |
|
|
sizeof(struct ucc_geth_thread_data_tx));
|
| 802 |
|
|
}
|
| 803 |
|
|
}
|
| 804 |
|
|
if (ugeth->p_thread_data_rx) {
|
| 805 |
|
|
int numThreadsRxNumerical;
|
| 806 |
|
|
switch (ugeth->ug_info->numThreadsRx) {
|
| 807 |
|
|
case UCC_GETH_NUM_OF_THREADS_1:
|
| 808 |
|
|
numThreadsRxNumerical = 1;
|
| 809 |
|
|
break;
|
| 810 |
|
|
case UCC_GETH_NUM_OF_THREADS_2:
|
| 811 |
|
|
numThreadsRxNumerical = 2;
|
| 812 |
|
|
break;
|
| 813 |
|
|
case UCC_GETH_NUM_OF_THREADS_4:
|
| 814 |
|
|
numThreadsRxNumerical = 4;
|
| 815 |
|
|
break;
|
| 816 |
|
|
case UCC_GETH_NUM_OF_THREADS_6:
|
| 817 |
|
|
numThreadsRxNumerical = 6;
|
| 818 |
|
|
break;
|
| 819 |
|
|
case UCC_GETH_NUM_OF_THREADS_8:
|
| 820 |
|
|
numThreadsRxNumerical = 8;
|
| 821 |
|
|
break;
|
| 822 |
|
|
default:
|
| 823 |
|
|
numThreadsRxNumerical = 0;
|
| 824 |
|
|
break;
|
| 825 |
|
|
}
|
| 826 |
|
|
|
| 827 |
|
|
ugeth_info("Thread data RX:");
|
| 828 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 829 |
|
|
(u32) ugeth->p_thread_data_rx);
|
| 830 |
|
|
for (i = 0; i < numThreadsRxNumerical; i++) {
|
| 831 |
|
|
ugeth_info("Thread data RX[%d]:", i);
|
| 832 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 833 |
|
|
(u32) & ugeth->p_thread_data_rx[i]);
|
| 834 |
|
|
mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
|
| 835 |
|
|
sizeof(struct ucc_geth_thread_data_rx));
|
| 836 |
|
|
}
|
| 837 |
|
|
}
|
| 838 |
|
|
if (ugeth->p_exf_glbl_param) {
|
| 839 |
|
|
ugeth_info("EXF global param:");
|
| 840 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 841 |
|
|
(u32) ugeth->p_exf_glbl_param);
|
| 842 |
|
|
mem_disp((u8 *) ugeth->p_exf_glbl_param,
|
| 843 |
|
|
sizeof(*ugeth->p_exf_glbl_param));
|
| 844 |
|
|
}
|
| 845 |
|
|
if (ugeth->p_tx_glbl_pram) {
|
| 846 |
|
|
ugeth_info("TX global param:");
|
| 847 |
|
|
ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
|
| 848 |
|
|
ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
|
| 849 |
|
|
(u32) & ugeth->p_tx_glbl_pram->temoder,
|
| 850 |
|
|
in_be16(&ugeth->p_tx_glbl_pram->temoder));
|
| 851 |
|
|
ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
|
| 852 |
|
|
(u32) & ugeth->p_tx_glbl_pram->sqptr,
|
| 853 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->sqptr));
|
| 854 |
|
|
ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
|
| 855 |
|
|
(u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
|
| 856 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->
|
| 857 |
|
|
schedulerbasepointer));
|
| 858 |
|
|
ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
|
| 859 |
|
|
(u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
|
| 860 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
|
| 861 |
|
|
ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
|
| 862 |
|
|
(u32) & ugeth->p_tx_glbl_pram->tstate,
|
| 863 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->tstate));
|
| 864 |
|
|
ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
|
| 865 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
|
| 866 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[0]);
|
| 867 |
|
|
ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
|
| 868 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
|
| 869 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[1]);
|
| 870 |
|
|
ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
|
| 871 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
|
| 872 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[2]);
|
| 873 |
|
|
ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
|
| 874 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
|
| 875 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[3]);
|
| 876 |
|
|
ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
|
| 877 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
|
| 878 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[4]);
|
| 879 |
|
|
ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
|
| 880 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
|
| 881 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[5]);
|
| 882 |
|
|
ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
|
| 883 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
|
| 884 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[6]);
|
| 885 |
|
|
ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
|
| 886 |
|
|
(u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
|
| 887 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[7]);
|
| 888 |
|
|
ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
|
| 889 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
|
| 890 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
|
| 891 |
|
|
ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
|
| 892 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
|
| 893 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
|
| 894 |
|
|
ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
|
| 895 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
|
| 896 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
|
| 897 |
|
|
ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
|
| 898 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
|
| 899 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
|
| 900 |
|
|
ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
|
| 901 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
|
| 902 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
|
| 903 |
|
|
ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
|
| 904 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
|
| 905 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
|
| 906 |
|
|
ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
|
| 907 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
|
| 908 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
|
| 909 |
|
|
ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
|
| 910 |
|
|
(u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
|
| 911 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
|
| 912 |
|
|
ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
|
| 913 |
|
|
(u32) & ugeth->p_tx_glbl_pram->tqptr,
|
| 914 |
|
|
in_be32(&ugeth->p_tx_glbl_pram->tqptr));
|
| 915 |
|
|
}
|
| 916 |
|
|
if (ugeth->p_rx_glbl_pram) {
|
| 917 |
|
|
ugeth_info("RX global param:");
|
| 918 |
|
|
ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
|
| 919 |
|
|
ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
|
| 920 |
|
|
(u32) & ugeth->p_rx_glbl_pram->remoder,
|
| 921 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->remoder));
|
| 922 |
|
|
ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
|
| 923 |
|
|
(u32) & ugeth->p_rx_glbl_pram->rqptr,
|
| 924 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->rqptr));
|
| 925 |
|
|
ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
|
| 926 |
|
|
(u32) & ugeth->p_rx_glbl_pram->typeorlen,
|
| 927 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
|
| 928 |
|
|
ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
|
| 929 |
|
|
(u32) & ugeth->p_rx_glbl_pram->rxgstpack,
|
| 930 |
|
|
ugeth->p_rx_glbl_pram->rxgstpack);
|
| 931 |
|
|
ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
|
| 932 |
|
|
(u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
|
| 933 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
|
| 934 |
|
|
ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
|
| 935 |
|
|
(u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
|
| 936 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
|
| 937 |
|
|
ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
|
| 938 |
|
|
(u32) & ugeth->p_rx_glbl_pram->rstate,
|
| 939 |
|
|
ugeth->p_rx_glbl_pram->rstate);
|
| 940 |
|
|
ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
|
| 941 |
|
|
(u32) & ugeth->p_rx_glbl_pram->mrblr,
|
| 942 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->mrblr));
|
| 943 |
|
|
ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
|
| 944 |
|
|
(u32) & ugeth->p_rx_glbl_pram->rbdqptr,
|
| 945 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
|
| 946 |
|
|
ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
|
| 947 |
|
|
(u32) & ugeth->p_rx_glbl_pram->mflr,
|
| 948 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->mflr));
|
| 949 |
|
|
ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
|
| 950 |
|
|
(u32) & ugeth->p_rx_glbl_pram->minflr,
|
| 951 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->minflr));
|
| 952 |
|
|
ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
|
| 953 |
|
|
(u32) & ugeth->p_rx_glbl_pram->maxd1,
|
| 954 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->maxd1));
|
| 955 |
|
|
ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
|
| 956 |
|
|
(u32) & ugeth->p_rx_glbl_pram->maxd2,
|
| 957 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->maxd2));
|
| 958 |
|
|
ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
|
| 959 |
|
|
(u32) & ugeth->p_rx_glbl_pram->ecamptr,
|
| 960 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
|
| 961 |
|
|
ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
|
| 962 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l2qt,
|
| 963 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l2qt));
|
| 964 |
|
|
ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
|
| 965 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[0],
|
| 966 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
|
| 967 |
|
|
ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
|
| 968 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[1],
|
| 969 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
|
| 970 |
|
|
ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
|
| 971 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[2],
|
| 972 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
|
| 973 |
|
|
ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
|
| 974 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[3],
|
| 975 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
|
| 976 |
|
|
ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
|
| 977 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[4],
|
| 978 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
|
| 979 |
|
|
ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
|
| 980 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[5],
|
| 981 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
|
| 982 |
|
|
ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
|
| 983 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[6],
|
| 984 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
|
| 985 |
|
|
ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
|
| 986 |
|
|
(u32) & ugeth->p_rx_glbl_pram->l3qt[7],
|
| 987 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
|
| 988 |
|
|
ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
|
| 989 |
|
|
(u32) & ugeth->p_rx_glbl_pram->vlantype,
|
| 990 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->vlantype));
|
| 991 |
|
|
ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
|
| 992 |
|
|
(u32) & ugeth->p_rx_glbl_pram->vlantci,
|
| 993 |
|
|
in_be16(&ugeth->p_rx_glbl_pram->vlantci));
|
| 994 |
|
|
for (i = 0; i < 64; i++)
|
| 995 |
|
|
ugeth_info
|
| 996 |
|
|
("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
|
| 997 |
|
|
i,
|
| 998 |
|
|
(u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
|
| 999 |
|
|
ugeth->p_rx_glbl_pram->addressfiltering[i]);
|
| 1000 |
|
|
ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
|
| 1001 |
|
|
(u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
|
| 1002 |
|
|
in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
|
| 1003 |
|
|
}
|
| 1004 |
|
|
if (ugeth->p_send_q_mem_reg) {
|
| 1005 |
|
|
ugeth_info("Send Q memory registers:");
|
| 1006 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1007 |
|
|
(u32) ugeth->p_send_q_mem_reg);
|
| 1008 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
|
| 1009 |
|
|
ugeth_info("SQQD[%d]:", i);
|
| 1010 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1011 |
|
|
(u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
|
| 1012 |
|
|
mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
|
| 1013 |
|
|
sizeof(struct ucc_geth_send_queue_qd));
|
| 1014 |
|
|
}
|
| 1015 |
|
|
}
|
| 1016 |
|
|
if (ugeth->p_scheduler) {
|
| 1017 |
|
|
ugeth_info("Scheduler:");
|
| 1018 |
|
|
ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
|
| 1019 |
|
|
mem_disp((u8 *) ugeth->p_scheduler,
|
| 1020 |
|
|
sizeof(*ugeth->p_scheduler));
|
| 1021 |
|
|
}
|
| 1022 |
|
|
if (ugeth->p_tx_fw_statistics_pram) {
|
| 1023 |
|
|
ugeth_info("TX FW statistics pram:");
|
| 1024 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1025 |
|
|
(u32) ugeth->p_tx_fw_statistics_pram);
|
| 1026 |
|
|
mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
|
| 1027 |
|
|
sizeof(*ugeth->p_tx_fw_statistics_pram));
|
| 1028 |
|
|
}
|
| 1029 |
|
|
if (ugeth->p_rx_fw_statistics_pram) {
|
| 1030 |
|
|
ugeth_info("RX FW statistics pram:");
|
| 1031 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1032 |
|
|
(u32) ugeth->p_rx_fw_statistics_pram);
|
| 1033 |
|
|
mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
|
| 1034 |
|
|
sizeof(*ugeth->p_rx_fw_statistics_pram));
|
| 1035 |
|
|
}
|
| 1036 |
|
|
if (ugeth->p_rx_irq_coalescing_tbl) {
|
| 1037 |
|
|
ugeth_info("RX IRQ coalescing tables:");
|
| 1038 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1039 |
|
|
(u32) ugeth->p_rx_irq_coalescing_tbl);
|
| 1040 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
|
| 1041 |
|
|
ugeth_info("RX IRQ coalescing table entry[%d]:", i);
|
| 1042 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1043 |
|
|
(u32) & ugeth->p_rx_irq_coalescing_tbl->
|
| 1044 |
|
|
coalescingentry[i]);
|
| 1045 |
|
|
ugeth_info
|
| 1046 |
|
|
("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
|
| 1047 |
|
|
(u32) & ugeth->p_rx_irq_coalescing_tbl->
|
| 1048 |
|
|
coalescingentry[i].interruptcoalescingmaxvalue,
|
| 1049 |
|
|
in_be32(&ugeth->p_rx_irq_coalescing_tbl->
|
| 1050 |
|
|
coalescingentry[i].
|
| 1051 |
|
|
interruptcoalescingmaxvalue));
|
| 1052 |
|
|
ugeth_info
|
| 1053 |
|
|
("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
|
| 1054 |
|
|
(u32) & ugeth->p_rx_irq_coalescing_tbl->
|
| 1055 |
|
|
coalescingentry[i].interruptcoalescingcounter,
|
| 1056 |
|
|
in_be32(&ugeth->p_rx_irq_coalescing_tbl->
|
| 1057 |
|
|
coalescingentry[i].
|
| 1058 |
|
|
interruptcoalescingcounter));
|
| 1059 |
|
|
}
|
| 1060 |
|
|
}
|
| 1061 |
|
|
if (ugeth->p_rx_bd_qs_tbl) {
|
| 1062 |
|
|
ugeth_info("RX BD QS tables:");
|
| 1063 |
|
|
ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
|
| 1064 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
|
| 1065 |
|
|
ugeth_info("RX BD QS table[%d]:", i);
|
| 1066 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1067 |
|
|
(u32) & ugeth->p_rx_bd_qs_tbl[i]);
|
| 1068 |
|
|
ugeth_info
|
| 1069 |
|
|
("bdbaseptr : addr - 0x%08x, val - 0x%08x",
|
| 1070 |
|
|
(u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
|
| 1071 |
|
|
in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
|
| 1072 |
|
|
ugeth_info
|
| 1073 |
|
|
("bdptr : addr - 0x%08x, val - 0x%08x",
|
| 1074 |
|
|
(u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
|
| 1075 |
|
|
in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
|
| 1076 |
|
|
ugeth_info
|
| 1077 |
|
|
("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
|
| 1078 |
|
|
(u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
|
| 1079 |
|
|
in_be32(&ugeth->p_rx_bd_qs_tbl[i].
|
| 1080 |
|
|
externalbdbaseptr));
|
| 1081 |
|
|
ugeth_info
|
| 1082 |
|
|
("externalbdptr : addr - 0x%08x, val - 0x%08x",
|
| 1083 |
|
|
(u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
|
| 1084 |
|
|
in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
|
| 1085 |
|
|
ugeth_info("ucode RX Prefetched BDs:");
|
| 1086 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1087 |
|
|
(u32)
|
| 1088 |
|
|
qe_muram_addr(in_be32
|
| 1089 |
|
|
(&ugeth->p_rx_bd_qs_tbl[i].
|
| 1090 |
|
|
bdbaseptr)));
|
| 1091 |
|
|
mem_disp((u8 *)
|
| 1092 |
|
|
qe_muram_addr(in_be32
|
| 1093 |
|
|
(&ugeth->p_rx_bd_qs_tbl[i].
|
| 1094 |
|
|
bdbaseptr)),
|
| 1095 |
|
|
sizeof(struct ucc_geth_rx_prefetched_bds));
|
| 1096 |
|
|
}
|
| 1097 |
|
|
}
|
| 1098 |
|
|
if (ugeth->p_init_enet_param_shadow) {
|
| 1099 |
|
|
int size;
|
| 1100 |
|
|
ugeth_info("Init enet param shadow:");
|
| 1101 |
|
|
ugeth_info("Base address: 0x%08x",
|
| 1102 |
|
|
(u32) ugeth->p_init_enet_param_shadow);
|
| 1103 |
|
|
mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
|
| 1104 |
|
|
sizeof(*ugeth->p_init_enet_param_shadow));
|
| 1105 |
|
|
|
| 1106 |
|
|
size = sizeof(struct ucc_geth_thread_rx_pram);
|
| 1107 |
|
|
if (ugeth->ug_info->rxExtendedFiltering) {
|
| 1108 |
|
|
size +=
|
| 1109 |
|
|
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
|
| 1110 |
|
|
if (ugeth->ug_info->largestexternallookupkeysize ==
|
| 1111 |
|
|
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
|
| 1112 |
|
|
size +=
|
| 1113 |
|
|
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
|
| 1114 |
|
|
if (ugeth->ug_info->largestexternallookupkeysize ==
|
| 1115 |
|
|
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
|
| 1116 |
|
|
size +=
|
| 1117 |
|
|
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
|
| 1118 |
|
|
}
|
| 1119 |
|
|
|
| 1120 |
|
|
dump_init_enet_entries(ugeth,
|
| 1121 |
|
|
&(ugeth->p_init_enet_param_shadow->
|
| 1122 |
|
|
txthread[0]),
|
| 1123 |
|
|
ENET_INIT_PARAM_MAX_ENTRIES_TX,
|
| 1124 |
|
|
sizeof(struct ucc_geth_thread_tx_pram),
|
| 1125 |
|
|
ugeth->ug_info->riscTx, 0);
|
| 1126 |
|
|
dump_init_enet_entries(ugeth,
|
| 1127 |
|
|
&(ugeth->p_init_enet_param_shadow->
|
| 1128 |
|
|
rxthread[0]),
|
| 1129 |
|
|
ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
|
| 1130 |
|
|
ugeth->ug_info->riscRx, 1);
|
| 1131 |
|
|
}
|
| 1132 |
|
|
}
|
| 1133 |
|
|
#endif /* DEBUG */
|
| 1134 |
|
|
|
| 1135 |
|
|
static void init_default_reg_vals(volatile u32 *upsmr_register,
|
| 1136 |
|
|
volatile u32 *maccfg1_register,
|
| 1137 |
|
|
volatile u32 *maccfg2_register)
|
| 1138 |
|
|
{
|
| 1139 |
|
|
out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
|
| 1140 |
|
|
out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
|
| 1141 |
|
|
out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
|
| 1142 |
|
|
}
|
| 1143 |
|
|
|
| 1144 |
|
|
static int init_half_duplex_params(int alt_beb,
|
| 1145 |
|
|
int back_pressure_no_backoff,
|
| 1146 |
|
|
int no_backoff,
|
| 1147 |
|
|
int excess_defer,
|
| 1148 |
|
|
u8 alt_beb_truncation,
|
| 1149 |
|
|
u8 max_retransmissions,
|
| 1150 |
|
|
u8 collision_window,
|
| 1151 |
|
|
volatile u32 *hafdup_register)
|
| 1152 |
|
|
{
|
| 1153 |
|
|
u32 value = 0;
|
| 1154 |
|
|
|
| 1155 |
|
|
if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
|
| 1156 |
|
|
(max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
|
| 1157 |
|
|
(collision_window > HALFDUP_COLLISION_WINDOW_MAX))
|
| 1158 |
|
|
return -EINVAL;
|
| 1159 |
|
|
|
| 1160 |
|
|
value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
|
| 1161 |
|
|
|
| 1162 |
|
|
if (alt_beb)
|
| 1163 |
|
|
value |= HALFDUP_ALT_BEB;
|
| 1164 |
|
|
if (back_pressure_no_backoff)
|
| 1165 |
|
|
value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
|
| 1166 |
|
|
if (no_backoff)
|
| 1167 |
|
|
value |= HALFDUP_NO_BACKOFF;
|
| 1168 |
|
|
if (excess_defer)
|
| 1169 |
|
|
value |= HALFDUP_EXCESSIVE_DEFER;
|
| 1170 |
|
|
|
| 1171 |
|
|
value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
|
| 1172 |
|
|
|
| 1173 |
|
|
value |= collision_window;
|
| 1174 |
|
|
|
| 1175 |
|
|
out_be32(hafdup_register, value);
|
| 1176 |
|
|
return 0;
|
| 1177 |
|
|
}
|
| 1178 |
|
|
|
| 1179 |
|
|
static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
|
| 1180 |
|
|
u8 non_btb_ipg,
|
| 1181 |
|
|
u8 min_ifg,
|
| 1182 |
|
|
u8 btb_ipg,
|
| 1183 |
|
|
volatile u32 *ipgifg_register)
|
| 1184 |
|
|
{
|
| 1185 |
|
|
u32 value = 0;
|
| 1186 |
|
|
|
| 1187 |
|
|
/* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
|
| 1188 |
|
|
IPG part 2 */
|
| 1189 |
|
|
if (non_btb_cs_ipg > non_btb_ipg)
|
| 1190 |
|
|
return -EINVAL;
|
| 1191 |
|
|
|
| 1192 |
|
|
if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
|
| 1193 |
|
|
(non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
|
| 1194 |
|
|
/*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
|
| 1195 |
|
|
(btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
|
| 1196 |
|
|
return -EINVAL;
|
| 1197 |
|
|
|
| 1198 |
|
|
value |=
|
| 1199 |
|
|
((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
|
| 1200 |
|
|
IPGIFG_NBTB_CS_IPG_MASK);
|
| 1201 |
|
|
value |=
|
| 1202 |
|
|
((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
|
| 1203 |
|
|
IPGIFG_NBTB_IPG_MASK);
|
| 1204 |
|
|
value |=
|
| 1205 |
|
|
((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
|
| 1206 |
|
|
IPGIFG_MIN_IFG_MASK);
|
| 1207 |
|
|
value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
|
| 1208 |
|
|
|
| 1209 |
|
|
out_be32(ipgifg_register, value);
|
| 1210 |
|
|
return 0;
|
| 1211 |
|
|
}
|
| 1212 |
|
|
|
| 1213 |
|
|
int init_flow_control_params(u32 automatic_flow_control_mode,
|
| 1214 |
|
|
int rx_flow_control_enable,
|
| 1215 |
|
|
int tx_flow_control_enable,
|
| 1216 |
|
|
u16 pause_period,
|
| 1217 |
|
|
u16 extension_field,
|
| 1218 |
|
|
volatile u32 *upsmr_register,
|
| 1219 |
|
|
volatile u32 *uempr_register,
|
| 1220 |
|
|
volatile u32 *maccfg1_register)
|
| 1221 |
|
|
{
|
| 1222 |
|
|
u32 value = 0;
|
| 1223 |
|
|
|
| 1224 |
|
|
/* Set UEMPR register */
|
| 1225 |
|
|
value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
|
| 1226 |
|
|
value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
|
| 1227 |
|
|
out_be32(uempr_register, value);
|
| 1228 |
|
|
|
| 1229 |
|
|
/* Set UPSMR register */
|
| 1230 |
|
|
value = in_be32(upsmr_register);
|
| 1231 |
|
|
value |= automatic_flow_control_mode;
|
| 1232 |
|
|
out_be32(upsmr_register, value);
|
| 1233 |
|
|
|
| 1234 |
|
|
value = in_be32(maccfg1_register);
|
| 1235 |
|
|
if (rx_flow_control_enable)
|
| 1236 |
|
|
value |= MACCFG1_FLOW_RX;
|
| 1237 |
|
|
if (tx_flow_control_enable)
|
| 1238 |
|
|
value |= MACCFG1_FLOW_TX;
|
| 1239 |
|
|
out_be32(maccfg1_register, value);
|
| 1240 |
|
|
|
| 1241 |
|
|
return 0;
|
| 1242 |
|
|
}
|
| 1243 |
|
|
|
| 1244 |
|
|
static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
|
| 1245 |
|
|
int auto_zero_hardware_statistics,
|
| 1246 |
|
|
volatile u32 *upsmr_register,
|
| 1247 |
|
|
volatile u16 *uescr_register)
|
| 1248 |
|
|
{
|
| 1249 |
|
|
u32 upsmr_value = 0;
|
| 1250 |
|
|
u16 uescr_value = 0;
|
| 1251 |
|
|
/* Enable hardware statistics gathering if requested */
|
| 1252 |
|
|
if (enable_hardware_statistics) {
|
| 1253 |
|
|
upsmr_value = in_be32(upsmr_register);
|
| 1254 |
|
|
upsmr_value |= UPSMR_HSE;
|
| 1255 |
|
|
out_be32(upsmr_register, upsmr_value);
|
| 1256 |
|
|
}
|
| 1257 |
|
|
|
| 1258 |
|
|
/* Clear hardware statistics counters */
|
| 1259 |
|
|
uescr_value = in_be16(uescr_register);
|
| 1260 |
|
|
uescr_value |= UESCR_CLRCNT;
|
| 1261 |
|
|
/* Automatically zero hardware statistics counters on read,
|
| 1262 |
|
|
if requested */
|
| 1263 |
|
|
if (auto_zero_hardware_statistics)
|
| 1264 |
|
|
uescr_value |= UESCR_AUTOZ;
|
| 1265 |
|
|
out_be16(uescr_register, uescr_value);
|
| 1266 |
|
|
|
| 1267 |
|
|
return 0;
|
| 1268 |
|
|
}
|
| 1269 |
|
|
|
| 1270 |
|
|
static int init_firmware_statistics_gathering_mode(int
|
| 1271 |
|
|
enable_tx_firmware_statistics,
|
| 1272 |
|
|
int enable_rx_firmware_statistics,
|
| 1273 |
|
|
volatile u32 *tx_rmon_base_ptr,
|
| 1274 |
|
|
u32 tx_firmware_statistics_structure_address,
|
| 1275 |
|
|
volatile u32 *rx_rmon_base_ptr,
|
| 1276 |
|
|
u32 rx_firmware_statistics_structure_address,
|
| 1277 |
|
|
volatile u16 *temoder_register,
|
| 1278 |
|
|
volatile u32 *remoder_register)
|
| 1279 |
|
|
{
|
| 1280 |
|
|
/* Note: this function does not check if */
|
| 1281 |
|
|
/* the parameters it receives are NULL */
|
| 1282 |
|
|
u16 temoder_value;
|
| 1283 |
|
|
u32 remoder_value;
|
| 1284 |
|
|
|
| 1285 |
|
|
if (enable_tx_firmware_statistics) {
|
| 1286 |
|
|
out_be32(tx_rmon_base_ptr,
|
| 1287 |
|
|
tx_firmware_statistics_structure_address);
|
| 1288 |
|
|
temoder_value = in_be16(temoder_register);
|
| 1289 |
|
|
temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
|
| 1290 |
|
|
out_be16(temoder_register, temoder_value);
|
| 1291 |
|
|
}
|
| 1292 |
|
|
|
| 1293 |
|
|
if (enable_rx_firmware_statistics) {
|
| 1294 |
|
|
out_be32(rx_rmon_base_ptr,
|
| 1295 |
|
|
rx_firmware_statistics_structure_address);
|
| 1296 |
|
|
remoder_value = in_be32(remoder_register);
|
| 1297 |
|
|
remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
|
| 1298 |
|
|
out_be32(remoder_register, remoder_value);
|
| 1299 |
|
|
}
|
| 1300 |
|
|
|
| 1301 |
|
|
return 0;
|
| 1302 |
|
|
}
|
| 1303 |
|
|
|
| 1304 |
|
|
static int init_mac_station_addr_regs(u8 address_byte_0,
|
| 1305 |
|
|
u8 address_byte_1,
|
| 1306 |
|
|
u8 address_byte_2,
|
| 1307 |
|
|
u8 address_byte_3,
|
| 1308 |
|
|
u8 address_byte_4,
|
| 1309 |
|
|
u8 address_byte_5,
|
| 1310 |
|
|
volatile u32 *macstnaddr1_register,
|
| 1311 |
|
|
volatile u32 *macstnaddr2_register)
|
| 1312 |
|
|
{
|
| 1313 |
|
|
u32 value = 0;
|
| 1314 |
|
|
|
| 1315 |
|
|
/* Example: for a station address of 0x12345678ABCD, */
|
| 1316 |
|
|
/* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
|
| 1317 |
|
|
|
| 1318 |
|
|
/* MACSTNADDR1 Register: */
|
| 1319 |
|
|
|
| 1320 |
|
|
/* 0 7 8 15 */
|
| 1321 |
|
|
/* station address byte 5 station address byte 4 */
|
| 1322 |
|
|
/* 16 23 24 31 */
|
| 1323 |
|
|
/* station address byte 3 station address byte 2 */
|
| 1324 |
|
|
value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
|
| 1325 |
|
|
value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
|
| 1326 |
|
|
value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
|
| 1327 |
|
|
value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
|
| 1328 |
|
|
|
| 1329 |
|
|
out_be32(macstnaddr1_register, value);
|
| 1330 |
|
|
|
| 1331 |
|
|
/* MACSTNADDR2 Register: */
|
| 1332 |
|
|
|
| 1333 |
|
|
/* 0 7 8 15 */
|
| 1334 |
|
|
/* station address byte 1 station address byte 0 */
|
| 1335 |
|
|
/* 16 23 24 31 */
|
| 1336 |
|
|
/* reserved reserved */
|
| 1337 |
|
|
value = 0;
|
| 1338 |
|
|
value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
|
| 1339 |
|
|
value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
|
| 1340 |
|
|
|
| 1341 |
|
|
out_be32(macstnaddr2_register, value);
|
| 1342 |
|
|
|
| 1343 |
|
|
return 0;
|
| 1344 |
|
|
}
|
| 1345 |
|
|
|
| 1346 |
|
|
static int init_check_frame_length_mode(int length_check,
|
| 1347 |
|
|
volatile u32 *maccfg2_register)
|
| 1348 |
|
|
{
|
| 1349 |
|
|
u32 value = 0;
|
| 1350 |
|
|
|
| 1351 |
|
|
value = in_be32(maccfg2_register);
|
| 1352 |
|
|
|
| 1353 |
|
|
if (length_check)
|
| 1354 |
|
|
value |= MACCFG2_LC;
|
| 1355 |
|
|
else
|
| 1356 |
|
|
value &= ~MACCFG2_LC;
|
| 1357 |
|
|
|
| 1358 |
|
|
out_be32(maccfg2_register, value);
|
| 1359 |
|
|
return 0;
|
| 1360 |
|
|
}
|
| 1361 |
|
|
|
| 1362 |
|
|
static int init_preamble_length(u8 preamble_length,
|
| 1363 |
|
|
volatile u32 *maccfg2_register)
|
| 1364 |
|
|
{
|
| 1365 |
|
|
u32 value = 0;
|
| 1366 |
|
|
|
| 1367 |
|
|
if ((preamble_length < 3) || (preamble_length > 7))
|
| 1368 |
|
|
return -EINVAL;
|
| 1369 |
|
|
|
| 1370 |
|
|
value = in_be32(maccfg2_register);
|
| 1371 |
|
|
value &= ~MACCFG2_PREL_MASK;
|
| 1372 |
|
|
value |= (preamble_length << MACCFG2_PREL_SHIFT);
|
| 1373 |
|
|
out_be32(maccfg2_register, value);
|
| 1374 |
|
|
return 0;
|
| 1375 |
|
|
}
|
| 1376 |
|
|
|
| 1377 |
|
|
static int init_rx_parameters(int reject_broadcast,
|
| 1378 |
|
|
int receive_short_frames,
|
| 1379 |
|
|
int promiscuous, volatile u32 *upsmr_register)
|
| 1380 |
|
|
{
|
| 1381 |
|
|
u32 value = 0;
|
| 1382 |
|
|
|
| 1383 |
|
|
value = in_be32(upsmr_register);
|
| 1384 |
|
|
|
| 1385 |
|
|
if (reject_broadcast)
|
| 1386 |
|
|
value |= UPSMR_BRO;
|
| 1387 |
|
|
else
|
| 1388 |
|
|
value &= ~UPSMR_BRO;
|
| 1389 |
|
|
|
| 1390 |
|
|
if (receive_short_frames)
|
| 1391 |
|
|
value |= UPSMR_RSH;
|
| 1392 |
|
|
else
|
| 1393 |
|
|
value &= ~UPSMR_RSH;
|
| 1394 |
|
|
|
| 1395 |
|
|
if (promiscuous)
|
| 1396 |
|
|
value |= UPSMR_PRO;
|
| 1397 |
|
|
else
|
| 1398 |
|
|
value &= ~UPSMR_PRO;
|
| 1399 |
|
|
|
| 1400 |
|
|
out_be32(upsmr_register, value);
|
| 1401 |
|
|
|
| 1402 |
|
|
return 0;
|
| 1403 |
|
|
}
|
| 1404 |
|
|
|
| 1405 |
|
|
static int init_max_rx_buff_len(u16 max_rx_buf_len,
|
| 1406 |
|
|
volatile u16 *mrblr_register)
|
| 1407 |
|
|
{
|
| 1408 |
|
|
/* max_rx_buf_len value must be a multiple of 128 */
|
| 1409 |
|
|
if ((max_rx_buf_len == 0)
|
| 1410 |
|
|
|| (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
|
| 1411 |
|
|
return -EINVAL;
|
| 1412 |
|
|
|
| 1413 |
|
|
out_be16(mrblr_register, max_rx_buf_len);
|
| 1414 |
|
|
return 0;
|
| 1415 |
|
|
}
|
| 1416 |
|
|
|
| 1417 |
|
|
static int init_min_frame_len(u16 min_frame_length,
|
| 1418 |
|
|
volatile u16 *minflr_register,
|
| 1419 |
|
|
volatile u16 *mrblr_register)
|
| 1420 |
|
|
{
|
| 1421 |
|
|
u16 mrblr_value = 0;
|
| 1422 |
|
|
|
| 1423 |
|
|
mrblr_value = in_be16(mrblr_register);
|
| 1424 |
|
|
if (min_frame_length >= (mrblr_value - 4))
|
| 1425 |
|
|
return -EINVAL;
|
| 1426 |
|
|
|
| 1427 |
|
|
out_be16(minflr_register, min_frame_length);
|
| 1428 |
|
|
return 0;
|
| 1429 |
|
|
}
|
| 1430 |
|
|
|
| 1431 |
|
|
static int adjust_enet_interface(struct ucc_geth_private *ugeth)
|
| 1432 |
|
|
{
|
| 1433 |
|
|
struct ucc_geth_info *ug_info;
|
| 1434 |
|
|
struct ucc_geth *ug_regs;
|
| 1435 |
|
|
struct ucc_fast *uf_regs;
|
| 1436 |
|
|
int ret_val;
|
| 1437 |
|
|
u32 upsmr, maccfg2, tbiBaseAddress;
|
| 1438 |
|
|
u16 value;
|
| 1439 |
|
|
|
| 1440 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 1441 |
|
|
|
| 1442 |
|
|
ug_info = ugeth->ug_info;
|
| 1443 |
|
|
ug_regs = ugeth->ug_regs;
|
| 1444 |
|
|
uf_regs = ugeth->uccf->uf_regs;
|
| 1445 |
|
|
|
| 1446 |
|
|
/* Set MACCFG2 */
|
| 1447 |
|
|
maccfg2 = in_be32(&ug_regs->maccfg2);
|
| 1448 |
|
|
maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
|
| 1449 |
|
|
if ((ugeth->max_speed == SPEED_10) ||
|
| 1450 |
|
|
(ugeth->max_speed == SPEED_100))
|
| 1451 |
|
|
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
|
| 1452 |
|
|
else if (ugeth->max_speed == SPEED_1000)
|
| 1453 |
|
|
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
|
| 1454 |
|
|
maccfg2 |= ug_info->padAndCrc;
|
| 1455 |
|
|
out_be32(&ug_regs->maccfg2, maccfg2);
|
| 1456 |
|
|
|
| 1457 |
|
|
/* Set UPSMR */
|
| 1458 |
|
|
upsmr = in_be32(&uf_regs->upsmr);
|
| 1459 |
|
|
upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
|
| 1460 |
|
|
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
|
| 1461 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
|
| 1462 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
|
| 1463 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
|
| 1464 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
|
| 1465 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
|
| 1466 |
|
|
upsmr |= UPSMR_RPM;
|
| 1467 |
|
|
switch (ugeth->max_speed) {
|
| 1468 |
|
|
case SPEED_10:
|
| 1469 |
|
|
upsmr |= UPSMR_R10M;
|
| 1470 |
|
|
/* FALLTHROUGH */
|
| 1471 |
|
|
case SPEED_100:
|
| 1472 |
|
|
if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
|
| 1473 |
|
|
upsmr |= UPSMR_RMM;
|
| 1474 |
|
|
}
|
| 1475 |
|
|
}
|
| 1476 |
|
|
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
|
| 1477 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
|
| 1478 |
|
|
upsmr |= UPSMR_TBIM;
|
| 1479 |
|
|
}
|
| 1480 |
|
|
out_be32(&uf_regs->upsmr, upsmr);
|
| 1481 |
|
|
|
| 1482 |
|
|
/* Disable autonegotiation in tbi mode, because by default it
|
| 1483 |
|
|
comes up in autonegotiation mode. */
|
| 1484 |
|
|
/* Note that this depends on proper setting in utbipar register. */
|
| 1485 |
|
|
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
|
| 1486 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
|
| 1487 |
|
|
tbiBaseAddress = in_be32(&ug_regs->utbipar);
|
| 1488 |
|
|
tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
|
| 1489 |
|
|
tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
|
| 1490 |
|
|
value = ugeth->phydev->bus->read(ugeth->phydev->bus,
|
| 1491 |
|
|
(u8) tbiBaseAddress, ENET_TBI_MII_CR);
|
| 1492 |
|
|
value &= ~0x1000; /* Turn off autonegotiation */
|
| 1493 |
|
|
ugeth->phydev->bus->write(ugeth->phydev->bus,
|
| 1494 |
|
|
(u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
|
| 1495 |
|
|
}
|
| 1496 |
|
|
|
| 1497 |
|
|
init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
|
| 1498 |
|
|
|
| 1499 |
|
|
ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
|
| 1500 |
|
|
if (ret_val != 0) {
|
| 1501 |
|
|
if (netif_msg_probe(ugeth))
|
| 1502 |
|
|
ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
|
| 1503 |
|
|
__FUNCTION__);
|
| 1504 |
|
|
return ret_val;
|
| 1505 |
|
|
}
|
| 1506 |
|
|
|
| 1507 |
|
|
return 0;
|
| 1508 |
|
|
}
|
| 1509 |
|
|
|
| 1510 |
|
|
/* Called every time the controller might need to be made
|
| 1511 |
|
|
* aware of new link state. The PHY code conveys this
|
| 1512 |
|
|
* information through variables in the ugeth structure, and this
|
| 1513 |
|
|
* function converts those variables into the appropriate
|
| 1514 |
|
|
* register values, and can bring down the device if needed.
|
| 1515 |
|
|
*/
|
| 1516 |
|
|
|
| 1517 |
|
|
static void adjust_link(struct net_device *dev)
|
| 1518 |
|
|
{
|
| 1519 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 1520 |
|
|
struct ucc_geth *ug_regs;
|
| 1521 |
|
|
struct ucc_fast *uf_regs;
|
| 1522 |
|
|
struct phy_device *phydev = ugeth->phydev;
|
| 1523 |
|
|
unsigned long flags;
|
| 1524 |
|
|
int new_state = 0;
|
| 1525 |
|
|
|
| 1526 |
|
|
ug_regs = ugeth->ug_regs;
|
| 1527 |
|
|
uf_regs = ugeth->uccf->uf_regs;
|
| 1528 |
|
|
|
| 1529 |
|
|
spin_lock_irqsave(&ugeth->lock, flags);
|
| 1530 |
|
|
|
| 1531 |
|
|
if (phydev->link) {
|
| 1532 |
|
|
u32 tempval = in_be32(&ug_regs->maccfg2);
|
| 1533 |
|
|
u32 upsmr = in_be32(&uf_regs->upsmr);
|
| 1534 |
|
|
/* Now we make sure that we can be in full duplex mode.
|
| 1535 |
|
|
* If not, we operate in half-duplex mode. */
|
| 1536 |
|
|
if (phydev->duplex != ugeth->oldduplex) {
|
| 1537 |
|
|
new_state = 1;
|
| 1538 |
|
|
if (!(phydev->duplex))
|
| 1539 |
|
|
tempval &= ~(MACCFG2_FDX);
|
| 1540 |
|
|
else
|
| 1541 |
|
|
tempval |= MACCFG2_FDX;
|
| 1542 |
|
|
ugeth->oldduplex = phydev->duplex;
|
| 1543 |
|
|
}
|
| 1544 |
|
|
|
| 1545 |
|
|
if (phydev->speed != ugeth->oldspeed) {
|
| 1546 |
|
|
new_state = 1;
|
| 1547 |
|
|
switch (phydev->speed) {
|
| 1548 |
|
|
case SPEED_1000:
|
| 1549 |
|
|
tempval = ((tempval &
|
| 1550 |
|
|
~(MACCFG2_INTERFACE_MODE_MASK)) |
|
| 1551 |
|
|
MACCFG2_INTERFACE_MODE_BYTE);
|
| 1552 |
|
|
break;
|
| 1553 |
|
|
case SPEED_100:
|
| 1554 |
|
|
case SPEED_10:
|
| 1555 |
|
|
tempval = ((tempval &
|
| 1556 |
|
|
~(MACCFG2_INTERFACE_MODE_MASK)) |
|
| 1557 |
|
|
MACCFG2_INTERFACE_MODE_NIBBLE);
|
| 1558 |
|
|
/* if reduced mode, re-set UPSMR.R10M */
|
| 1559 |
|
|
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
|
| 1560 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
|
| 1561 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
|
| 1562 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
|
| 1563 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
|
| 1564 |
|
|
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
|
| 1565 |
|
|
if (phydev->speed == SPEED_10)
|
| 1566 |
|
|
upsmr |= UPSMR_R10M;
|
| 1567 |
|
|
else
|
| 1568 |
|
|
upsmr &= ~(UPSMR_R10M);
|
| 1569 |
|
|
}
|
| 1570 |
|
|
break;
|
| 1571 |
|
|
default:
|
| 1572 |
|
|
if (netif_msg_link(ugeth))
|
| 1573 |
|
|
ugeth_warn(
|
| 1574 |
|
|
"%s: Ack! Speed (%d) is not 10/100/1000!",
|
| 1575 |
|
|
dev->name, phydev->speed);
|
| 1576 |
|
|
break;
|
| 1577 |
|
|
}
|
| 1578 |
|
|
ugeth->oldspeed = phydev->speed;
|
| 1579 |
|
|
}
|
| 1580 |
|
|
|
| 1581 |
|
|
out_be32(&ug_regs->maccfg2, tempval);
|
| 1582 |
|
|
out_be32(&uf_regs->upsmr, upsmr);
|
| 1583 |
|
|
|
| 1584 |
|
|
if (!ugeth->oldlink) {
|
| 1585 |
|
|
new_state = 1;
|
| 1586 |
|
|
ugeth->oldlink = 1;
|
| 1587 |
|
|
netif_schedule(dev);
|
| 1588 |
|
|
}
|
| 1589 |
|
|
} else if (ugeth->oldlink) {
|
| 1590 |
|
|
new_state = 1;
|
| 1591 |
|
|
ugeth->oldlink = 0;
|
| 1592 |
|
|
ugeth->oldspeed = 0;
|
| 1593 |
|
|
ugeth->oldduplex = -1;
|
| 1594 |
|
|
}
|
| 1595 |
|
|
|
| 1596 |
|
|
if (new_state && netif_msg_link(ugeth))
|
| 1597 |
|
|
phy_print_status(phydev);
|
| 1598 |
|
|
|
| 1599 |
|
|
spin_unlock_irqrestore(&ugeth->lock, flags);
|
| 1600 |
|
|
}
|
| 1601 |
|
|
|
| 1602 |
|
|
/* Configure the PHY for dev.
|
| 1603 |
|
|
* returns 0 if success. -1 if failure
|
| 1604 |
|
|
*/
|
| 1605 |
|
|
static int init_phy(struct net_device *dev)
|
| 1606 |
|
|
{
|
| 1607 |
|
|
struct ucc_geth_private *priv = netdev_priv(dev);
|
| 1608 |
|
|
struct phy_device *phydev;
|
| 1609 |
|
|
char phy_id[BUS_ID_SIZE];
|
| 1610 |
|
|
|
| 1611 |
|
|
priv->oldlink = 0;
|
| 1612 |
|
|
priv->oldspeed = 0;
|
| 1613 |
|
|
priv->oldduplex = -1;
|
| 1614 |
|
|
|
| 1615 |
|
|
snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
|
| 1616 |
|
|
priv->ug_info->phy_address);
|
| 1617 |
|
|
|
| 1618 |
|
|
phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
|
| 1619 |
|
|
|
| 1620 |
|
|
if (IS_ERR(phydev)) {
|
| 1621 |
|
|
printk("%s: Could not attach to PHY\n", dev->name);
|
| 1622 |
|
|
return PTR_ERR(phydev);
|
| 1623 |
|
|
}
|
| 1624 |
|
|
|
| 1625 |
|
|
phydev->supported &= (ADVERTISED_10baseT_Half |
|
| 1626 |
|
|
ADVERTISED_10baseT_Full |
|
| 1627 |
|
|
ADVERTISED_100baseT_Half |
|
| 1628 |
|
|
ADVERTISED_100baseT_Full);
|
| 1629 |
|
|
|
| 1630 |
|
|
if (priv->max_speed == SPEED_1000)
|
| 1631 |
|
|
phydev->supported |= ADVERTISED_1000baseT_Full;
|
| 1632 |
|
|
|
| 1633 |
|
|
phydev->advertising = phydev->supported;
|
| 1634 |
|
|
|
| 1635 |
|
|
priv->phydev = phydev;
|
| 1636 |
|
|
|
| 1637 |
|
|
return 0;
|
| 1638 |
|
|
}
|
| 1639 |
|
|
|
| 1640 |
|
|
|
| 1641 |
|
|
|
| 1642 |
|
|
static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
|
| 1643 |
|
|
{
|
| 1644 |
|
|
struct ucc_fast_private *uccf;
|
| 1645 |
|
|
u32 cecr_subblock;
|
| 1646 |
|
|
u32 temp;
|
| 1647 |
|
|
|
| 1648 |
|
|
uccf = ugeth->uccf;
|
| 1649 |
|
|
|
| 1650 |
|
|
/* Mask GRACEFUL STOP TX interrupt bit and clear it */
|
| 1651 |
|
|
temp = in_be32(uccf->p_uccm);
|
| 1652 |
|
|
temp &= ~UCCE_GRA;
|
| 1653 |
|
|
out_be32(uccf->p_uccm, temp);
|
| 1654 |
|
|
out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
|
| 1655 |
|
|
|
| 1656 |
|
|
/* Issue host command */
|
| 1657 |
|
|
cecr_subblock =
|
| 1658 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
|
| 1659 |
|
|
qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
|
| 1660 |
|
|
QE_CR_PROTOCOL_ETHERNET, 0);
|
| 1661 |
|
|
|
| 1662 |
|
|
/* Wait for command to complete */
|
| 1663 |
|
|
do {
|
| 1664 |
|
|
temp = in_be32(uccf->p_ucce);
|
| 1665 |
|
|
} while (!(temp & UCCE_GRA));
|
| 1666 |
|
|
|
| 1667 |
|
|
uccf->stopped_tx = 1;
|
| 1668 |
|
|
|
| 1669 |
|
|
return 0;
|
| 1670 |
|
|
}
|
| 1671 |
|
|
|
| 1672 |
|
|
static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
|
| 1673 |
|
|
{
|
| 1674 |
|
|
struct ucc_fast_private *uccf;
|
| 1675 |
|
|
u32 cecr_subblock;
|
| 1676 |
|
|
u8 temp;
|
| 1677 |
|
|
|
| 1678 |
|
|
uccf = ugeth->uccf;
|
| 1679 |
|
|
|
| 1680 |
|
|
/* Clear acknowledge bit */
|
| 1681 |
|
|
temp = ugeth->p_rx_glbl_pram->rxgstpack;
|
| 1682 |
|
|
temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
|
| 1683 |
|
|
ugeth->p_rx_glbl_pram->rxgstpack = temp;
|
| 1684 |
|
|
|
| 1685 |
|
|
/* Keep issuing command and checking acknowledge bit until
|
| 1686 |
|
|
it is asserted, according to spec */
|
| 1687 |
|
|
do {
|
| 1688 |
|
|
/* Issue host command */
|
| 1689 |
|
|
cecr_subblock =
|
| 1690 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
|
| 1691 |
|
|
ucc_num);
|
| 1692 |
|
|
qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
|
| 1693 |
|
|
QE_CR_PROTOCOL_ETHERNET, 0);
|
| 1694 |
|
|
|
| 1695 |
|
|
temp = ugeth->p_rx_glbl_pram->rxgstpack;
|
| 1696 |
|
|
} while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
|
| 1697 |
|
|
|
| 1698 |
|
|
uccf->stopped_rx = 1;
|
| 1699 |
|
|
|
| 1700 |
|
|
return 0;
|
| 1701 |
|
|
}
|
| 1702 |
|
|
|
| 1703 |
|
|
static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
|
| 1704 |
|
|
{
|
| 1705 |
|
|
struct ucc_fast_private *uccf;
|
| 1706 |
|
|
u32 cecr_subblock;
|
| 1707 |
|
|
|
| 1708 |
|
|
uccf = ugeth->uccf;
|
| 1709 |
|
|
|
| 1710 |
|
|
cecr_subblock =
|
| 1711 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
|
| 1712 |
|
|
qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
|
| 1713 |
|
|
uccf->stopped_tx = 0;
|
| 1714 |
|
|
|
| 1715 |
|
|
return 0;
|
| 1716 |
|
|
}
|
| 1717 |
|
|
|
| 1718 |
|
|
static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
|
| 1719 |
|
|
{
|
| 1720 |
|
|
struct ucc_fast_private *uccf;
|
| 1721 |
|
|
u32 cecr_subblock;
|
| 1722 |
|
|
|
| 1723 |
|
|
uccf = ugeth->uccf;
|
| 1724 |
|
|
|
| 1725 |
|
|
cecr_subblock =
|
| 1726 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
|
| 1727 |
|
|
qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
|
| 1728 |
|
|
0);
|
| 1729 |
|
|
uccf->stopped_rx = 0;
|
| 1730 |
|
|
|
| 1731 |
|
|
return 0;
|
| 1732 |
|
|
}
|
| 1733 |
|
|
|
| 1734 |
|
|
static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
|
| 1735 |
|
|
{
|
| 1736 |
|
|
struct ucc_fast_private *uccf;
|
| 1737 |
|
|
int enabled_tx, enabled_rx;
|
| 1738 |
|
|
|
| 1739 |
|
|
uccf = ugeth->uccf;
|
| 1740 |
|
|
|
| 1741 |
|
|
/* check if the UCC number is in range. */
|
| 1742 |
|
|
if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
|
| 1743 |
|
|
if (netif_msg_probe(ugeth))
|
| 1744 |
|
|
ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
|
| 1745 |
|
|
return -EINVAL;
|
| 1746 |
|
|
}
|
| 1747 |
|
|
|
| 1748 |
|
|
enabled_tx = uccf->enabled_tx;
|
| 1749 |
|
|
enabled_rx = uccf->enabled_rx;
|
| 1750 |
|
|
|
| 1751 |
|
|
/* Get Tx and Rx going again, in case this channel was actively
|
| 1752 |
|
|
disabled. */
|
| 1753 |
|
|
if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
|
| 1754 |
|
|
ugeth_restart_tx(ugeth);
|
| 1755 |
|
|
if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
|
| 1756 |
|
|
ugeth_restart_rx(ugeth);
|
| 1757 |
|
|
|
| 1758 |
|
|
ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
|
| 1759 |
|
|
|
| 1760 |
|
|
return 0;
|
| 1761 |
|
|
|
| 1762 |
|
|
}
|
| 1763 |
|
|
|
| 1764 |
|
|
static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
|
| 1765 |
|
|
{
|
| 1766 |
|
|
struct ucc_fast_private *uccf;
|
| 1767 |
|
|
|
| 1768 |
|
|
uccf = ugeth->uccf;
|
| 1769 |
|
|
|
| 1770 |
|
|
/* check if the UCC number is in range. */
|
| 1771 |
|
|
if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
|
| 1772 |
|
|
if (netif_msg_probe(ugeth))
|
| 1773 |
|
|
ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
|
| 1774 |
|
|
return -EINVAL;
|
| 1775 |
|
|
}
|
| 1776 |
|
|
|
| 1777 |
|
|
/* Stop any transmissions */
|
| 1778 |
|
|
if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
|
| 1779 |
|
|
ugeth_graceful_stop_tx(ugeth);
|
| 1780 |
|
|
|
| 1781 |
|
|
/* Stop any receptions */
|
| 1782 |
|
|
if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
|
| 1783 |
|
|
ugeth_graceful_stop_rx(ugeth);
|
| 1784 |
|
|
|
| 1785 |
|
|
ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
|
| 1786 |
|
|
|
| 1787 |
|
|
return 0;
|
| 1788 |
|
|
}
|
| 1789 |
|
|
|
| 1790 |
|
|
static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
|
| 1791 |
|
|
{
|
| 1792 |
|
|
#ifdef DEBUG
|
| 1793 |
|
|
ucc_fast_dump_regs(ugeth->uccf);
|
| 1794 |
|
|
dump_regs(ugeth);
|
| 1795 |
|
|
dump_bds(ugeth);
|
| 1796 |
|
|
#endif
|
| 1797 |
|
|
}
|
| 1798 |
|
|
|
| 1799 |
|
|
#ifdef CONFIG_UGETH_FILTERING
|
| 1800 |
|
|
static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
|
| 1801 |
|
|
p_UccGethTadParams,
|
| 1802 |
|
|
struct qe_fltr_tad *qe_fltr_tad)
|
| 1803 |
|
|
{
|
| 1804 |
|
|
u16 temp;
|
| 1805 |
|
|
|
| 1806 |
|
|
/* Zero serialized TAD */
|
| 1807 |
|
|
memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
|
| 1808 |
|
|
|
| 1809 |
|
|
qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
|
| 1810 |
|
|
if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
|
| 1811 |
|
|
(p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
|
| 1812 |
|
|
|| (p_UccGethTadParams->vnontag_op !=
|
| 1813 |
|
|
UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
|
| 1814 |
|
|
)
|
| 1815 |
|
|
qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
|
| 1816 |
|
|
if (p_UccGethTadParams->reject_frame)
|
| 1817 |
|
|
qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
|
| 1818 |
|
|
temp =
|
| 1819 |
|
|
(u16) (((u16) p_UccGethTadParams->
|
| 1820 |
|
|
vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
|
| 1821 |
|
|
qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
|
| 1822 |
|
|
|
| 1823 |
|
|
qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
|
| 1824 |
|
|
if (p_UccGethTadParams->vnontag_op ==
|
| 1825 |
|
|
UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
|
| 1826 |
|
|
qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
|
| 1827 |
|
|
qe_fltr_tad->serialized[1] |=
|
| 1828 |
|
|
p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
|
| 1829 |
|
|
|
| 1830 |
|
|
qe_fltr_tad->serialized[2] |=
|
| 1831 |
|
|
p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
|
| 1832 |
|
|
/* upper bits */
|
| 1833 |
|
|
qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
|
| 1834 |
|
|
/* lower bits */
|
| 1835 |
|
|
qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
|
| 1836 |
|
|
|
| 1837 |
|
|
return 0;
|
| 1838 |
|
|
}
|
| 1839 |
|
|
|
| 1840 |
|
|
static struct enet_addr_container_t
|
| 1841 |
|
|
*ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
|
| 1842 |
|
|
struct enet_addr *p_enet_addr)
|
| 1843 |
|
|
{
|
| 1844 |
|
|
struct enet_addr_container *enet_addr_cont;
|
| 1845 |
|
|
struct list_head *p_lh;
|
| 1846 |
|
|
u16 i, num;
|
| 1847 |
|
|
int32_t j;
|
| 1848 |
|
|
u8 *p_counter;
|
| 1849 |
|
|
|
| 1850 |
|
|
if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
|
| 1851 |
|
|
p_lh = &ugeth->group_hash_q;
|
| 1852 |
|
|
p_counter = &(ugeth->numGroupAddrInHash);
|
| 1853 |
|
|
} else {
|
| 1854 |
|
|
p_lh = &ugeth->ind_hash_q;
|
| 1855 |
|
|
p_counter = &(ugeth->numIndAddrInHash);
|
| 1856 |
|
|
}
|
| 1857 |
|
|
|
| 1858 |
|
|
if (!p_lh)
|
| 1859 |
|
|
return NULL;
|
| 1860 |
|
|
|
| 1861 |
|
|
num = *p_counter;
|
| 1862 |
|
|
|
| 1863 |
|
|
for (i = 0; i < num; i++) {
|
| 1864 |
|
|
enet_addr_cont =
|
| 1865 |
|
|
(struct enet_addr_container *)
|
| 1866 |
|
|
ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
|
| 1867 |
|
|
for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
|
| 1868 |
|
|
if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
|
| 1869 |
|
|
break;
|
| 1870 |
|
|
if (j == 0)
|
| 1871 |
|
|
return enet_addr_cont; /* Found */
|
| 1872 |
|
|
}
|
| 1873 |
|
|
enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
|
| 1874 |
|
|
}
|
| 1875 |
|
|
return NULL;
|
| 1876 |
|
|
}
|
| 1877 |
|
|
|
| 1878 |
|
|
static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
|
| 1879 |
|
|
struct enet_addr *p_enet_addr)
|
| 1880 |
|
|
{
|
| 1881 |
|
|
enum ucc_geth_enet_address_recognition_location location;
|
| 1882 |
|
|
struct enet_addr_container *enet_addr_cont;
|
| 1883 |
|
|
struct list_head *p_lh;
|
| 1884 |
|
|
u8 i;
|
| 1885 |
|
|
u32 limit;
|
| 1886 |
|
|
u8 *p_counter;
|
| 1887 |
|
|
|
| 1888 |
|
|
if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
|
| 1889 |
|
|
p_lh = &ugeth->group_hash_q;
|
| 1890 |
|
|
limit = ugeth->ug_info->maxGroupAddrInHash;
|
| 1891 |
|
|
location =
|
| 1892 |
|
|
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
|
| 1893 |
|
|
p_counter = &(ugeth->numGroupAddrInHash);
|
| 1894 |
|
|
} else {
|
| 1895 |
|
|
p_lh = &ugeth->ind_hash_q;
|
| 1896 |
|
|
limit = ugeth->ug_info->maxIndAddrInHash;
|
| 1897 |
|
|
location =
|
| 1898 |
|
|
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
|
| 1899 |
|
|
p_counter = &(ugeth->numIndAddrInHash);
|
| 1900 |
|
|
}
|
| 1901 |
|
|
|
| 1902 |
|
|
if ((enet_addr_cont =
|
| 1903 |
|
|
ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
|
| 1904 |
|
|
list_add(p_lh, &enet_addr_cont->node); /* Put it back */
|
| 1905 |
|
|
return 0;
|
| 1906 |
|
|
}
|
| 1907 |
|
|
if ((!p_lh) || (!(*p_counter < limit)))
|
| 1908 |
|
|
return -EBUSY;
|
| 1909 |
|
|
if (!(enet_addr_cont = get_enet_addr_container()))
|
| 1910 |
|
|
return -ENOMEM;
|
| 1911 |
|
|
for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
|
| 1912 |
|
|
(enet_addr_cont->address)[i] = (*p_enet_addr)[i];
|
| 1913 |
|
|
enet_addr_cont->location = location;
|
| 1914 |
|
|
enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
|
| 1915 |
|
|
++(*p_counter);
|
| 1916 |
|
|
|
| 1917 |
|
|
hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
|
| 1918 |
|
|
return 0;
|
| 1919 |
|
|
}
|
| 1920 |
|
|
|
| 1921 |
|
|
static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
|
| 1922 |
|
|
struct enet_addr *p_enet_addr)
|
| 1923 |
|
|
{
|
| 1924 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 1925 |
|
|
struct enet_addr_container *enet_addr_cont;
|
| 1926 |
|
|
struct ucc_fast_private *uccf;
|
| 1927 |
|
|
enum comm_dir comm_dir;
|
| 1928 |
|
|
u16 i, num;
|
| 1929 |
|
|
struct list_head *p_lh;
|
| 1930 |
|
|
u32 *addr_h, *addr_l;
|
| 1931 |
|
|
u8 *p_counter;
|
| 1932 |
|
|
|
| 1933 |
|
|
uccf = ugeth->uccf;
|
| 1934 |
|
|
|
| 1935 |
|
|
p_82xx_addr_filt =
|
| 1936 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
|
| 1937 |
|
|
addressfiltering;
|
| 1938 |
|
|
|
| 1939 |
|
|
if (!
|
| 1940 |
|
|
(enet_addr_cont =
|
| 1941 |
|
|
ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
|
| 1942 |
|
|
return -ENOENT;
|
| 1943 |
|
|
|
| 1944 |
|
|
/* It's been found and removed from the CQ. */
|
| 1945 |
|
|
/* Now destroy its container */
|
| 1946 |
|
|
put_enet_addr_container(enet_addr_cont);
|
| 1947 |
|
|
|
| 1948 |
|
|
if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
|
| 1949 |
|
|
addr_h = &(p_82xx_addr_filt->gaddr_h);
|
| 1950 |
|
|
addr_l = &(p_82xx_addr_filt->gaddr_l);
|
| 1951 |
|
|
p_lh = &ugeth->group_hash_q;
|
| 1952 |
|
|
p_counter = &(ugeth->numGroupAddrInHash);
|
| 1953 |
|
|
} else {
|
| 1954 |
|
|
addr_h = &(p_82xx_addr_filt->iaddr_h);
|
| 1955 |
|
|
addr_l = &(p_82xx_addr_filt->iaddr_l);
|
| 1956 |
|
|
p_lh = &ugeth->ind_hash_q;
|
| 1957 |
|
|
p_counter = &(ugeth->numIndAddrInHash);
|
| 1958 |
|
|
}
|
| 1959 |
|
|
|
| 1960 |
|
|
comm_dir = 0;
|
| 1961 |
|
|
if (uccf->enabled_tx)
|
| 1962 |
|
|
comm_dir |= COMM_DIR_TX;
|
| 1963 |
|
|
if (uccf->enabled_rx)
|
| 1964 |
|
|
comm_dir |= COMM_DIR_RX;
|
| 1965 |
|
|
if (comm_dir)
|
| 1966 |
|
|
ugeth_disable(ugeth, comm_dir);
|
| 1967 |
|
|
|
| 1968 |
|
|
/* Clear the hash table. */
|
| 1969 |
|
|
out_be32(addr_h, 0x00000000);
|
| 1970 |
|
|
out_be32(addr_l, 0x00000000);
|
| 1971 |
|
|
|
| 1972 |
|
|
/* Add all remaining CQ elements back into hash */
|
| 1973 |
|
|
num = --(*p_counter);
|
| 1974 |
|
|
for (i = 0; i < num; i++) {
|
| 1975 |
|
|
enet_addr_cont =
|
| 1976 |
|
|
(struct enet_addr_container *)
|
| 1977 |
|
|
ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
|
| 1978 |
|
|
hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
|
| 1979 |
|
|
enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
|
| 1980 |
|
|
}
|
| 1981 |
|
|
|
| 1982 |
|
|
if (comm_dir)
|
| 1983 |
|
|
ugeth_enable(ugeth, comm_dir);
|
| 1984 |
|
|
|
| 1985 |
|
|
return 0;
|
| 1986 |
|
|
}
|
| 1987 |
|
|
#endif /* CONFIG_UGETH_FILTERING */
|
| 1988 |
|
|
|
| 1989 |
|
|
static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
|
| 1990 |
|
|
ugeth,
|
| 1991 |
|
|
enum enet_addr_type
|
| 1992 |
|
|
enet_addr_type)
|
| 1993 |
|
|
{
|
| 1994 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 1995 |
|
|
struct ucc_fast_private *uccf;
|
| 1996 |
|
|
enum comm_dir comm_dir;
|
| 1997 |
|
|
struct list_head *p_lh;
|
| 1998 |
|
|
u16 i, num;
|
| 1999 |
|
|
u32 *addr_h, *addr_l;
|
| 2000 |
|
|
u8 *p_counter;
|
| 2001 |
|
|
|
| 2002 |
|
|
uccf = ugeth->uccf;
|
| 2003 |
|
|
|
| 2004 |
|
|
p_82xx_addr_filt =
|
| 2005 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
|
| 2006 |
|
|
addressfiltering;
|
| 2007 |
|
|
|
| 2008 |
|
|
if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
|
| 2009 |
|
|
addr_h = &(p_82xx_addr_filt->gaddr_h);
|
| 2010 |
|
|
addr_l = &(p_82xx_addr_filt->gaddr_l);
|
| 2011 |
|
|
p_lh = &ugeth->group_hash_q;
|
| 2012 |
|
|
p_counter = &(ugeth->numGroupAddrInHash);
|
| 2013 |
|
|
} else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
|
| 2014 |
|
|
addr_h = &(p_82xx_addr_filt->iaddr_h);
|
| 2015 |
|
|
addr_l = &(p_82xx_addr_filt->iaddr_l);
|
| 2016 |
|
|
p_lh = &ugeth->ind_hash_q;
|
| 2017 |
|
|
p_counter = &(ugeth->numIndAddrInHash);
|
| 2018 |
|
|
} else
|
| 2019 |
|
|
return -EINVAL;
|
| 2020 |
|
|
|
| 2021 |
|
|
comm_dir = 0;
|
| 2022 |
|
|
if (uccf->enabled_tx)
|
| 2023 |
|
|
comm_dir |= COMM_DIR_TX;
|
| 2024 |
|
|
if (uccf->enabled_rx)
|
| 2025 |
|
|
comm_dir |= COMM_DIR_RX;
|
| 2026 |
|
|
if (comm_dir)
|
| 2027 |
|
|
ugeth_disable(ugeth, comm_dir);
|
| 2028 |
|
|
|
| 2029 |
|
|
/* Clear the hash table. */
|
| 2030 |
|
|
out_be32(addr_h, 0x00000000);
|
| 2031 |
|
|
out_be32(addr_l, 0x00000000);
|
| 2032 |
|
|
|
| 2033 |
|
|
if (!p_lh)
|
| 2034 |
|
|
return 0;
|
| 2035 |
|
|
|
| 2036 |
|
|
num = *p_counter;
|
| 2037 |
|
|
|
| 2038 |
|
|
/* Delete all remaining CQ elements */
|
| 2039 |
|
|
for (i = 0; i < num; i++)
|
| 2040 |
|
|
put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
|
| 2041 |
|
|
|
| 2042 |
|
|
*p_counter = 0;
|
| 2043 |
|
|
|
| 2044 |
|
|
if (comm_dir)
|
| 2045 |
|
|
ugeth_enable(ugeth, comm_dir);
|
| 2046 |
|
|
|
| 2047 |
|
|
return 0;
|
| 2048 |
|
|
}
|
| 2049 |
|
|
|
| 2050 |
|
|
#ifdef CONFIG_UGETH_FILTERING
|
| 2051 |
|
|
static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
|
| 2052 |
|
|
struct enet_addr *p_enet_addr,
|
| 2053 |
|
|
u8 paddr_num)
|
| 2054 |
|
|
{
|
| 2055 |
|
|
int i;
|
| 2056 |
|
|
|
| 2057 |
|
|
if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
|
| 2058 |
|
|
ugeth_warn
|
| 2059 |
|
|
("%s: multicast address added to paddr will have no "
|
| 2060 |
|
|
"effect - is this what you wanted?",
|
| 2061 |
|
|
__FUNCTION__);
|
| 2062 |
|
|
|
| 2063 |
|
|
ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
|
| 2064 |
|
|
/* store address in our database */
|
| 2065 |
|
|
for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
|
| 2066 |
|
|
ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
|
| 2067 |
|
|
/* put in hardware */
|
| 2068 |
|
|
return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
|
| 2069 |
|
|
}
|
| 2070 |
|
|
#endif /* CONFIG_UGETH_FILTERING */
|
| 2071 |
|
|
|
| 2072 |
|
|
static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
|
| 2073 |
|
|
u8 paddr_num)
|
| 2074 |
|
|
{
|
| 2075 |
|
|
ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
|
| 2076 |
|
|
return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
|
| 2077 |
|
|
}
|
| 2078 |
|
|
|
| 2079 |
|
|
static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
|
| 2080 |
|
|
{
|
| 2081 |
|
|
u16 i, j;
|
| 2082 |
|
|
u8 *bd;
|
| 2083 |
|
|
|
| 2084 |
|
|
if (!ugeth)
|
| 2085 |
|
|
return;
|
| 2086 |
|
|
|
| 2087 |
|
|
if (ugeth->uccf)
|
| 2088 |
|
|
ucc_fast_free(ugeth->uccf);
|
| 2089 |
|
|
|
| 2090 |
|
|
if (ugeth->p_thread_data_tx) {
|
| 2091 |
|
|
qe_muram_free(ugeth->thread_dat_tx_offset);
|
| 2092 |
|
|
ugeth->p_thread_data_tx = NULL;
|
| 2093 |
|
|
}
|
| 2094 |
|
|
if (ugeth->p_thread_data_rx) {
|
| 2095 |
|
|
qe_muram_free(ugeth->thread_dat_rx_offset);
|
| 2096 |
|
|
ugeth->p_thread_data_rx = NULL;
|
| 2097 |
|
|
}
|
| 2098 |
|
|
if (ugeth->p_exf_glbl_param) {
|
| 2099 |
|
|
qe_muram_free(ugeth->exf_glbl_param_offset);
|
| 2100 |
|
|
ugeth->p_exf_glbl_param = NULL;
|
| 2101 |
|
|
}
|
| 2102 |
|
|
if (ugeth->p_rx_glbl_pram) {
|
| 2103 |
|
|
qe_muram_free(ugeth->rx_glbl_pram_offset);
|
| 2104 |
|
|
ugeth->p_rx_glbl_pram = NULL;
|
| 2105 |
|
|
}
|
| 2106 |
|
|
if (ugeth->p_tx_glbl_pram) {
|
| 2107 |
|
|
qe_muram_free(ugeth->tx_glbl_pram_offset);
|
| 2108 |
|
|
ugeth->p_tx_glbl_pram = NULL;
|
| 2109 |
|
|
}
|
| 2110 |
|
|
if (ugeth->p_send_q_mem_reg) {
|
| 2111 |
|
|
qe_muram_free(ugeth->send_q_mem_reg_offset);
|
| 2112 |
|
|
ugeth->p_send_q_mem_reg = NULL;
|
| 2113 |
|
|
}
|
| 2114 |
|
|
if (ugeth->p_scheduler) {
|
| 2115 |
|
|
qe_muram_free(ugeth->scheduler_offset);
|
| 2116 |
|
|
ugeth->p_scheduler = NULL;
|
| 2117 |
|
|
}
|
| 2118 |
|
|
if (ugeth->p_tx_fw_statistics_pram) {
|
| 2119 |
|
|
qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
|
| 2120 |
|
|
ugeth->p_tx_fw_statistics_pram = NULL;
|
| 2121 |
|
|
}
|
| 2122 |
|
|
if (ugeth->p_rx_fw_statistics_pram) {
|
| 2123 |
|
|
qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
|
| 2124 |
|
|
ugeth->p_rx_fw_statistics_pram = NULL;
|
| 2125 |
|
|
}
|
| 2126 |
|
|
if (ugeth->p_rx_irq_coalescing_tbl) {
|
| 2127 |
|
|
qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
|
| 2128 |
|
|
ugeth->p_rx_irq_coalescing_tbl = NULL;
|
| 2129 |
|
|
}
|
| 2130 |
|
|
if (ugeth->p_rx_bd_qs_tbl) {
|
| 2131 |
|
|
qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
|
| 2132 |
|
|
ugeth->p_rx_bd_qs_tbl = NULL;
|
| 2133 |
|
|
}
|
| 2134 |
|
|
if (ugeth->p_init_enet_param_shadow) {
|
| 2135 |
|
|
return_init_enet_entries(ugeth,
|
| 2136 |
|
|
&(ugeth->p_init_enet_param_shadow->
|
| 2137 |
|
|
rxthread[0]),
|
| 2138 |
|
|
ENET_INIT_PARAM_MAX_ENTRIES_RX,
|
| 2139 |
|
|
ugeth->ug_info->riscRx, 1);
|
| 2140 |
|
|
return_init_enet_entries(ugeth,
|
| 2141 |
|
|
&(ugeth->p_init_enet_param_shadow->
|
| 2142 |
|
|
txthread[0]),
|
| 2143 |
|
|
ENET_INIT_PARAM_MAX_ENTRIES_TX,
|
| 2144 |
|
|
ugeth->ug_info->riscTx, 0);
|
| 2145 |
|
|
kfree(ugeth->p_init_enet_param_shadow);
|
| 2146 |
|
|
ugeth->p_init_enet_param_shadow = NULL;
|
| 2147 |
|
|
}
|
| 2148 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
|
| 2149 |
|
|
bd = ugeth->p_tx_bd_ring[i];
|
| 2150 |
|
|
if (!bd)
|
| 2151 |
|
|
continue;
|
| 2152 |
|
|
for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
|
| 2153 |
|
|
if (ugeth->tx_skbuff[i][j]) {
|
| 2154 |
|
|
dma_unmap_single(NULL,
|
| 2155 |
|
|
((struct qe_bd *)bd)->buf,
|
| 2156 |
|
|
(in_be32((u32 *)bd) &
|
| 2157 |
|
|
BD_LENGTH_MASK),
|
| 2158 |
|
|
DMA_TO_DEVICE);
|
| 2159 |
|
|
dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
|
| 2160 |
|
|
ugeth->tx_skbuff[i][j] = NULL;
|
| 2161 |
|
|
}
|
| 2162 |
|
|
}
|
| 2163 |
|
|
|
| 2164 |
|
|
kfree(ugeth->tx_skbuff[i]);
|
| 2165 |
|
|
|
| 2166 |
|
|
if (ugeth->p_tx_bd_ring[i]) {
|
| 2167 |
|
|
if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 2168 |
|
|
MEM_PART_SYSTEM)
|
| 2169 |
|
|
kfree((void *)ugeth->tx_bd_ring_offset[i]);
|
| 2170 |
|
|
else if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 2171 |
|
|
MEM_PART_MURAM)
|
| 2172 |
|
|
qe_muram_free(ugeth->tx_bd_ring_offset[i]);
|
| 2173 |
|
|
ugeth->p_tx_bd_ring[i] = NULL;
|
| 2174 |
|
|
}
|
| 2175 |
|
|
}
|
| 2176 |
|
|
for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
|
| 2177 |
|
|
if (ugeth->p_rx_bd_ring[i]) {
|
| 2178 |
|
|
/* Return existing data buffers in ring */
|
| 2179 |
|
|
bd = ugeth->p_rx_bd_ring[i];
|
| 2180 |
|
|
for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
|
| 2181 |
|
|
if (ugeth->rx_skbuff[i][j]) {
|
| 2182 |
|
|
dma_unmap_single(NULL,
|
| 2183 |
|
|
((struct qe_bd *)bd)->buf,
|
| 2184 |
|
|
ugeth->ug_info->
|
| 2185 |
|
|
uf_info.max_rx_buf_length +
|
| 2186 |
|
|
UCC_GETH_RX_DATA_BUF_ALIGNMENT,
|
| 2187 |
|
|
DMA_FROM_DEVICE);
|
| 2188 |
|
|
dev_kfree_skb_any(
|
| 2189 |
|
|
ugeth->rx_skbuff[i][j]);
|
| 2190 |
|
|
ugeth->rx_skbuff[i][j] = NULL;
|
| 2191 |
|
|
}
|
| 2192 |
|
|
bd += sizeof(struct qe_bd);
|
| 2193 |
|
|
}
|
| 2194 |
|
|
|
| 2195 |
|
|
kfree(ugeth->rx_skbuff[i]);
|
| 2196 |
|
|
|
| 2197 |
|
|
if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 2198 |
|
|
MEM_PART_SYSTEM)
|
| 2199 |
|
|
kfree((void *)ugeth->rx_bd_ring_offset[i]);
|
| 2200 |
|
|
else if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 2201 |
|
|
MEM_PART_MURAM)
|
| 2202 |
|
|
qe_muram_free(ugeth->rx_bd_ring_offset[i]);
|
| 2203 |
|
|
ugeth->p_rx_bd_ring[i] = NULL;
|
| 2204 |
|
|
}
|
| 2205 |
|
|
}
|
| 2206 |
|
|
while (!list_empty(&ugeth->group_hash_q))
|
| 2207 |
|
|
put_enet_addr_container(ENET_ADDR_CONT_ENTRY
|
| 2208 |
|
|
(dequeue(&ugeth->group_hash_q)));
|
| 2209 |
|
|
while (!list_empty(&ugeth->ind_hash_q))
|
| 2210 |
|
|
put_enet_addr_container(ENET_ADDR_CONT_ENTRY
|
| 2211 |
|
|
(dequeue(&ugeth->ind_hash_q)));
|
| 2212 |
|
|
|
| 2213 |
|
|
}
|
| 2214 |
|
|
|
| 2215 |
|
|
static void ucc_geth_set_multi(struct net_device *dev)
|
| 2216 |
|
|
{
|
| 2217 |
|
|
struct ucc_geth_private *ugeth;
|
| 2218 |
|
|
struct dev_mc_list *dmi;
|
| 2219 |
|
|
struct ucc_fast *uf_regs;
|
| 2220 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 2221 |
|
|
int i;
|
| 2222 |
|
|
|
| 2223 |
|
|
ugeth = netdev_priv(dev);
|
| 2224 |
|
|
|
| 2225 |
|
|
uf_regs = ugeth->uccf->uf_regs;
|
| 2226 |
|
|
|
| 2227 |
|
|
if (dev->flags & IFF_PROMISC) {
|
| 2228 |
|
|
|
| 2229 |
|
|
uf_regs->upsmr |= UPSMR_PRO;
|
| 2230 |
|
|
|
| 2231 |
|
|
} else {
|
| 2232 |
|
|
|
| 2233 |
|
|
uf_regs->upsmr &= ~UPSMR_PRO;
|
| 2234 |
|
|
|
| 2235 |
|
|
p_82xx_addr_filt =
|
| 2236 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->
|
| 2237 |
|
|
p_rx_glbl_pram->addressfiltering;
|
| 2238 |
|
|
|
| 2239 |
|
|
if (dev->flags & IFF_ALLMULTI) {
|
| 2240 |
|
|
/* Catch all multicast addresses, so set the
|
| 2241 |
|
|
* filter to all 1's.
|
| 2242 |
|
|
*/
|
| 2243 |
|
|
out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
|
| 2244 |
|
|
out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
|
| 2245 |
|
|
} else {
|
| 2246 |
|
|
/* Clear filter and add the addresses in the list.
|
| 2247 |
|
|
*/
|
| 2248 |
|
|
out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
|
| 2249 |
|
|
out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
|
| 2250 |
|
|
|
| 2251 |
|
|
dmi = dev->mc_list;
|
| 2252 |
|
|
|
| 2253 |
|
|
for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
|
| 2254 |
|
|
|
| 2255 |
|
|
/* Only support group multicast for now.
|
| 2256 |
|
|
*/
|
| 2257 |
|
|
if (!(dmi->dmi_addr[0] & 1))
|
| 2258 |
|
|
continue;
|
| 2259 |
|
|
|
| 2260 |
|
|
/* Ask CPM to run CRC and set bit in
|
| 2261 |
|
|
* filter mask.
|
| 2262 |
|
|
*/
|
| 2263 |
|
|
hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
|
| 2264 |
|
|
}
|
| 2265 |
|
|
}
|
| 2266 |
|
|
}
|
| 2267 |
|
|
}
|
| 2268 |
|
|
|
| 2269 |
|
|
static void ucc_geth_stop(struct ucc_geth_private *ugeth)
|
| 2270 |
|
|
{
|
| 2271 |
|
|
struct ucc_geth *ug_regs = ugeth->ug_regs;
|
| 2272 |
|
|
struct phy_device *phydev = ugeth->phydev;
|
| 2273 |
|
|
u32 tempval;
|
| 2274 |
|
|
|
| 2275 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 2276 |
|
|
|
| 2277 |
|
|
/* Disable the controller */
|
| 2278 |
|
|
ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
|
| 2279 |
|
|
|
| 2280 |
|
|
/* Tell the kernel the link is down */
|
| 2281 |
|
|
phy_stop(phydev);
|
| 2282 |
|
|
|
| 2283 |
|
|
/* Mask all interrupts */
|
| 2284 |
|
|
out_be32(ugeth->uccf->p_uccm, 0x00000000);
|
| 2285 |
|
|
|
| 2286 |
|
|
/* Clear all interrupts */
|
| 2287 |
|
|
out_be32(ugeth->uccf->p_ucce, 0xffffffff);
|
| 2288 |
|
|
|
| 2289 |
|
|
/* Disable Rx and Tx */
|
| 2290 |
|
|
tempval = in_be32(&ug_regs->maccfg1);
|
| 2291 |
|
|
tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
|
| 2292 |
|
|
out_be32(&ug_regs->maccfg1, tempval);
|
| 2293 |
|
|
|
| 2294 |
|
|
free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
|
| 2295 |
|
|
|
| 2296 |
|
|
ucc_geth_memclean(ugeth);
|
| 2297 |
|
|
}
|
| 2298 |
|
|
|
| 2299 |
|
|
static int ucc_struct_init(struct ucc_geth_private *ugeth)
|
| 2300 |
|
|
{
|
| 2301 |
|
|
struct ucc_geth_info *ug_info;
|
| 2302 |
|
|
struct ucc_fast_info *uf_info;
|
| 2303 |
|
|
int i;
|
| 2304 |
|
|
|
| 2305 |
|
|
ug_info = ugeth->ug_info;
|
| 2306 |
|
|
uf_info = &ug_info->uf_info;
|
| 2307 |
|
|
|
| 2308 |
|
|
/* Create CQs for hash tables */
|
| 2309 |
|
|
INIT_LIST_HEAD(&ugeth->group_hash_q);
|
| 2310 |
|
|
INIT_LIST_HEAD(&ugeth->ind_hash_q);
|
| 2311 |
|
|
|
| 2312 |
|
|
if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
|
| 2313 |
|
|
(uf_info->bd_mem_part == MEM_PART_MURAM))) {
|
| 2314 |
|
|
if (netif_msg_probe(ugeth))
|
| 2315 |
|
|
ugeth_err("%s: Bad memory partition value.",
|
| 2316 |
|
|
__FUNCTION__);
|
| 2317 |
|
|
return -EINVAL;
|
| 2318 |
|
|
}
|
| 2319 |
|
|
|
| 2320 |
|
|
/* Rx BD lengths */
|
| 2321 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++) {
|
| 2322 |
|
|
if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
|
| 2323 |
|
|
(ug_info->bdRingLenRx[i] %
|
| 2324 |
|
|
UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
|
| 2325 |
|
|
if (netif_msg_probe(ugeth))
|
| 2326 |
|
|
ugeth_err
|
| 2327 |
|
|
("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
|
| 2328 |
|
|
__FUNCTION__);
|
| 2329 |
|
|
return -EINVAL;
|
| 2330 |
|
|
}
|
| 2331 |
|
|
}
|
| 2332 |
|
|
|
| 2333 |
|
|
/* Tx BD lengths */
|
| 2334 |
|
|
for (i = 0; i < ug_info->numQueuesTx; i++) {
|
| 2335 |
|
|
if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
|
| 2336 |
|
|
if (netif_msg_probe(ugeth))
|
| 2337 |
|
|
ugeth_err
|
| 2338 |
|
|
("%s: Tx BD ring length must be no smaller than 2.",
|
| 2339 |
|
|
__FUNCTION__);
|
| 2340 |
|
|
return -EINVAL;
|
| 2341 |
|
|
}
|
| 2342 |
|
|
}
|
| 2343 |
|
|
|
| 2344 |
|
|
/* mrblr */
|
| 2345 |
|
|
if ((uf_info->max_rx_buf_length == 0) ||
|
| 2346 |
|
|
(uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
|
| 2347 |
|
|
if (netif_msg_probe(ugeth))
|
| 2348 |
|
|
ugeth_err
|
| 2349 |
|
|
("%s: max_rx_buf_length must be non-zero multiple of 128.",
|
| 2350 |
|
|
__FUNCTION__);
|
| 2351 |
|
|
return -EINVAL;
|
| 2352 |
|
|
}
|
| 2353 |
|
|
|
| 2354 |
|
|
/* num Tx queues */
|
| 2355 |
|
|
if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
|
| 2356 |
|
|
if (netif_msg_probe(ugeth))
|
| 2357 |
|
|
ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
|
| 2358 |
|
|
return -EINVAL;
|
| 2359 |
|
|
}
|
| 2360 |
|
|
|
| 2361 |
|
|
/* num Rx queues */
|
| 2362 |
|
|
if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
|
| 2363 |
|
|
if (netif_msg_probe(ugeth))
|
| 2364 |
|
|
ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
|
| 2365 |
|
|
return -EINVAL;
|
| 2366 |
|
|
}
|
| 2367 |
|
|
|
| 2368 |
|
|
/* l2qt */
|
| 2369 |
|
|
for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
|
| 2370 |
|
|
if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
|
| 2371 |
|
|
if (netif_msg_probe(ugeth))
|
| 2372 |
|
|
ugeth_err
|
| 2373 |
|
|
("%s: VLAN priority table entry must not be"
|
| 2374 |
|
|
" larger than number of Rx queues.",
|
| 2375 |
|
|
__FUNCTION__);
|
| 2376 |
|
|
return -EINVAL;
|
| 2377 |
|
|
}
|
| 2378 |
|
|
}
|
| 2379 |
|
|
|
| 2380 |
|
|
/* l3qt */
|
| 2381 |
|
|
for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
|
| 2382 |
|
|
if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
|
| 2383 |
|
|
if (netif_msg_probe(ugeth))
|
| 2384 |
|
|
ugeth_err
|
| 2385 |
|
|
("%s: IP priority table entry must not be"
|
| 2386 |
|
|
" larger than number of Rx queues.",
|
| 2387 |
|
|
__FUNCTION__);
|
| 2388 |
|
|
return -EINVAL;
|
| 2389 |
|
|
}
|
| 2390 |
|
|
}
|
| 2391 |
|
|
|
| 2392 |
|
|
if (ug_info->cam && !ug_info->ecamptr) {
|
| 2393 |
|
|
if (netif_msg_probe(ugeth))
|
| 2394 |
|
|
ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
|
| 2395 |
|
|
__FUNCTION__);
|
| 2396 |
|
|
return -EINVAL;
|
| 2397 |
|
|
}
|
| 2398 |
|
|
|
| 2399 |
|
|
if ((ug_info->numStationAddresses !=
|
| 2400 |
|
|
UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
|
| 2401 |
|
|
&& ug_info->rxExtendedFiltering) {
|
| 2402 |
|
|
if (netif_msg_probe(ugeth))
|
| 2403 |
|
|
ugeth_err("%s: Number of station addresses greater than 1 "
|
| 2404 |
|
|
"not allowed in extended parsing mode.",
|
| 2405 |
|
|
__FUNCTION__);
|
| 2406 |
|
|
return -EINVAL;
|
| 2407 |
|
|
}
|
| 2408 |
|
|
|
| 2409 |
|
|
/* Generate uccm_mask for receive */
|
| 2410 |
|
|
uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
|
| 2411 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++)
|
| 2412 |
|
|
uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
|
| 2413 |
|
|
|
| 2414 |
|
|
for (i = 0; i < ug_info->numQueuesTx; i++)
|
| 2415 |
|
|
uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
|
| 2416 |
|
|
/* Initialize the general fast UCC block. */
|
| 2417 |
|
|
if (ucc_fast_init(uf_info, &ugeth->uccf)) {
|
| 2418 |
|
|
if (netif_msg_probe(ugeth))
|
| 2419 |
|
|
ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
|
| 2420 |
|
|
ucc_geth_memclean(ugeth);
|
| 2421 |
|
|
return -ENOMEM;
|
| 2422 |
|
|
}
|
| 2423 |
|
|
|
| 2424 |
|
|
ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
|
| 2425 |
|
|
|
| 2426 |
|
|
return 0;
|
| 2427 |
|
|
}
|
| 2428 |
|
|
|
| 2429 |
|
|
static int ucc_geth_startup(struct ucc_geth_private *ugeth)
|
| 2430 |
|
|
{
|
| 2431 |
|
|
struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
|
| 2432 |
|
|
struct ucc_geth_init_pram *p_init_enet_pram;
|
| 2433 |
|
|
struct ucc_fast_private *uccf;
|
| 2434 |
|
|
struct ucc_geth_info *ug_info;
|
| 2435 |
|
|
struct ucc_fast_info *uf_info;
|
| 2436 |
|
|
struct ucc_fast *uf_regs;
|
| 2437 |
|
|
struct ucc_geth *ug_regs;
|
| 2438 |
|
|
int ret_val = -EINVAL;
|
| 2439 |
|
|
u32 remoder = UCC_GETH_REMODER_INIT;
|
| 2440 |
|
|
u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
|
| 2441 |
|
|
u32 ifstat, i, j, size, l2qt, l3qt, length;
|
| 2442 |
|
|
u16 temoder = UCC_GETH_TEMODER_INIT;
|
| 2443 |
|
|
u16 test;
|
| 2444 |
|
|
u8 function_code = 0;
|
| 2445 |
|
|
u8 *bd, *endOfRing;
|
| 2446 |
|
|
u8 numThreadsRxNumerical, numThreadsTxNumerical;
|
| 2447 |
|
|
|
| 2448 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 2449 |
|
|
uccf = ugeth->uccf;
|
| 2450 |
|
|
ug_info = ugeth->ug_info;
|
| 2451 |
|
|
uf_info = &ug_info->uf_info;
|
| 2452 |
|
|
uf_regs = uccf->uf_regs;
|
| 2453 |
|
|
ug_regs = ugeth->ug_regs;
|
| 2454 |
|
|
|
| 2455 |
|
|
switch (ug_info->numThreadsRx) {
|
| 2456 |
|
|
case UCC_GETH_NUM_OF_THREADS_1:
|
| 2457 |
|
|
numThreadsRxNumerical = 1;
|
| 2458 |
|
|
break;
|
| 2459 |
|
|
case UCC_GETH_NUM_OF_THREADS_2:
|
| 2460 |
|
|
numThreadsRxNumerical = 2;
|
| 2461 |
|
|
break;
|
| 2462 |
|
|
case UCC_GETH_NUM_OF_THREADS_4:
|
| 2463 |
|
|
numThreadsRxNumerical = 4;
|
| 2464 |
|
|
break;
|
| 2465 |
|
|
case UCC_GETH_NUM_OF_THREADS_6:
|
| 2466 |
|
|
numThreadsRxNumerical = 6;
|
| 2467 |
|
|
break;
|
| 2468 |
|
|
case UCC_GETH_NUM_OF_THREADS_8:
|
| 2469 |
|
|
numThreadsRxNumerical = 8;
|
| 2470 |
|
|
break;
|
| 2471 |
|
|
default:
|
| 2472 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2473 |
|
|
ugeth_err("%s: Bad number of Rx threads value.",
|
| 2474 |
|
|
__FUNCTION__);
|
| 2475 |
|
|
ucc_geth_memclean(ugeth);
|
| 2476 |
|
|
return -EINVAL;
|
| 2477 |
|
|
break;
|
| 2478 |
|
|
}
|
| 2479 |
|
|
|
| 2480 |
|
|
switch (ug_info->numThreadsTx) {
|
| 2481 |
|
|
case UCC_GETH_NUM_OF_THREADS_1:
|
| 2482 |
|
|
numThreadsTxNumerical = 1;
|
| 2483 |
|
|
break;
|
| 2484 |
|
|
case UCC_GETH_NUM_OF_THREADS_2:
|
| 2485 |
|
|
numThreadsTxNumerical = 2;
|
| 2486 |
|
|
break;
|
| 2487 |
|
|
case UCC_GETH_NUM_OF_THREADS_4:
|
| 2488 |
|
|
numThreadsTxNumerical = 4;
|
| 2489 |
|
|
break;
|
| 2490 |
|
|
case UCC_GETH_NUM_OF_THREADS_6:
|
| 2491 |
|
|
numThreadsTxNumerical = 6;
|
| 2492 |
|
|
break;
|
| 2493 |
|
|
case UCC_GETH_NUM_OF_THREADS_8:
|
| 2494 |
|
|
numThreadsTxNumerical = 8;
|
| 2495 |
|
|
break;
|
| 2496 |
|
|
default:
|
| 2497 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2498 |
|
|
ugeth_err("%s: Bad number of Tx threads value.",
|
| 2499 |
|
|
__FUNCTION__);
|
| 2500 |
|
|
ucc_geth_memclean(ugeth);
|
| 2501 |
|
|
return -EINVAL;
|
| 2502 |
|
|
break;
|
| 2503 |
|
|
}
|
| 2504 |
|
|
|
| 2505 |
|
|
/* Calculate rx_extended_features */
|
| 2506 |
|
|
ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
|
| 2507 |
|
|
ug_info->ipAddressAlignment ||
|
| 2508 |
|
|
(ug_info->numStationAddresses !=
|
| 2509 |
|
|
UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
|
| 2510 |
|
|
|
| 2511 |
|
|
ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
|
| 2512 |
|
|
(ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
|
| 2513 |
|
|
|| (ug_info->vlanOperationNonTagged !=
|
| 2514 |
|
|
UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
|
| 2515 |
|
|
|
| 2516 |
|
|
init_default_reg_vals(&uf_regs->upsmr,
|
| 2517 |
|
|
&ug_regs->maccfg1, &ug_regs->maccfg2);
|
| 2518 |
|
|
|
| 2519 |
|
|
/* Set UPSMR */
|
| 2520 |
|
|
/* For more details see the hardware spec. */
|
| 2521 |
|
|
init_rx_parameters(ug_info->bro,
|
| 2522 |
|
|
ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
|
| 2523 |
|
|
|
| 2524 |
|
|
/* We're going to ignore other registers for now, */
|
| 2525 |
|
|
/* except as needed to get up and running */
|
| 2526 |
|
|
|
| 2527 |
|
|
/* Set MACCFG1 */
|
| 2528 |
|
|
/* For more details see the hardware spec. */
|
| 2529 |
|
|
init_flow_control_params(ug_info->aufc,
|
| 2530 |
|
|
ug_info->receiveFlowControl,
|
| 2531 |
|
|
ug_info->transmitFlowControl,
|
| 2532 |
|
|
ug_info->pausePeriod,
|
| 2533 |
|
|
ug_info->extensionField,
|
| 2534 |
|
|
&uf_regs->upsmr,
|
| 2535 |
|
|
&ug_regs->uempr, &ug_regs->maccfg1);
|
| 2536 |
|
|
|
| 2537 |
|
|
maccfg1 = in_be32(&ug_regs->maccfg1);
|
| 2538 |
|
|
maccfg1 |= MACCFG1_ENABLE_RX;
|
| 2539 |
|
|
maccfg1 |= MACCFG1_ENABLE_TX;
|
| 2540 |
|
|
out_be32(&ug_regs->maccfg1, maccfg1);
|
| 2541 |
|
|
|
| 2542 |
|
|
/* Set IPGIFG */
|
| 2543 |
|
|
/* For more details see the hardware spec. */
|
| 2544 |
|
|
ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
|
| 2545 |
|
|
ug_info->nonBackToBackIfgPart2,
|
| 2546 |
|
|
ug_info->
|
| 2547 |
|
|
miminumInterFrameGapEnforcement,
|
| 2548 |
|
|
ug_info->backToBackInterFrameGap,
|
| 2549 |
|
|
&ug_regs->ipgifg);
|
| 2550 |
|
|
if (ret_val != 0) {
|
| 2551 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2552 |
|
|
ugeth_err("%s: IPGIFG initialization parameter too large.",
|
| 2553 |
|
|
__FUNCTION__);
|
| 2554 |
|
|
ucc_geth_memclean(ugeth);
|
| 2555 |
|
|
return ret_val;
|
| 2556 |
|
|
}
|
| 2557 |
|
|
|
| 2558 |
|
|
/* Set HAFDUP */
|
| 2559 |
|
|
/* For more details see the hardware spec. */
|
| 2560 |
|
|
ret_val = init_half_duplex_params(ug_info->altBeb,
|
| 2561 |
|
|
ug_info->backPressureNoBackoff,
|
| 2562 |
|
|
ug_info->noBackoff,
|
| 2563 |
|
|
ug_info->excessDefer,
|
| 2564 |
|
|
ug_info->altBebTruncation,
|
| 2565 |
|
|
ug_info->maxRetransmission,
|
| 2566 |
|
|
ug_info->collisionWindow,
|
| 2567 |
|
|
&ug_regs->hafdup);
|
| 2568 |
|
|
if (ret_val != 0) {
|
| 2569 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2570 |
|
|
ugeth_err("%s: Half Duplex initialization parameter too large.",
|
| 2571 |
|
|
__FUNCTION__);
|
| 2572 |
|
|
ucc_geth_memclean(ugeth);
|
| 2573 |
|
|
return ret_val;
|
| 2574 |
|
|
}
|
| 2575 |
|
|
|
| 2576 |
|
|
/* Set IFSTAT */
|
| 2577 |
|
|
/* For more details see the hardware spec. */
|
| 2578 |
|
|
/* Read only - resets upon read */
|
| 2579 |
|
|
ifstat = in_be32(&ug_regs->ifstat);
|
| 2580 |
|
|
|
| 2581 |
|
|
/* Clear UEMPR */
|
| 2582 |
|
|
/* For more details see the hardware spec. */
|
| 2583 |
|
|
out_be32(&ug_regs->uempr, 0);
|
| 2584 |
|
|
|
| 2585 |
|
|
/* Set UESCR */
|
| 2586 |
|
|
/* For more details see the hardware spec. */
|
| 2587 |
|
|
init_hw_statistics_gathering_mode((ug_info->statisticsMode &
|
| 2588 |
|
|
UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
|
| 2589 |
|
|
0, &uf_regs->upsmr, &ug_regs->uescr);
|
| 2590 |
|
|
|
| 2591 |
|
|
/* Allocate Tx bds */
|
| 2592 |
|
|
for (j = 0; j < ug_info->numQueuesTx; j++) {
|
| 2593 |
|
|
/* Allocate in multiple of
|
| 2594 |
|
|
UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
|
| 2595 |
|
|
according to spec */
|
| 2596 |
|
|
length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
|
| 2597 |
|
|
/ UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
|
| 2598 |
|
|
* UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
|
| 2599 |
|
|
if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
|
| 2600 |
|
|
UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
|
| 2601 |
|
|
length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
|
| 2602 |
|
|
if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
|
| 2603 |
|
|
u32 align = 4;
|
| 2604 |
|
|
if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
|
| 2605 |
|
|
align = UCC_GETH_TX_BD_RING_ALIGNMENT;
|
| 2606 |
|
|
ugeth->tx_bd_ring_offset[j] =
|
| 2607 |
|
|
kmalloc((u32) (length + align), GFP_KERNEL);
|
| 2608 |
|
|
|
| 2609 |
|
|
if (ugeth->tx_bd_ring_offset[j] != 0)
|
| 2610 |
|
|
ugeth->p_tx_bd_ring[j] =
|
| 2611 |
|
|
(void*)((ugeth->tx_bd_ring_offset[j] +
|
| 2612 |
|
|
align) & ~(align - 1));
|
| 2613 |
|
|
} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
|
| 2614 |
|
|
ugeth->tx_bd_ring_offset[j] =
|
| 2615 |
|
|
qe_muram_alloc(length,
|
| 2616 |
|
|
UCC_GETH_TX_BD_RING_ALIGNMENT);
|
| 2617 |
|
|
if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
|
| 2618 |
|
|
ugeth->p_tx_bd_ring[j] =
|
| 2619 |
|
|
(u8 *) qe_muram_addr(ugeth->
|
| 2620 |
|
|
tx_bd_ring_offset[j]);
|
| 2621 |
|
|
}
|
| 2622 |
|
|
if (!ugeth->p_tx_bd_ring[j]) {
|
| 2623 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2624 |
|
|
ugeth_err
|
| 2625 |
|
|
("%s: Can not allocate memory for Tx bd rings.",
|
| 2626 |
|
|
__FUNCTION__);
|
| 2627 |
|
|
ucc_geth_memclean(ugeth);
|
| 2628 |
|
|
return -ENOMEM;
|
| 2629 |
|
|
}
|
| 2630 |
|
|
/* Zero unused end of bd ring, according to spec */
|
| 2631 |
|
|
memset(ugeth->p_tx_bd_ring[j] +
|
| 2632 |
|
|
ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
|
| 2633 |
|
|
length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
|
| 2634 |
|
|
}
|
| 2635 |
|
|
|
| 2636 |
|
|
/* Allocate Rx bds */
|
| 2637 |
|
|
for (j = 0; j < ug_info->numQueuesRx; j++) {
|
| 2638 |
|
|
length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
|
| 2639 |
|
|
if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
|
| 2640 |
|
|
u32 align = 4;
|
| 2641 |
|
|
if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
|
| 2642 |
|
|
align = UCC_GETH_RX_BD_RING_ALIGNMENT;
|
| 2643 |
|
|
ugeth->rx_bd_ring_offset[j] =
|
| 2644 |
|
|
kmalloc((u32) (length + align), GFP_KERNEL);
|
| 2645 |
|
|
if (ugeth->rx_bd_ring_offset[j] != 0)
|
| 2646 |
|
|
ugeth->p_rx_bd_ring[j] =
|
| 2647 |
|
|
(void*)((ugeth->rx_bd_ring_offset[j] +
|
| 2648 |
|
|
align) & ~(align - 1));
|
| 2649 |
|
|
} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
|
| 2650 |
|
|
ugeth->rx_bd_ring_offset[j] =
|
| 2651 |
|
|
qe_muram_alloc(length,
|
| 2652 |
|
|
UCC_GETH_RX_BD_RING_ALIGNMENT);
|
| 2653 |
|
|
if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
|
| 2654 |
|
|
ugeth->p_rx_bd_ring[j] =
|
| 2655 |
|
|
(u8 *) qe_muram_addr(ugeth->
|
| 2656 |
|
|
rx_bd_ring_offset[j]);
|
| 2657 |
|
|
}
|
| 2658 |
|
|
if (!ugeth->p_rx_bd_ring[j]) {
|
| 2659 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2660 |
|
|
ugeth_err
|
| 2661 |
|
|
("%s: Can not allocate memory for Rx bd rings.",
|
| 2662 |
|
|
__FUNCTION__);
|
| 2663 |
|
|
ucc_geth_memclean(ugeth);
|
| 2664 |
|
|
return -ENOMEM;
|
| 2665 |
|
|
}
|
| 2666 |
|
|
}
|
| 2667 |
|
|
|
| 2668 |
|
|
/* Init Tx bds */
|
| 2669 |
|
|
for (j = 0; j < ug_info->numQueuesTx; j++) {
|
| 2670 |
|
|
/* Setup the skbuff rings */
|
| 2671 |
|
|
ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
|
| 2672 |
|
|
ugeth->ug_info->bdRingLenTx[j],
|
| 2673 |
|
|
GFP_KERNEL);
|
| 2674 |
|
|
|
| 2675 |
|
|
if (ugeth->tx_skbuff[j] == NULL) {
|
| 2676 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2677 |
|
|
ugeth_err("%s: Could not allocate tx_skbuff",
|
| 2678 |
|
|
__FUNCTION__);
|
| 2679 |
|
|
ucc_geth_memclean(ugeth);
|
| 2680 |
|
|
return -ENOMEM;
|
| 2681 |
|
|
}
|
| 2682 |
|
|
|
| 2683 |
|
|
for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
|
| 2684 |
|
|
ugeth->tx_skbuff[j][i] = NULL;
|
| 2685 |
|
|
|
| 2686 |
|
|
ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
|
| 2687 |
|
|
bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
|
| 2688 |
|
|
for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
|
| 2689 |
|
|
/* clear bd buffer */
|
| 2690 |
|
|
out_be32(&((struct qe_bd *)bd)->buf, 0);
|
| 2691 |
|
|
/* set bd status and length */
|
| 2692 |
|
|
out_be32((u32 *)bd, 0);
|
| 2693 |
|
|
bd += sizeof(struct qe_bd);
|
| 2694 |
|
|
}
|
| 2695 |
|
|
bd -= sizeof(struct qe_bd);
|
| 2696 |
|
|
/* set bd status and length */
|
| 2697 |
|
|
out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */
|
| 2698 |
|
|
}
|
| 2699 |
|
|
|
| 2700 |
|
|
/* Init Rx bds */
|
| 2701 |
|
|
for (j = 0; j < ug_info->numQueuesRx; j++) {
|
| 2702 |
|
|
/* Setup the skbuff rings */
|
| 2703 |
|
|
ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
|
| 2704 |
|
|
ugeth->ug_info->bdRingLenRx[j],
|
| 2705 |
|
|
GFP_KERNEL);
|
| 2706 |
|
|
|
| 2707 |
|
|
if (ugeth->rx_skbuff[j] == NULL) {
|
| 2708 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2709 |
|
|
ugeth_err("%s: Could not allocate rx_skbuff",
|
| 2710 |
|
|
__FUNCTION__);
|
| 2711 |
|
|
ucc_geth_memclean(ugeth);
|
| 2712 |
|
|
return -ENOMEM;
|
| 2713 |
|
|
}
|
| 2714 |
|
|
|
| 2715 |
|
|
for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
|
| 2716 |
|
|
ugeth->rx_skbuff[j][i] = NULL;
|
| 2717 |
|
|
|
| 2718 |
|
|
ugeth->skb_currx[j] = 0;
|
| 2719 |
|
|
bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
|
| 2720 |
|
|
for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
|
| 2721 |
|
|
/* set bd status and length */
|
| 2722 |
|
|
out_be32((u32 *)bd, R_I);
|
| 2723 |
|
|
/* clear bd buffer */
|
| 2724 |
|
|
out_be32(&((struct qe_bd *)bd)->buf, 0);
|
| 2725 |
|
|
bd += sizeof(struct qe_bd);
|
| 2726 |
|
|
}
|
| 2727 |
|
|
bd -= sizeof(struct qe_bd);
|
| 2728 |
|
|
/* set bd status and length */
|
| 2729 |
|
|
out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
|
| 2730 |
|
|
}
|
| 2731 |
|
|
|
| 2732 |
|
|
/*
|
| 2733 |
|
|
* Global PRAM
|
| 2734 |
|
|
*/
|
| 2735 |
|
|
/* Tx global PRAM */
|
| 2736 |
|
|
/* Allocate global tx parameter RAM page */
|
| 2737 |
|
|
ugeth->tx_glbl_pram_offset =
|
| 2738 |
|
|
qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
|
| 2739 |
|
|
UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
|
| 2740 |
|
|
if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
|
| 2741 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2742 |
|
|
ugeth_err
|
| 2743 |
|
|
("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
|
| 2744 |
|
|
__FUNCTION__);
|
| 2745 |
|
|
ucc_geth_memclean(ugeth);
|
| 2746 |
|
|
return -ENOMEM;
|
| 2747 |
|
|
}
|
| 2748 |
|
|
ugeth->p_tx_glbl_pram =
|
| 2749 |
|
|
(struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
|
| 2750 |
|
|
tx_glbl_pram_offset);
|
| 2751 |
|
|
/* Zero out p_tx_glbl_pram */
|
| 2752 |
|
|
memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
|
| 2753 |
|
|
|
| 2754 |
|
|
/* Fill global PRAM */
|
| 2755 |
|
|
|
| 2756 |
|
|
/* TQPTR */
|
| 2757 |
|
|
/* Size varies with number of Tx threads */
|
| 2758 |
|
|
ugeth->thread_dat_tx_offset =
|
| 2759 |
|
|
qe_muram_alloc(numThreadsTxNumerical *
|
| 2760 |
|
|
sizeof(struct ucc_geth_thread_data_tx) +
|
| 2761 |
|
|
32 * (numThreadsTxNumerical == 1),
|
| 2762 |
|
|
UCC_GETH_THREAD_DATA_ALIGNMENT);
|
| 2763 |
|
|
if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
|
| 2764 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2765 |
|
|
ugeth_err
|
| 2766 |
|
|
("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
|
| 2767 |
|
|
__FUNCTION__);
|
| 2768 |
|
|
ucc_geth_memclean(ugeth);
|
| 2769 |
|
|
return -ENOMEM;
|
| 2770 |
|
|
}
|
| 2771 |
|
|
|
| 2772 |
|
|
ugeth->p_thread_data_tx =
|
| 2773 |
|
|
(struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
|
| 2774 |
|
|
thread_dat_tx_offset);
|
| 2775 |
|
|
out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
|
| 2776 |
|
|
|
| 2777 |
|
|
/* vtagtable */
|
| 2778 |
|
|
for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
|
| 2779 |
|
|
out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
|
| 2780 |
|
|
ug_info->vtagtable[i]);
|
| 2781 |
|
|
|
| 2782 |
|
|
/* iphoffset */
|
| 2783 |
|
|
for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
|
| 2784 |
|
|
ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
|
| 2785 |
|
|
|
| 2786 |
|
|
/* SQPTR */
|
| 2787 |
|
|
/* Size varies with number of Tx queues */
|
| 2788 |
|
|
ugeth->send_q_mem_reg_offset =
|
| 2789 |
|
|
qe_muram_alloc(ug_info->numQueuesTx *
|
| 2790 |
|
|
sizeof(struct ucc_geth_send_queue_qd),
|
| 2791 |
|
|
UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
|
| 2792 |
|
|
if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
|
| 2793 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2794 |
|
|
ugeth_err
|
| 2795 |
|
|
("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
|
| 2796 |
|
|
__FUNCTION__);
|
| 2797 |
|
|
ucc_geth_memclean(ugeth);
|
| 2798 |
|
|
return -ENOMEM;
|
| 2799 |
|
|
}
|
| 2800 |
|
|
|
| 2801 |
|
|
ugeth->p_send_q_mem_reg =
|
| 2802 |
|
|
(struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
|
| 2803 |
|
|
send_q_mem_reg_offset);
|
| 2804 |
|
|
out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
|
| 2805 |
|
|
|
| 2806 |
|
|
/* Setup the table */
|
| 2807 |
|
|
/* Assume BD rings are already established */
|
| 2808 |
|
|
for (i = 0; i < ug_info->numQueuesTx; i++) {
|
| 2809 |
|
|
endOfRing =
|
| 2810 |
|
|
ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
|
| 2811 |
|
|
1) * sizeof(struct qe_bd);
|
| 2812 |
|
|
if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
|
| 2813 |
|
|
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
|
| 2814 |
|
|
(u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
|
| 2815 |
|
|
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
|
| 2816 |
|
|
last_bd_completed_address,
|
| 2817 |
|
|
(u32) virt_to_phys(endOfRing));
|
| 2818 |
|
|
} else if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 2819 |
|
|
MEM_PART_MURAM) {
|
| 2820 |
|
|
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
|
| 2821 |
|
|
(u32) immrbar_virt_to_phys(ugeth->
|
| 2822 |
|
|
p_tx_bd_ring[i]));
|
| 2823 |
|
|
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
|
| 2824 |
|
|
last_bd_completed_address,
|
| 2825 |
|
|
(u32) immrbar_virt_to_phys(endOfRing));
|
| 2826 |
|
|
}
|
| 2827 |
|
|
}
|
| 2828 |
|
|
|
| 2829 |
|
|
/* schedulerbasepointer */
|
| 2830 |
|
|
|
| 2831 |
|
|
if (ug_info->numQueuesTx > 1) {
|
| 2832 |
|
|
/* scheduler exists only if more than 1 tx queue */
|
| 2833 |
|
|
ugeth->scheduler_offset =
|
| 2834 |
|
|
qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
|
| 2835 |
|
|
UCC_GETH_SCHEDULER_ALIGNMENT);
|
| 2836 |
|
|
if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
|
| 2837 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2838 |
|
|
ugeth_err
|
| 2839 |
|
|
("%s: Can not allocate DPRAM memory for p_scheduler.",
|
| 2840 |
|
|
__FUNCTION__);
|
| 2841 |
|
|
ucc_geth_memclean(ugeth);
|
| 2842 |
|
|
return -ENOMEM;
|
| 2843 |
|
|
}
|
| 2844 |
|
|
|
| 2845 |
|
|
ugeth->p_scheduler =
|
| 2846 |
|
|
(struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
|
| 2847 |
|
|
scheduler_offset);
|
| 2848 |
|
|
out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
|
| 2849 |
|
|
ugeth->scheduler_offset);
|
| 2850 |
|
|
/* Zero out p_scheduler */
|
| 2851 |
|
|
memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
|
| 2852 |
|
|
|
| 2853 |
|
|
/* Set values in scheduler */
|
| 2854 |
|
|
out_be32(&ugeth->p_scheduler->mblinterval,
|
| 2855 |
|
|
ug_info->mblinterval);
|
| 2856 |
|
|
out_be16(&ugeth->p_scheduler->nortsrbytetime,
|
| 2857 |
|
|
ug_info->nortsrbytetime);
|
| 2858 |
|
|
ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
|
| 2859 |
|
|
ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
|
| 2860 |
|
|
ugeth->p_scheduler->txasap = ug_info->txasap;
|
| 2861 |
|
|
ugeth->p_scheduler->extrabw = ug_info->extrabw;
|
| 2862 |
|
|
for (i = 0; i < NUM_TX_QUEUES; i++)
|
| 2863 |
|
|
ugeth->p_scheduler->weightfactor[i] =
|
| 2864 |
|
|
ug_info->weightfactor[i];
|
| 2865 |
|
|
|
| 2866 |
|
|
/* Set pointers to cpucount registers in scheduler */
|
| 2867 |
|
|
ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
|
| 2868 |
|
|
ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
|
| 2869 |
|
|
ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
|
| 2870 |
|
|
ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
|
| 2871 |
|
|
ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
|
| 2872 |
|
|
ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
|
| 2873 |
|
|
ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
|
| 2874 |
|
|
ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
|
| 2875 |
|
|
}
|
| 2876 |
|
|
|
| 2877 |
|
|
/* schedulerbasepointer */
|
| 2878 |
|
|
/* TxRMON_PTR (statistics) */
|
| 2879 |
|
|
if (ug_info->
|
| 2880 |
|
|
statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
|
| 2881 |
|
|
ugeth->tx_fw_statistics_pram_offset =
|
| 2882 |
|
|
qe_muram_alloc(sizeof
|
| 2883 |
|
|
(struct ucc_geth_tx_firmware_statistics_pram),
|
| 2884 |
|
|
UCC_GETH_TX_STATISTICS_ALIGNMENT);
|
| 2885 |
|
|
if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
|
| 2886 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2887 |
|
|
ugeth_err
|
| 2888 |
|
|
("%s: Can not allocate DPRAM memory for"
|
| 2889 |
|
|
" p_tx_fw_statistics_pram.",
|
| 2890 |
|
|
__FUNCTION__);
|
| 2891 |
|
|
ucc_geth_memclean(ugeth);
|
| 2892 |
|
|
return -ENOMEM;
|
| 2893 |
|
|
}
|
| 2894 |
|
|
ugeth->p_tx_fw_statistics_pram =
|
| 2895 |
|
|
(struct ucc_geth_tx_firmware_statistics_pram *)
|
| 2896 |
|
|
qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
|
| 2897 |
|
|
/* Zero out p_tx_fw_statistics_pram */
|
| 2898 |
|
|
memset(ugeth->p_tx_fw_statistics_pram,
|
| 2899 |
|
|
0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
|
| 2900 |
|
|
}
|
| 2901 |
|
|
|
| 2902 |
|
|
/* temoder */
|
| 2903 |
|
|
/* Already has speed set */
|
| 2904 |
|
|
|
| 2905 |
|
|
if (ug_info->numQueuesTx > 1)
|
| 2906 |
|
|
temoder |= TEMODER_SCHEDULER_ENABLE;
|
| 2907 |
|
|
if (ug_info->ipCheckSumGenerate)
|
| 2908 |
|
|
temoder |= TEMODER_IP_CHECKSUM_GENERATE;
|
| 2909 |
|
|
temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
|
| 2910 |
|
|
out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
|
| 2911 |
|
|
|
| 2912 |
|
|
test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
|
| 2913 |
|
|
|
| 2914 |
|
|
/* Function code register value to be used later */
|
| 2915 |
|
|
function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
|
| 2916 |
|
|
/* Required for QE */
|
| 2917 |
|
|
|
| 2918 |
|
|
/* function code register */
|
| 2919 |
|
|
out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
|
| 2920 |
|
|
|
| 2921 |
|
|
/* Rx global PRAM */
|
| 2922 |
|
|
/* Allocate global rx parameter RAM page */
|
| 2923 |
|
|
ugeth->rx_glbl_pram_offset =
|
| 2924 |
|
|
qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
|
| 2925 |
|
|
UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
|
| 2926 |
|
|
if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
|
| 2927 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2928 |
|
|
ugeth_err
|
| 2929 |
|
|
("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
|
| 2930 |
|
|
__FUNCTION__);
|
| 2931 |
|
|
ucc_geth_memclean(ugeth);
|
| 2932 |
|
|
return -ENOMEM;
|
| 2933 |
|
|
}
|
| 2934 |
|
|
ugeth->p_rx_glbl_pram =
|
| 2935 |
|
|
(struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
|
| 2936 |
|
|
rx_glbl_pram_offset);
|
| 2937 |
|
|
/* Zero out p_rx_glbl_pram */
|
| 2938 |
|
|
memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
|
| 2939 |
|
|
|
| 2940 |
|
|
/* Fill global PRAM */
|
| 2941 |
|
|
|
| 2942 |
|
|
/* RQPTR */
|
| 2943 |
|
|
/* Size varies with number of Rx threads */
|
| 2944 |
|
|
ugeth->thread_dat_rx_offset =
|
| 2945 |
|
|
qe_muram_alloc(numThreadsRxNumerical *
|
| 2946 |
|
|
sizeof(struct ucc_geth_thread_data_rx),
|
| 2947 |
|
|
UCC_GETH_THREAD_DATA_ALIGNMENT);
|
| 2948 |
|
|
if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
|
| 2949 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2950 |
|
|
ugeth_err
|
| 2951 |
|
|
("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
|
| 2952 |
|
|
__FUNCTION__);
|
| 2953 |
|
|
ucc_geth_memclean(ugeth);
|
| 2954 |
|
|
return -ENOMEM;
|
| 2955 |
|
|
}
|
| 2956 |
|
|
|
| 2957 |
|
|
ugeth->p_thread_data_rx =
|
| 2958 |
|
|
(struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
|
| 2959 |
|
|
thread_dat_rx_offset);
|
| 2960 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
|
| 2961 |
|
|
|
| 2962 |
|
|
/* typeorlen */
|
| 2963 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
|
| 2964 |
|
|
|
| 2965 |
|
|
/* rxrmonbaseptr (statistics) */
|
| 2966 |
|
|
if (ug_info->
|
| 2967 |
|
|
statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
|
| 2968 |
|
|
ugeth->rx_fw_statistics_pram_offset =
|
| 2969 |
|
|
qe_muram_alloc(sizeof
|
| 2970 |
|
|
(struct ucc_geth_rx_firmware_statistics_pram),
|
| 2971 |
|
|
UCC_GETH_RX_STATISTICS_ALIGNMENT);
|
| 2972 |
|
|
if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
|
| 2973 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2974 |
|
|
ugeth_err
|
| 2975 |
|
|
("%s: Can not allocate DPRAM memory for"
|
| 2976 |
|
|
" p_rx_fw_statistics_pram.", __FUNCTION__);
|
| 2977 |
|
|
ucc_geth_memclean(ugeth);
|
| 2978 |
|
|
return -ENOMEM;
|
| 2979 |
|
|
}
|
| 2980 |
|
|
ugeth->p_rx_fw_statistics_pram =
|
| 2981 |
|
|
(struct ucc_geth_rx_firmware_statistics_pram *)
|
| 2982 |
|
|
qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
|
| 2983 |
|
|
/* Zero out p_rx_fw_statistics_pram */
|
| 2984 |
|
|
memset(ugeth->p_rx_fw_statistics_pram, 0,
|
| 2985 |
|
|
sizeof(struct ucc_geth_rx_firmware_statistics_pram));
|
| 2986 |
|
|
}
|
| 2987 |
|
|
|
| 2988 |
|
|
/* intCoalescingPtr */
|
| 2989 |
|
|
|
| 2990 |
|
|
/* Size varies with number of Rx queues */
|
| 2991 |
|
|
ugeth->rx_irq_coalescing_tbl_offset =
|
| 2992 |
|
|
qe_muram_alloc(ug_info->numQueuesRx *
|
| 2993 |
|
|
sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
|
| 2994 |
|
|
+ 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
|
| 2995 |
|
|
if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
|
| 2996 |
|
|
if (netif_msg_ifup(ugeth))
|
| 2997 |
|
|
ugeth_err
|
| 2998 |
|
|
("%s: Can not allocate DPRAM memory for"
|
| 2999 |
|
|
" p_rx_irq_coalescing_tbl.", __FUNCTION__);
|
| 3000 |
|
|
ucc_geth_memclean(ugeth);
|
| 3001 |
|
|
return -ENOMEM;
|
| 3002 |
|
|
}
|
| 3003 |
|
|
|
| 3004 |
|
|
ugeth->p_rx_irq_coalescing_tbl =
|
| 3005 |
|
|
(struct ucc_geth_rx_interrupt_coalescing_table *)
|
| 3006 |
|
|
qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
|
| 3007 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
|
| 3008 |
|
|
ugeth->rx_irq_coalescing_tbl_offset);
|
| 3009 |
|
|
|
| 3010 |
|
|
/* Fill interrupt coalescing table */
|
| 3011 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++) {
|
| 3012 |
|
|
out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
|
| 3013 |
|
|
interruptcoalescingmaxvalue,
|
| 3014 |
|
|
ug_info->interruptcoalescingmaxvalue[i]);
|
| 3015 |
|
|
out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
|
| 3016 |
|
|
interruptcoalescingcounter,
|
| 3017 |
|
|
ug_info->interruptcoalescingmaxvalue[i]);
|
| 3018 |
|
|
}
|
| 3019 |
|
|
|
| 3020 |
|
|
/* MRBLR */
|
| 3021 |
|
|
init_max_rx_buff_len(uf_info->max_rx_buf_length,
|
| 3022 |
|
|
&ugeth->p_rx_glbl_pram->mrblr);
|
| 3023 |
|
|
/* MFLR */
|
| 3024 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
|
| 3025 |
|
|
/* MINFLR */
|
| 3026 |
|
|
init_min_frame_len(ug_info->minFrameLength,
|
| 3027 |
|
|
&ugeth->p_rx_glbl_pram->minflr,
|
| 3028 |
|
|
&ugeth->p_rx_glbl_pram->mrblr);
|
| 3029 |
|
|
/* MAXD1 */
|
| 3030 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
|
| 3031 |
|
|
/* MAXD2 */
|
| 3032 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
|
| 3033 |
|
|
|
| 3034 |
|
|
/* l2qt */
|
| 3035 |
|
|
l2qt = 0;
|
| 3036 |
|
|
for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
|
| 3037 |
|
|
l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
|
| 3038 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
|
| 3039 |
|
|
|
| 3040 |
|
|
/* l3qt */
|
| 3041 |
|
|
for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
|
| 3042 |
|
|
l3qt = 0;
|
| 3043 |
|
|
for (i = 0; i < 8; i++)
|
| 3044 |
|
|
l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
|
| 3045 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
|
| 3046 |
|
|
}
|
| 3047 |
|
|
|
| 3048 |
|
|
/* vlantype */
|
| 3049 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
|
| 3050 |
|
|
|
| 3051 |
|
|
/* vlantci */
|
| 3052 |
|
|
out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
|
| 3053 |
|
|
|
| 3054 |
|
|
/* ecamptr */
|
| 3055 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
|
| 3056 |
|
|
|
| 3057 |
|
|
/* RBDQPTR */
|
| 3058 |
|
|
/* Size varies with number of Rx queues */
|
| 3059 |
|
|
ugeth->rx_bd_qs_tbl_offset =
|
| 3060 |
|
|
qe_muram_alloc(ug_info->numQueuesRx *
|
| 3061 |
|
|
(sizeof(struct ucc_geth_rx_bd_queues_entry) +
|
| 3062 |
|
|
sizeof(struct ucc_geth_rx_prefetched_bds)),
|
| 3063 |
|
|
UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
|
| 3064 |
|
|
if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
|
| 3065 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3066 |
|
|
ugeth_err
|
| 3067 |
|
|
("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
|
| 3068 |
|
|
__FUNCTION__);
|
| 3069 |
|
|
ucc_geth_memclean(ugeth);
|
| 3070 |
|
|
return -ENOMEM;
|
| 3071 |
|
|
}
|
| 3072 |
|
|
|
| 3073 |
|
|
ugeth->p_rx_bd_qs_tbl =
|
| 3074 |
|
|
(struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
|
| 3075 |
|
|
rx_bd_qs_tbl_offset);
|
| 3076 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
|
| 3077 |
|
|
/* Zero out p_rx_bd_qs_tbl */
|
| 3078 |
|
|
memset(ugeth->p_rx_bd_qs_tbl,
|
| 3079 |
|
|
0,
|
| 3080 |
|
|
ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
|
| 3081 |
|
|
sizeof(struct ucc_geth_rx_prefetched_bds)));
|
| 3082 |
|
|
|
| 3083 |
|
|
/* Setup the table */
|
| 3084 |
|
|
/* Assume BD rings are already established */
|
| 3085 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++) {
|
| 3086 |
|
|
if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
|
| 3087 |
|
|
out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
|
| 3088 |
|
|
(u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
|
| 3089 |
|
|
} else if (ugeth->ug_info->uf_info.bd_mem_part ==
|
| 3090 |
|
|
MEM_PART_MURAM) {
|
| 3091 |
|
|
out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
|
| 3092 |
|
|
(u32) immrbar_virt_to_phys(ugeth->
|
| 3093 |
|
|
p_rx_bd_ring[i]));
|
| 3094 |
|
|
}
|
| 3095 |
|
|
/* rest of fields handled by QE */
|
| 3096 |
|
|
}
|
| 3097 |
|
|
|
| 3098 |
|
|
/* remoder */
|
| 3099 |
|
|
/* Already has speed set */
|
| 3100 |
|
|
|
| 3101 |
|
|
if (ugeth->rx_extended_features)
|
| 3102 |
|
|
remoder |= REMODER_RX_EXTENDED_FEATURES;
|
| 3103 |
|
|
if (ug_info->rxExtendedFiltering)
|
| 3104 |
|
|
remoder |= REMODER_RX_EXTENDED_FILTERING;
|
| 3105 |
|
|
if (ug_info->dynamicMaxFrameLength)
|
| 3106 |
|
|
remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
|
| 3107 |
|
|
if (ug_info->dynamicMinFrameLength)
|
| 3108 |
|
|
remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
|
| 3109 |
|
|
remoder |=
|
| 3110 |
|
|
ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
|
| 3111 |
|
|
remoder |=
|
| 3112 |
|
|
ug_info->
|
| 3113 |
|
|
vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
|
| 3114 |
|
|
remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
|
| 3115 |
|
|
remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
|
| 3116 |
|
|
if (ug_info->ipCheckSumCheck)
|
| 3117 |
|
|
remoder |= REMODER_IP_CHECKSUM_CHECK;
|
| 3118 |
|
|
if (ug_info->ipAddressAlignment)
|
| 3119 |
|
|
remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
|
| 3120 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
|
| 3121 |
|
|
|
| 3122 |
|
|
/* Note that this function must be called */
|
| 3123 |
|
|
/* ONLY AFTER p_tx_fw_statistics_pram */
|
| 3124 |
|
|
/* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
|
| 3125 |
|
|
init_firmware_statistics_gathering_mode((ug_info->
|
| 3126 |
|
|
statisticsMode &
|
| 3127 |
|
|
UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
|
| 3128 |
|
|
(ug_info->statisticsMode &
|
| 3129 |
|
|
UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
|
| 3130 |
|
|
&ugeth->p_tx_glbl_pram->txrmonbaseptr,
|
| 3131 |
|
|
ugeth->tx_fw_statistics_pram_offset,
|
| 3132 |
|
|
&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
|
| 3133 |
|
|
ugeth->rx_fw_statistics_pram_offset,
|
| 3134 |
|
|
&ugeth->p_tx_glbl_pram->temoder,
|
| 3135 |
|
|
&ugeth->p_rx_glbl_pram->remoder);
|
| 3136 |
|
|
|
| 3137 |
|
|
/* function code register */
|
| 3138 |
|
|
ugeth->p_rx_glbl_pram->rstate = function_code;
|
| 3139 |
|
|
|
| 3140 |
|
|
/* initialize extended filtering */
|
| 3141 |
|
|
if (ug_info->rxExtendedFiltering) {
|
| 3142 |
|
|
if (!ug_info->extendedFilteringChainPointer) {
|
| 3143 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3144 |
|
|
ugeth_err("%s: Null Extended Filtering Chain Pointer.",
|
| 3145 |
|
|
__FUNCTION__);
|
| 3146 |
|
|
ucc_geth_memclean(ugeth);
|
| 3147 |
|
|
return -EINVAL;
|
| 3148 |
|
|
}
|
| 3149 |
|
|
|
| 3150 |
|
|
/* Allocate memory for extended filtering Mode Global
|
| 3151 |
|
|
Parameters */
|
| 3152 |
|
|
ugeth->exf_glbl_param_offset =
|
| 3153 |
|
|
qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
|
| 3154 |
|
|
UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
|
| 3155 |
|
|
if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
|
| 3156 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3157 |
|
|
ugeth_err
|
| 3158 |
|
|
("%s: Can not allocate DPRAM memory for"
|
| 3159 |
|
|
" p_exf_glbl_param.", __FUNCTION__);
|
| 3160 |
|
|
ucc_geth_memclean(ugeth);
|
| 3161 |
|
|
return -ENOMEM;
|
| 3162 |
|
|
}
|
| 3163 |
|
|
|
| 3164 |
|
|
ugeth->p_exf_glbl_param =
|
| 3165 |
|
|
(struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
|
| 3166 |
|
|
exf_glbl_param_offset);
|
| 3167 |
|
|
out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
|
| 3168 |
|
|
ugeth->exf_glbl_param_offset);
|
| 3169 |
|
|
out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
|
| 3170 |
|
|
(u32) ug_info->extendedFilteringChainPointer);
|
| 3171 |
|
|
|
| 3172 |
|
|
} else { /* initialize 82xx style address filtering */
|
| 3173 |
|
|
|
| 3174 |
|
|
/* Init individual address recognition registers to disabled */
|
| 3175 |
|
|
|
| 3176 |
|
|
for (j = 0; j < NUM_OF_PADDRS; j++)
|
| 3177 |
|
|
ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
|
| 3178 |
|
|
|
| 3179 |
|
|
p_82xx_addr_filt =
|
| 3180 |
|
|
(struct ucc_geth_82xx_address_filtering_pram *) ugeth->
|
| 3181 |
|
|
p_rx_glbl_pram->addressfiltering;
|
| 3182 |
|
|
|
| 3183 |
|
|
ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
|
| 3184 |
|
|
ENET_ADDR_TYPE_GROUP);
|
| 3185 |
|
|
ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
|
| 3186 |
|
|
ENET_ADDR_TYPE_INDIVIDUAL);
|
| 3187 |
|
|
}
|
| 3188 |
|
|
|
| 3189 |
|
|
/*
|
| 3190 |
|
|
* Initialize UCC at QE level
|
| 3191 |
|
|
*/
|
| 3192 |
|
|
|
| 3193 |
|
|
command = QE_INIT_TX_RX;
|
| 3194 |
|
|
|
| 3195 |
|
|
/* Allocate shadow InitEnet command parameter structure.
|
| 3196 |
|
|
* This is needed because after the InitEnet command is executed,
|
| 3197 |
|
|
* the structure in DPRAM is released, because DPRAM is a premium
|
| 3198 |
|
|
* resource.
|
| 3199 |
|
|
* This shadow structure keeps a copy of what was done so that the
|
| 3200 |
|
|
* allocated resources can be released when the channel is freed.
|
| 3201 |
|
|
*/
|
| 3202 |
|
|
if (!(ugeth->p_init_enet_param_shadow =
|
| 3203 |
|
|
kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
|
| 3204 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3205 |
|
|
ugeth_err
|
| 3206 |
|
|
("%s: Can not allocate memory for"
|
| 3207 |
|
|
" p_UccInitEnetParamShadows.", __FUNCTION__);
|
| 3208 |
|
|
ucc_geth_memclean(ugeth);
|
| 3209 |
|
|
return -ENOMEM;
|
| 3210 |
|
|
}
|
| 3211 |
|
|
/* Zero out *p_init_enet_param_shadow */
|
| 3212 |
|
|
memset((char *)ugeth->p_init_enet_param_shadow,
|
| 3213 |
|
|
0, sizeof(struct ucc_geth_init_pram));
|
| 3214 |
|
|
|
| 3215 |
|
|
/* Fill shadow InitEnet command parameter structure */
|
| 3216 |
|
|
|
| 3217 |
|
|
ugeth->p_init_enet_param_shadow->resinit1 =
|
| 3218 |
|
|
ENET_INIT_PARAM_MAGIC_RES_INIT1;
|
| 3219 |
|
|
ugeth->p_init_enet_param_shadow->resinit2 =
|
| 3220 |
|
|
ENET_INIT_PARAM_MAGIC_RES_INIT2;
|
| 3221 |
|
|
ugeth->p_init_enet_param_shadow->resinit3 =
|
| 3222 |
|
|
ENET_INIT_PARAM_MAGIC_RES_INIT3;
|
| 3223 |
|
|
ugeth->p_init_enet_param_shadow->resinit4 =
|
| 3224 |
|
|
ENET_INIT_PARAM_MAGIC_RES_INIT4;
|
| 3225 |
|
|
ugeth->p_init_enet_param_shadow->resinit5 =
|
| 3226 |
|
|
ENET_INIT_PARAM_MAGIC_RES_INIT5;
|
| 3227 |
|
|
ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
|
| 3228 |
|
|
((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
|
| 3229 |
|
|
ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
|
| 3230 |
|
|
((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
|
| 3231 |
|
|
|
| 3232 |
|
|
ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
|
| 3233 |
|
|
ugeth->rx_glbl_pram_offset | ug_info->riscRx;
|
| 3234 |
|
|
if ((ug_info->largestexternallookupkeysize !=
|
| 3235 |
|
|
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
|
| 3236 |
|
|
&& (ug_info->largestexternallookupkeysize !=
|
| 3237 |
|
|
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
|
| 3238 |
|
|
&& (ug_info->largestexternallookupkeysize !=
|
| 3239 |
|
|
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
|
| 3240 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3241 |
|
|
ugeth_err("%s: Invalid largest External Lookup Key Size.",
|
| 3242 |
|
|
__FUNCTION__);
|
| 3243 |
|
|
ucc_geth_memclean(ugeth);
|
| 3244 |
|
|
return -EINVAL;
|
| 3245 |
|
|
}
|
| 3246 |
|
|
ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
|
| 3247 |
|
|
ug_info->largestexternallookupkeysize;
|
| 3248 |
|
|
size = sizeof(struct ucc_geth_thread_rx_pram);
|
| 3249 |
|
|
if (ug_info->rxExtendedFiltering) {
|
| 3250 |
|
|
size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
|
| 3251 |
|
|
if (ug_info->largestexternallookupkeysize ==
|
| 3252 |
|
|
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
|
| 3253 |
|
|
size +=
|
| 3254 |
|
|
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
|
| 3255 |
|
|
if (ug_info->largestexternallookupkeysize ==
|
| 3256 |
|
|
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
|
| 3257 |
|
|
size +=
|
| 3258 |
|
|
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
|
| 3259 |
|
|
}
|
| 3260 |
|
|
|
| 3261 |
|
|
if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
|
| 3262 |
|
|
p_init_enet_param_shadow->rxthread[0]),
|
| 3263 |
|
|
(u8) (numThreadsRxNumerical + 1)
|
| 3264 |
|
|
/* Rx needs one extra for terminator */
|
| 3265 |
|
|
, size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
|
| 3266 |
|
|
ug_info->riscRx, 1)) != 0) {
|
| 3267 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3268 |
|
|
ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
|
| 3269 |
|
|
__FUNCTION__);
|
| 3270 |
|
|
ucc_geth_memclean(ugeth);
|
| 3271 |
|
|
return ret_val;
|
| 3272 |
|
|
}
|
| 3273 |
|
|
|
| 3274 |
|
|
ugeth->p_init_enet_param_shadow->txglobal =
|
| 3275 |
|
|
ugeth->tx_glbl_pram_offset | ug_info->riscTx;
|
| 3276 |
|
|
if ((ret_val =
|
| 3277 |
|
|
fill_init_enet_entries(ugeth,
|
| 3278 |
|
|
&(ugeth->p_init_enet_param_shadow->
|
| 3279 |
|
|
txthread[0]), numThreadsTxNumerical,
|
| 3280 |
|
|
sizeof(struct ucc_geth_thread_tx_pram),
|
| 3281 |
|
|
UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
|
| 3282 |
|
|
ug_info->riscTx, 0)) != 0) {
|
| 3283 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3284 |
|
|
ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
|
| 3285 |
|
|
__FUNCTION__);
|
| 3286 |
|
|
ucc_geth_memclean(ugeth);
|
| 3287 |
|
|
return ret_val;
|
| 3288 |
|
|
}
|
| 3289 |
|
|
|
| 3290 |
|
|
/* Load Rx bds with buffers */
|
| 3291 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++) {
|
| 3292 |
|
|
if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
|
| 3293 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3294 |
|
|
ugeth_err("%s: Can not fill Rx bds with buffers.",
|
| 3295 |
|
|
__FUNCTION__);
|
| 3296 |
|
|
ucc_geth_memclean(ugeth);
|
| 3297 |
|
|
return ret_val;
|
| 3298 |
|
|
}
|
| 3299 |
|
|
}
|
| 3300 |
|
|
|
| 3301 |
|
|
/* Allocate InitEnet command parameter structure */
|
| 3302 |
|
|
init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
|
| 3303 |
|
|
if (IS_ERR_VALUE(init_enet_pram_offset)) {
|
| 3304 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3305 |
|
|
ugeth_err
|
| 3306 |
|
|
("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
|
| 3307 |
|
|
__FUNCTION__);
|
| 3308 |
|
|
ucc_geth_memclean(ugeth);
|
| 3309 |
|
|
return -ENOMEM;
|
| 3310 |
|
|
}
|
| 3311 |
|
|
p_init_enet_pram =
|
| 3312 |
|
|
(struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
|
| 3313 |
|
|
|
| 3314 |
|
|
/* Copy shadow InitEnet command parameter structure into PRAM */
|
| 3315 |
|
|
p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
|
| 3316 |
|
|
p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
|
| 3317 |
|
|
p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
|
| 3318 |
|
|
p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
|
| 3319 |
|
|
out_be16(&p_init_enet_pram->resinit5,
|
| 3320 |
|
|
ugeth->p_init_enet_param_shadow->resinit5);
|
| 3321 |
|
|
p_init_enet_pram->largestexternallookupkeysize =
|
| 3322 |
|
|
ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
|
| 3323 |
|
|
out_be32(&p_init_enet_pram->rgftgfrxglobal,
|
| 3324 |
|
|
ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
|
| 3325 |
|
|
for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
|
| 3326 |
|
|
out_be32(&p_init_enet_pram->rxthread[i],
|
| 3327 |
|
|
ugeth->p_init_enet_param_shadow->rxthread[i]);
|
| 3328 |
|
|
out_be32(&p_init_enet_pram->txglobal,
|
| 3329 |
|
|
ugeth->p_init_enet_param_shadow->txglobal);
|
| 3330 |
|
|
for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
|
| 3331 |
|
|
out_be32(&p_init_enet_pram->txthread[i],
|
| 3332 |
|
|
ugeth->p_init_enet_param_shadow->txthread[i]);
|
| 3333 |
|
|
|
| 3334 |
|
|
/* Issue QE command */
|
| 3335 |
|
|
cecr_subblock =
|
| 3336 |
|
|
ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
|
| 3337 |
|
|
qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
|
| 3338 |
|
|
init_enet_pram_offset);
|
| 3339 |
|
|
|
| 3340 |
|
|
/* Free InitEnet command parameter */
|
| 3341 |
|
|
qe_muram_free(init_enet_pram_offset);
|
| 3342 |
|
|
|
| 3343 |
|
|
return 0;
|
| 3344 |
|
|
}
|
| 3345 |
|
|
|
| 3346 |
|
|
/* ucc_geth_timeout gets called when a packet has not been
|
| 3347 |
|
|
* transmitted after a set amount of time.
|
| 3348 |
|
|
* For now, assume that clearing out all the structures, and
|
| 3349 |
|
|
* starting over will fix the problem. */
|
| 3350 |
|
|
static void ucc_geth_timeout(struct net_device *dev)
|
| 3351 |
|
|
{
|
| 3352 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3353 |
|
|
|
| 3354 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3355 |
|
|
|
| 3356 |
|
|
dev->stats.tx_errors++;
|
| 3357 |
|
|
|
| 3358 |
|
|
ugeth_dump_regs(ugeth);
|
| 3359 |
|
|
|
| 3360 |
|
|
if (dev->flags & IFF_UP) {
|
| 3361 |
|
|
ucc_geth_stop(ugeth);
|
| 3362 |
|
|
ucc_geth_startup(ugeth);
|
| 3363 |
|
|
}
|
| 3364 |
|
|
|
| 3365 |
|
|
netif_schedule(dev);
|
| 3366 |
|
|
}
|
| 3367 |
|
|
|
| 3368 |
|
|
/* This is called by the kernel when a frame is ready for transmission. */
|
| 3369 |
|
|
/* It is pointed to by the dev->hard_start_xmit function pointer */
|
| 3370 |
|
|
static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
| 3371 |
|
|
{
|
| 3372 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3373 |
|
|
#ifdef CONFIG_UGETH_TX_ON_DEMAND
|
| 3374 |
|
|
struct ucc_fast_private *uccf;
|
| 3375 |
|
|
#endif
|
| 3376 |
|
|
u8 *bd; /* BD pointer */
|
| 3377 |
|
|
u32 bd_status;
|
| 3378 |
|
|
u8 txQ = 0;
|
| 3379 |
|
|
|
| 3380 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3381 |
|
|
|
| 3382 |
|
|
spin_lock_irq(&ugeth->lock);
|
| 3383 |
|
|
|
| 3384 |
|
|
dev->stats.tx_bytes += skb->len;
|
| 3385 |
|
|
|
| 3386 |
|
|
/* Start from the next BD that should be filled */
|
| 3387 |
|
|
bd = ugeth->txBd[txQ];
|
| 3388 |
|
|
bd_status = in_be32((u32 *)bd);
|
| 3389 |
|
|
/* Save the skb pointer so we can free it later */
|
| 3390 |
|
|
ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
|
| 3391 |
|
|
|
| 3392 |
|
|
/* Update the current skb pointer (wrapping if this was the last) */
|
| 3393 |
|
|
ugeth->skb_curtx[txQ] =
|
| 3394 |
|
|
(ugeth->skb_curtx[txQ] +
|
| 3395 |
|
|
1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
|
| 3396 |
|
|
|
| 3397 |
|
|
/* set up the buffer descriptor */
|
| 3398 |
|
|
out_be32(&((struct qe_bd *)bd)->buf,
|
| 3399 |
|
|
dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
|
| 3400 |
|
|
|
| 3401 |
|
|
/* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
|
| 3402 |
|
|
|
| 3403 |
|
|
bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
|
| 3404 |
|
|
|
| 3405 |
|
|
/* set bd status and length */
|
| 3406 |
|
|
out_be32((u32 *)bd, bd_status);
|
| 3407 |
|
|
|
| 3408 |
|
|
dev->trans_start = jiffies;
|
| 3409 |
|
|
|
| 3410 |
|
|
/* Move to next BD in the ring */
|
| 3411 |
|
|
if (!(bd_status & T_W))
|
| 3412 |
|
|
bd += sizeof(struct qe_bd);
|
| 3413 |
|
|
else
|
| 3414 |
|
|
bd = ugeth->p_tx_bd_ring[txQ];
|
| 3415 |
|
|
|
| 3416 |
|
|
/* If the next BD still needs to be cleaned up, then the bds
|
| 3417 |
|
|
are full. We need to tell the kernel to stop sending us stuff. */
|
| 3418 |
|
|
if (bd == ugeth->confBd[txQ]) {
|
| 3419 |
|
|
if (!netif_queue_stopped(dev))
|
| 3420 |
|
|
netif_stop_queue(dev);
|
| 3421 |
|
|
}
|
| 3422 |
|
|
|
| 3423 |
|
|
ugeth->txBd[txQ] = bd;
|
| 3424 |
|
|
|
| 3425 |
|
|
if (ugeth->p_scheduler) {
|
| 3426 |
|
|
ugeth->cpucount[txQ]++;
|
| 3427 |
|
|
/* Indicate to QE that there are more Tx bds ready for
|
| 3428 |
|
|
transmission */
|
| 3429 |
|
|
/* This is done by writing a running counter of the bd
|
| 3430 |
|
|
count to the scheduler PRAM. */
|
| 3431 |
|
|
out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
|
| 3432 |
|
|
}
|
| 3433 |
|
|
|
| 3434 |
|
|
#ifdef CONFIG_UGETH_TX_ON_DEMAND
|
| 3435 |
|
|
uccf = ugeth->uccf;
|
| 3436 |
|
|
out_be16(uccf->p_utodr, UCC_FAST_TOD);
|
| 3437 |
|
|
#endif
|
| 3438 |
|
|
spin_unlock_irq(&ugeth->lock);
|
| 3439 |
|
|
|
| 3440 |
|
|
return 0;
|
| 3441 |
|
|
}
|
| 3442 |
|
|
|
| 3443 |
|
|
static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
|
| 3444 |
|
|
{
|
| 3445 |
|
|
struct sk_buff *skb;
|
| 3446 |
|
|
u8 *bd;
|
| 3447 |
|
|
u16 length, howmany = 0;
|
| 3448 |
|
|
u32 bd_status;
|
| 3449 |
|
|
u8 *bdBuffer;
|
| 3450 |
|
|
struct net_device *dev;
|
| 3451 |
|
|
|
| 3452 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3453 |
|
|
|
| 3454 |
|
|
dev = ugeth->dev;
|
| 3455 |
|
|
|
| 3456 |
|
|
/* collect received buffers */
|
| 3457 |
|
|
bd = ugeth->rxBd[rxQ];
|
| 3458 |
|
|
|
| 3459 |
|
|
bd_status = in_be32((u32 *)bd);
|
| 3460 |
|
|
|
| 3461 |
|
|
/* while there are received buffers and BD is full (~R_E) */
|
| 3462 |
|
|
while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
|
| 3463 |
|
|
bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
|
| 3464 |
|
|
length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
|
| 3465 |
|
|
skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
|
| 3466 |
|
|
|
| 3467 |
|
|
/* determine whether buffer is first, last, first and last
|
| 3468 |
|
|
(single buffer frame) or middle (not first and not last) */
|
| 3469 |
|
|
if (!skb ||
|
| 3470 |
|
|
(!(bd_status & (R_F | R_L))) ||
|
| 3471 |
|
|
(bd_status & R_ERRORS_FATAL)) {
|
| 3472 |
|
|
if (netif_msg_rx_err(ugeth))
|
| 3473 |
|
|
ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
|
| 3474 |
|
|
__FUNCTION__, __LINE__, (u32) skb);
|
| 3475 |
|
|
if (skb)
|
| 3476 |
|
|
dev_kfree_skb_any(skb);
|
| 3477 |
|
|
|
| 3478 |
|
|
ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
|
| 3479 |
|
|
dev->stats.rx_dropped++;
|
| 3480 |
|
|
} else {
|
| 3481 |
|
|
dev->stats.rx_packets++;
|
| 3482 |
|
|
howmany++;
|
| 3483 |
|
|
|
| 3484 |
|
|
/* Prep the skb for the packet */
|
| 3485 |
|
|
skb_put(skb, length);
|
| 3486 |
|
|
|
| 3487 |
|
|
/* Tell the skb what kind of packet this is */
|
| 3488 |
|
|
skb->protocol = eth_type_trans(skb, ugeth->dev);
|
| 3489 |
|
|
|
| 3490 |
|
|
dev->stats.rx_bytes += length;
|
| 3491 |
|
|
/* Send the packet up the stack */
|
| 3492 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3493 |
|
|
netif_receive_skb(skb);
|
| 3494 |
|
|
#else
|
| 3495 |
|
|
netif_rx(skb);
|
| 3496 |
|
|
#endif /* CONFIG_UGETH_NAPI */
|
| 3497 |
|
|
}
|
| 3498 |
|
|
|
| 3499 |
|
|
ugeth->dev->last_rx = jiffies;
|
| 3500 |
|
|
|
| 3501 |
|
|
skb = get_new_skb(ugeth, bd);
|
| 3502 |
|
|
if (!skb) {
|
| 3503 |
|
|
if (netif_msg_rx_err(ugeth))
|
| 3504 |
|
|
ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
|
| 3505 |
|
|
dev->stats.rx_dropped++;
|
| 3506 |
|
|
break;
|
| 3507 |
|
|
}
|
| 3508 |
|
|
|
| 3509 |
|
|
ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
|
| 3510 |
|
|
|
| 3511 |
|
|
/* update to point at the next skb */
|
| 3512 |
|
|
ugeth->skb_currx[rxQ] =
|
| 3513 |
|
|
(ugeth->skb_currx[rxQ] +
|
| 3514 |
|
|
1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
|
| 3515 |
|
|
|
| 3516 |
|
|
if (bd_status & R_W)
|
| 3517 |
|
|
bd = ugeth->p_rx_bd_ring[rxQ];
|
| 3518 |
|
|
else
|
| 3519 |
|
|
bd += sizeof(struct qe_bd);
|
| 3520 |
|
|
|
| 3521 |
|
|
bd_status = in_be32((u32 *)bd);
|
| 3522 |
|
|
}
|
| 3523 |
|
|
|
| 3524 |
|
|
ugeth->rxBd[rxQ] = bd;
|
| 3525 |
|
|
return howmany;
|
| 3526 |
|
|
}
|
| 3527 |
|
|
|
| 3528 |
|
|
static int ucc_geth_tx(struct net_device *dev, u8 txQ)
|
| 3529 |
|
|
{
|
| 3530 |
|
|
/* Start from the next BD that should be filled */
|
| 3531 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3532 |
|
|
u8 *bd; /* BD pointer */
|
| 3533 |
|
|
u32 bd_status;
|
| 3534 |
|
|
|
| 3535 |
|
|
bd = ugeth->confBd[txQ];
|
| 3536 |
|
|
bd_status = in_be32((u32 *)bd);
|
| 3537 |
|
|
|
| 3538 |
|
|
/* Normal processing. */
|
| 3539 |
|
|
while ((bd_status & T_R) == 0) {
|
| 3540 |
|
|
/* BD contains already transmitted buffer. */
|
| 3541 |
|
|
/* Handle the transmitted buffer and release */
|
| 3542 |
|
|
/* the BD to be used with the current frame */
|
| 3543 |
|
|
|
| 3544 |
|
|
if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
|
| 3545 |
|
|
break;
|
| 3546 |
|
|
|
| 3547 |
|
|
dev->stats.tx_packets++;
|
| 3548 |
|
|
|
| 3549 |
|
|
/* Free the sk buffer associated with this TxBD */
|
| 3550 |
|
|
dev_kfree_skb_irq(ugeth->
|
| 3551 |
|
|
tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
|
| 3552 |
|
|
ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
|
| 3553 |
|
|
ugeth->skb_dirtytx[txQ] =
|
| 3554 |
|
|
(ugeth->skb_dirtytx[txQ] +
|
| 3555 |
|
|
1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
|
| 3556 |
|
|
|
| 3557 |
|
|
/* We freed a buffer, so now we can restart transmission */
|
| 3558 |
|
|
if (netif_queue_stopped(dev))
|
| 3559 |
|
|
netif_wake_queue(dev);
|
| 3560 |
|
|
|
| 3561 |
|
|
/* Advance the confirmation BD pointer */
|
| 3562 |
|
|
if (!(bd_status & T_W))
|
| 3563 |
|
|
bd += sizeof(struct qe_bd);
|
| 3564 |
|
|
else
|
| 3565 |
|
|
bd = ugeth->p_tx_bd_ring[txQ];
|
| 3566 |
|
|
bd_status = in_be32((u32 *)bd);
|
| 3567 |
|
|
}
|
| 3568 |
|
|
ugeth->confBd[txQ] = bd;
|
| 3569 |
|
|
return 0;
|
| 3570 |
|
|
}
|
| 3571 |
|
|
|
| 3572 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3573 |
|
|
static int ucc_geth_poll(struct napi_struct *napi, int budget)
|
| 3574 |
|
|
{
|
| 3575 |
|
|
struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
|
| 3576 |
|
|
struct net_device *dev = ugeth->dev;
|
| 3577 |
|
|
struct ucc_geth_info *ug_info;
|
| 3578 |
|
|
int howmany, i;
|
| 3579 |
|
|
|
| 3580 |
|
|
ug_info = ugeth->ug_info;
|
| 3581 |
|
|
|
| 3582 |
|
|
howmany = 0;
|
| 3583 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++)
|
| 3584 |
|
|
howmany += ucc_geth_rx(ugeth, i, budget - howmany);
|
| 3585 |
|
|
|
| 3586 |
|
|
if (howmany < budget) {
|
| 3587 |
|
|
struct ucc_fast_private *uccf;
|
| 3588 |
|
|
u32 uccm;
|
| 3589 |
|
|
|
| 3590 |
|
|
netif_rx_complete(dev, napi);
|
| 3591 |
|
|
uccf = ugeth->uccf;
|
| 3592 |
|
|
uccm = in_be32(uccf->p_uccm);
|
| 3593 |
|
|
uccm |= UCCE_RX_EVENTS;
|
| 3594 |
|
|
out_be32(uccf->p_uccm, uccm);
|
| 3595 |
|
|
}
|
| 3596 |
|
|
|
| 3597 |
|
|
return howmany;
|
| 3598 |
|
|
}
|
| 3599 |
|
|
#endif /* CONFIG_UGETH_NAPI */
|
| 3600 |
|
|
|
| 3601 |
|
|
static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
|
| 3602 |
|
|
{
|
| 3603 |
|
|
struct net_device *dev = info;
|
| 3604 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3605 |
|
|
struct ucc_fast_private *uccf;
|
| 3606 |
|
|
struct ucc_geth_info *ug_info;
|
| 3607 |
|
|
register u32 ucce;
|
| 3608 |
|
|
register u32 uccm;
|
| 3609 |
|
|
#ifndef CONFIG_UGETH_NAPI
|
| 3610 |
|
|
register u32 rx_mask;
|
| 3611 |
|
|
#endif
|
| 3612 |
|
|
register u32 tx_mask;
|
| 3613 |
|
|
u8 i;
|
| 3614 |
|
|
|
| 3615 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3616 |
|
|
|
| 3617 |
|
|
if (!ugeth)
|
| 3618 |
|
|
return IRQ_NONE;
|
| 3619 |
|
|
|
| 3620 |
|
|
uccf = ugeth->uccf;
|
| 3621 |
|
|
ug_info = ugeth->ug_info;
|
| 3622 |
|
|
|
| 3623 |
|
|
/* read and clear events */
|
| 3624 |
|
|
ucce = (u32) in_be32(uccf->p_ucce);
|
| 3625 |
|
|
uccm = (u32) in_be32(uccf->p_uccm);
|
| 3626 |
|
|
ucce &= uccm;
|
| 3627 |
|
|
out_be32(uccf->p_ucce, ucce);
|
| 3628 |
|
|
|
| 3629 |
|
|
/* check for receive events that require processing */
|
| 3630 |
|
|
if (ucce & UCCE_RX_EVENTS) {
|
| 3631 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3632 |
|
|
if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
|
| 3633 |
|
|
uccm &= ~UCCE_RX_EVENTS;
|
| 3634 |
|
|
out_be32(uccf->p_uccm, uccm);
|
| 3635 |
|
|
__netif_rx_schedule(dev, &ugeth->napi);
|
| 3636 |
|
|
}
|
| 3637 |
|
|
#else
|
| 3638 |
|
|
rx_mask = UCCE_RXBF_SINGLE_MASK;
|
| 3639 |
|
|
for (i = 0; i < ug_info->numQueuesRx; i++) {
|
| 3640 |
|
|
if (ucce & rx_mask)
|
| 3641 |
|
|
ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
|
| 3642 |
|
|
ucce &= ~rx_mask;
|
| 3643 |
|
|
rx_mask <<= 1;
|
| 3644 |
|
|
}
|
| 3645 |
|
|
#endif /* CONFIG_UGETH_NAPI */
|
| 3646 |
|
|
}
|
| 3647 |
|
|
|
| 3648 |
|
|
/* Tx event processing */
|
| 3649 |
|
|
if (ucce & UCCE_TX_EVENTS) {
|
| 3650 |
|
|
spin_lock(&ugeth->lock);
|
| 3651 |
|
|
tx_mask = UCCE_TXBF_SINGLE_MASK;
|
| 3652 |
|
|
for (i = 0; i < ug_info->numQueuesTx; i++) {
|
| 3653 |
|
|
if (ucce & tx_mask)
|
| 3654 |
|
|
ucc_geth_tx(dev, i);
|
| 3655 |
|
|
ucce &= ~tx_mask;
|
| 3656 |
|
|
tx_mask <<= 1;
|
| 3657 |
|
|
}
|
| 3658 |
|
|
spin_unlock(&ugeth->lock);
|
| 3659 |
|
|
}
|
| 3660 |
|
|
|
| 3661 |
|
|
/* Errors and other events */
|
| 3662 |
|
|
if (ucce & UCCE_OTHER) {
|
| 3663 |
|
|
if (ucce & UCCE_BSY) {
|
| 3664 |
|
|
dev->stats.rx_errors++;
|
| 3665 |
|
|
}
|
| 3666 |
|
|
if (ucce & UCCE_TXE) {
|
| 3667 |
|
|
dev->stats.tx_errors++;
|
| 3668 |
|
|
}
|
| 3669 |
|
|
}
|
| 3670 |
|
|
|
| 3671 |
|
|
return IRQ_HANDLED;
|
| 3672 |
|
|
}
|
| 3673 |
|
|
|
| 3674 |
|
|
/* Called when something needs to use the ethernet device */
|
| 3675 |
|
|
/* Returns 0 for success. */
|
| 3676 |
|
|
static int ucc_geth_open(struct net_device *dev)
|
| 3677 |
|
|
{
|
| 3678 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3679 |
|
|
int err;
|
| 3680 |
|
|
|
| 3681 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3682 |
|
|
|
| 3683 |
|
|
/* Test station address */
|
| 3684 |
|
|
if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
|
| 3685 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3686 |
|
|
ugeth_err("%s: Multicast address used for station address"
|
| 3687 |
|
|
" - is this what you wanted?", __FUNCTION__);
|
| 3688 |
|
|
return -EINVAL;
|
| 3689 |
|
|
}
|
| 3690 |
|
|
|
| 3691 |
|
|
err = ucc_struct_init(ugeth);
|
| 3692 |
|
|
if (err) {
|
| 3693 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3694 |
|
|
ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
|
| 3695 |
|
|
return err;
|
| 3696 |
|
|
}
|
| 3697 |
|
|
|
| 3698 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3699 |
|
|
napi_enable(&ugeth->napi);
|
| 3700 |
|
|
#endif
|
| 3701 |
|
|
err = ucc_geth_startup(ugeth);
|
| 3702 |
|
|
if (err) {
|
| 3703 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3704 |
|
|
ugeth_err("%s: Cannot configure net device, aborting.",
|
| 3705 |
|
|
dev->name);
|
| 3706 |
|
|
goto out_err;
|
| 3707 |
|
|
}
|
| 3708 |
|
|
|
| 3709 |
|
|
err = adjust_enet_interface(ugeth);
|
| 3710 |
|
|
if (err) {
|
| 3711 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3712 |
|
|
ugeth_err("%s: Cannot configure net device, aborting.",
|
| 3713 |
|
|
dev->name);
|
| 3714 |
|
|
goto out_err;
|
| 3715 |
|
|
}
|
| 3716 |
|
|
|
| 3717 |
|
|
/* Set MACSTNADDR1, MACSTNADDR2 */
|
| 3718 |
|
|
/* For more details see the hardware spec. */
|
| 3719 |
|
|
init_mac_station_addr_regs(dev->dev_addr[0],
|
| 3720 |
|
|
dev->dev_addr[1],
|
| 3721 |
|
|
dev->dev_addr[2],
|
| 3722 |
|
|
dev->dev_addr[3],
|
| 3723 |
|
|
dev->dev_addr[4],
|
| 3724 |
|
|
dev->dev_addr[5],
|
| 3725 |
|
|
&ugeth->ug_regs->macstnaddr1,
|
| 3726 |
|
|
&ugeth->ug_regs->macstnaddr2);
|
| 3727 |
|
|
|
| 3728 |
|
|
err = init_phy(dev);
|
| 3729 |
|
|
if (err) {
|
| 3730 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3731 |
|
|
ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
|
| 3732 |
|
|
goto out_err;
|
| 3733 |
|
|
}
|
| 3734 |
|
|
|
| 3735 |
|
|
phy_start(ugeth->phydev);
|
| 3736 |
|
|
|
| 3737 |
|
|
err =
|
| 3738 |
|
|
request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
|
| 3739 |
|
|
"UCC Geth", dev);
|
| 3740 |
|
|
if (err) {
|
| 3741 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3742 |
|
|
ugeth_err("%s: Cannot get IRQ for net device, aborting.",
|
| 3743 |
|
|
dev->name);
|
| 3744 |
|
|
ucc_geth_stop(ugeth);
|
| 3745 |
|
|
goto out_err;
|
| 3746 |
|
|
}
|
| 3747 |
|
|
|
| 3748 |
|
|
err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
|
| 3749 |
|
|
if (err) {
|
| 3750 |
|
|
if (netif_msg_ifup(ugeth))
|
| 3751 |
|
|
ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
|
| 3752 |
|
|
ucc_geth_stop(ugeth);
|
| 3753 |
|
|
goto out_err;
|
| 3754 |
|
|
}
|
| 3755 |
|
|
|
| 3756 |
|
|
netif_start_queue(dev);
|
| 3757 |
|
|
|
| 3758 |
|
|
return err;
|
| 3759 |
|
|
|
| 3760 |
|
|
out_err:
|
| 3761 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3762 |
|
|
napi_disable(&ugeth->napi);
|
| 3763 |
|
|
#endif
|
| 3764 |
|
|
return err;
|
| 3765 |
|
|
}
|
| 3766 |
|
|
|
| 3767 |
|
|
/* Stops the kernel queue, and halts the controller */
|
| 3768 |
|
|
static int ucc_geth_close(struct net_device *dev)
|
| 3769 |
|
|
{
|
| 3770 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3771 |
|
|
|
| 3772 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3773 |
|
|
|
| 3774 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3775 |
|
|
napi_disable(&ugeth->napi);
|
| 3776 |
|
|
#endif
|
| 3777 |
|
|
|
| 3778 |
|
|
ucc_geth_stop(ugeth);
|
| 3779 |
|
|
|
| 3780 |
|
|
phy_disconnect(ugeth->phydev);
|
| 3781 |
|
|
ugeth->phydev = NULL;
|
| 3782 |
|
|
|
| 3783 |
|
|
netif_stop_queue(dev);
|
| 3784 |
|
|
|
| 3785 |
|
|
return 0;
|
| 3786 |
|
|
}
|
| 3787 |
|
|
|
| 3788 |
|
|
static phy_interface_t to_phy_interface(const char *phy_connection_type)
|
| 3789 |
|
|
{
|
| 3790 |
|
|
if (strcasecmp(phy_connection_type, "mii") == 0)
|
| 3791 |
|
|
return PHY_INTERFACE_MODE_MII;
|
| 3792 |
|
|
if (strcasecmp(phy_connection_type, "gmii") == 0)
|
| 3793 |
|
|
return PHY_INTERFACE_MODE_GMII;
|
| 3794 |
|
|
if (strcasecmp(phy_connection_type, "tbi") == 0)
|
| 3795 |
|
|
return PHY_INTERFACE_MODE_TBI;
|
| 3796 |
|
|
if (strcasecmp(phy_connection_type, "rmii") == 0)
|
| 3797 |
|
|
return PHY_INTERFACE_MODE_RMII;
|
| 3798 |
|
|
if (strcasecmp(phy_connection_type, "rgmii") == 0)
|
| 3799 |
|
|
return PHY_INTERFACE_MODE_RGMII;
|
| 3800 |
|
|
if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
|
| 3801 |
|
|
return PHY_INTERFACE_MODE_RGMII_ID;
|
| 3802 |
|
|
if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
|
| 3803 |
|
|
return PHY_INTERFACE_MODE_RGMII_TXID;
|
| 3804 |
|
|
if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
|
| 3805 |
|
|
return PHY_INTERFACE_MODE_RGMII_RXID;
|
| 3806 |
|
|
if (strcasecmp(phy_connection_type, "rtbi") == 0)
|
| 3807 |
|
|
return PHY_INTERFACE_MODE_RTBI;
|
| 3808 |
|
|
|
| 3809 |
|
|
return PHY_INTERFACE_MODE_MII;
|
| 3810 |
|
|
}
|
| 3811 |
|
|
|
| 3812 |
|
|
static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
|
| 3813 |
|
|
{
|
| 3814 |
|
|
struct device *device = &ofdev->dev;
|
| 3815 |
|
|
struct device_node *np = ofdev->node;
|
| 3816 |
|
|
struct device_node *mdio;
|
| 3817 |
|
|
struct net_device *dev = NULL;
|
| 3818 |
|
|
struct ucc_geth_private *ugeth = NULL;
|
| 3819 |
|
|
struct ucc_geth_info *ug_info;
|
| 3820 |
|
|
struct resource res;
|
| 3821 |
|
|
struct device_node *phy;
|
| 3822 |
|
|
int err, ucc_num, max_speed = 0;
|
| 3823 |
|
|
const phandle *ph;
|
| 3824 |
|
|
const unsigned int *prop;
|
| 3825 |
|
|
const void *mac_addr;
|
| 3826 |
|
|
phy_interface_t phy_interface;
|
| 3827 |
|
|
static const int enet_to_speed[] = {
|
| 3828 |
|
|
SPEED_10, SPEED_10, SPEED_10,
|
| 3829 |
|
|
SPEED_100, SPEED_100, SPEED_100,
|
| 3830 |
|
|
SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
|
| 3831 |
|
|
};
|
| 3832 |
|
|
static const phy_interface_t enet_to_phy_interface[] = {
|
| 3833 |
|
|
PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
|
| 3834 |
|
|
PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
|
| 3835 |
|
|
PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
|
| 3836 |
|
|
PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
|
| 3837 |
|
|
PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
|
| 3838 |
|
|
};
|
| 3839 |
|
|
|
| 3840 |
|
|
ugeth_vdbg("%s: IN", __FUNCTION__);
|
| 3841 |
|
|
|
| 3842 |
|
|
prop = of_get_property(np, "device-id", NULL);
|
| 3843 |
|
|
ucc_num = *prop - 1;
|
| 3844 |
|
|
if ((ucc_num < 0) || (ucc_num > 7))
|
| 3845 |
|
|
return -ENODEV;
|
| 3846 |
|
|
|
| 3847 |
|
|
ug_info = &ugeth_info[ucc_num];
|
| 3848 |
|
|
if (ug_info == NULL) {
|
| 3849 |
|
|
if (netif_msg_probe(&debug))
|
| 3850 |
|
|
ugeth_err("%s: [%d] Missing additional data!",
|
| 3851 |
|
|
__FUNCTION__, ucc_num);
|
| 3852 |
|
|
return -ENODEV;
|
| 3853 |
|
|
}
|
| 3854 |
|
|
|
| 3855 |
|
|
ug_info->uf_info.ucc_num = ucc_num;
|
| 3856 |
|
|
|
| 3857 |
|
|
prop = of_get_property(np, "rx-clock", NULL);
|
| 3858 |
|
|
ug_info->uf_info.rx_clock = *prop;
|
| 3859 |
|
|
prop = of_get_property(np, "tx-clock", NULL);
|
| 3860 |
|
|
ug_info->uf_info.tx_clock = *prop;
|
| 3861 |
|
|
err = of_address_to_resource(np, 0, &res);
|
| 3862 |
|
|
if (err)
|
| 3863 |
|
|
return -EINVAL;
|
| 3864 |
|
|
|
| 3865 |
|
|
ug_info->uf_info.regs = res.start;
|
| 3866 |
|
|
ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
|
| 3867 |
|
|
|
| 3868 |
|
|
ph = of_get_property(np, "phy-handle", NULL);
|
| 3869 |
|
|
phy = of_find_node_by_phandle(*ph);
|
| 3870 |
|
|
|
| 3871 |
|
|
if (phy == NULL)
|
| 3872 |
|
|
return -ENODEV;
|
| 3873 |
|
|
|
| 3874 |
|
|
/* set the PHY address */
|
| 3875 |
|
|
prop = of_get_property(phy, "reg", NULL);
|
| 3876 |
|
|
if (prop == NULL)
|
| 3877 |
|
|
return -1;
|
| 3878 |
|
|
ug_info->phy_address = *prop;
|
| 3879 |
|
|
|
| 3880 |
|
|
/* get the phy interface type, or default to MII */
|
| 3881 |
|
|
prop = of_get_property(np, "phy-connection-type", NULL);
|
| 3882 |
|
|
if (!prop) {
|
| 3883 |
|
|
/* handle interface property present in old trees */
|
| 3884 |
|
|
prop = of_get_property(phy, "interface", NULL);
|
| 3885 |
|
|
if (prop != NULL) {
|
| 3886 |
|
|
phy_interface = enet_to_phy_interface[*prop];
|
| 3887 |
|
|
max_speed = enet_to_speed[*prop];
|
| 3888 |
|
|
} else
|
| 3889 |
|
|
phy_interface = PHY_INTERFACE_MODE_MII;
|
| 3890 |
|
|
} else {
|
| 3891 |
|
|
phy_interface = to_phy_interface((const char *)prop);
|
| 3892 |
|
|
}
|
| 3893 |
|
|
|
| 3894 |
|
|
/* get speed, or derive from PHY interface */
|
| 3895 |
|
|
if (max_speed == 0)
|
| 3896 |
|
|
switch (phy_interface) {
|
| 3897 |
|
|
case PHY_INTERFACE_MODE_GMII:
|
| 3898 |
|
|
case PHY_INTERFACE_MODE_RGMII:
|
| 3899 |
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
| 3900 |
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
| 3901 |
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
| 3902 |
|
|
case PHY_INTERFACE_MODE_TBI:
|
| 3903 |
|
|
case PHY_INTERFACE_MODE_RTBI:
|
| 3904 |
|
|
max_speed = SPEED_1000;
|
| 3905 |
|
|
break;
|
| 3906 |
|
|
default:
|
| 3907 |
|
|
max_speed = SPEED_100;
|
| 3908 |
|
|
break;
|
| 3909 |
|
|
}
|
| 3910 |
|
|
|
| 3911 |
|
|
if (max_speed == SPEED_1000) {
|
| 3912 |
|
|
/* configure muram FIFOs for gigabit operation */
|
| 3913 |
|
|
ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
|
| 3914 |
|
|
ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
|
| 3915 |
|
|
ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
|
| 3916 |
|
|
ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
|
| 3917 |
|
|
ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
|
| 3918 |
|
|
ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
|
| 3919 |
|
|
}
|
| 3920 |
|
|
|
| 3921 |
|
|
/* Set the bus id */
|
| 3922 |
|
|
mdio = of_get_parent(phy);
|
| 3923 |
|
|
|
| 3924 |
|
|
if (mdio == NULL)
|
| 3925 |
|
|
return -1;
|
| 3926 |
|
|
|
| 3927 |
|
|
err = of_address_to_resource(mdio, 0, &res);
|
| 3928 |
|
|
of_node_put(mdio);
|
| 3929 |
|
|
|
| 3930 |
|
|
if (err)
|
| 3931 |
|
|
return -1;
|
| 3932 |
|
|
|
| 3933 |
|
|
ug_info->mdio_bus = res.start;
|
| 3934 |
|
|
|
| 3935 |
|
|
if (netif_msg_probe(&debug))
|
| 3936 |
|
|
printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
|
| 3937 |
|
|
ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
|
| 3938 |
|
|
ug_info->uf_info.irq);
|
| 3939 |
|
|
|
| 3940 |
|
|
/* Create an ethernet device instance */
|
| 3941 |
|
|
dev = alloc_etherdev(sizeof(*ugeth));
|
| 3942 |
|
|
|
| 3943 |
|
|
if (dev == NULL)
|
| 3944 |
|
|
return -ENOMEM;
|
| 3945 |
|
|
|
| 3946 |
|
|
ugeth = netdev_priv(dev);
|
| 3947 |
|
|
spin_lock_init(&ugeth->lock);
|
| 3948 |
|
|
|
| 3949 |
|
|
dev_set_drvdata(device, dev);
|
| 3950 |
|
|
|
| 3951 |
|
|
/* Set the dev->base_addr to the gfar reg region */
|
| 3952 |
|
|
dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
|
| 3953 |
|
|
|
| 3954 |
|
|
SET_NETDEV_DEV(dev, device);
|
| 3955 |
|
|
|
| 3956 |
|
|
/* Fill in the dev structure */
|
| 3957 |
|
|
uec_set_ethtool_ops(dev);
|
| 3958 |
|
|
dev->open = ucc_geth_open;
|
| 3959 |
|
|
dev->hard_start_xmit = ucc_geth_start_xmit;
|
| 3960 |
|
|
dev->tx_timeout = ucc_geth_timeout;
|
| 3961 |
|
|
dev->watchdog_timeo = TX_TIMEOUT;
|
| 3962 |
|
|
#ifdef CONFIG_UGETH_NAPI
|
| 3963 |
|
|
netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
|
| 3964 |
|
|
#endif /* CONFIG_UGETH_NAPI */
|
| 3965 |
|
|
dev->stop = ucc_geth_close;
|
| 3966 |
|
|
// dev->change_mtu = ucc_geth_change_mtu;
|
| 3967 |
|
|
dev->mtu = 1500;
|
| 3968 |
|
|
dev->set_multicast_list = ucc_geth_set_multi;
|
| 3969 |
|
|
|
| 3970 |
|
|
ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
|
| 3971 |
|
|
ugeth->phy_interface = phy_interface;
|
| 3972 |
|
|
ugeth->max_speed = max_speed;
|
| 3973 |
|
|
|
| 3974 |
|
|
err = register_netdev(dev);
|
| 3975 |
|
|
if (err) {
|
| 3976 |
|
|
if (netif_msg_probe(ugeth))
|
| 3977 |
|
|
ugeth_err("%s: Cannot register net device, aborting.",
|
| 3978 |
|
|
dev->name);
|
| 3979 |
|
|
free_netdev(dev);
|
| 3980 |
|
|
return err;
|
| 3981 |
|
|
}
|
| 3982 |
|
|
|
| 3983 |
|
|
mac_addr = of_get_mac_address(np);
|
| 3984 |
|
|
if (mac_addr)
|
| 3985 |
|
|
memcpy(dev->dev_addr, mac_addr, 6);
|
| 3986 |
|
|
|
| 3987 |
|
|
ugeth->ug_info = ug_info;
|
| 3988 |
|
|
ugeth->dev = dev;
|
| 3989 |
|
|
|
| 3990 |
|
|
return 0;
|
| 3991 |
|
|
}
|
| 3992 |
|
|
|
| 3993 |
|
|
static int ucc_geth_remove(struct of_device* ofdev)
|
| 3994 |
|
|
{
|
| 3995 |
|
|
struct device *device = &ofdev->dev;
|
| 3996 |
|
|
struct net_device *dev = dev_get_drvdata(device);
|
| 3997 |
|
|
struct ucc_geth_private *ugeth = netdev_priv(dev);
|
| 3998 |
|
|
|
| 3999 |
|
|
dev_set_drvdata(device, NULL);
|
| 4000 |
|
|
ucc_geth_memclean(ugeth);
|
| 4001 |
|
|
free_netdev(dev);
|
| 4002 |
|
|
|
| 4003 |
|
|
return 0;
|
| 4004 |
|
|
}
|
| 4005 |
|
|
|
| 4006 |
|
|
static struct of_device_id ucc_geth_match[] = {
|
| 4007 |
|
|
{
|
| 4008 |
|
|
.type = "network",
|
| 4009 |
|
|
.compatible = "ucc_geth",
|
| 4010 |
|
|
},
|
| 4011 |
|
|
{},
|
| 4012 |
|
|
};
|
| 4013 |
|
|
|
| 4014 |
|
|
MODULE_DEVICE_TABLE(of, ucc_geth_match);
|
| 4015 |
|
|
|
| 4016 |
|
|
static struct of_platform_driver ucc_geth_driver = {
|
| 4017 |
|
|
.name = DRV_NAME,
|
| 4018 |
|
|
.match_table = ucc_geth_match,
|
| 4019 |
|
|
.probe = ucc_geth_probe,
|
| 4020 |
|
|
.remove = ucc_geth_remove,
|
| 4021 |
|
|
};
|
| 4022 |
|
|
|
| 4023 |
|
|
static int __init ucc_geth_init(void)
|
| 4024 |
|
|
{
|
| 4025 |
|
|
int i, ret;
|
| 4026 |
|
|
|
| 4027 |
|
|
ret = uec_mdio_init();
|
| 4028 |
|
|
|
| 4029 |
|
|
if (ret)
|
| 4030 |
|
|
return ret;
|
| 4031 |
|
|
|
| 4032 |
|
|
if (netif_msg_drv(&debug))
|
| 4033 |
|
|
printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
|
| 4034 |
|
|
for (i = 0; i < 8; i++)
|
| 4035 |
|
|
memcpy(&(ugeth_info[i]), &ugeth_primary_info,
|
| 4036 |
|
|
sizeof(ugeth_primary_info));
|
| 4037 |
|
|
|
| 4038 |
|
|
ret = of_register_platform_driver(&ucc_geth_driver);
|
| 4039 |
|
|
|
| 4040 |
|
|
if (ret)
|
| 4041 |
|
|
uec_mdio_exit();
|
| 4042 |
|
|
|
| 4043 |
|
|
return ret;
|
| 4044 |
|
|
}
|
| 4045 |
|
|
|
| 4046 |
|
|
static void __exit ucc_geth_exit(void)
|
| 4047 |
|
|
{
|
| 4048 |
|
|
of_unregister_platform_driver(&ucc_geth_driver);
|
| 4049 |
|
|
uec_mdio_exit();
|
| 4050 |
|
|
}
|
| 4051 |
|
|
|
| 4052 |
|
|
module_init(ucc_geth_init);
|
| 4053 |
|
|
module_exit(ucc_geth_exit);
|
| 4054 |
|
|
|
| 4055 |
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc");
|
| 4056 |
|
|
MODULE_DESCRIPTION(DRV_DESC);
|
| 4057 |
|
|
MODULE_VERSION(DRV_VERSION);
|
| 4058 |
|
|
MODULE_LICENSE("GPL");
|
