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marcus.erl |
/*
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* drivers/net/ucc_geth_mii.h
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*
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* QE UCC Gigabit Ethernet Driver -- MII Management Bus Implementation
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* Provides Bus interface for MII Management regs in the UCC register space
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*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Authors: Li Yang <leoli@freescale.com>
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* Kim Phillips <kim.phillips@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __UEC_MII_H
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#define __UEC_MII_H
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/* UCC GETH MIIMCFG (MII Management Configuration Register) */
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#define MIIMCFG_RESET_MANAGEMENT 0x80000000 /* Reset
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management */
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#define MIIMCFG_NO_PREAMBLE 0x00000010 /* Preamble
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suppress */
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#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) /* clock divide
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<< shift */
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#define MIIMCFG_CLOCK_DIVIDE_MAX 0xf /* max clock divide */
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2 0x00000000
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16 0x00000008
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32 0x00000009
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48 0x0000000a
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64 0x0000000b
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80 0x0000000c
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112 0x0000000d
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160 0x0000000e
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224 0x0000000f
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/* UCC GETH MIIMCOM (MII Management Command Register) */
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#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
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#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
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/* UCC GETH MIIMADD (MII Management Address Register) */
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#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) /* PHY Address
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<< shift */
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#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) /* PHY Register
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<< shift */
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/* UCC GETH MIIMCON (MII Management Control Register) */
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#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) /* PHY Control
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<< shift */
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#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) /* PHY Status
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<< shift */
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/* UCC GETH MIIMIND (MII Management Indicator Register) */
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#define MIIMIND_NOT_VALID 0x00000004 /* Not valid */
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#define MIIMIND_SCAN 0x00000002 /* Scan in
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progress */
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#define MIIMIND_BUSY 0x00000001
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/* Initial TBI Physical Address */
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#define UTBIPAR_INIT_TBIPA 0x1f
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struct ucc_mii_mng {
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u32 miimcfg; /* MII management configuration reg */
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u32 miimcom; /* MII management command reg */
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u32 miimadd; /* MII management address reg */
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u32 miimcon; /* MII management control reg */
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u32 miimstat; /* MII management status reg */
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u32 miimind; /* MII management indication reg */
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u8 notcare[28]; /* Space holder */
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u32 utbipar; /* TBI phy address reg */
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} __attribute__ ((packed));
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/* TBI / MII Set Register */
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enum enet_tbi_mii_reg {
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ENET_TBI_MII_CR = 0x00, /* Control */
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ENET_TBI_MII_SR = 0x01, /* Status */
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ENET_TBI_MII_ANA = 0x04, /* AN advertisement */
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ENET_TBI_MII_ANLPBPA = 0x05, /* AN link partner base page ability */
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ENET_TBI_MII_ANEX = 0x06, /* AN expansion */
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ENET_TBI_MII_ANNPT = 0x07, /* AN next page transmit */
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ENET_TBI_MII_ANLPANP = 0x08, /* AN link partner ability next page */
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ENET_TBI_MII_EXST = 0x0F, /* Extended status */
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ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics */
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ENET_TBI_MII_TBICON = 0x11 /* TBI control */
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};
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int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
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int uec_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
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int __init uec_mdio_init(void);
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void uec_mdio_exit(void);
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#endif /* __UEC_MII_H */
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