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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [net/] [wireless/] [p54pci.c] - Blame information for rev 62

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/*
 * Linux device driver for PCI based Prism54
 *
 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
 *
 * Based on the islsm (softmac prism54) driver, which is:
 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
 
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <net/mac80211.h>
 
#include "p54.h"
#include "p54pci.h"
 
MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");
 
static struct pci_device_id p54p_table[] __devinitdata = {
        /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
        { PCI_DEVICE(0x1260, 0x3890) },
        /* 3COM 3CRWE154G72 Wireless LAN adapter */
        { PCI_DEVICE(0x10b7, 0x6001) },
        /* Intersil PRISM Indigo Wireless LAN adapter */
        { PCI_DEVICE(0x1260, 0x3877) },
        /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
        { PCI_DEVICE(0x1260, 0x3886) },
        { },
};
 
MODULE_DEVICE_TABLE(pci, p54p_table);
 
static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
        struct p54p_priv *priv = dev->priv;
        const struct firmware *fw_entry = NULL;
        __le32 reg;
        int err;
        u32 *data;
        u32 remains, left, device_addr;
 
        P54P_WRITE(int_enable, 0);
        P54P_READ(int_enable);
        udelay(10);
 
        reg = P54P_READ(ctrl_stat);
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
        P54P_WRITE(ctrl_stat, reg);
        P54P_READ(ctrl_stat);
        udelay(10);
 
        reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
        P54P_WRITE(ctrl_stat, reg);
        wmb();
        udelay(10);
 
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
        P54P_WRITE(ctrl_stat, reg);
        wmb();
 
        mdelay(50);
 
        err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
        if (err) {
                printk(KERN_ERR "%s (prism54pci): cannot find firmware "
                       "(isl3886)\n", pci_name(priv->pdev));
                return err;
        }
 
        p54_parse_firmware(dev, fw_entry);
 
        data = (u32 *) fw_entry->data;
        remains = fw_entry->size;
        device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
        while (remains) {
                u32 i = 0;
                left = min((u32)0x1000, remains);
                P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
                P54P_READ(int_enable);
 
                device_addr += 0x1000;
                while (i < left) {
                        P54P_WRITE(direct_mem_win[i], *data++);
                        i += sizeof(u32);
                }
 
                remains -= left;
                P54P_READ(int_enable);
        }
 
        release_firmware(fw_entry);
 
        reg = P54P_READ(ctrl_stat);
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
        reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
        P54P_WRITE(ctrl_stat, reg);
        P54P_READ(ctrl_stat);
        udelay(10);
 
        reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
        P54P_WRITE(ctrl_stat, reg);
        wmb();
        udelay(10);
 
        reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
        P54P_WRITE(ctrl_stat, reg);
        wmb();
        udelay(10);
 
        return 0;
}
 
static irqreturn_t p54p_simple_interrupt(int irq, void *dev_id)
{
        struct p54p_priv *priv = (struct p54p_priv *) dev_id;
        __le32 reg;
 
        reg = P54P_READ(int_ident);
        P54P_WRITE(int_ack, reg);
 
        if (reg & P54P_READ(int_enable))
                complete(&priv->boot_comp);
 
        return IRQ_HANDLED;
}
 
static int p54p_read_eeprom(struct ieee80211_hw *dev)
{
        struct p54p_priv *priv = dev->priv;
        int err;
        struct p54_control_hdr *hdr;
        void *eeprom;
        dma_addr_t rx_mapping, tx_mapping;
        u16 alen;
 
        init_completion(&priv->boot_comp);
        err = request_irq(priv->pdev->irq, &p54p_simple_interrupt,
                          IRQF_SHARED, "prism54pci", priv);
        if (err) {
                printk(KERN_ERR "%s (prism54pci): failed to register IRQ handler\n",
                       pci_name(priv->pdev));
                return err;
        }
 
        eeprom = kmalloc(0x2010 + EEPROM_READBACK_LEN, GFP_KERNEL);
        if (!eeprom) {
                printk(KERN_ERR "%s (prism54pci): no memory for eeprom!\n",
                       pci_name(priv->pdev));
                err = -ENOMEM;
                goto out;
        }
 
        memset(priv->ring_control, 0, sizeof(*priv->ring_control));
        P54P_WRITE(ring_control_base, priv->ring_control_dma);
        P54P_READ(ring_control_base);
        udelay(10);
 
        P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
        P54P_READ(int_enable);
        udelay(10);
 
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 
        if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
                printk(KERN_ERR "%s (prism54pci): Cannot boot firmware!\n",
                       pci_name(priv->pdev));
                err = -EINVAL;
                goto out;
        }
 
        P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
        P54P_READ(int_enable);
 
        hdr = eeprom + 0x2010;
        p54_fill_eeprom_readback(hdr);
        hdr->req_id = cpu_to_le32(priv->common.rx_start);
 
        rx_mapping = pci_map_single(priv->pdev, eeprom,
                                    0x2010, PCI_DMA_FROMDEVICE);
        tx_mapping = pci_map_single(priv->pdev, (void *)hdr,
                                    EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);
 
        priv->ring_control->rx_mgmt[0].host_addr = cpu_to_le32(rx_mapping);
        priv->ring_control->rx_mgmt[0].len = cpu_to_le16(0x2010);
        priv->ring_control->tx_data[0].host_addr = cpu_to_le32(tx_mapping);
        priv->ring_control->tx_data[0].device_addr = hdr->req_id;
        priv->ring_control->tx_data[0].len = cpu_to_le16(EEPROM_READBACK_LEN);
 
        priv->ring_control->host_idx[2] = cpu_to_le32(1);
        priv->ring_control->host_idx[1] = cpu_to_le32(1);
 
        wmb();
        mdelay(100);
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 
        wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);
        wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);
 
        pci_unmap_single(priv->pdev, tx_mapping,
                         EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);
        pci_unmap_single(priv->pdev, rx_mapping,
                         0x2010, PCI_DMA_FROMDEVICE);
 
        alen = le16_to_cpu(priv->ring_control->rx_mgmt[0].len);
        if (le32_to_cpu(priv->ring_control->device_idx[2]) != 1 ||
            alen < 0x10) {
                printk(KERN_ERR "%s (prism54pci): Cannot read eeprom!\n",
                       pci_name(priv->pdev));
                err = -EINVAL;
                goto out;
        }
 
        p54_parse_eeprom(dev, (u8 *)eeprom + 0x10, alen - 0x10);
 
 out:
        kfree(eeprom);
        P54P_WRITE(int_enable, 0);
        P54P_READ(int_enable);
        udelay(10);
        free_irq(priv->pdev->irq, priv);
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
        return err;
}
 
static void p54p_refill_rx_ring(struct ieee80211_hw *dev)
{
        struct p54p_priv *priv = dev->priv;
        u32 limit, host_idx, idx;
 
        host_idx = le32_to_cpu(priv->ring_control->host_idx[0]);
        limit = host_idx;
        limit -= le32_to_cpu(priv->ring_control->device_idx[0]);
        limit = ARRAY_SIZE(priv->ring_control->rx_data) - limit;
 
        idx = host_idx % ARRAY_SIZE(priv->ring_control->rx_data);
        while (limit-- > 1) {
                struct p54p_desc *desc = &priv->ring_control->rx_data[idx];
 
                if (!desc->host_addr) {
                        struct sk_buff *skb;
                        dma_addr_t mapping;
                        skb = dev_alloc_skb(MAX_RX_SIZE);
                        if (!skb)
                                break;
 
                        mapping = pci_map_single(priv->pdev,
                                                 skb_tail_pointer(skb),
                                                 MAX_RX_SIZE,
                                                 PCI_DMA_FROMDEVICE);
                        desc->host_addr = cpu_to_le32(mapping);
                        desc->device_addr = 0;   // FIXME: necessary?
                        desc->len = cpu_to_le16(MAX_RX_SIZE);
                        desc->flags = 0;
                        priv->rx_buf[idx] = skb;
                }
 
                idx++;
                host_idx++;
                idx %= ARRAY_SIZE(priv->ring_control->rx_data);
        }
 
        wmb();
        priv->ring_control->host_idx[0] = cpu_to_le32(host_idx);
}
 
static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
        struct ieee80211_hw *dev = dev_id;
        struct p54p_priv *priv = dev->priv;
        __le32 reg;
 
        spin_lock(&priv->lock);
        reg = P54P_READ(int_ident);
        if (unlikely(reg == 0xFFFFFFFF)) {
                spin_unlock(&priv->lock);
                return IRQ_HANDLED;
        }
 
        P54P_WRITE(int_ack, reg);
 
        reg &= P54P_READ(int_enable);
 
        if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
                struct p54p_desc *desc;
                u32 idx, i;
                i = priv->tx_idx;
                i %= ARRAY_SIZE(priv->ring_control->tx_data);
                priv->tx_idx = idx = le32_to_cpu(priv->ring_control->device_idx[1]);
                idx %= ARRAY_SIZE(priv->ring_control->tx_data);
 
                while (i != idx) {
                        desc = &priv->ring_control->tx_data[i];
                        if (priv->tx_buf[i]) {
                                kfree(priv->tx_buf[i]);
                                priv->tx_buf[i] = NULL;
                        }
 
                        pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
                                         le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 
                        desc->host_addr = 0;
                        desc->device_addr = 0;
                        desc->len = 0;
                        desc->flags = 0;
 
                        i++;
                        i %= ARRAY_SIZE(priv->ring_control->tx_data);
                }
 
                i = priv->rx_idx;
                i %= ARRAY_SIZE(priv->ring_control->rx_data);
                priv->rx_idx = idx = le32_to_cpu(priv->ring_control->device_idx[0]);
                idx %= ARRAY_SIZE(priv->ring_control->rx_data);
                while (i != idx) {
                        u16 len;
                        struct sk_buff *skb;
                        desc = &priv->ring_control->rx_data[i];
                        len = le16_to_cpu(desc->len);
                        skb = priv->rx_buf[i];
 
                        skb_put(skb, len);
 
                        if (p54_rx(dev, skb)) {
                                pci_unmap_single(priv->pdev,
                                                 le32_to_cpu(desc->host_addr),
                                                 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 
                                priv->rx_buf[i] = NULL;
                                desc->host_addr = 0;
                        } else {
                                skb_trim(skb, 0);
                                desc->len = cpu_to_le16(MAX_RX_SIZE);
                        }
 
                        i++;
                        i %= ARRAY_SIZE(priv->ring_control->rx_data);
                }
 
                p54p_refill_rx_ring(dev);
 
                wmb();
                P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
        } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
                complete(&priv->boot_comp);
 
        spin_unlock(&priv->lock);
 
        return reg ? IRQ_HANDLED : IRQ_NONE;
}
 
static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data,
                    size_t len, int free_on_tx)
{
        struct p54p_priv *priv = dev->priv;
        unsigned long flags;
        struct p54p_desc *desc;
        dma_addr_t mapping;
        u32 device_idx, idx, i;
 
        spin_lock_irqsave(&priv->lock, flags);
 
        device_idx = le32_to_cpu(priv->ring_control->device_idx[1]);
        idx = le32_to_cpu(priv->ring_control->host_idx[1]);
        i = idx % ARRAY_SIZE(priv->ring_control->tx_data);
 
        mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);
        desc = &priv->ring_control->tx_data[i];
        desc->host_addr = cpu_to_le32(mapping);
        desc->device_addr = data->req_id;
        desc->len = cpu_to_le16(len);
        desc->flags = 0;
 
        wmb();
        priv->ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 
        if (free_on_tx)
                priv->tx_buf[i] = data;
 
        spin_unlock_irqrestore(&priv->lock, flags);
 
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
        P54P_READ(dev_int);
 
        /* FIXME: unlikely to happen because the device usually runs out of
           memory before we fill the ring up, but we can make it impossible */
        if (idx - device_idx > ARRAY_SIZE(priv->ring_control->tx_data) - 2)
                printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
}
 
static int p54p_open(struct ieee80211_hw *dev)
{
        struct p54p_priv *priv = dev->priv;
        int err;
 
        init_completion(&priv->boot_comp);
        err = request_irq(priv->pdev->irq, &p54p_interrupt,
                          IRQF_SHARED, "prism54pci", dev);
        if (err) {
                printk(KERN_ERR "%s: failed to register IRQ handler\n",
                       wiphy_name(dev->wiphy));
                return err;
        }
 
        memset(priv->ring_control, 0, sizeof(*priv->ring_control));
        priv->rx_idx = priv->tx_idx = 0;
        p54p_refill_rx_ring(dev);
 
        p54p_upload_firmware(dev);
 
        P54P_WRITE(ring_control_base, priv->ring_control_dma);
        P54P_READ(ring_control_base);
        wmb();
        udelay(10);
 
        P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
        P54P_READ(int_enable);
        wmb();
        udelay(10);
 
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
        P54P_READ(dev_int);
 
        if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
                printk(KERN_ERR "%s: Cannot boot firmware!\n",
                       wiphy_name(dev->wiphy));
                free_irq(priv->pdev->irq, dev);
                return -ETIMEDOUT;
        }
 
        P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
        P54P_READ(int_enable);
        wmb();
        udelay(10);
 
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
        P54P_READ(dev_int);
        wmb();
        udelay(10);
 
        return 0;
}
 
static void p54p_stop(struct ieee80211_hw *dev)
{
        struct p54p_priv *priv = dev->priv;
        unsigned int i;
        struct p54p_desc *desc;
 
        P54P_WRITE(int_enable, 0);
        P54P_READ(int_enable);
        udelay(10);
 
        free_irq(priv->pdev->irq, dev);
 
        P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 
        for (i = 0; i < ARRAY_SIZE(priv->rx_buf); i++) {
                desc = &priv->ring_control->rx_data[i];
                if (desc->host_addr)
                        pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
                                         MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
                kfree_skb(priv->rx_buf[i]);
                priv->rx_buf[i] = NULL;
        }
 
        for (i = 0; i < ARRAY_SIZE(priv->tx_buf); i++) {
                desc = &priv->ring_control->tx_data[i];
                if (desc->host_addr)
                        pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
                                         le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 
                kfree(priv->tx_buf[i]);
                priv->tx_buf[i] = NULL;
        }
 
        memset(priv->ring_control, 0, sizeof(*priv->ring_control));
}
 
static int __devinit p54p_probe(struct pci_dev *pdev,
                                const struct pci_device_id *id)
{
        struct p54p_priv *priv;
        struct ieee80211_hw *dev;
        unsigned long mem_addr, mem_len;
        int err;
        DECLARE_MAC_BUF(mac);
 
        err = pci_enable_device(pdev);
        if (err) {
                printk(KERN_ERR "%s (prism54pci): Cannot enable new PCI device\n",
                       pci_name(pdev));
                return err;
        }
 
        mem_addr = pci_resource_start(pdev, 0);
        mem_len = pci_resource_len(pdev, 0);
        if (mem_len < sizeof(struct p54p_csr)) {
                printk(KERN_ERR "%s (prism54pci): Too short PCI resources\n",
                       pci_name(pdev));
                pci_disable_device(pdev);
                return err;
        }
 
        err = pci_request_regions(pdev, "prism54pci");
        if (err) {
                printk(KERN_ERR "%s (prism54pci): Cannot obtain PCI resources\n",
                       pci_name(pdev));
                return err;
        }
 
        if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
            pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
                printk(KERN_ERR "%s (prism54pci): No suitable DMA available\n",
                       pci_name(pdev));
                goto err_free_reg;
        }
 
        pci_set_master(pdev);
        pci_try_set_mwi(pdev);
 
        pci_write_config_byte(pdev, 0x40, 0);
        pci_write_config_byte(pdev, 0x41, 0);
 
        dev = p54_init_common(sizeof(*priv));
        if (!dev) {
                printk(KERN_ERR "%s (prism54pci): ieee80211 alloc failed\n",
                       pci_name(pdev));
                err = -ENOMEM;
                goto err_free_reg;
        }
 
        priv = dev->priv;
        priv->pdev = pdev;
 
        SET_IEEE80211_DEV(dev, &pdev->dev);
        pci_set_drvdata(pdev, dev);
 
        priv->map = ioremap(mem_addr, mem_len);
        if (!priv->map) {
                printk(KERN_ERR "%s (prism54pci): Cannot map device memory\n",
                       pci_name(pdev));
                err = -EINVAL;  // TODO: use a better error code?
                goto err_free_dev;
        }
 
        priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
                                                  &priv->ring_control_dma);
        if (!priv->ring_control) {
                printk(KERN_ERR "%s (prism54pci): Cannot allocate rings\n",
                       pci_name(pdev));
                err = -ENOMEM;
                goto err_iounmap;
        }
        memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 
        err = p54p_upload_firmware(dev);
        if (err)
                goto err_free_desc;
 
        err = p54p_read_eeprom(dev);
        if (err)
                goto err_free_desc;
 
        priv->common.open = p54p_open;
        priv->common.stop = p54p_stop;
        priv->common.tx = p54p_tx;
 
        spin_lock_init(&priv->lock);
 
        err = ieee80211_register_hw(dev);
        if (err) {
                printk(KERN_ERR "%s (prism54pci): Cannot register netdevice\n",
                       pci_name(pdev));
                goto err_free_common;
        }
 
        printk(KERN_INFO "%s: hwaddr %s, isl38%02x\n",
               wiphy_name(dev->wiphy),
               print_mac(mac, dev->wiphy->perm_addr),
               priv->common.version);
 
        return 0;
 
 err_free_common:
        p54_free_common(dev);
 
 err_free_desc:
        pci_free_consistent(pdev, sizeof(*priv->ring_control),
                            priv->ring_control, priv->ring_control_dma);
 
 err_iounmap:
        iounmap(priv->map);
 
 err_free_dev:
        pci_set_drvdata(pdev, NULL);
        ieee80211_free_hw(dev);
 
 err_free_reg:
        pci_release_regions(pdev);
        pci_disable_device(pdev);
        return err;
}
 
static void __devexit p54p_remove(struct pci_dev *pdev)
{
        struct ieee80211_hw *dev = pci_get_drvdata(pdev);
        struct p54p_priv *priv;
 
        if (!dev)
                return;
 
        ieee80211_unregister_hw(dev);
        priv = dev->priv;
        pci_free_consistent(pdev, sizeof(*priv->ring_control),
                            priv->ring_control, priv->ring_control_dma);
        p54_free_common(dev);
        iounmap(priv->map);
        pci_release_regions(pdev);
        pci_disable_device(pdev);
        ieee80211_free_hw(dev);
}
 
#ifdef CONFIG_PM
static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
{
        struct ieee80211_hw *dev = pci_get_drvdata(pdev);
        struct p54p_priv *priv = dev->priv;
 
        if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {
                ieee80211_stop_queues(dev);
                p54p_stop(dev);
        }
 
        pci_save_state(pdev);
        pci_set_power_state(pdev, pci_choose_state(pdev, state));
        return 0;
}
 
static int p54p_resume(struct pci_dev *pdev)
{
        struct ieee80211_hw *dev = pci_get_drvdata(pdev);
        struct p54p_priv *priv = dev->priv;
 
        pci_set_power_state(pdev, PCI_D0);
        pci_restore_state(pdev);
 
        if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {
                p54p_open(dev);
                ieee80211_start_queues(dev);
        }
 
        return 0;
}
#endif /* CONFIG_PM */
 
static struct pci_driver p54p_driver = {
        .name           = "prism54pci",
        .id_table       = p54p_table,
        .probe          = p54p_probe,
        .remove         = __devexit_p(p54p_remove),
#ifdef CONFIG_PM
        .suspend        = p54p_suspend,
        .resume         = p54p_resume,
#endif /* CONFIG_PM */
};
 
static int __init p54p_init(void)
{
        return pci_register_driver(&p54p_driver);
}
 
static void __exit p54p_exit(void)
{
        pci_unregister_driver(&p54p_driver);
}
 
module_init(p54p_init);
module_exit(p54p_exit);

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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [net/] [wireless/] [p54pci.c] - Blame information for rev 62

Line No.	Rev	Author	Line
1	62	marcus.erl
2			`/*`
3			`* Linux device driver for PCI based Prism54`
4			`*`
5			`* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>`
6			`*`
7			`* Based on the islsm (softmac prism54) driver, which is:`
8			`* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.`
9			`*`
10			`* This program is free software; you can redistribute it and/or modify`
11			`* it under the terms of the GNU General Public License version 2 as`
12			`* published by the Free Software Foundation.`
13			`*/`
14
15			`#include <linux/init.h>`
16			`#include <linux/pci.h>`
17			`#include <linux/firmware.h>`
18			`#include <linux/etherdevice.h>`
19			`#include <linux/delay.h>`
20			`#include <linux/completion.h>`
21			`#include <net/mac80211.h>`
22
23			`#include "p54.h"`
24			`#include "p54pci.h"`
25
26			`MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");`
27			`MODULE_DESCRIPTION("Prism54 PCI wireless driver");`
28			`MODULE_LICENSE("GPL");`
29			`MODULE_ALIAS("prism54pci");`
30
31			`static struct pci_device_id p54p_table[] __devinitdata = {`
32			`/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */`
33			`{ PCI_DEVICE(0x1260, 0x3890) },`
34			`/* 3COM 3CRWE154G72 Wireless LAN adapter */`
35			`{ PCI_DEVICE(0x10b7, 0x6001) },`
36			`/* Intersil PRISM Indigo Wireless LAN adapter */`
37			`{ PCI_DEVICE(0x1260, 0x3877) },`
38			`/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */`
39			`{ PCI_DEVICE(0x1260, 0x3886) },`
40			`{ },`
41			`};`
42
43			`MODULE_DEVICE_TABLE(pci, p54p_table);`
44
45			`static int p54p_upload_firmware(struct ieee80211_hw *dev)`
46			`{`
47			`struct p54p_priv *priv = dev->priv;`
48			`const struct firmware *fw_entry = NULL;`
49			`__le32 reg;`
50			`int err;`
51			`u32 *data;`
52			`u32 remains, left, device_addr;`
53
54			`P54P_WRITE(int_enable, 0);`
55			`P54P_READ(int_enable);`
56			`udelay(10);`
57
58			`reg = P54P_READ(ctrl_stat);`
59			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);`
60			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);`
61			`P54P_WRITE(ctrl_stat, reg);`
62			`P54P_READ(ctrl_stat);`
63			`udelay(10);`
64
65			`reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);`
66			`P54P_WRITE(ctrl_stat, reg);`
67			`wmb();`
68			`udelay(10);`
69
70			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);`
71			`P54P_WRITE(ctrl_stat, reg);`
72			`wmb();`
73
74			`mdelay(50);`
75
76			`err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);`
77			`if (err) {`
78			`printk(KERN_ERR "%s (prism54pci): cannot find firmware "`
79			`"(isl3886)\n", pci_name(priv->pdev));`
80			`return err;`
81			`}`
82
83			`p54_parse_firmware(dev, fw_entry);`
84
85			`data = (u32 *) fw_entry->data;`
86			`remains = fw_entry->size;`
87			`device_addr = ISL38XX_DEV_FIRMWARE_ADDR;`
88			`while (remains) {`
89			`u32 i = 0;`
90			`left = min((u32)0x1000, remains);`
91			`P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));`
92			`P54P_READ(int_enable);`
93
94			`device_addr += 0x1000;`
95			`while (i < left) {`
96			`P54P_WRITE(direct_mem_win[i], *data++);`
97			`i += sizeof(u32);`
98			`}`
99
100			`remains -= left;`
101			`P54P_READ(int_enable);`
102			`}`
103
104			`release_firmware(fw_entry);`
105
106			`reg = P54P_READ(ctrl_stat);`
107			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);`
108			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);`
109			`reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);`
110			`P54P_WRITE(ctrl_stat, reg);`
111			`P54P_READ(ctrl_stat);`
112			`udelay(10);`
113
114			`reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);`
115			`P54P_WRITE(ctrl_stat, reg);`
116			`wmb();`
117			`udelay(10);`
118
119			`reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);`
120			`P54P_WRITE(ctrl_stat, reg);`
121			`wmb();`
122			`udelay(10);`
123
124			`return 0;`
125			`}`
126
127			`static irqreturn_t p54p_simple_interrupt(int irq, void *dev_id)`
128			`{`
129			`struct p54p_priv priv = (struct p54p_priv ) dev_id;`
130			`__le32 reg;`
131
132			`reg = P54P_READ(int_ident);`
133			`P54P_WRITE(int_ack, reg);`
134
135			`if (reg & P54P_READ(int_enable))`
136			`complete(&priv->boot_comp);`
137
138			`return IRQ_HANDLED;`
139			`}`
140
141			`static int p54p_read_eeprom(struct ieee80211_hw *dev)`
142			`{`
143			`struct p54p_priv *priv = dev->priv;`
144			`int err;`
145			`struct p54_control_hdr *hdr;`
146			`void *eeprom;`
147			`dma_addr_t rx_mapping, tx_mapping;`
148			`u16 alen;`
149
150			`init_completion(&priv->boot_comp);`
151			`err = request_irq(priv->pdev->irq, &p54p_simple_interrupt,`
152			`IRQF_SHARED, "prism54pci", priv);`
153			`if (err) {`
154			`printk(KERN_ERR "%s (prism54pci): failed to register IRQ handler\n",`
155			`pci_name(priv->pdev));`
156			`return err;`
157			`}`
158
159			`eeprom = kmalloc(0x2010 + EEPROM_READBACK_LEN, GFP_KERNEL);`
160			`if (!eeprom) {`
161			`printk(KERN_ERR "%s (prism54pci): no memory for eeprom!\n",`
162			`pci_name(priv->pdev));`
163			`err = -ENOMEM;`
164			`goto out;`
165			`}`
166
167			`memset(priv->ring_control, 0, sizeof(*priv->ring_control));`
168			`P54P_WRITE(ring_control_base, priv->ring_control_dma);`
169			`P54P_READ(ring_control_base);`
170			`udelay(10);`
171
172			`P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));`
173			`P54P_READ(int_enable);`
174			`udelay(10);`
175
176			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));`
177
178			`if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {`
179			`printk(KERN_ERR "%s (prism54pci): Cannot boot firmware!\n",`
180			`pci_name(priv->pdev));`
181			`err = -EINVAL;`
182			`goto out;`
183			`}`
184
185			`P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));`
186			`P54P_READ(int_enable);`
187
188			`hdr = eeprom + 0x2010;`
189			`p54_fill_eeprom_readback(hdr);`
190			`hdr->req_id = cpu_to_le32(priv->common.rx_start);`
191
192			`rx_mapping = pci_map_single(priv->pdev, eeprom,`
193			`0x2010, PCI_DMA_FROMDEVICE);`
194			`tx_mapping = pci_map_single(priv->pdev, (void *)hdr,`
195			`EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);`
196
197			`priv->ring_control->rx_mgmt[0].host_addr = cpu_to_le32(rx_mapping);`
198			`priv->ring_control->rx_mgmt[0].len = cpu_to_le16(0x2010);`
199			`priv->ring_control->tx_data[0].host_addr = cpu_to_le32(tx_mapping);`
200			`priv->ring_control->tx_data[0].device_addr = hdr->req_id;`
201			`priv->ring_control->tx_data[0].len = cpu_to_le16(EEPROM_READBACK_LEN);`
202
203			`priv->ring_control->host_idx[2] = cpu_to_le32(1);`
204			`priv->ring_control->host_idx[1] = cpu_to_le32(1);`
205
206			`wmb();`
207			`mdelay(100);`
208			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));`
209
210			`wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);`
211			`wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);`
212
213			`pci_unmap_single(priv->pdev, tx_mapping,`
214			`EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);`
215			`pci_unmap_single(priv->pdev, rx_mapping,`
216			`0x2010, PCI_DMA_FROMDEVICE);`
217
218			`alen = le16_to_cpu(priv->ring_control->rx_mgmt[0].len);`
219			`if (le32_to_cpu(priv->ring_control->device_idx[2]) != 1 \|\|`
220			`alen < 0x10) {`
221			`printk(KERN_ERR "%s (prism54pci): Cannot read eeprom!\n",`
222			`pci_name(priv->pdev));`
223			`err = -EINVAL;`
224			`goto out;`
225			`}`
226
227			`p54_parse_eeprom(dev, (u8 *)eeprom + 0x10, alen - 0x10);`
228
229			`out:`
230			`kfree(eeprom);`
231			`P54P_WRITE(int_enable, 0);`
232			`P54P_READ(int_enable);`
233			`udelay(10);`
234			`free_irq(priv->pdev->irq, priv);`
235			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));`
236			`return err;`
237			`}`
238
239			`static void p54p_refill_rx_ring(struct ieee80211_hw *dev)`
240			`{`
241			`struct p54p_priv *priv = dev->priv;`
242			`u32 limit, host_idx, idx;`
243
244			`host_idx = le32_to_cpu(priv->ring_control->host_idx[0]);`
245			`limit = host_idx;`
246			`limit -= le32_to_cpu(priv->ring_control->device_idx[0]);`
247			`limit = ARRAY_SIZE(priv->ring_control->rx_data) - limit;`
248
249			`idx = host_idx % ARRAY_SIZE(priv->ring_control->rx_data);`
250			`while (limit-- > 1) {`
251			`struct p54p_desc *desc = &priv->ring_control->rx_data[idx];`
252
253			`if (!desc->host_addr) {`
254			`struct sk_buff *skb;`
255			`dma_addr_t mapping;`
256			`skb = dev_alloc_skb(MAX_RX_SIZE);`
257			`if (!skb)`
258			`break;`
259
260			`mapping = pci_map_single(priv->pdev,`
261			`skb_tail_pointer(skb),`
262			`MAX_RX_SIZE,`
263			`PCI_DMA_FROMDEVICE);`
264			`desc->host_addr = cpu_to_le32(mapping);`
265			`desc->device_addr = 0; // FIXME: necessary?`
266			`desc->len = cpu_to_le16(MAX_RX_SIZE);`
267			`desc->flags = 0;`
268			`priv->rx_buf[idx] = skb;`
269			`}`
270
271			`idx++;`
272			`host_idx++;`
273			`idx %= ARRAY_SIZE(priv->ring_control->rx_data);`
274			`}`
275
276			`wmb();`
277			`priv->ring_control->host_idx[0] = cpu_to_le32(host_idx);`
278			`}`
279
280			`static irqreturn_t p54p_interrupt(int irq, void *dev_id)`
281			`{`
282			`struct ieee80211_hw *dev = dev_id;`
283			`struct p54p_priv *priv = dev->priv;`
284			`__le32 reg;`
285
286			`spin_lock(&priv->lock);`
287			`reg = P54P_READ(int_ident);`
288			`if (unlikely(reg == 0xFFFFFFFF)) {`
289			`spin_unlock(&priv->lock);`
290			`return IRQ_HANDLED;`
291			`}`
292
293			`P54P_WRITE(int_ack, reg);`
294
295			`reg &= P54P_READ(int_enable);`
296
297			`if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {`
298			`struct p54p_desc *desc;`
299			`u32 idx, i;`
300			`i = priv->tx_idx;`
301			`i %= ARRAY_SIZE(priv->ring_control->tx_data);`
302			`priv->tx_idx = idx = le32_to_cpu(priv->ring_control->device_idx[1]);`
303			`idx %= ARRAY_SIZE(priv->ring_control->tx_data);`
304
305			`while (i != idx) {`
306			`desc = &priv->ring_control->tx_data[i];`
307			`if (priv->tx_buf[i]) {`
308			`kfree(priv->tx_buf[i]);`
309			`priv->tx_buf[i] = NULL;`
310			`}`
311
312			`pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),`
313			`le16_to_cpu(desc->len), PCI_DMA_TODEVICE);`
314
315			`desc->host_addr = 0;`
316			`desc->device_addr = 0;`
317			`desc->len = 0;`
318			`desc->flags = 0;`
319
320			`i++;`
321			`i %= ARRAY_SIZE(priv->ring_control->tx_data);`
322			`}`
323
324			`i = priv->rx_idx;`
325			`i %= ARRAY_SIZE(priv->ring_control->rx_data);`
326			`priv->rx_idx = idx = le32_to_cpu(priv->ring_control->device_idx[0]);`
327			`idx %= ARRAY_SIZE(priv->ring_control->rx_data);`
328			`while (i != idx) {`
329			`u16 len;`
330			`struct sk_buff *skb;`
331			`desc = &priv->ring_control->rx_data[i];`
332			`len = le16_to_cpu(desc->len);`
333			`skb = priv->rx_buf[i];`
334
335			`skb_put(skb, len);`
336
337			`if (p54_rx(dev, skb)) {`
338			`pci_unmap_single(priv->pdev,`
339			`le32_to_cpu(desc->host_addr),`
340			`MAX_RX_SIZE, PCI_DMA_FROMDEVICE);`
341
342			`priv->rx_buf[i] = NULL;`
343			`desc->host_addr = 0;`
344			`} else {`
345			`skb_trim(skb, 0);`
346			`desc->len = cpu_to_le16(MAX_RX_SIZE);`
347			`}`
348
349			`i++;`
350			`i %= ARRAY_SIZE(priv->ring_control->rx_data);`
351			`}`
352
353			`p54p_refill_rx_ring(dev);`
354
355			`wmb();`
356			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));`
357			`} else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))`
358			`complete(&priv->boot_comp);`
359
360			`spin_unlock(&priv->lock);`
361
362			`return reg ? IRQ_HANDLED : IRQ_NONE;`
363			`}`
364
365			`static void p54p_tx(struct ieee80211_hw dev, struct p54_control_hdr data,`
366			`size_t len, int free_on_tx)`
367			`{`
368			`struct p54p_priv *priv = dev->priv;`
369			`unsigned long flags;`
370			`struct p54p_desc *desc;`
371			`dma_addr_t mapping;`
372			`u32 device_idx, idx, i;`
373
374			`spin_lock_irqsave(&priv->lock, flags);`
375
376			`device_idx = le32_to_cpu(priv->ring_control->device_idx[1]);`
377			`idx = le32_to_cpu(priv->ring_control->host_idx[1]);`
378			`i = idx % ARRAY_SIZE(priv->ring_control->tx_data);`
379
380			`mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);`
381			`desc = &priv->ring_control->tx_data[i];`
382			`desc->host_addr = cpu_to_le32(mapping);`
383			`desc->device_addr = data->req_id;`
384			`desc->len = cpu_to_le16(len);`
385			`desc->flags = 0;`
386
387			`wmb();`
388			`priv->ring_control->host_idx[1] = cpu_to_le32(idx + 1);`
389
390			`if (free_on_tx)`
391			`priv->tx_buf[i] = data;`
392
393			`spin_unlock_irqrestore(&priv->lock, flags);`
394
395			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));`
396			`P54P_READ(dev_int);`
397
398			`/* FIXME: unlikely to happen because the device usually runs out of`
399			`memory before we fill the ring up, but we can make it impossible */`
400			`if (idx - device_idx > ARRAY_SIZE(priv->ring_control->tx_data) - 2)`
401			`printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));`
402			`}`
403
404			`static int p54p_open(struct ieee80211_hw *dev)`
405			`{`
406			`struct p54p_priv *priv = dev->priv;`
407			`int err;`
408
409			`init_completion(&priv->boot_comp);`
410			`err = request_irq(priv->pdev->irq, &p54p_interrupt,`
411			`IRQF_SHARED, "prism54pci", dev);`
412			`if (err) {`
413			`printk(KERN_ERR "%s: failed to register IRQ handler\n",`
414			`wiphy_name(dev->wiphy));`
415			`return err;`
416			`}`
417
418			`memset(priv->ring_control, 0, sizeof(*priv->ring_control));`
419			`priv->rx_idx = priv->tx_idx = 0;`
420			`p54p_refill_rx_ring(dev);`
421
422			`p54p_upload_firmware(dev);`
423
424			`P54P_WRITE(ring_control_base, priv->ring_control_dma);`
425			`P54P_READ(ring_control_base);`
426			`wmb();`
427			`udelay(10);`
428
429			`P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));`
430			`P54P_READ(int_enable);`
431			`wmb();`
432			`udelay(10);`
433
434			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));`
435			`P54P_READ(dev_int);`
436
437			`if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {`
438			`printk(KERN_ERR "%s: Cannot boot firmware!\n",`
439			`wiphy_name(dev->wiphy));`
440			`free_irq(priv->pdev->irq, dev);`
441			`return -ETIMEDOUT;`
442			`}`
443
444			`P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));`
445			`P54P_READ(int_enable);`
446			`wmb();`
447			`udelay(10);`
448
449			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));`
450			`P54P_READ(dev_int);`
451			`wmb();`
452			`udelay(10);`
453
454			`return 0;`
455			`}`
456
457			`static void p54p_stop(struct ieee80211_hw *dev)`
458			`{`
459			`struct p54p_priv *priv = dev->priv;`
460			`unsigned int i;`
461			`struct p54p_desc *desc;`
462
463			`P54P_WRITE(int_enable, 0);`
464			`P54P_READ(int_enable);`
465			`udelay(10);`
466
467			`free_irq(priv->pdev->irq, dev);`
468
469			`P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));`
470
471			`for (i = 0; i < ARRAY_SIZE(priv->rx_buf); i++) {`
472			`desc = &priv->ring_control->rx_data[i];`
473			`if (desc->host_addr)`
474			`pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),`
475			`MAX_RX_SIZE, PCI_DMA_FROMDEVICE);`
476			`kfree_skb(priv->rx_buf[i]);`
477			`priv->rx_buf[i] = NULL;`
478			`}`
479
480			`for (i = 0; i < ARRAY_SIZE(priv->tx_buf); i++) {`
481			`desc = &priv->ring_control->tx_data[i];`
482			`if (desc->host_addr)`
483			`pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),`
484			`le16_to_cpu(desc->len), PCI_DMA_TODEVICE);`
485
486			`kfree(priv->tx_buf[i]);`
487			`priv->tx_buf[i] = NULL;`
488			`}`
489
490			`memset(priv->ring_control, 0, sizeof(*priv->ring_control));`
491			`}`
492
493			`static int __devinit p54p_probe(struct pci_dev *pdev,`
494			`const struct pci_device_id *id)`
495			`{`
496			`struct p54p_priv *priv;`
497			`struct ieee80211_hw *dev;`
498			`unsigned long mem_addr, mem_len;`
499			`int err;`
500			`DECLARE_MAC_BUF(mac);`
501
502			`err = pci_enable_device(pdev);`
503			`if (err) {`
504			`printk(KERN_ERR "%s (prism54pci): Cannot enable new PCI device\n",`
505			`pci_name(pdev));`
506			`return err;`
507			`}`
508
509			`mem_addr = pci_resource_start(pdev, 0);`
510			`mem_len = pci_resource_len(pdev, 0);`
511			`if (mem_len < sizeof(struct p54p_csr)) {`
512			`printk(KERN_ERR "%s (prism54pci): Too short PCI resources\n",`
513			`pci_name(pdev));`
514			`pci_disable_device(pdev);`
515			`return err;`
516			`}`
517
518			`err = pci_request_regions(pdev, "prism54pci");`
519			`if (err) {`
520			`printk(KERN_ERR "%s (prism54pci): Cannot obtain PCI resources\n",`
521			`pci_name(pdev));`
522			`return err;`
523			`}`
524
525			`if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) \|\|`
526			`pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {`
527			`printk(KERN_ERR "%s (prism54pci): No suitable DMA available\n",`
528			`pci_name(pdev));`
529			`goto err_free_reg;`
530			`}`
531
532			`pci_set_master(pdev);`
533			`pci_try_set_mwi(pdev);`
534
535			`pci_write_config_byte(pdev, 0x40, 0);`
536			`pci_write_config_byte(pdev, 0x41, 0);`
537
538			`dev = p54_init_common(sizeof(*priv));`
539			`if (!dev) {`
540			`printk(KERN_ERR "%s (prism54pci): ieee80211 alloc failed\n",`
541			`pci_name(pdev));`
542			`err = -ENOMEM;`
543			`goto err_free_reg;`
544			`}`
545
546			`priv = dev->priv;`
547			`priv->pdev = pdev;`
548
549			`SET_IEEE80211_DEV(dev, &pdev->dev);`
550			`pci_set_drvdata(pdev, dev);`
551
552			`priv->map = ioremap(mem_addr, mem_len);`
553			`if (!priv->map) {`
554			`printk(KERN_ERR "%s (prism54pci): Cannot map device memory\n",`
555			`pci_name(pdev));`
556			`err = -EINVAL; // TODO: use a better error code?`
557			`goto err_free_dev;`
558			`}`
559
560			`priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),`
561			`&priv->ring_control_dma);`
562			`if (!priv->ring_control) {`
563			`printk(KERN_ERR "%s (prism54pci): Cannot allocate rings\n",`
564			`pci_name(pdev));`
565			`err = -ENOMEM;`
566			`goto err_iounmap;`
567			`}`
568			`memset(priv->ring_control, 0, sizeof(*priv->ring_control));`
569
570			`err = p54p_upload_firmware(dev);`
571			`if (err)`
572			`goto err_free_desc;`
573
574			`err = p54p_read_eeprom(dev);`
575			`if (err)`
576			`goto err_free_desc;`
577
578			`priv->common.open = p54p_open;`
579			`priv->common.stop = p54p_stop;`
580			`priv->common.tx = p54p_tx;`
581
582			`spin_lock_init(&priv->lock);`
583
584			`err = ieee80211_register_hw(dev);`
585			`if (err) {`
586			`printk(KERN_ERR "%s (prism54pci): Cannot register netdevice\n",`
587			`pci_name(pdev));`
588			`goto err_free_common;`
589			`}`
590
591			`printk(KERN_INFO "%s: hwaddr %s, isl38%02x\n",`
592			`wiphy_name(dev->wiphy),`
593			`print_mac(mac, dev->wiphy->perm_addr),`
594			`priv->common.version);`
595
596			`return 0;`
597
598			`err_free_common:`
599			`p54_free_common(dev);`
600
601			`err_free_desc:`
602			`pci_free_consistent(pdev, sizeof(*priv->ring_control),`
603			`priv->ring_control, priv->ring_control_dma);`
604
605			`err_iounmap:`
606			`iounmap(priv->map);`
607
608			`err_free_dev:`
609			`pci_set_drvdata(pdev, NULL);`
610			`ieee80211_free_hw(dev);`
611
612			`err_free_reg:`
613			`pci_release_regions(pdev);`
614			`pci_disable_device(pdev);`
615			`return err;`
616			`}`
617
618			`static void __devexit p54p_remove(struct pci_dev *pdev)`
619			`{`
620			`struct ieee80211_hw *dev = pci_get_drvdata(pdev);`
621			`struct p54p_priv *priv;`
622
623			`if (!dev)`
624			`return;`
625
626			`ieee80211_unregister_hw(dev);`
627			`priv = dev->priv;`
628			`pci_free_consistent(pdev, sizeof(*priv->ring_control),`
629			`priv->ring_control, priv->ring_control_dma);`
630			`p54_free_common(dev);`
631			`iounmap(priv->map);`
632			`pci_release_regions(pdev);`
633			`pci_disable_device(pdev);`
634			`ieee80211_free_hw(dev);`
635			`}`
636
637			`#ifdef CONFIG_PM`
638			`static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)`
639			`{`
640			`struct ieee80211_hw *dev = pci_get_drvdata(pdev);`
641			`struct p54p_priv *priv = dev->priv;`
642
643			`if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {`
644			`ieee80211_stop_queues(dev);`
645			`p54p_stop(dev);`
646			`}`
647
648			`pci_save_state(pdev);`
649			`pci_set_power_state(pdev, pci_choose_state(pdev, state));`
650			`return 0;`
651			`}`
652
653			`static int p54p_resume(struct pci_dev *pdev)`
654			`{`
655			`struct ieee80211_hw *dev = pci_get_drvdata(pdev);`
656			`struct p54p_priv *priv = dev->priv;`
657
658			`pci_set_power_state(pdev, PCI_D0);`
659			`pci_restore_state(pdev);`
660
661			`if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {`
662			`p54p_open(dev);`
663			`ieee80211_start_queues(dev);`
664			`}`
665
666			`return 0;`
667			`}`
668			`#endif /* CONFIG_PM */`
669
670			`static struct pci_driver p54p_driver = {`
671			`.name = "prism54pci",`
672			`.id_table = p54p_table,`
673			`.probe = p54p_probe,`
674			`.remove = __devexit_p(p54p_remove),`
675			`#ifdef CONFIG_PM`
676			`.suspend = p54p_suspend,`
677			`.resume = p54p_resume,`
678			`#endif /* CONFIG_PM */`
679			`};`
680
681			`static int __init p54p_init(void)`
682			`{`
683			`return pci_register_driver(&p54p_driver);`
684			`}`
685
686			`static void __exit p54p_exit(void)`
687			`{`
688			`pci_unregister_driver(&p54p_driver);`
689			`}`
690
691			`module_init(p54p_init);`
692			`module_exit(p54p_exit);`