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/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */

/*

        Written 1997-2001 by Donald Becker.

        This software may be used and distributed according to the terms of

        the GNU General Public License (GPL), incorporated herein by reference.

        Drivers based on or derived from this code fall under the GPL and must

        retain the authorship, copyright and license notice.  This file is not

        a complete program and may only be used when the entire operating

        system is licensed under the GPL.

        This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.

        It also supports the Symbios Logic version of the same chip core.

        The author may be reached as becker@scyld.com, or C/O

        Scyld Computing Corporation

        410 Severn Ave., Suite 210

        Annapolis MD 21403

        Support and updates available at

        http://www.scyld.com/network/yellowfin.html

        [link no longer provides useful info -jgarzik]

*/

#define DRV_NAME        "yellowfin"

#define DRV_VERSION     "2.1"

#define DRV_RELDATE     "Sep 11, 2006"

#define PFX DRV_NAME ": "

/* The user-configurable values.

   These may be modified when a driver module is loaded.*/

static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

static int max_interrupt_work = 20;

static int mtu;

#ifdef YF_PROTOTYPE                     /* Support for prototype hardware errata. */

/* System-wide count of bogus-rx frames. */

static int bogus_rx;

static int dma_ctrl = 0x004A0263;                       /* Constrained by errata */

static int fifo_cfg = 0x0020;                           /* Bypass external Tx FIFO. */

#elif defined(YF_NEW)                                   /* A future perfect board :->.  */

static int dma_ctrl = 0x00CAC277;                       /* Override when loading module! */

static int fifo_cfg = 0x0028;

#else

static const int dma_ctrl = 0x004A0263;                         /* Constrained by errata */

static const int fifo_cfg = 0x0020;                             /* Bypass external Tx FIFO. */

#endif

/* Set the copy breakpoint for the copy-only-tiny-frames scheme.

   Setting to > 1514 effectively disables this feature. */

static int rx_copybreak;

/* Used to pass the media type, etc.

   No media types are currently defined.  These exist for driver

   interoperability.

*/

#define MAX_UNITS 8                             /* More are supported, limit only on options */

static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

/* Do ugly workaround for GX server chipset errata. */

static int gx_fix;

/* Operational parameters that are set at compile time. */

/* Keep the ring sizes a power of two for efficiency.

   Making the Tx ring too long decreases the effectiveness of channel

   bonding and packet priority.

   There are no ill effects from too-large receive rings. */

#define TX_RING_SIZE    16

#define TX_QUEUE_SIZE   12              /* Must be > 4 && <= TX_RING_SIZE */

#define RX_RING_SIZE    64

#define STATUS_TOTAL_SIZE       TX_RING_SIZE*sizeof(struct tx_status_words)

#define TX_TOTAL_SIZE           2*TX_RING_SIZE*sizeof(struct yellowfin_desc)

#define RX_TOTAL_SIZE           RX_RING_SIZE*sizeof(struct yellowfin_desc)

/* Operational parameters that usually are not changed. */

/* Time in jiffies before concluding the transmitter is hung. */

#define TX_TIMEOUT  (2*HZ)

#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/

#define yellowfin_debug debug

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/string.h>

#include <linux/timer.h>

#include <linux/errno.h>

#include <linux/ioport.h>

#include <linux/slab.h>

#include <linux/interrupt.h>

#include <linux/pci.h>

#include <linux/init.h>

#include <linux/mii.h>

#include <linux/netdevice.h>

#include <linux/etherdevice.h>

#include <linux/skbuff.h>

#include <linux/ethtool.h>

#include <linux/crc32.h>

#include <linux/bitops.h>

#include <asm/uaccess.h>

#include <asm/processor.h>              /* Processor type for cache alignment. */

#include <asm/unaligned.h>

#include <asm/io.h>

/* These identify the driver base version and may not be removed. */

static char version[] __devinitdata =

KERN_INFO DRV_NAME ".c:v1.05  1/09/2001  Written by Donald Becker <becker@scyld.com>\n"

KERN_INFO "  (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";

MODULE_AUTHOR("Donald Becker <becker@scyld.com>");

MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");

MODULE_LICENSE("GPL");

module_param(max_interrupt_work, int, 0);

module_param(mtu, int, 0);

module_param(debug, int, 0);

module_param(rx_copybreak, int, 0);

module_param_array(options, int, NULL, 0);

module_param_array(full_duplex, int, NULL, 0);

module_param(gx_fix, int, 0);

MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");

MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");

MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");

MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");

MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");

MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");

MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");

/*

                                Theory of Operation

I. Board Compatibility

This device driver is designed for the Packet Engines "Yellowfin" Gigabit

Ethernet adapter.  The G-NIC 64-bit PCI card is supported, as well as the

Symbios 53C885E dual function chip.

II. Board-specific settings

PCI bus devices are configured by the system at boot time, so no jumpers

need to be set on the board.  The system BIOS preferably should assign the

PCI INTA signal to an otherwise unused system IRQ line.

Note: Kernel versions earlier than 1.3.73 do not support shared PCI

interrupt lines.

III. Driver operation

IIIa. Ring buffers

The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.

This is a descriptor list scheme similar to that used by the EEPro100 and

Tulip.  This driver uses two statically allocated fixed-size descriptor lists

formed into rings by a branch from the final descriptor to the beginning of

the list.  The ring sizes are set at compile time by RX/TX_RING_SIZE.

The driver allocates full frame size skbuffs for the Rx ring buffers at

open() time and passes the skb->data field to the Yellowfin as receive data

buffers.  When an incoming frame is less than RX_COPYBREAK bytes long,

a fresh skbuff is allocated and the frame is copied to the new skbuff.

When the incoming frame is larger, the skbuff is passed directly up the

protocol stack and replaced by a newly allocated skbuff.

The RX_COPYBREAK value is chosen to trade-off the memory wasted by

using a full-sized skbuff for small frames vs. the copying costs of larger

frames.  For small frames the copying cost is negligible (esp. considering

that we are pre-loading the cache with immediately useful header

information).  For large frames the copying cost is non-trivial, and the

larger copy might flush the cache of useful data.

IIIC. Synchronization

The driver runs as two independent, single-threaded flows of control.  One

is the send-packet routine, which enforces single-threaded use by the

dev->tbusy flag.  The other thread is the interrupt handler, which is single

threaded by the hardware and other software.

The send packet thread has partial control over the Tx ring and 'dev->tbusy'

flag.  It sets the tbusy flag whenever it's queuing a Tx packet. If the next

queue slot is empty, it clears the tbusy flag when finished otherwise it sets

the 'yp->tx_full' flag.

The interrupt handler has exclusive control over the Rx ring and records stats

from the Tx ring.  After reaping the stats, it marks the Tx queue entry as

empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it

clears both the tx_full and tbusy flags.

IV. Notes

Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.

Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board

and an AlphaStation to verifty the Alpha port!

IVb. References

Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential

Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary

   Data Manual v3.0

http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html

http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html

IVc. Errata

See Packet Engines confidential appendix (prototype chips only).

*/

enum capability_flags {

        HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,

        HasMACAddrBug=32, /* Only on early revs.  */

        DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */

};

/* The PCI I/O space extent. */

enum {

        YELLOWFIN_SIZE  = 0x100,

};

struct pci_id_info {

        const char *name;

        struct match_info {

                int     pci, pci_mask, subsystem, subsystem_mask;

                int revision, revision_mask;                            /* Only 8 bits. */

        } id;

        int drv_flags;                          /* Driver use, intended as capability flags. */

};

static const struct pci_id_info pci_id_tbl[] = {

        {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},

         FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},

        {"Symbios SYM83C885", { 0x07011000, 0xffffffff},

          HasMII | DontUseEeprom },

        { }

};

static const struct pci_device_id yellowfin_pci_tbl[] = {

        { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },

        { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },

        { }

};

MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);

/* Offsets to the Yellowfin registers.  Various sizes and alignments. */

enum yellowfin_offsets {

        TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,

        TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,

        RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,

        RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,

        EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,

        ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,

        Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,

        MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,

        MII_Status=0xAE,

        RxDepth=0xB8, FlowCtrl=0xBC,

        AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,

        EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,

        EEFeature=0xF5,

};

/* The Yellowfin Rx and Tx buffer descriptors.

   Elements are written as 32 bit for endian portability. */

struct yellowfin_desc {

        __le32 dbdma_cmd;

        __le32 addr;

        __le32 branch_addr;

        __le32 result_status;

};

struct tx_status_words {

#ifdef __BIG_ENDIAN

        u16 tx_errs;

        u16 tx_cnt;

        u16 paused;

        u16 total_tx_cnt;

#else  /* Little endian chips. */

        u16 tx_cnt;

        u16 tx_errs;

        u16 total_tx_cnt;

        u16 paused;

#endif /* __BIG_ENDIAN */

};

/* Bits in yellowfin_desc.cmd */

enum desc_cmd_bits {

        CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,

        CMD_NOP=0x60000000, CMD_STOP=0x70000000,

        BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,

        BRANCH_IFTRUE=0x040000,

};

/* Bits in yellowfin_desc.status */

enum desc_status_bits { RX_EOP=0x0040, };

/* Bits in the interrupt status/mask registers. */

enum intr_status_bits {

        IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,

        IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,

        IntrEarlyRx=0x100, IntrWakeup=0x200, };

#define PRIV_ALIGN      31      /* Required alignment mask */

#define MII_CNT         4

struct yellowfin_private {

        /* Descriptor rings first for alignment.

           Tx requires a second descriptor for status. */

        struct yellowfin_desc *rx_ring;

        struct yellowfin_desc *tx_ring;

        struct sk_buff* rx_skbuff[RX_RING_SIZE];

        struct sk_buff* tx_skbuff[TX_RING_SIZE];

        dma_addr_t rx_ring_dma;

        dma_addr_t tx_ring_dma;

        struct tx_status_words *tx_status;

        dma_addr_t tx_status_dma;

        struct timer_list timer;        /* Media selection timer. */

        /* Frequently used and paired value: keep adjacent for cache effect. */

        int chip_id, drv_flags;

        struct pci_dev *pci_dev;

        unsigned int cur_rx, dirty_rx;          /* Producer/consumer ring indices */

        unsigned int rx_buf_sz;                         /* Based on MTU+slack. */

        struct tx_status_words *tx_tail_desc;

        unsigned int cur_tx, dirty_tx;

        int tx_threshold;

        unsigned int tx_full:1;                         /* The Tx queue is full. */

        unsigned int full_duplex:1;                     /* Full-duplex operation requested. */

        unsigned int duplex_lock:1;

        unsigned int medialock:1;                       /* Do not sense media. */

        unsigned int default_port:4;            /* Last dev->if_port value. */

        /* MII transceiver section. */

        int mii_cnt;                                            /* MII device addresses. */

        u16 advertising;                                        /* NWay media advertisement */

        unsigned char phys[MII_CNT];            /* MII device addresses, only first one used */

        spinlock_t lock;

        void __iomem *base;

};

static int read_eeprom(void __iomem *ioaddr, int location);

static int mdio_read(void __iomem *ioaddr, int phy_id, int location);

static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);

static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

static int yellowfin_open(struct net_device *dev);

static void yellowfin_timer(unsigned long data);

static void yellowfin_tx_timeout(struct net_device *dev);

static void yellowfin_init_ring(struct net_device *dev);

static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);

static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);

static int yellowfin_rx(struct net_device *dev);

static void yellowfin_error(struct net_device *dev, int intr_status);

static int yellowfin_close(struct net_device *dev);

static void set_rx_mode(struct net_device *dev);

static const struct ethtool_ops ethtool_ops;

static int __devinit yellowfin_init_one(struct pci_dev *pdev,

                                        const struct pci_device_id *ent)

{

        struct net_device *dev;

        struct yellowfin_private *np;

        int irq;

        int chip_idx = ent->driver_data;

        static int find_cnt;

        void __iomem *ioaddr;

        int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;

        int drv_flags = pci_id_tbl[chip_idx].drv_flags;

        void *ring_space;

        dma_addr_t ring_dma;

#ifdef USE_IO_OPS

        int bar = 0;

#else

        int bar = 1;

#endif

        DECLARE_MAC_BUF(mac);

/* when built into the kernel, we only print version if device is found */

#ifndef MODULE

        static int printed_version;

        if (!printed_version++)

                printk(version);

#endif

        i = pci_enable_device(pdev);

        if (i) return i;

        dev = alloc_etherdev(sizeof(*np));

        if (!dev) {

                printk (KERN_ERR PFX "cannot allocate ethernet device\n");

                return -ENOMEM;

        }

        SET_NETDEV_DEV(dev, &pdev->dev);

        np = netdev_priv(dev);

        if (pci_request_regions(pdev, DRV_NAME))

                goto err_out_free_netdev;

        pci_set_master (pdev);

        ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);

        if (!ioaddr)

                goto err_out_free_res;

        irq = pdev->irq;

        if (drv_flags & DontUseEeprom)

                for (i = 0; i < 6; i++)

                        dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);

        else {

                int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);

                for (i = 0; i < 6; i++)

                        dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);

        }

        /* Reset the chip. */

        iowrite32(0x80000000, ioaddr + DMACtrl);

        dev->base_addr = (unsigned long)ioaddr;

        dev->irq = irq;

        pci_set_drvdata(pdev, dev);

        spin_lock_init(&np->lock);

        np->pci_dev = pdev;

        np->chip_id = chip_idx;

        np->drv_flags = drv_flags;

        np->base = ioaddr;

        ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);

        if (!ring_space)

                goto err_out_cleardev;

        np->tx_ring = (struct yellowfin_desc *)ring_space;

        np->tx_ring_dma = ring_dma;

        ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);

        if (!ring_space)

                goto err_out_unmap_tx;

        np->rx_ring = (struct yellowfin_desc *)ring_space;

        np->rx_ring_dma = ring_dma;

        ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);

        if (!ring_space)

                goto err_out_unmap_rx;

        np->tx_status = (struct tx_status_words *)ring_space;

        np->tx_status_dma = ring_dma;

        if (dev->mem_start)

                option = dev->mem_start;

        /* The lower four bits are the media type. */

        if (option > 0) {

                if (option & 0x200)

                        np->full_duplex = 1;

                np->default_port = option & 15;

                if (np->default_port)

                        np->medialock = 1;

        }

        if (find_cnt < MAX_UNITS  &&  full_duplex[find_cnt] > 0)

                np->full_duplex = 1;

        if (np->full_duplex)

                np->duplex_lock = 1;

        /* The Yellowfin-specific entries in the device structure. */

        dev->open = &yellowfin_open;

        dev->hard_start_xmit = &yellowfin_start_xmit;

        dev->stop = &yellowfin_close;

        dev->set_multicast_list = &set_rx_mode;

        dev->do_ioctl = &netdev_ioctl;

        SET_ETHTOOL_OPS(dev, &ethtool_ops);

        dev->tx_timeout = yellowfin_tx_timeout;

        dev->watchdog_timeo = TX_TIMEOUT;

        if (mtu)

                dev->mtu = mtu;

        i = register_netdev(dev);

        if (i)

                goto err_out_unmap_status;

        printk(KERN_INFO "%s: %s type %8x at %p, %s, IRQ %d.\n",

                   dev->name, pci_id_tbl[chip_idx].name,

                   ioread32(ioaddr + ChipRev), ioaddr,

                   print_mac(mac, dev->dev_addr), irq);

        if (np->drv_flags & HasMII) {

                int phy, phy_idx = 0;

                for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {

                        int mii_status = mdio_read(ioaddr, phy, 1);

                        if (mii_status != 0xffff  &&  mii_status != 0x0000) {

                                np->phys[phy_idx++] = phy;

                                np->advertising = mdio_read(ioaddr, phy, 4);

                                printk(KERN_INFO "%s: MII PHY found at address %d, status "

                                           "0x%4.4x advertising %4.4x.\n",

                                           dev->name, phy, mii_status, np->advertising);

                        }

                }

                np->mii_cnt = phy_idx;

        }

        find_cnt++;

        return 0;

err_out_unmap_status:

        pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,

                np->tx_status_dma);

err_out_unmap_rx:

        pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);

err_out_unmap_tx:

        pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);

err_out_cleardev:

        pci_set_drvdata(pdev, NULL);

        pci_iounmap(pdev, ioaddr);

err_out_free_res:

        pci_release_regions(pdev);

err_out_free_netdev:

        free_netdev (dev);

        return -ENODEV;

}

static int __devinit read_eeprom(void __iomem *ioaddr, int location)

{

        int bogus_cnt = 10000;          /* Typical 33Mhz: 1050 ticks */

        iowrite8(location, ioaddr + EEAddr);

        iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);

        while ((ioread8(ioaddr + EEStatus) & 0x80)  &&  --bogus_cnt > 0)

                ;

        return ioread8(ioaddr + EERead);

}

/* MII Managemen Data I/O accesses.

   These routines assume the MDIO controller is idle, and do not exit until

   the command is finished. */

static int mdio_read(void __iomem *ioaddr, int phy_id, int location)

{

        int i;

        iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);

        iowrite16(1, ioaddr + MII_Cmd);

        for (i = 10000; i >= 0; i--)

                if ((ioread16(ioaddr + MII_Status) & 1) == 0)

                        break;

        return ioread16(ioaddr + MII_Rd_Data);

}

static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)

{

        int i;

        iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);

        iowrite16(value, ioaddr + MII_Wr_Data);

        /* Wait for the command to finish. */

        for (i = 10000; i >= 0; i--)

                if ((ioread16(ioaddr + MII_Status) & 1) == 0)

                        break;

        return;

}

static int yellowfin_open(struct net_device *dev)

{

        struct yellowfin_private *yp = netdev_priv(dev);

        void __iomem *ioaddr = yp->base;

        int i;

        /* Reset the chip. */

        iowrite32(0x80000000, ioaddr + DMACtrl);

        i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);

        if (i) return i;

        if (yellowfin_debug > 1)

                printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",

                           dev->name, dev->irq);

        yellowfin_init_ring(dev);

        iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);

        iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);

        for (i = 0; i < 6; i++)

                iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);

        /* Set up various condition 'select' registers.

           There are no options here. */

        iowrite32(0x00800080, ioaddr + TxIntrSel);      /* Interrupt on Tx abort */

        iowrite32(0x00800080, ioaddr + TxBranchSel);    /* Branch on Tx abort */

        iowrite32(0x00400040, ioaddr + TxWaitSel);      /* Wait on Tx status */

        iowrite32(0x00400040, ioaddr + RxIntrSel);      /* Interrupt on Rx done */

        iowrite32(0x00400040, ioaddr + RxBranchSel);    /* Branch on Rx error */

        iowrite32(0x00400040, ioaddr + RxWaitSel);      /* Wait on Rx done */

        /* Initialize other registers: with so many this eventually this will

           converted to an offset/value list. */

        iowrite32(dma_ctrl, ioaddr + DMACtrl);

        iowrite16(fifo_cfg, ioaddr + FIFOcfg);

        /* Enable automatic generation of flow control frames, period 0xffff. */

        iowrite32(0x0030FFFF, ioaddr + FlowCtrl);

        yp->tx_threshold = 32;

        iowrite32(yp->tx_threshold, ioaddr + TxThreshold);

        if (dev->if_port == 0)

                dev->if_port = yp->default_port;

        netif_start_queue(dev);

        /* Setting the Rx mode will start the Rx process. */

        if (yp->drv_flags & IsGigabit) {

                /* We are always in full-duplex mode with gigabit! */

                yp->full_duplex = 1;

                iowrite16(0x01CF, ioaddr + Cnfg);

        } else {

                iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */

                iowrite16(0x1018, ioaddr + FrameGap1);

                iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);

        }

        set_rx_mode(dev);

        /* Enable interrupts by setting the interrupt mask. */

        iowrite16(0x81ff, ioaddr + IntrEnb);                    /* See enum intr_status_bits */

        iowrite16(0x0000, ioaddr + EventStatus);                /* Clear non-interrupting events */

        iowrite32(0x80008000, ioaddr + RxCtrl);         /* Start Rx and Tx channels. */

        iowrite32(0x80008000, ioaddr + TxCtrl);

        if (yellowfin_debug > 2) {

                printk(KERN_DEBUG "%s: Done yellowfin_open().\n",

                           dev->name);

        }

        /* Set the timer to check for link beat. */

        init_timer(&yp->timer);

        yp->timer.expires = jiffies + 3*HZ;

        yp->timer.data = (unsigned long)dev;

        yp->timer.function = &yellowfin_timer;                          /* timer handler */

        add_timer(&yp->timer);

        return 0;

}

static void yellowfin_timer(unsigned long data)

{

        struct net_device *dev = (struct net_device *)data;

        struct yellowfin_private *yp = netdev_priv(dev);

        void __iomem *ioaddr = yp->base;

        int next_tick = 60*HZ;

        if (yellowfin_debug > 3) {

                printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",

                           dev->name, ioread16(ioaddr + IntrStatus));