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marcus.erl |
/*
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* cpcihp_zt5550.h
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*
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* Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions
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*
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* Copyright 2002 SOMA Networks, Inc.
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* Copyright 2001 Intel San Luis Obispo
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* Copyright 2000,2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <scottm@somanetworks.com>
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*/
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#ifndef _CPCIHP_ZT5550_H
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#define _CPCIHP_ZT5550_H
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/* Direct registers */
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#define CSR_HCINDEX 0x00
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#define CSR_HCDATA 0x04
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#define CSR_INTSTAT 0x08
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#define CSR_INTMASK 0x09
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#define CSR_CNT0CMD 0x0C
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#define CSR_CNT1CMD 0x0E
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#define CSR_CNT0 0x10
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#define CSR_CNT1 0x14
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/* Masks for interrupt bits in CSR_INTMASK direct register */
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#define CNT0_INT_MASK 0x01
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#define CNT1_INT_MASK 0x02
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#define ENUM_INT_MASK 0x04
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#define ALL_DIRECT_INTS_MASK 0x07
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/* Indexed registers (through CSR_INDEX, CSR_DATA) */
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#define HC_INT_MASK_REG 0x04
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#define HC_STATUS_REG 0x08
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#define HC_CMD_REG 0x0C
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#define ARB_CONFIG_GNT_REG 0x10
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#define ARB_CONFIG_CFG_REG 0x12
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#define ARB_CONFIG_REG 0x10
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#define ISOL_CONFIG_REG 0x18
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#define FAULT_STATUS_REG 0x20
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#define FAULT_CONFIG_REG 0x24
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#define WD_CONFIG_REG 0x2C
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#define HC_DIAG_REG 0x30
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#define SERIAL_COMM_REG 0x34
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#define SERIAL_OUT_REG 0x38
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#define SERIAL_IN_REG 0x3C
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/* Masks for interrupt bits in HC_INT_MASK_REG indexed register */
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#define SERIAL_INT_MASK 0x01
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#define FAULT_INT_MASK 0x02
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#define HCF_INT_MASK 0x04
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#define ALL_INDEXED_INTS_MASK 0x07
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/* Digital I/O port storing ENUM# */
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#define ENUM_PORT 0xE1
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/* Mask to get to the ENUM# bit on the bus */
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#define ENUM_MASK 0x40
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#endif /* _CPCIHP_ZT5550_H */
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