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marcus.erl |
/*
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* linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
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* with ICS 5342 dac (it is easy to add support for different dacs).
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*
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* Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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* Code is based on s3fb
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*/
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/svga.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
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#include <video/vga.h>
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#ifdef CONFIG_MTRR
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#include <asm/mtrr.h>
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#endif
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struct arkfb_info {
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int mclk_freq;
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int mtrr_reg;
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struct dac_info *dac;
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struct vgastate state;
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struct mutex open_lock;
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unsigned int ref_count;
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u32 pseudo_palette[16];
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};
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/* ------------------------------------------------------------------------- */
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static const struct svga_fb_format arkfb_formats[] = {
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{ 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
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FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
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{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
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{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
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FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
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{ 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
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{16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
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{16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
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{24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
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{32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
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FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
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SVGA_FORMAT_END
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};
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/* CRT timing register sets */
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static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
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static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
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static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
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static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
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static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
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static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
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static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
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static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
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static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
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// const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
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static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
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static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
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static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
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static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
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static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
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static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
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static const struct svga_timing_regs ark_timing_regs = {
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ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
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ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
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ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
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ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
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};
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/* ------------------------------------------------------------------------- */
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/* Module parameters */
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static char *mode = "640x480-8@60";
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#ifdef CONFIG_MTRR
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static int mtrr = 1;
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#endif
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MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
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module_param(mode, charp, 0444);
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MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
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#ifdef CONFIG_MTRR
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module_param(mtrr, int, 0444);
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MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
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#endif
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static int threshold = 4;
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module_param(threshold, int, 0644);
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MODULE_PARM_DESC(threshold, "FIFO threshold");
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/* ------------------------------------------------------------------------- */
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static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
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{
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const u8 *font = map->data;
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u8 __iomem *fb = (u8 __iomem *)info->screen_base;
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int i, c;
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if ((map->width != 8) || (map->height != 16) ||
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(map->depth != 1) || (map->length != 256)) {
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printk(KERN_ERR "fb%d: unsupported font parameters: width %d, "
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"height %d, depth %d, length %d\n", info->node,
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map->width, map->height, map->depth, map->length);
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return;
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}
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fb += 2;
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for (c = 0; c < map->length; c++) {
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for (i = 0; i < map->height; i++) {
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fb_writeb(font[i], &fb[i * 4]);
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fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
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}
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fb += 128;
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if ((c % 8) == 7)
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fb += 128*8;
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font += map->height;
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}
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}
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static struct fb_tile_ops arkfb_tile_ops = {
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.fb_settile = arkfb_settile,
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.fb_tilecopy = svga_tilecopy,
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.fb_tilefill = svga_tilefill,
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.fb_tileblit = svga_tileblit,
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.fb_tilecursor = svga_tilecursor,
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.fb_get_tilemax = svga_get_tilemax,
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};
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/* ------------------------------------------------------------------------- */
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/* image data is MSB-first, fb structure is MSB-first too */
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static inline u32 expand_color(u32 c)
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{
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return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
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}
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/* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
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static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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u32 fg = expand_color(image->fg_color);
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u32 bg = expand_color(image->bg_color);
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const u8 *src1, *src;
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u8 __iomem *dst1;
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u32 __iomem *dst;
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u32 val;
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int x, y;
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src1 = image->data;
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dst1 = info->screen_base + (image->dy * info->fix.line_length)
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+ ((image->dx / 8) * 4);
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for (y = 0; y < image->height; y++) {
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src = src1;
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dst = (u32 __iomem *) dst1;
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for (x = 0; x < image->width; x += 8) {
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val = *(src++) * 0x01010101;
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val = (val & fg) | (~val & bg);
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fb_writel(val, dst++);
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}
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src1 += image->width / 8;
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dst1 += info->fix.line_length;
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}
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}
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/* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
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static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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u32 fg = expand_color(rect->color);
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u8 __iomem *dst1;
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u32 __iomem *dst;
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int x, y;
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dst1 = info->screen_base + (rect->dy * info->fix.line_length)
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+ ((rect->dx / 8) * 4);
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for (y = 0; y < rect->height; y++) {
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dst = (u32 __iomem *) dst1;
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for (x = 0; x < rect->width; x += 8) {
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fb_writel(fg, dst++);
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}
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dst1 += info->fix.line_length;
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}
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}
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/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
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static inline u32 expand_pixel(u32 c)
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{
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return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
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((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
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}
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/* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
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static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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u32 fg = image->fg_color * 0x11111111;
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u32 bg = image->bg_color * 0x11111111;
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const u8 *src1, *src;
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u8 __iomem *dst1;
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u32 __iomem *dst;
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u32 val;
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int x, y;
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src1 = image->data;
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dst1 = info->screen_base + (image->dy * info->fix.line_length)
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+ ((image->dx / 8) * 4);
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for (y = 0; y < image->height; y++) {
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src = src1;
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dst = (u32 __iomem *) dst1;
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for (x = 0; x < image->width; x += 8) {
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val = expand_pixel(*(src++));
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val = (val & fg) | (~val & bg);
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fb_writel(val, dst++);
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}
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src1 += image->width / 8;
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dst1 += info->fix.line_length;
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}
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}
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static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
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&& ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
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if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
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arkfb_iplan_imageblit(info, image);
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else
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arkfb_cfb4_imageblit(info, image);
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} else
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cfb_imageblit(info, image);
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}
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277 |
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static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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if ((info->var.bits_per_pixel == 4)
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&& ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
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&& (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
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arkfb_iplan_fillrect(info, rect);
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else
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cfb_fillrect(info, rect);
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}
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288 |
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289 |
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/* ------------------------------------------------------------------------- */
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enum
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293 |
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{
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DAC_PSEUDO8_8,
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DAC_RGB1555_8,
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DAC_RGB0565_8,
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DAC_RGB0888_8,
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DAC_RGB8888_8,
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DAC_PSEUDO8_16,
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DAC_RGB1555_16,
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DAC_RGB0565_16,
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DAC_RGB0888_16,
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DAC_RGB8888_16,
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DAC_MAX
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};
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307 |
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struct dac_ops {
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308 |
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int (*dac_get_mode)(struct dac_info *info);
|
309 |
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int (*dac_set_mode)(struct dac_info *info, int mode);
|
310 |
|
|
int (*dac_get_freq)(struct dac_info *info, int channel);
|
311 |
|
|
int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
|
312 |
|
|
void (*dac_release)(struct dac_info *info);
|
313 |
|
|
};
|
314 |
|
|
|
315 |
|
|
typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
|
316 |
|
|
typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
|
317 |
|
|
|
318 |
|
|
struct dac_info
|
319 |
|
|
{
|
320 |
|
|
struct dac_ops *dacops;
|
321 |
|
|
dac_read_regs_t dac_read_regs;
|
322 |
|
|
dac_write_regs_t dac_write_regs;
|
323 |
|
|
void *data;
|
324 |
|
|
};
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
|
328 |
|
|
{
|
329 |
|
|
u8 code[2] = {reg, 0};
|
330 |
|
|
info->dac_read_regs(info->data, code, 1);
|
331 |
|
|
return code[1];
|
332 |
|
|
}
|
333 |
|
|
|
334 |
|
|
static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
|
335 |
|
|
{
|
336 |
|
|
info->dac_read_regs(info->data, code, count);
|
337 |
|
|
}
|
338 |
|
|
|
339 |
|
|
static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
|
340 |
|
|
{
|
341 |
|
|
u8 code[2] = {reg, val};
|
342 |
|
|
info->dac_write_regs(info->data, code, 1);
|
343 |
|
|
}
|
344 |
|
|
|
345 |
|
|
static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
|
346 |
|
|
{
|
347 |
|
|
info->dac_write_regs(info->data, code, count);
|
348 |
|
|
}
|
349 |
|
|
|
350 |
|
|
static inline int dac_set_mode(struct dac_info *info, int mode)
|
351 |
|
|
{
|
352 |
|
|
return info->dacops->dac_set_mode(info, mode);
|
353 |
|
|
}
|
354 |
|
|
|
355 |
|
|
static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
|
356 |
|
|
{
|
357 |
|
|
return info->dacops->dac_set_freq(info, channel, freq);
|
358 |
|
|
}
|
359 |
|
|
|
360 |
|
|
static inline void dac_release(struct dac_info *info)
|
361 |
|
|
{
|
362 |
|
|
info->dacops->dac_release(info);
|
363 |
|
|
}
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
/* ------------------------------------------------------------------------- */
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
/* ICS5342 DAC */
|
370 |
|
|
|
371 |
|
|
struct ics5342_info
|
372 |
|
|
{
|
373 |
|
|
struct dac_info dac;
|
374 |
|
|
u8 mode;
|
375 |
|
|
};
|
376 |
|
|
|
377 |
|
|
#define DAC_PAR(info) ((struct ics5342_info *) info)
|
378 |
|
|
|
379 |
|
|
/* LSB is set to distinguish unused slots */
|
380 |
|
|
static const u8 ics5342_mode_table[DAC_MAX] = {
|
381 |
|
|
[DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
|
382 |
|
|
[DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
|
383 |
|
|
[DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
|
384 |
|
|
};
|
385 |
|
|
|
386 |
|
|
static int ics5342_set_mode(struct dac_info *info, int mode)
|
387 |
|
|
{
|
388 |
|
|
u8 code;
|
389 |
|
|
|
390 |
|
|
if (mode >= DAC_MAX)
|
391 |
|
|
return -EINVAL;
|
392 |
|
|
|
393 |
|
|
code = ics5342_mode_table[mode];
|
394 |
|
|
|
395 |
|
|
if (! code)
|
396 |
|
|
return -EINVAL;
|
397 |
|
|
|
398 |
|
|
dac_write_reg(info, 6, code & 0xF0);
|
399 |
|
|
DAC_PAR(info)->mode = mode;
|
400 |
|
|
|
401 |
|
|
return 0;
|
402 |
|
|
}
|
403 |
|
|
|
404 |
|
|
static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
|
405 |
|
|
60000, 250000, 14318};
|
406 |
|
|
|
407 |
|
|
/* pd4 - allow only posdivider 4 (r=2) */
|
408 |
|
|
static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
|
409 |
|
|
60000, 335000, 14318};
|
410 |
|
|
|
411 |
|
|
/* 270 MHz should be upper bound for VCO clock according to specs,
|
412 |
|
|
but that is too restrictive in pd4 case */
|
413 |
|
|
|
414 |
|
|
static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
|
415 |
|
|
{
|
416 |
|
|
u16 m, n, r;
|
417 |
|
|
|
418 |
|
|
/* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
|
419 |
|
|
int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
|
420 |
|
|
? &ics5342_pll_pd4 : &ics5342_pll,
|
421 |
|
|
freq, &m, &n, &r, 0);
|
422 |
|
|
|
423 |
|
|
if (rv < 0) {
|
424 |
|
|
return -EINVAL;
|
425 |
|
|
} else {
|
426 |
|
|
u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
|
427 |
|
|
dac_write_regs(info, code, 3);
|
428 |
|
|
return 0;
|
429 |
|
|
}
|
430 |
|
|
}
|
431 |
|
|
|
432 |
|
|
static void ics5342_release(struct dac_info *info)
|
433 |
|
|
{
|
434 |
|
|
ics5342_set_mode(info, DAC_PSEUDO8_8);
|
435 |
|
|
kfree(info);
|
436 |
|
|
}
|
437 |
|
|
|
438 |
|
|
static struct dac_ops ics5342_ops = {
|
439 |
|
|
.dac_set_mode = ics5342_set_mode,
|
440 |
|
|
.dac_set_freq = ics5342_set_freq,
|
441 |
|
|
.dac_release = ics5342_release
|
442 |
|
|
};
|
443 |
|
|
|
444 |
|
|
|
445 |
|
|
static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
|
446 |
|
|
{
|
447 |
|
|
struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
|
448 |
|
|
|
449 |
|
|
if (! info)
|
450 |
|
|
return NULL;
|
451 |
|
|
|
452 |
|
|
info->dacops = &ics5342_ops;
|
453 |
|
|
info->dac_read_regs = drr;
|
454 |
|
|
info->dac_write_regs = dwr;
|
455 |
|
|
info->data = data;
|
456 |
|
|
DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
|
457 |
|
|
return info;
|
458 |
|
|
}
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
/* ------------------------------------------------------------------------- */
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
|
465 |
|
|
|
466 |
|
|
static void ark_dac_read_regs(void *data, u8 *code, int count)
|
467 |
|
|
{
|
468 |
|
|
u8 regval = vga_rseq(NULL, 0x1C);
|
469 |
|
|
|
470 |
|
|
while (count != 0)
|
471 |
|
|
{
|
472 |
|
|
vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
|
473 |
|
|
code[1] = vga_r(NULL, dac_regs[code[0] & 3]);
|
474 |
|
|
count--;
|
475 |
|
|
code += 2;
|
476 |
|
|
}
|
477 |
|
|
|
478 |
|
|
vga_wseq(NULL, 0x1C, regval);
|
479 |
|
|
}
|
480 |
|
|
|
481 |
|
|
static void ark_dac_write_regs(void *data, u8 *code, int count)
|
482 |
|
|
{
|
483 |
|
|
u8 regval = vga_rseq(NULL, 0x1C);
|
484 |
|
|
|
485 |
|
|
while (count != 0)
|
486 |
|
|
{
|
487 |
|
|
vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
|
488 |
|
|
vga_w(NULL, dac_regs[code[0] & 3], code[1]);
|
489 |
|
|
count--;
|
490 |
|
|
code += 2;
|
491 |
|
|
}
|
492 |
|
|
|
493 |
|
|
vga_wseq(NULL, 0x1C, regval);
|
494 |
|
|
}
|
495 |
|
|
|
496 |
|
|
|
497 |
|
|
static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
|
498 |
|
|
{
|
499 |
|
|
struct arkfb_info *par = info->par;
|
500 |
|
|
u8 regval;
|
501 |
|
|
|
502 |
|
|
int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
|
503 |
|
|
if (rv < 0) {
|
504 |
|
|
printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
|
505 |
|
|
return;
|
506 |
|
|
}
|
507 |
|
|
|
508 |
|
|
/* Set VGA misc register */
|
509 |
|
|
regval = vga_r(NULL, VGA_MIS_R);
|
510 |
|
|
vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
|
511 |
|
|
}
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
/* Open framebuffer */
|
515 |
|
|
|
516 |
|
|
static int arkfb_open(struct fb_info *info, int user)
|
517 |
|
|
{
|
518 |
|
|
struct arkfb_info *par = info->par;
|
519 |
|
|
|
520 |
|
|
mutex_lock(&(par->open_lock));
|
521 |
|
|
if (par->ref_count == 0) {
|
522 |
|
|
memset(&(par->state), 0, sizeof(struct vgastate));
|
523 |
|
|
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
|
524 |
|
|
par->state.num_crtc = 0x60;
|
525 |
|
|
par->state.num_seq = 0x30;
|
526 |
|
|
save_vga(&(par->state));
|
527 |
|
|
}
|
528 |
|
|
|
529 |
|
|
par->ref_count++;
|
530 |
|
|
mutex_unlock(&(par->open_lock));
|
531 |
|
|
|
532 |
|
|
return 0;
|
533 |
|
|
}
|
534 |
|
|
|
535 |
|
|
/* Close framebuffer */
|
536 |
|
|
|
537 |
|
|
static int arkfb_release(struct fb_info *info, int user)
|
538 |
|
|
{
|
539 |
|
|
struct arkfb_info *par = info->par;
|
540 |
|
|
|
541 |
|
|
mutex_lock(&(par->open_lock));
|
542 |
|
|
if (par->ref_count == 0) {
|
543 |
|
|
mutex_unlock(&(par->open_lock));
|
544 |
|
|
return -EINVAL;
|
545 |
|
|
}
|
546 |
|
|
|
547 |
|
|
if (par->ref_count == 1) {
|
548 |
|
|
restore_vga(&(par->state));
|
549 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_8);
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
par->ref_count--;
|
553 |
|
|
mutex_unlock(&(par->open_lock));
|
554 |
|
|
|
555 |
|
|
return 0;
|
556 |
|
|
}
|
557 |
|
|
|
558 |
|
|
/* Validate passed in var */
|
559 |
|
|
|
560 |
|
|
static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
|
561 |
|
|
{
|
562 |
|
|
int rv, mem, step;
|
563 |
|
|
|
564 |
|
|
/* Find appropriate format */
|
565 |
|
|
rv = svga_match_format (arkfb_formats, var, NULL);
|
566 |
|
|
if (rv < 0)
|
567 |
|
|
{
|
568 |
|
|
printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
|
569 |
|
|
return rv;
|
570 |
|
|
}
|
571 |
|
|
|
572 |
|
|
/* Do not allow to have real resoulution larger than virtual */
|
573 |
|
|
if (var->xres > var->xres_virtual)
|
574 |
|
|
var->xres_virtual = var->xres;
|
575 |
|
|
|
576 |
|
|
if (var->yres > var->yres_virtual)
|
577 |
|
|
var->yres_virtual = var->yres;
|
578 |
|
|
|
579 |
|
|
/* Round up xres_virtual to have proper alignment of lines */
|
580 |
|
|
step = arkfb_formats[rv].xresstep - 1;
|
581 |
|
|
var->xres_virtual = (var->xres_virtual+step) & ~step;
|
582 |
|
|
|
583 |
|
|
|
584 |
|
|
/* Check whether have enough memory */
|
585 |
|
|
mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
|
586 |
|
|
if (mem > info->screen_size)
|
587 |
|
|
{
|
588 |
|
|
printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
|
589 |
|
|
return -EINVAL;
|
590 |
|
|
}
|
591 |
|
|
|
592 |
|
|
rv = svga_check_timings (&ark_timing_regs, var, info->node);
|
593 |
|
|
if (rv < 0)
|
594 |
|
|
{
|
595 |
|
|
printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
|
596 |
|
|
return rv;
|
597 |
|
|
}
|
598 |
|
|
|
599 |
|
|
/* Interlaced mode is broken */
|
600 |
|
|
if (var->vmode & FB_VMODE_INTERLACED)
|
601 |
|
|
return -EINVAL;
|
602 |
|
|
|
603 |
|
|
return 0;
|
604 |
|
|
}
|
605 |
|
|
|
606 |
|
|
/* Set video mode from par */
|
607 |
|
|
|
608 |
|
|
static int arkfb_set_par(struct fb_info *info)
|
609 |
|
|
{
|
610 |
|
|
struct arkfb_info *par = info->par;
|
611 |
|
|
u32 value, mode, hmul, hdiv, offset_value, screen_size;
|
612 |
|
|
u32 bpp = info->var.bits_per_pixel;
|
613 |
|
|
u8 regval;
|
614 |
|
|
|
615 |
|
|
if (bpp != 0) {
|
616 |
|
|
info->fix.ypanstep = 1;
|
617 |
|
|
info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
|
618 |
|
|
|
619 |
|
|
info->flags &= ~FBINFO_MISC_TILEBLITTING;
|
620 |
|
|
info->tileops = NULL;
|
621 |
|
|
|
622 |
|
|
/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
|
623 |
|
|
info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
|
624 |
|
|
info->pixmap.blit_y = ~(u32)0;
|
625 |
|
|
|
626 |
|
|
offset_value = (info->var.xres_virtual * bpp) / 64;
|
627 |
|
|
screen_size = info->var.yres_virtual * info->fix.line_length;
|
628 |
|
|
} else {
|
629 |
|
|
info->fix.ypanstep = 16;
|
630 |
|
|
info->fix.line_length = 0;
|
631 |
|
|
|
632 |
|
|
info->flags |= FBINFO_MISC_TILEBLITTING;
|
633 |
|
|
info->tileops = &arkfb_tile_ops;
|
634 |
|
|
|
635 |
|
|
/* supports 8x16 tiles only */
|
636 |
|
|
info->pixmap.blit_x = 1 << (8 - 1);
|
637 |
|
|
info->pixmap.blit_y = 1 << (16 - 1);
|
638 |
|
|
|
639 |
|
|
offset_value = info->var.xres_virtual / 16;
|
640 |
|
|
screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
|
641 |
|
|
}
|
642 |
|
|
|
643 |
|
|
info->var.xoffset = 0;
|
644 |
|
|
info->var.yoffset = 0;
|
645 |
|
|
info->var.activate = FB_ACTIVATE_NOW;
|
646 |
|
|
|
647 |
|
|
/* Unlock registers */
|
648 |
|
|
svga_wcrt_mask(0x11, 0x00, 0x80);
|
649 |
|
|
|
650 |
|
|
/* Blank screen and turn off sync */
|
651 |
|
|
svga_wseq_mask(0x01, 0x20, 0x20);
|
652 |
|
|
svga_wcrt_mask(0x17, 0x00, 0x80);
|
653 |
|
|
|
654 |
|
|
/* Set default values */
|
655 |
|
|
svga_set_default_gfx_regs();
|
656 |
|
|
svga_set_default_atc_regs();
|
657 |
|
|
svga_set_default_seq_regs();
|
658 |
|
|
svga_set_default_crt_regs();
|
659 |
|
|
svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF);
|
660 |
|
|
svga_wcrt_multi(ark_start_address_regs, 0);
|
661 |
|
|
|
662 |
|
|
/* ARK specific initialization */
|
663 |
|
|
svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
|
664 |
|
|
svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
|
665 |
|
|
|
666 |
|
|
vga_wseq(NULL, 0x13, info->fix.smem_start >> 16);
|
667 |
|
|
vga_wseq(NULL, 0x14, info->fix.smem_start >> 24);
|
668 |
|
|
vga_wseq(NULL, 0x15, 0);
|
669 |
|
|
vga_wseq(NULL, 0x16, 0);
|
670 |
|
|
|
671 |
|
|
/* Set the FIFO threshold register */
|
672 |
|
|
/* It is fascinating way to store 5-bit value in 8-bit register */
|
673 |
|
|
regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
|
674 |
|
|
vga_wseq(NULL, 0x18, regval);
|
675 |
|
|
|
676 |
|
|
/* Set the offset register */
|
677 |
|
|
pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
|
678 |
|
|
svga_wcrt_multi(ark_offset_regs, offset_value);
|
679 |
|
|
|
680 |
|
|
/* fix for hi-res textmode */
|
681 |
|
|
svga_wcrt_mask(0x40, 0x08, 0x08);
|
682 |
|
|
|
683 |
|
|
if (info->var.vmode & FB_VMODE_DOUBLE)
|
684 |
|
|
svga_wcrt_mask(0x09, 0x80, 0x80);
|
685 |
|
|
else
|
686 |
|
|
svga_wcrt_mask(0x09, 0x00, 0x80);
|
687 |
|
|
|
688 |
|
|
if (info->var.vmode & FB_VMODE_INTERLACED)
|
689 |
|
|
svga_wcrt_mask(0x44, 0x04, 0x04);
|
690 |
|
|
else
|
691 |
|
|
svga_wcrt_mask(0x44, 0x00, 0x04);
|
692 |
|
|
|
693 |
|
|
hmul = 1;
|
694 |
|
|
hdiv = 1;
|
695 |
|
|
mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
|
696 |
|
|
|
697 |
|
|
/* Set mode-specific register values */
|
698 |
|
|
switch (mode) {
|
699 |
|
|
case 0:
|
700 |
|
|
pr_debug("fb%d: text mode\n", info->node);
|
701 |
|
|
svga_set_textmode_vga_regs();
|
702 |
|
|
|
703 |
|
|
vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
|
704 |
|
|
svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
|
705 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_8);
|
706 |
|
|
|
707 |
|
|
break;
|
708 |
|
|
case 1:
|
709 |
|
|
pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
|
710 |
|
|
vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
|
711 |
|
|
|
712 |
|
|
vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
|
713 |
|
|
svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
|
714 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_8);
|
715 |
|
|
break;
|
716 |
|
|
case 2:
|
717 |
|
|
pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
|
718 |
|
|
|
719 |
|
|
vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
|
720 |
|
|
svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
|
721 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_8);
|
722 |
|
|
break;
|
723 |
|
|
case 3:
|
724 |
|
|
pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
|
725 |
|
|
|
726 |
|
|
vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */
|
727 |
|
|
|
728 |
|
|
if (info->var.pixclock > 20000) {
|
729 |
|
|
pr_debug("fb%d: not using multiplex\n", info->node);
|
730 |
|
|
svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
|
731 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_8);
|
732 |
|
|
} else {
|
733 |
|
|
pr_debug("fb%d: using multiplex\n", info->node);
|
734 |
|
|
svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
|
735 |
|
|
dac_set_mode(par->dac, DAC_PSEUDO8_16);
|
736 |
|
|
hdiv = 2;
|
737 |
|
|
}
|
738 |
|
|
break;
|
739 |
|
|
case 4:
|
740 |
|
|
pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
|
741 |
|
|
|
742 |
|
|
vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
|
743 |
|
|
svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
|
744 |
|
|
dac_set_mode(par->dac, DAC_RGB1555_16);
|
745 |
|
|
break;
|
746 |
|
|
case 5:
|
747 |
|
|
pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
|
748 |
|
|
|
749 |
|
|
vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
|
750 |
|
|
svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
|
751 |
|
|
dac_set_mode(par->dac, DAC_RGB0565_16);
|
752 |
|
|
break;
|
753 |
|
|
case 6:
|
754 |
|
|
pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
|
755 |
|
|
|
756 |
|
|
vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */
|
757 |
|
|
svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
|
758 |
|
|
dac_set_mode(par->dac, DAC_RGB0888_16);
|
759 |
|
|
hmul = 3;
|
760 |
|
|
hdiv = 2;
|
761 |
|
|
break;
|
762 |
|
|
case 7:
|
763 |
|
|
pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
|
764 |
|
|
|
765 |
|
|
vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */
|
766 |
|
|
svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
|
767 |
|
|
dac_set_mode(par->dac, DAC_RGB8888_16);
|
768 |
|
|
hmul = 2;
|
769 |
|
|
break;
|
770 |
|
|
default:
|
771 |
|
|
printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
|
772 |
|
|
return -EINVAL;
|
773 |
|
|
}
|
774 |
|
|
|
775 |
|
|
ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
|
776 |
|
|
svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv,
|
777 |
|
|
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
|
778 |
|
|
(info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
|
779 |
|
|
hmul, info->node);
|
780 |
|
|
|
781 |
|
|
/* Set interlaced mode start/end register */
|
782 |
|
|
value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
|
783 |
|
|
value = ((value * hmul / hdiv) / 8) - 5;
|
784 |
|
|
vga_wcrt(NULL, 0x42, (value + 1) / 2);
|
785 |
|
|
|
786 |
|
|
memset_io(info->screen_base, 0x00, screen_size);
|
787 |
|
|
/* Device and screen back on */
|
788 |
|
|
svga_wcrt_mask(0x17, 0x80, 0x80);
|
789 |
|
|
svga_wseq_mask(0x01, 0x00, 0x20);
|
790 |
|
|
|
791 |
|
|
return 0;
|
792 |
|
|
}
|
793 |
|
|
|
794 |
|
|
/* Set a colour register */
|
795 |
|
|
|
796 |
|
|
static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
|
797 |
|
|
u_int transp, struct fb_info *fb)
|
798 |
|
|
{
|
799 |
|
|
switch (fb->var.bits_per_pixel) {
|
800 |
|
|
case 0:
|
801 |
|
|
case 4:
|
802 |
|
|
if (regno >= 16)
|
803 |
|
|
return -EINVAL;
|
804 |
|
|
|
805 |
|
|
if ((fb->var.bits_per_pixel == 4) &&
|
806 |
|
|
(fb->var.nonstd == 0)) {
|
807 |
|
|
outb(0xF0, VGA_PEL_MSK);
|
808 |
|
|
outb(regno*16, VGA_PEL_IW);
|
809 |
|
|
} else {
|
810 |
|
|
outb(0x0F, VGA_PEL_MSK);
|
811 |
|
|
outb(regno, VGA_PEL_IW);
|
812 |
|
|
}
|
813 |
|
|
outb(red >> 10, VGA_PEL_D);
|
814 |
|
|
outb(green >> 10, VGA_PEL_D);
|
815 |
|
|
outb(blue >> 10, VGA_PEL_D);
|
816 |
|
|
break;
|
817 |
|
|
case 8:
|
818 |
|
|
if (regno >= 256)
|
819 |
|
|
return -EINVAL;
|
820 |
|
|
|
821 |
|
|
outb(0xFF, VGA_PEL_MSK);
|
822 |
|
|
outb(regno, VGA_PEL_IW);
|
823 |
|
|
outb(red >> 10, VGA_PEL_D);
|
824 |
|
|
outb(green >> 10, VGA_PEL_D);
|
825 |
|
|
outb(blue >> 10, VGA_PEL_D);
|
826 |
|
|
break;
|
827 |
|
|
case 16:
|
828 |
|
|
if (regno >= 16)
|
829 |
|
|
return 0;
|
830 |
|
|
|
831 |
|
|
if (fb->var.green.length == 5)
|
832 |
|
|
((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
|
833 |
|
|
((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
|
834 |
|
|
else if (fb->var.green.length == 6)
|
835 |
|
|
((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
|
836 |
|
|
((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
|
837 |
|
|
else
|
838 |
|
|
return -EINVAL;
|
839 |
|
|
break;
|
840 |
|
|
case 24:
|
841 |
|
|
case 32:
|
842 |
|
|
if (regno >= 16)
|
843 |
|
|
return 0;
|
844 |
|
|
|
845 |
|
|
((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
|
846 |
|
|
(green & 0xFF00) | ((blue & 0xFF00) >> 8);
|
847 |
|
|
break;
|
848 |
|
|
default:
|
849 |
|
|
return -EINVAL;
|
850 |
|
|
}
|
851 |
|
|
|
852 |
|
|
return 0;
|
853 |
|
|
}
|
854 |
|
|
|
855 |
|
|
/* Set the display blanking state */
|
856 |
|
|
|
857 |
|
|
static int arkfb_blank(int blank_mode, struct fb_info *info)
|
858 |
|
|
{
|
859 |
|
|
switch (blank_mode) {
|
860 |
|
|
case FB_BLANK_UNBLANK:
|
861 |
|
|
pr_debug("fb%d: unblank\n", info->node);
|
862 |
|
|
svga_wseq_mask(0x01, 0x00, 0x20);
|
863 |
|
|
svga_wcrt_mask(0x17, 0x80, 0x80);
|
864 |
|
|
break;
|
865 |
|
|
case FB_BLANK_NORMAL:
|
866 |
|
|
pr_debug("fb%d: blank\n", info->node);
|
867 |
|
|
svga_wseq_mask(0x01, 0x20, 0x20);
|
868 |
|
|
svga_wcrt_mask(0x17, 0x80, 0x80);
|
869 |
|
|
break;
|
870 |
|
|
case FB_BLANK_POWERDOWN:
|
871 |
|
|
case FB_BLANK_HSYNC_SUSPEND:
|
872 |
|
|
case FB_BLANK_VSYNC_SUSPEND:
|
873 |
|
|
pr_debug("fb%d: sync down\n", info->node);
|
874 |
|
|
svga_wseq_mask(0x01, 0x20, 0x20);
|
875 |
|
|
svga_wcrt_mask(0x17, 0x00, 0x80);
|
876 |
|
|
break;
|
877 |
|
|
}
|
878 |
|
|
return 0;
|
879 |
|
|
}
|
880 |
|
|
|
881 |
|
|
|
882 |
|
|
/* Pan the display */
|
883 |
|
|
|
884 |
|
|
static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
|
885 |
|
|
{
|
886 |
|
|
unsigned int offset;
|
887 |
|
|
|
888 |
|
|
/* Calculate the offset */
|
889 |
|
|
if (var->bits_per_pixel == 0) {
|
890 |
|
|
offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
|
891 |
|
|
offset = offset >> 2;
|
892 |
|
|
} else {
|
893 |
|
|
offset = (var->yoffset * info->fix.line_length) +
|
894 |
|
|
(var->xoffset * var->bits_per_pixel / 8);
|
895 |
|
|
offset = offset >> ((var->bits_per_pixel == 4) ? 2 : 3);
|
896 |
|
|
}
|
897 |
|
|
|
898 |
|
|
/* Set the offset */
|
899 |
|
|
svga_wcrt_multi(ark_start_address_regs, offset);
|
900 |
|
|
|
901 |
|
|
return 0;
|
902 |
|
|
}
|
903 |
|
|
|
904 |
|
|
|
905 |
|
|
/* ------------------------------------------------------------------------- */
|
906 |
|
|
|
907 |
|
|
|
908 |
|
|
/* Frame buffer operations */
|
909 |
|
|
|
910 |
|
|
static struct fb_ops arkfb_ops = {
|
911 |
|
|
.owner = THIS_MODULE,
|
912 |
|
|
.fb_open = arkfb_open,
|
913 |
|
|
.fb_release = arkfb_release,
|
914 |
|
|
.fb_check_var = arkfb_check_var,
|
915 |
|
|
.fb_set_par = arkfb_set_par,
|
916 |
|
|
.fb_setcolreg = arkfb_setcolreg,
|
917 |
|
|
.fb_blank = arkfb_blank,
|
918 |
|
|
.fb_pan_display = arkfb_pan_display,
|
919 |
|
|
.fb_fillrect = arkfb_fillrect,
|
920 |
|
|
.fb_copyarea = cfb_copyarea,
|
921 |
|
|
.fb_imageblit = arkfb_imageblit,
|
922 |
|
|
.fb_get_caps = svga_get_caps,
|
923 |
|
|
};
|
924 |
|
|
|
925 |
|
|
|
926 |
|
|
/* ------------------------------------------------------------------------- */
|
927 |
|
|
|
928 |
|
|
|
929 |
|
|
/* PCI probe */
|
930 |
|
|
static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
931 |
|
|
{
|
932 |
|
|
struct fb_info *info;
|
933 |
|
|
struct arkfb_info *par;
|
934 |
|
|
int rc;
|
935 |
|
|
u8 regval;
|
936 |
|
|
|
937 |
|
|
/* Ignore secondary VGA device because there is no VGA arbitration */
|
938 |
|
|
if (! svga_primary_device(dev)) {
|
939 |
|
|
dev_info(&(dev->dev), "ignoring secondary device\n");
|
940 |
|
|
return -ENODEV;
|
941 |
|
|
}
|
942 |
|
|
|
943 |
|
|
/* Allocate and fill driver data structure */
|
944 |
|
|
info = framebuffer_alloc(sizeof(struct arkfb_info), NULL);
|
945 |
|
|
if (! info) {
|
946 |
|
|
dev_err(&(dev->dev), "cannot allocate memory\n");
|
947 |
|
|
return -ENOMEM;
|
948 |
|
|
}
|
949 |
|
|
|
950 |
|
|
par = info->par;
|
951 |
|
|
mutex_init(&par->open_lock);
|
952 |
|
|
|
953 |
|
|
info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
|
954 |
|
|
info->fbops = &arkfb_ops;
|
955 |
|
|
|
956 |
|
|
/* Prepare PCI device */
|
957 |
|
|
rc = pci_enable_device(dev);
|
958 |
|
|
if (rc < 0) {
|
959 |
|
|
dev_err(&(dev->dev), "cannot enable PCI device\n");
|
960 |
|
|
goto err_enable_device;
|
961 |
|
|
}
|
962 |
|
|
|
963 |
|
|
rc = pci_request_regions(dev, "arkfb");
|
964 |
|
|
if (rc < 0) {
|
965 |
|
|
dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
|
966 |
|
|
goto err_request_regions;
|
967 |
|
|
}
|
968 |
|
|
|
969 |
|
|
par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
|
970 |
|
|
if (! par->dac) {
|
971 |
|
|
rc = -ENOMEM;
|
972 |
|
|
dev_err(&(dev->dev), "RAMDAC initialization failed\n");
|
973 |
|
|
goto err_dac;
|
974 |
|
|
}
|
975 |
|
|
|
976 |
|
|
info->fix.smem_start = pci_resource_start(dev, 0);
|
977 |
|
|
info->fix.smem_len = pci_resource_len(dev, 0);
|
978 |
|
|
|
979 |
|
|
/* Map physical IO memory address into kernel space */
|
980 |
|
|
info->screen_base = pci_iomap(dev, 0, 0);
|
981 |
|
|
if (! info->screen_base) {
|
982 |
|
|
rc = -ENOMEM;
|
983 |
|
|
dev_err(&(dev->dev), "iomap for framebuffer failed\n");
|
984 |
|
|
goto err_iomap;
|
985 |
|
|
}
|
986 |
|
|
|
987 |
|
|
/* FIXME get memsize */
|
988 |
|
|
regval = vga_rseq(NULL, 0x10);
|
989 |
|
|
info->screen_size = (1 << (regval >> 6)) << 20;
|
990 |
|
|
info->fix.smem_len = info->screen_size;
|
991 |
|
|
|
992 |
|
|
strcpy(info->fix.id, "ARK 2000PV");
|
993 |
|
|
info->fix.mmio_start = 0;
|
994 |
|
|
info->fix.mmio_len = 0;
|
995 |
|
|
info->fix.type = FB_TYPE_PACKED_PIXELS;
|
996 |
|
|
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
|
997 |
|
|
info->fix.ypanstep = 0;
|
998 |
|
|
info->fix.accel = FB_ACCEL_NONE;
|
999 |
|
|
info->pseudo_palette = (void*) (par->pseudo_palette);
|
1000 |
|
|
|
1001 |
|
|
/* Prepare startup mode */
|
1002 |
|
|
rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
|
1003 |
|
|
if (! ((rc == 1) || (rc == 2))) {
|
1004 |
|
|
rc = -EINVAL;
|
1005 |
|
|
dev_err(&(dev->dev), "mode %s not found\n", mode);
|
1006 |
|
|
goto err_find_mode;
|
1007 |
|
|
}
|
1008 |
|
|
|
1009 |
|
|
rc = fb_alloc_cmap(&info->cmap, 256, 0);
|
1010 |
|
|
if (rc < 0) {
|
1011 |
|
|
dev_err(&(dev->dev), "cannot allocate colormap\n");
|
1012 |
|
|
goto err_alloc_cmap;
|
1013 |
|
|
}
|
1014 |
|
|
|
1015 |
|
|
rc = register_framebuffer(info);
|
1016 |
|
|
if (rc < 0) {
|
1017 |
|
|
dev_err(&(dev->dev), "cannot register framebugger\n");
|
1018 |
|
|
goto err_reg_fb;
|
1019 |
|
|
}
|
1020 |
|
|
|
1021 |
|
|
printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id,
|
1022 |
|
|
pci_name(dev), info->fix.smem_len >> 20);
|
1023 |
|
|
|
1024 |
|
|
/* Record a reference to the driver data */
|
1025 |
|
|
pci_set_drvdata(dev, info);
|
1026 |
|
|
|
1027 |
|
|
#ifdef CONFIG_MTRR
|
1028 |
|
|
if (mtrr) {
|
1029 |
|
|
par->mtrr_reg = -1;
|
1030 |
|
|
par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
|
1031 |
|
|
}
|
1032 |
|
|
#endif
|
1033 |
|
|
|
1034 |
|
|
return 0;
|
1035 |
|
|
|
1036 |
|
|
/* Error handling */
|
1037 |
|
|
err_reg_fb:
|
1038 |
|
|
fb_dealloc_cmap(&info->cmap);
|
1039 |
|
|
err_alloc_cmap:
|
1040 |
|
|
err_find_mode:
|
1041 |
|
|
pci_iounmap(dev, info->screen_base);
|
1042 |
|
|
err_iomap:
|
1043 |
|
|
dac_release(par->dac);
|
1044 |
|
|
err_dac:
|
1045 |
|
|
pci_release_regions(dev);
|
1046 |
|
|
err_request_regions:
|
1047 |
|
|
/* pci_disable_device(dev); */
|
1048 |
|
|
err_enable_device:
|
1049 |
|
|
framebuffer_release(info);
|
1050 |
|
|
return rc;
|
1051 |
|
|
}
|
1052 |
|
|
|
1053 |
|
|
/* PCI remove */
|
1054 |
|
|
|
1055 |
|
|
static void __devexit ark_pci_remove(struct pci_dev *dev)
|
1056 |
|
|
{
|
1057 |
|
|
struct fb_info *info = pci_get_drvdata(dev);
|
1058 |
|
|
|
1059 |
|
|
if (info) {
|
1060 |
|
|
struct arkfb_info *par = info->par;
|
1061 |
|
|
|
1062 |
|
|
#ifdef CONFIG_MTRR
|
1063 |
|
|
if (par->mtrr_reg >= 0) {
|
1064 |
|
|
mtrr_del(par->mtrr_reg, 0, 0);
|
1065 |
|
|
par->mtrr_reg = -1;
|
1066 |
|
|
}
|
1067 |
|
|
#endif
|
1068 |
|
|
|
1069 |
|
|
dac_release(par->dac);
|
1070 |
|
|
unregister_framebuffer(info);
|
1071 |
|
|
fb_dealloc_cmap(&info->cmap);
|
1072 |
|
|
|
1073 |
|
|
pci_iounmap(dev, info->screen_base);
|
1074 |
|
|
pci_release_regions(dev);
|
1075 |
|
|
/* pci_disable_device(dev); */
|
1076 |
|
|
|
1077 |
|
|
pci_set_drvdata(dev, NULL);
|
1078 |
|
|
framebuffer_release(info);
|
1079 |
|
|
}
|
1080 |
|
|
}
|
1081 |
|
|
|
1082 |
|
|
|
1083 |
|
|
#ifdef CONFIG_PM
|
1084 |
|
|
/* PCI suspend */
|
1085 |
|
|
|
1086 |
|
|
static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
|
1087 |
|
|
{
|
1088 |
|
|
struct fb_info *info = pci_get_drvdata(dev);
|
1089 |
|
|
struct arkfb_info *par = info->par;
|
1090 |
|
|
|
1091 |
|
|
dev_info(&(dev->dev), "suspend\n");
|
1092 |
|
|
|
1093 |
|
|
acquire_console_sem();
|
1094 |
|
|
mutex_lock(&(par->open_lock));
|
1095 |
|
|
|
1096 |
|
|
if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
|
1097 |
|
|
mutex_unlock(&(par->open_lock));
|
1098 |
|
|
release_console_sem();
|
1099 |
|
|
return 0;
|
1100 |
|
|
}
|
1101 |
|
|
|
1102 |
|
|
fb_set_suspend(info, 1);
|
1103 |
|
|
|
1104 |
|
|
pci_save_state(dev);
|
1105 |
|
|
pci_disable_device(dev);
|
1106 |
|
|
pci_set_power_state(dev, pci_choose_state(dev, state));
|
1107 |
|
|
|
1108 |
|
|
mutex_unlock(&(par->open_lock));
|
1109 |
|
|
release_console_sem();
|
1110 |
|
|
|
1111 |
|
|
return 0;
|
1112 |
|
|
}
|
1113 |
|
|
|
1114 |
|
|
|
1115 |
|
|
/* PCI resume */
|
1116 |
|
|
|
1117 |
|
|
static int ark_pci_resume (struct pci_dev* dev)
|
1118 |
|
|
{
|
1119 |
|
|
struct fb_info *info = pci_get_drvdata(dev);
|
1120 |
|
|
struct arkfb_info *par = info->par;
|
1121 |
|
|
|
1122 |
|
|
dev_info(&(dev->dev), "resume\n");
|
1123 |
|
|
|
1124 |
|
|
acquire_console_sem();
|
1125 |
|
|
mutex_lock(&(par->open_lock));
|
1126 |
|
|
|
1127 |
|
|
if (par->ref_count == 0) {
|
1128 |
|
|
mutex_unlock(&(par->open_lock));
|
1129 |
|
|
release_console_sem();
|
1130 |
|
|
return 0;
|
1131 |
|
|
}
|
1132 |
|
|
|
1133 |
|
|
pci_set_power_state(dev, PCI_D0);
|
1134 |
|
|
pci_restore_state(dev);
|
1135 |
|
|
|
1136 |
|
|
if (pci_enable_device(dev))
|
1137 |
|
|
goto fail;
|
1138 |
|
|
|
1139 |
|
|
pci_set_master(dev);
|
1140 |
|
|
|
1141 |
|
|
arkfb_set_par(info);
|
1142 |
|
|
fb_set_suspend(info, 0);
|
1143 |
|
|
|
1144 |
|
|
mutex_unlock(&(par->open_lock));
|
1145 |
|
|
fail:
|
1146 |
|
|
release_console_sem();
|
1147 |
|
|
return 0;
|
1148 |
|
|
}
|
1149 |
|
|
#else
|
1150 |
|
|
#define ark_pci_suspend NULL
|
1151 |
|
|
#define ark_pci_resume NULL
|
1152 |
|
|
#endif /* CONFIG_PM */
|
1153 |
|
|
|
1154 |
|
|
/* List of boards that we are trying to support */
|
1155 |
|
|
|
1156 |
|
|
static struct pci_device_id ark_devices[] __devinitdata = {
|
1157 |
|
|
{PCI_DEVICE(0xEDD8, 0xA099)},
|
1158 |
|
|
{0, 0, 0, 0, 0, 0, 0}
|
1159 |
|
|
};
|
1160 |
|
|
|
1161 |
|
|
|
1162 |
|
|
MODULE_DEVICE_TABLE(pci, ark_devices);
|
1163 |
|
|
|
1164 |
|
|
static struct pci_driver arkfb_pci_driver = {
|
1165 |
|
|
.name = "arkfb",
|
1166 |
|
|
.id_table = ark_devices,
|
1167 |
|
|
.probe = ark_pci_probe,
|
1168 |
|
|
.remove = __devexit_p(ark_pci_remove),
|
1169 |
|
|
.suspend = ark_pci_suspend,
|
1170 |
|
|
.resume = ark_pci_resume,
|
1171 |
|
|
};
|
1172 |
|
|
|
1173 |
|
|
/* Cleanup */
|
1174 |
|
|
|
1175 |
|
|
static void __exit arkfb_cleanup(void)
|
1176 |
|
|
{
|
1177 |
|
|
pr_debug("arkfb: cleaning up\n");
|
1178 |
|
|
pci_unregister_driver(&arkfb_pci_driver);
|
1179 |
|
|
}
|
1180 |
|
|
|
1181 |
|
|
/* Driver Initialisation */
|
1182 |
|
|
|
1183 |
|
|
static int __init arkfb_init(void)
|
1184 |
|
|
{
|
1185 |
|
|
|
1186 |
|
|
#ifndef MODULE
|
1187 |
|
|
char *option = NULL;
|
1188 |
|
|
|
1189 |
|
|
if (fb_get_options("arkfb", &option))
|
1190 |
|
|
return -ENODEV;
|
1191 |
|
|
|
1192 |
|
|
if (option && *option)
|
1193 |
|
|
mode = option;
|
1194 |
|
|
#endif
|
1195 |
|
|
|
1196 |
|
|
pr_debug("arkfb: initializing\n");
|
1197 |
|
|
return pci_register_driver(&arkfb_pci_driver);
|
1198 |
|
|
}
|
1199 |
|
|
|
1200 |
|
|
module_init(arkfb_init);
|
1201 |
|
|
module_exit(arkfb_cleanup);
|