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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [video/] [chipsfb.c] - Blame information for rev 62

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1 62 marcus.erl
/*
2
 *  drivers/video/chipsfb.c -- frame buffer device for
3
 *  Chips & Technologies 65550 chip.
4
 *
5
 *  Copyright (C) 1998-2002 Paul Mackerras
6
 *
7
 *  This file is derived from the Powermac "chips" driver:
8
 *  Copyright (C) 1997 Fabio Riccardi.
9
 *  And from the frame buffer device for Open Firmware-initialized devices:
10
 *  Copyright (C) 1997 Geert Uytterhoeven.
11
 *
12
 *  This file is subject to the terms and conditions of the GNU General Public
13
 *  License. See the file COPYING in the main directory of this archive for
14
 *  more details.
15
 */
16
 
17
#include <linux/module.h>
18
#include <linux/kernel.h>
19
#include <linux/errno.h>
20
#include <linux/string.h>
21
#include <linux/mm.h>
22
#include <linux/slab.h>
23
#include <linux/vmalloc.h>
24
#include <linux/delay.h>
25
#include <linux/interrupt.h>
26
#include <linux/fb.h>
27
#include <linux/pm.h>
28
#include <linux/init.h>
29
#include <linux/pci.h>
30
#include <linux/console.h>
31
#include <asm/io.h>
32
 
33
#ifdef CONFIG_PMAC_BACKLIGHT
34
#include <asm/backlight.h>
35
#endif
36
 
37
/*
38
 * Since we access the display with inb/outb to fixed port numbers,
39
 * we can only handle one 6555x chip.  -- paulus
40
 */
41
#define write_ind(num, val, ap, dp)     do { \
42
        outb((num), (ap)); outb((val), (dp)); \
43
} while (0)
44
#define read_ind(num, var, ap, dp)      do { \
45
        outb((num), (ap)); var = inb((dp)); \
46
} while (0)
47
 
48
/* extension registers */
49
#define write_xr(num, val)      write_ind(num, val, 0x3d6, 0x3d7)
50
#define read_xr(num, var)       read_ind(num, var, 0x3d6, 0x3d7)
51
/* flat panel registers */
52
#define write_fr(num, val)      write_ind(num, val, 0x3d0, 0x3d1)
53
#define read_fr(num, var)       read_ind(num, var, 0x3d0, 0x3d1)
54
/* CRTC registers */
55
#define write_cr(num, val)      write_ind(num, val, 0x3d4, 0x3d5)
56
#define read_cr(num, var)       read_ind(num, var, 0x3d4, 0x3d5)
57
/* graphics registers */
58
#define write_gr(num, val)      write_ind(num, val, 0x3ce, 0x3cf)
59
#define read_gr(num, var)       read_ind(num, var, 0x3ce, 0x3cf)
60
/* sequencer registers */
61
#define write_sr(num, val)      write_ind(num, val, 0x3c4, 0x3c5)
62
#define read_sr(num, var)       read_ind(num, var, 0x3c4, 0x3c5)
63
/* attribute registers - slightly strange */
64
#define write_ar(num, val)      do { \
65
        inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
66
} while (0)
67
#define read_ar(num, var)       do { \
68
        inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
69
} while (0)
70
 
71
/*
72
 * Exported functions
73
 */
74
int chips_init(void);
75
 
76
static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
77
static int chipsfb_check_var(struct fb_var_screeninfo *var,
78
                             struct fb_info *info);
79
static int chipsfb_set_par(struct fb_info *info);
80
static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
81
                             u_int transp, struct fb_info *info);
82
static int chipsfb_blank(int blank, struct fb_info *info);
83
 
84
static struct fb_ops chipsfb_ops = {
85
        .owner          = THIS_MODULE,
86
        .fb_check_var   = chipsfb_check_var,
87
        .fb_set_par     = chipsfb_set_par,
88
        .fb_setcolreg   = chipsfb_setcolreg,
89
        .fb_blank       = chipsfb_blank,
90
        .fb_fillrect    = cfb_fillrect,
91
        .fb_copyarea    = cfb_copyarea,
92
        .fb_imageblit   = cfb_imageblit,
93
};
94
 
95
static int chipsfb_check_var(struct fb_var_screeninfo *var,
96
                             struct fb_info *info)
97
{
98
        if (var->xres > 800 || var->yres > 600
99
            || var->xres_virtual > 800 || var->yres_virtual > 600
100
            || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
101
            || var->nonstd
102
            || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
103
                return -EINVAL;
104
 
105
        var->xres = var->xres_virtual = 800;
106
        var->yres = var->yres_virtual = 600;
107
 
108
        return 0;
109
}
110
 
111
static int chipsfb_set_par(struct fb_info *info)
112
{
113
        if (info->var.bits_per_pixel == 16) {
114
                write_cr(0x13, 200);            // Set line length (doublewords)
115
                write_xr(0x81, 0x14);           // 15 bit (555) color mode
116
                write_xr(0x82, 0x00);           // Disable palettes
117
                write_xr(0x20, 0x10);           // 16 bit blitter mode
118
 
119
                info->fix.line_length = 800*2;
120
                info->fix.visual = FB_VISUAL_TRUECOLOR;
121
 
122
                info->var.red.offset = 10;
123
                info->var.green.offset = 5;
124
                info->var.blue.offset = 0;
125
                info->var.red.length = info->var.green.length =
126
                        info->var.blue.length = 5;
127
 
128
        } else {
129
                /* p->var.bits_per_pixel == 8 */
130
                write_cr(0x13, 100);            // Set line length (doublewords)
131
                write_xr(0x81, 0x12);           // 8 bit color mode
132
                write_xr(0x82, 0x08);           // Graphics gamma enable
133
                write_xr(0x20, 0x00);           // 8 bit blitter mode
134
 
135
                info->fix.line_length = 800;
136
                info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
137
 
138
                info->var.red.offset = info->var.green.offset =
139
                        info->var.blue.offset = 0;
140
                info->var.red.length = info->var.green.length =
141
                        info->var.blue.length = 8;
142
 
143
        }
144
        return 0;
145
}
146
 
147
static int chipsfb_blank(int blank, struct fb_info *info)
148
{
149
        return 1;       /* get fb_blank to set the colormap to all black */
150
}
151
 
152
static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
153
                             u_int transp, struct fb_info *info)
154
{
155
        if (regno > 255)
156
                return 1;
157
        red >>= 8;
158
        green >>= 8;
159
        blue >>= 8;
160
        outb(regno, 0x3c8);
161
        udelay(1);
162
        outb(red, 0x3c9);
163
        outb(green, 0x3c9);
164
        outb(blue, 0x3c9);
165
 
166
        return 0;
167
}
168
 
169
struct chips_init_reg {
170
        unsigned char addr;
171
        unsigned char data;
172
};
173
 
174
static struct chips_init_reg chips_init_sr[] = {
175
        { 0x00, 0x03 },
176
        { 0x01, 0x01 },
177
        { 0x02, 0x0f },
178
        { 0x04, 0x0e }
179
};
180
 
181
static struct chips_init_reg chips_init_gr[] = {
182
        { 0x05, 0x00 },
183
        { 0x06, 0x0d },
184
        { 0x08, 0xff }
185
};
186
 
187
static struct chips_init_reg chips_init_ar[] = {
188
        { 0x10, 0x01 },
189
        { 0x12, 0x0f },
190
        { 0x13, 0x00 }
191
};
192
 
193
static struct chips_init_reg chips_init_cr[] = {
194
        { 0x00, 0x7f },
195
        { 0x01, 0x63 },
196
        { 0x02, 0x63 },
197
        { 0x03, 0x83 },
198
        { 0x04, 0x66 },
199
        { 0x05, 0x10 },
200
        { 0x06, 0x72 },
201
        { 0x07, 0x3e },
202
        { 0x08, 0x00 },
203
        { 0x09, 0x40 },
204
        { 0x0c, 0x00 },
205
        { 0x0d, 0x00 },
206
        { 0x10, 0x59 },
207
        { 0x11, 0x0d },
208
        { 0x12, 0x57 },
209
        { 0x13, 0x64 },
210
        { 0x14, 0x00 },
211
        { 0x15, 0x57 },
212
        { 0x16, 0x73 },
213
        { 0x17, 0xe3 },
214
        { 0x18, 0xff },
215
        { 0x30, 0x02 },
216
        { 0x31, 0x02 },
217
        { 0x32, 0x02 },
218
        { 0x33, 0x02 },
219
        { 0x40, 0x00 },
220
        { 0x41, 0x00 },
221
        { 0x40, 0x80 }
222
};
223
 
224
static struct chips_init_reg chips_init_fr[] = {
225
        { 0x01, 0x02 },
226
        { 0x03, 0x08 },
227
        { 0x04, 0x81 },
228
        { 0x05, 0x21 },
229
        { 0x08, 0x0c },
230
        { 0x0a, 0x74 },
231
        { 0x0b, 0x11 },
232
        { 0x10, 0x0c },
233
        { 0x11, 0xe0 },
234
        /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
235
        { 0x20, 0x63 },
236
        { 0x21, 0x68 },
237
        { 0x22, 0x19 },
238
        { 0x23, 0x7f },
239
        { 0x24, 0x68 },
240
        { 0x26, 0x00 },
241
        { 0x27, 0x0f },
242
        { 0x30, 0x57 },
243
        { 0x31, 0x58 },
244
        { 0x32, 0x0d },
245
        { 0x33, 0x72 },
246
        { 0x34, 0x02 },
247
        { 0x35, 0x22 },
248
        { 0x36, 0x02 },
249
        { 0x37, 0x00 }
250
};
251
 
252
static struct chips_init_reg chips_init_xr[] = {
253
        { 0xce, 0x00 },         /* set default memory clock */
254
        { 0xcc, 0x43 },         /* memory clock ratio */
255
        { 0xcd, 0x18 },
256
        { 0xce, 0xa1 },
257
        { 0xc8, 0x84 },
258
        { 0xc9, 0x0a },
259
        { 0xca, 0x00 },
260
        { 0xcb, 0x20 },
261
        { 0xcf, 0x06 },
262
        { 0xd0, 0x0e },
263
        { 0x09, 0x01 },
264
        { 0x0a, 0x02 },
265
        { 0x0b, 0x01 },
266
        { 0x20, 0x00 },
267
        { 0x40, 0x03 },
268
        { 0x41, 0x01 },
269
        { 0x42, 0x00 },
270
        { 0x80, 0x82 },
271
        { 0x81, 0x12 },
272
        { 0x82, 0x08 },
273
        { 0xa0, 0x00 },
274
        { 0xa8, 0x00 }
275
};
276
 
277
static void __init chips_hw_init(void)
278
{
279
        int i;
280
 
281
        for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
282
                write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
283
        outb(0x29, 0x3c2); /* set misc output reg */
284
        for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
285
                write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
286
        for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
287
                write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
288
        for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
289
                write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
290
        for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
291
                write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
292
        for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
293
                write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
294
}
295
 
296
static struct fb_fix_screeninfo chipsfb_fix __devinitdata = {
297
        .id =           "C&T 65550",
298
        .type =         FB_TYPE_PACKED_PIXELS,
299
        .visual =       FB_VISUAL_PSEUDOCOLOR,
300
        .accel =        FB_ACCEL_NONE,
301
        .line_length =  800,
302
 
303
// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
304
// * "3500" PowerBook G3 (the original PB G3) has 2MB.
305
// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
306
//   Motherboard actually supports 2MB -- there are two blank locations
307
//   for a second pair of DRAMs.  (Thanks, Apple!)
308
// * 3400 has 1MB (I think).  Don't know if it's expandable.
309
// -- Tim Seufert
310
        .smem_len =     0x100000,       /* 1MB */
311
};
312
 
313
static struct fb_var_screeninfo chipsfb_var __devinitdata = {
314
        .xres = 800,
315
        .yres = 600,
316
        .xres_virtual = 800,
317
        .yres_virtual = 600,
318
        .bits_per_pixel = 8,
319
        .red = { .length = 8 },
320
        .green = { .length = 8 },
321
        .blue = { .length = 8 },
322
        .height = -1,
323
        .width = -1,
324
        .vmode = FB_VMODE_NONINTERLACED,
325
        .pixclock = 10000,
326
        .left_margin = 16,
327
        .right_margin = 16,
328
        .upper_margin = 16,
329
        .lower_margin = 16,
330
        .hsync_len = 8,
331
        .vsync_len = 8,
332
};
333
 
334
static void __devinit init_chips(struct fb_info *p, unsigned long addr)
335
{
336
        memset(p->screen_base, 0, 0x100000);
337
 
338
        p->fix = chipsfb_fix;
339
        p->fix.smem_start = addr;
340
 
341
        p->var = chipsfb_var;
342
 
343
        p->fbops = &chipsfb_ops;
344
        p->flags = FBINFO_DEFAULT;
345
 
346
        fb_alloc_cmap(&p->cmap, 256, 0);
347
 
348
        chips_hw_init();
349
}
350
 
351
static int __devinit
352
chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
353
{
354
        struct fb_info *p;
355
        unsigned long addr, size;
356
        unsigned short cmd;
357
        int rc = -ENODEV;
358
 
359
        if (pci_enable_device(dp) < 0) {
360
                dev_err(&dp->dev, "Cannot enable PCI device\n");
361
                goto err_out;
362
        }
363
 
364
        if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
365
                goto err_disable;
366
        addr = pci_resource_start(dp, 0);
367
        size = pci_resource_len(dp, 0);
368
        if (addr == 0)
369
                goto err_disable;
370
 
371
        p = framebuffer_alloc(0, &dp->dev);
372
        if (p == NULL) {
373
                dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
374
                rc = -ENOMEM;
375
                goto err_disable;
376
        }
377
 
378
        if (pci_request_region(dp, 0, "chipsfb") != 0) {
379
                dev_err(&dp->dev, "Cannot request framebuffer\n");
380
                rc = -EBUSY;
381
                goto err_release_fb;
382
        }
383
 
384
#ifdef __BIG_ENDIAN
385
        addr += 0x800000;       // Use big-endian aperture
386
#endif
387
 
388
        /* we should use pci_enable_device here, but,
389
           the device doesn't declare its I/O ports in its BARs
390
           so pci_enable_device won't turn on I/O responses */
391
        pci_read_config_word(dp, PCI_COMMAND, &cmd);
392
        cmd |= 3;       /* enable memory and IO space */
393
        pci_write_config_word(dp, PCI_COMMAND, cmd);
394
 
395
#ifdef CONFIG_PMAC_BACKLIGHT
396
        /* turn on the backlight */
397
        mutex_lock(&pmac_backlight_mutex);
398
        if (pmac_backlight) {
399
                pmac_backlight->props.power = FB_BLANK_UNBLANK;
400
                backlight_update_status(pmac_backlight);
401
        }
402
        mutex_unlock(&pmac_backlight_mutex);
403
#endif /* CONFIG_PMAC_BACKLIGHT */
404
 
405
#ifdef CONFIG_PPC
406
        p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
407
#else
408
        p->screen_base = ioremap(addr, 0x200000);
409
#endif
410
        if (p->screen_base == NULL) {
411
                dev_err(&dp->dev, "Cannot map framebuffer\n");
412
                rc = -ENOMEM;
413
                goto err_release_pci;
414
        }
415
 
416
        pci_set_drvdata(dp, p);
417
        p->device = &dp->dev;
418
 
419
        init_chips(p, addr);
420
 
421
        if (register_framebuffer(p) < 0) {
422
                dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
423
                goto err_unmap;
424
        }
425
 
426
        dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
427
                 " (%dK RAM detected)\n",
428
                 p->node, p->fix.smem_len / 1024);
429
 
430
        return 0;
431
 
432
 err_unmap:
433
        iounmap(p->screen_base);
434
 err_release_pci:
435
        pci_release_region(dp, 0);
436
 err_release_fb:
437
        framebuffer_release(p);
438
 err_disable:
439
 err_out:
440
        return rc;
441
}
442
 
443
static void __devexit chipsfb_remove(struct pci_dev *dp)
444
{
445
        struct fb_info *p = pci_get_drvdata(dp);
446
 
447
        if (p->screen_base == NULL)
448
                return;
449
        unregister_framebuffer(p);
450
        iounmap(p->screen_base);
451
        p->screen_base = NULL;
452
        pci_release_region(dp, 0);
453
}
454
 
455
#ifdef CONFIG_PM
456
static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
457
{
458
        struct fb_info *p = pci_get_drvdata(pdev);
459
 
460
        if (state.event == pdev->dev.power.power_state.event)
461
                return 0;
462
        if (state.event != PM_EVENT_SUSPEND)
463
                goto done;
464
 
465
        acquire_console_sem();
466
        chipsfb_blank(1, p);
467
        fb_set_suspend(p, 1);
468
        release_console_sem();
469
 done:
470
        pdev->dev.power.power_state = state;
471
        return 0;
472
}
473
 
474
static int chipsfb_pci_resume(struct pci_dev *pdev)
475
{
476
        struct fb_info *p = pci_get_drvdata(pdev);
477
 
478
        acquire_console_sem();
479
        fb_set_suspend(p, 0);
480
        chipsfb_blank(0, p);
481
        release_console_sem();
482
 
483
        pdev->dev.power.power_state = PMSG_ON;
484
        return 0;
485
}
486
#endif /* CONFIG_PM */
487
 
488
 
489
static struct pci_device_id chipsfb_pci_tbl[] = {
490
        { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
491
        { 0 }
492
};
493
 
494
MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
495
 
496
static struct pci_driver chipsfb_driver = {
497
        .name =         "chipsfb",
498
        .id_table =     chipsfb_pci_tbl,
499
        .probe =        chipsfb_pci_init,
500
        .remove =       __devexit_p(chipsfb_remove),
501
#ifdef CONFIG_PM
502
        .suspend =      chipsfb_pci_suspend,
503
        .resume =       chipsfb_pci_resume,
504
#endif
505
};
506
 
507
int __init chips_init(void)
508
{
509
        if (fb_get_options("chipsfb", NULL))
510
                return -ENODEV;
511
 
512
        return pci_register_driver(&chipsfb_driver);
513
}
514
 
515
module_init(chips_init);
516
 
517
static void __exit chipsfb_exit(void)
518
{
519
        pci_unregister_driver(&chipsfb_driver);
520
}
521
 
522
MODULE_LICENSE("GPL");

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