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[/] [test_project/] [trunk/] [linux_sd_driver/] [drivers/] [video/] [imsttfb.c] - Blame information for rev 62

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1 62 marcus.erl
/*
2
 *  drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
3
 *
4
 *  This file is derived from the powermac console "imstt" driver:
5
 *  Copyright (C) 1997 Sigurdur Asgeirsson
6
 *  With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7
 *  Modified by Danilo Beuche 1998
8
 *  Some register values added by Damien Doligez, INRIA Rocquencourt
9
 *  Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
10
 *
11
 *  This file was written by Ryan Nielsen (ran@krazynet.com)
12
 *  Most of the frame buffer device stuff was copied from atyfb.c
13
 *
14
 *  This file is subject to the terms and conditions of the GNU General Public
15
 *  License. See the file COPYING in the main directory of this archive for
16
 *  more details.
17
 */
18
 
19
#include <linux/module.h>
20
#include <linux/kernel.h>
21
#include <linux/errno.h>
22
#include <linux/string.h>
23
#include <linux/mm.h>
24
#include <linux/slab.h>
25
#include <linux/vmalloc.h>
26
#include <linux/delay.h>
27
#include <linux/interrupt.h>
28
#include <linux/fb.h>
29
#include <linux/init.h>
30
#include <linux/pci.h>
31
#include <asm/io.h>
32
#include <linux/uaccess.h>
33
 
34
#if defined(CONFIG_PPC)
35
#include <linux/nvram.h>
36
#include <asm/prom.h>
37
#include <asm/pci-bridge.h>
38
#include "macmodes.h"
39
#endif
40
 
41
#ifndef __powerpc__
42
#define eieio()         /* Enforce In-order Execution of I/O */
43
#endif
44
 
45
/* TwinTurbo (Cosmo) registers */
46
enum {
47
        S1SA    =  0, /* 0x00 */
48
        S2SA    =  1, /* 0x04 */
49
        SP      =  2, /* 0x08 */
50
        DSA     =  3, /* 0x0C */
51
        CNT     =  4, /* 0x10 */
52
        DP_OCTL =  5, /* 0x14 */
53
        CLR     =  6, /* 0x18 */
54
        BI      =  8, /* 0x20 */
55
        MBC     =  9, /* 0x24 */
56
        BLTCTL  = 10, /* 0x28 */
57
 
58
        /* Scan Timing Generator Registers */
59
        HES     = 12, /* 0x30 */
60
        HEB     = 13, /* 0x34 */
61
        HSB     = 14, /* 0x38 */
62
        HT      = 15, /* 0x3C */
63
        VES     = 16, /* 0x40 */
64
        VEB     = 17, /* 0x44 */
65
        VSB     = 18, /* 0x48 */
66
        VT      = 19, /* 0x4C */
67
        HCIV    = 20, /* 0x50 */
68
        VCIV    = 21, /* 0x54 */
69
        TCDR    = 22, /* 0x58 */
70
        VIL     = 23, /* 0x5C */
71
        STGCTL  = 24, /* 0x60 */
72
 
73
        /* Screen Refresh Generator Registers */
74
        SSR     = 25, /* 0x64 */
75
        HRIR    = 26, /* 0x68 */
76
        SPR     = 27, /* 0x6C */
77
        CMR     = 28, /* 0x70 */
78
        SRGCTL  = 29, /* 0x74 */
79
 
80
        /* RAM Refresh Generator Registers */
81
        RRCIV   = 30, /* 0x78 */
82
        RRSC    = 31, /* 0x7C */
83
        RRCR    = 34, /* 0x88 */
84
 
85
        /* System Registers */
86
        GIOE    = 32, /* 0x80 */
87
        GIO     = 33, /* 0x84 */
88
        SCR     = 35, /* 0x8C */
89
        SSTATUS = 36, /* 0x90 */
90
        PRC     = 37, /* 0x94 */
91
 
92
#if 0   
93
        /* PCI Registers */
94
        DVID    = 0x00000000L,
95
        SC      = 0x00000004L,
96
        CCR     = 0x00000008L,
97
        OG      = 0x0000000CL,
98
        BARM    = 0x00000010L,
99
        BARER   = 0x00000030L,
100
#endif
101
};
102
 
103
/* IBM 624 RAMDAC Direct Registers */
104
enum {
105
        PADDRW  = 0x00,
106
        PDATA   = 0x04,
107
        PPMASK  = 0x08,
108
        PADDRR  = 0x0c,
109
        PIDXLO  = 0x10,
110
        PIDXHI  = 0x14,
111
        PIDXDATA= 0x18,
112
        PIDXCTL = 0x1c
113
};
114
 
115
/* IBM 624 RAMDAC Indirect Registers */
116
enum {
117
        CLKCTL          = 0x02, /* (0x01) Miscellaneous Clock Control */
118
        SYNCCTL         = 0x03, /* (0x00) Sync Control */
119
        HSYNCPOS        = 0x04, /* (0x00) Horizontal Sync Position */
120
        PWRMNGMT        = 0x05, /* (0x00) Power Management */
121
        DACOP           = 0x06, /* (0x02) DAC Operation */
122
        PALETCTL        = 0x07, /* (0x00) Palette Control */
123
        SYSCLKCTL       = 0x08, /* (0x01) System Clock Control */
124
        PIXFMT          = 0x0a, /* () Pixel Format  [bpp >> 3 + 2] */
125
        BPP8            = 0x0b, /* () 8 Bits/Pixel Control */
126
        BPP16           = 0x0c, /* () 16 Bits/Pixel Control  [bit 1=1 for 565] */
127
        BPP24           = 0x0d, /* () 24 Bits/Pixel Control */
128
        BPP32           = 0x0e, /* () 32 Bits/Pixel Control */
129
        PIXCTL1         = 0x10, /* (0x05) Pixel PLL Control 1 */
130
        PIXCTL2         = 0x11, /* (0x00) Pixel PLL Control 2 */
131
        SYSCLKN         = 0x15, /* () System Clock N (System PLL Reference Divider) */
132
        SYSCLKM         = 0x16, /* () System Clock M (System PLL VCO Divider) */
133
        SYSCLKP         = 0x17, /* () System Clock P */
134
        SYSCLKC         = 0x18, /* () System Clock C */
135
        /*
136
         * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
137
         * c is charge pump bias which depends on the VCO frequency
138
         */
139
        PIXM0           = 0x20, /* () Pixel M 0 */
140
        PIXN0           = 0x21, /* () Pixel N 0 */
141
        PIXP0           = 0x22, /* () Pixel P 0 */
142
        PIXC0           = 0x23, /* () Pixel C 0 */
143
        CURSCTL         = 0x30, /* (0x00) Cursor Control */
144
        CURSXLO         = 0x31, /* () Cursor X position, low 8 bits */
145
        CURSXHI         = 0x32, /* () Cursor X position, high 8 bits */
146
        CURSYLO         = 0x33, /* () Cursor Y position, low 8 bits */
147
        CURSYHI         = 0x34, /* () Cursor Y position, high 8 bits */
148
        CURSHOTX        = 0x35, /* () Cursor Hot Spot X */
149
        CURSHOTY        = 0x36, /* () Cursor Hot Spot Y */
150
        CURSACCTL       = 0x37, /* () Advanced Cursor Control Enable */
151
        CURSACATTR      = 0x38, /* () Advanced Cursor Attribute */
152
        CURS1R          = 0x40, /* () Cursor 1 Red */
153
        CURS1G          = 0x41, /* () Cursor 1 Green */
154
        CURS1B          = 0x42, /* () Cursor 1 Blue */
155
        CURS2R          = 0x43, /* () Cursor 2 Red */
156
        CURS2G          = 0x44, /* () Cursor 2 Green */
157
        CURS2B          = 0x45, /* () Cursor 2 Blue */
158
        CURS3R          = 0x46, /* () Cursor 3 Red */
159
        CURS3G          = 0x47, /* () Cursor 3 Green */
160
        CURS3B          = 0x48, /* () Cursor 3 Blue */
161
        BORDR           = 0x60, /* () Border Color Red */
162
        BORDG           = 0x61, /* () Border Color Green */
163
        BORDB           = 0x62, /* () Border Color Blue */
164
        MISCTL1         = 0x70, /* (0x00) Miscellaneous Control 1 */
165
        MISCTL2         = 0x71, /* (0x00) Miscellaneous Control 2 */
166
        MISCTL3         = 0x72, /* (0x00) Miscellaneous Control 3 */
167
        KEYCTL          = 0x78  /* (0x00) Key Control/DB Operation */
168
};
169
 
170
/* TI TVP 3030 RAMDAC Direct Registers */
171
enum {
172
        TVPADDRW = 0x00,        /* 0  Palette/Cursor RAM Write Address/Index */
173
        TVPPDATA = 0x04,        /* 1  Palette Data RAM Data */
174
        TVPPMASK = 0x08,        /* 2  Pixel Read-Mask */
175
        TVPPADRR = 0x0c,        /* 3  Palette/Cursor RAM Read Address */
176
        TVPCADRW = 0x10,        /* 4  Cursor/Overscan Color Write Address */
177
        TVPCDATA = 0x14,        /* 5  Cursor/Overscan Color Data */
178
                                /* 6  reserved */
179
        TVPCADRR = 0x1c,        /* 7  Cursor/Overscan Color Read Address */
180
                                /* 8  reserved */
181
        TVPDCCTL = 0x24,        /* 9  Direct Cursor Control */
182
        TVPIDATA = 0x28,        /* 10 Index Data */
183
        TVPCRDAT = 0x2c,        /* 11 Cursor RAM Data */
184
        TVPCXPOL = 0x30,        /* 12 Cursor-Position X LSB */
185
        TVPCXPOH = 0x34,        /* 13 Cursor-Position X MSB */
186
        TVPCYPOL = 0x38,        /* 14 Cursor-Position Y LSB */
187
        TVPCYPOH = 0x3c,        /* 15 Cursor-Position Y MSB */
188
};
189
 
190
/* TI TVP 3030 RAMDAC Indirect Registers */
191
enum {
192
        TVPIRREV = 0x01,        /* Silicon Revision [RO] */
193
        TVPIRICC = 0x06,        /* Indirect Cursor Control      (0x00) */
194
        TVPIRBRC = 0x07,        /* Byte Router Control  (0xe4) */
195
        TVPIRLAC = 0x0f,        /* Latch Control                (0x06) */
196
        TVPIRTCC = 0x18,        /* True Color Control   (0x80) */
197
        TVPIRMXC = 0x19,        /* Multiplex Control            (0x98) */
198
        TVPIRCLS = 0x1a,        /* Clock Selection              (0x07) */
199
        TVPIRPPG = 0x1c,        /* Palette Page         (0x00) */
200
        TVPIRGEC = 0x1d,        /* General Control              (0x00) */
201
        TVPIRMIC = 0x1e,        /* Miscellaneous Control        (0x00) */
202
        TVPIRPLA = 0x2c,        /* PLL Address */
203
        TVPIRPPD = 0x2d,        /* Pixel Clock PLL Data */
204
        TVPIRMPD = 0x2e,        /* Memory Clock PLL Data */
205
        TVPIRLPD = 0x2f,        /* Loop Clock PLL Data */
206
        TVPIRCKL = 0x30,        /* Color-Key Overlay Low */
207
        TVPIRCKH = 0x31,        /* Color-Key Overlay High */
208
        TVPIRCRL = 0x32,        /* Color-Key Red Low */
209
        TVPIRCRH = 0x33,        /* Color-Key Red High */
210
        TVPIRCGL = 0x34,        /* Color-Key Green Low */
211
        TVPIRCGH = 0x35,        /* Color-Key Green High */
212
        TVPIRCBL = 0x36,        /* Color-Key Blue Low */
213
        TVPIRCBH = 0x37,        /* Color-Key Blue High */
214
        TVPIRCKC = 0x38,        /* Color-Key Control            (0x00) */
215
        TVPIRMLC = 0x39,        /* MCLK/Loop Clock Control      (0x18) */
216
        TVPIRSEN = 0x3a,        /* Sense Test                   (0x00) */
217
        TVPIRTMD = 0x3b,        /* Test Mode Data */
218
        TVPIRRML = 0x3c,        /* CRC Remainder LSB [RO] */
219
        TVPIRRMM = 0x3d,        /* CRC Remainder MSB [RO] */
220
        TVPIRRMS = 0x3e,        /* CRC  Bit Select [WO] */
221
        TVPIRDID = 0x3f,        /* Device ID [RO]               (0x30) */
222
        TVPIRRES = 0xff         /* Software Reset [WO] */
223
};
224
 
225
struct initvalues {
226
        __u8 addr, value;
227
};
228
 
229
static struct initvalues ibm_initregs[] __devinitdata = {
230
        { CLKCTL,       0x21 },
231
        { SYNCCTL,      0x00 },
232
        { HSYNCPOS,     0x00 },
233
        { PWRMNGMT,     0x00 },
234
        { DACOP,        0x02 },
235
        { PALETCTL,     0x00 },
236
        { SYSCLKCTL,    0x01 },
237
 
238
        /*
239
         * Note that colors in X are correct only if all video data is
240
         * passed through the palette in the DAC.  That is, "indirect
241
         * color" must be configured.  This is the case for the IBM DAC
242
         * used in the 2MB and 4MB cards, at least.
243
         */
244
        { BPP8,         0x00 },
245
        { BPP16,        0x01 },
246
        { BPP24,        0x00 },
247
        { BPP32,        0x00 },
248
 
249
        { PIXCTL1,      0x05 },
250
        { PIXCTL2,      0x00 },
251
        { SYSCLKN,      0x08 },
252
        { SYSCLKM,      0x4f },
253
        { SYSCLKP,      0x00 },
254
        { SYSCLKC,      0x00 },
255
        { CURSCTL,      0x00 },
256
        { CURSACCTL,    0x01 },
257
        { CURSACATTR,   0xa8 },
258
        { CURS1R,       0xff },
259
        { CURS1G,       0xff },
260
        { CURS1B,       0xff },
261
        { CURS2R,       0xff },
262
        { CURS2G,       0xff },
263
        { CURS2B,       0xff },
264
        { CURS3R,       0xff },
265
        { CURS3G,       0xff },
266
        { CURS3B,       0xff },
267
        { BORDR,        0xff },
268
        { BORDG,        0xff },
269
        { BORDB,        0xff },
270
        { MISCTL1,      0x01 },
271
        { MISCTL2,      0x45 },
272
        { MISCTL3,      0x00 },
273
        { KEYCTL,       0x00 }
274
};
275
 
276
static struct initvalues tvp_initregs[] __devinitdata = {
277
        { TVPIRICC,     0x00 },
278
        { TVPIRBRC,     0xe4 },
279
        { TVPIRLAC,     0x06 },
280
        { TVPIRTCC,     0x80 },
281
        { TVPIRMXC,     0x4d },
282
        { TVPIRCLS,     0x05 },
283
        { TVPIRPPG,     0x00 },
284
        { TVPIRGEC,     0x00 },
285
        { TVPIRMIC,     0x08 },
286
        { TVPIRCKL,     0xff },
287
        { TVPIRCKH,     0xff },
288
        { TVPIRCRL,     0xff },
289
        { TVPIRCRH,     0xff },
290
        { TVPIRCGL,     0xff },
291
        { TVPIRCGH,     0xff },
292
        { TVPIRCBL,     0xff },
293
        { TVPIRCBH,     0xff },
294
        { TVPIRCKC,     0x00 },
295
        { TVPIRPLA,     0x00 },
296
        { TVPIRPPD,     0xc0 },
297
        { TVPIRPPD,     0xd5 },
298
        { TVPIRPPD,     0xea },
299
        { TVPIRPLA,     0x00 },
300
        { TVPIRMPD,     0xb9 },
301
        { TVPIRMPD,     0x3a },
302
        { TVPIRMPD,     0xb1 },
303
        { TVPIRPLA,     0x00 },
304
        { TVPIRLPD,     0xc1 },
305
        { TVPIRLPD,     0x3d },
306
        { TVPIRLPD,     0xf3 },
307
};
308
 
309
struct imstt_regvals {
310
        __u32 pitch;
311
        __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
312
        __u8 pclk_m, pclk_n, pclk_p;
313
        /* Values of the tvp which change depending on colormode x resolution */
314
        __u8 mlc[3];    /* Memory Loop Config 0x39 */
315
        __u8 lckl_p[3]; /* P value of LCKL PLL */
316
};
317
 
318
struct imstt_par {
319
        struct imstt_regvals init;
320
        __u32 __iomem *dc_regs;
321
        unsigned long cmap_regs_phys;
322
        __u8 *cmap_regs;
323
        __u32 ramdac;
324
        __u32 palette[16];
325
};
326
 
327
enum {
328
        IBM = 0,
329
        TVP = 1
330
};
331
 
332
#define USE_NV_MODES            1
333
#define INIT_BPP                8
334
#define INIT_XRES               640
335
#define INIT_YRES               480
336
 
337
static int inverse = 0;
338
static char fontname[40] __initdata = { 0 };
339
#if defined(CONFIG_PPC)
340
static signed char init_vmode __devinitdata = -1, init_cmode __devinitdata = -1;
341
#endif
342
 
343
static struct imstt_regvals tvp_reg_init_2 = {
344
        512,
345
        0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
346
        0xec, 0x2a, 0xf3,
347
        { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
348
};
349
 
350
static struct imstt_regvals tvp_reg_init_6 = {
351
        640,
352
        0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
353
        0xef, 0x2e, 0xb2,
354
        { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
355
};
356
 
357
static struct imstt_regvals tvp_reg_init_12 = {
358
        800,
359
        0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
360
        0xf6, 0x2e, 0xf2,
361
        { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
362
};
363
 
364
static struct imstt_regvals tvp_reg_init_13 = {
365
        832,
366
        0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
367
        0xfe, 0x3e, 0xf1,
368
        { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
369
};
370
 
371
static struct imstt_regvals tvp_reg_init_17 = {
372
        1024,
373
        0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
374
        0xfc, 0x3a, 0xf1,
375
        { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
376
};
377
 
378
static struct imstt_regvals tvp_reg_init_18 = {
379
        1152,
380
        0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
381
        0xfd, 0x3a, 0xf1,
382
        { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
383
};
384
 
385
static struct imstt_regvals tvp_reg_init_19 = {
386
        1280,
387
        0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
388
        0xf7, 0x36, 0xf0,
389
        { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
390
};
391
 
392
static struct imstt_regvals tvp_reg_init_20 = {
393
        1280,
394
        0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
395
        0xf0, 0x2d, 0xf0,
396
        { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
397
};
398
 
399
/*
400
 * PCI driver prototypes
401
 */
402
static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
403
static void imsttfb_remove(struct pci_dev *pdev);
404
 
405
/*
406
 * Register access
407
 */
408
static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
409
{
410
#ifdef __powerpc__
411
        return in_le32(base + regindex);
412
#else
413
        return readl(base + regindex);
414
#endif
415
}
416
 
417
static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
418
{
419
#ifdef __powerpc__
420
        out_le32(base + regindex, val);
421
#else
422
        writel(val, base + regindex);
423
#endif
424
}
425
 
426
static __u32
427
getclkMHz(struct imstt_par *par)
428
{
429
        __u32 clk_m, clk_n, clk_p;
430
 
431
        clk_m = par->init.pclk_m;
432
        clk_n = par->init.pclk_n;
433
        clk_p = par->init.pclk_p;
434
 
435
        return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
436
}
437
 
438
static void
439
setclkMHz(struct imstt_par *par, __u32 MHz)
440
{
441
        __u32 clk_m, clk_n, x, stage, spilled;
442
 
443
        clk_m = clk_n = 0;
444
        stage = spilled = 0;
445
        for (;;) {
446
                switch (stage) {
447
                        case 0:
448
                                clk_m++;
449
                                break;
450
                        case 1:
451
                                clk_n++;
452
                                break;
453
                }
454
                x = 20 * (clk_m + 1) / (clk_n + 1);
455
                if (x == MHz)
456
                        break;
457
                if (x > MHz) {
458
                        spilled = 1;
459
                        stage = 1;
460
                } else if (spilled && x < MHz) {
461
                        stage = 0;
462
                }
463
        }
464
 
465
        par->init.pclk_m = clk_m;
466
        par->init.pclk_n = clk_n;
467
        par->init.pclk_p = 0;
468
}
469
 
470
static struct imstt_regvals *
471
compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
472
{
473
        struct imstt_regvals *init = &par->init;
474
        __u32 MHz, hes, heb, veb, htp, vtp;
475
 
476
        switch (xres) {
477
                case 640:
478
                        hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
479
                        MHz = 30 /* .25 */ ;
480
                        break;
481
                case 832:
482
                        hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
483
                        MHz = 57 /* .27_ */ ;
484
                        break;
485
                case 1024:
486
                        hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
487
                        MHz = 80;
488
                        break;
489
                case 1152:
490
                        hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
491
                        MHz = 101 /* .6_ */ ;
492
                        break;
493
                case 1280:
494
                        hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
495
                        MHz = yres == 960 ? 126 : 135;
496
                        break;
497
                case 1600:
498
                        hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
499
                        MHz = 200;
500
                        break;
501
                default:
502
                        return NULL;
503
        }
504
 
505
        setclkMHz(par, MHz);
506
 
507
        init->hes = hes;
508
        init->heb = heb;
509
        init->hsb = init->heb + (xres >> 3);
510
        init->ht = init->hsb + htp;
511
        init->ves = 0x0003;
512
        init->veb = veb;
513
        init->vsb = init->veb + yres;
514
        init->vt = init->vsb + vtp;
515
        init->vil = init->vsb;
516
 
517
        init->pitch = xres;
518
        return init;
519
}
520
 
521
static struct imstt_regvals *
522
compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
523
{
524
        struct imstt_regvals *init;
525
 
526
        switch (xres) {
527
                case 512:
528
                        init = &tvp_reg_init_2;
529
                        break;
530
                case 640:
531
                        init = &tvp_reg_init_6;
532
                        break;
533
                case 800:
534
                        init = &tvp_reg_init_12;
535
                        break;
536
                case 832:
537
                        init = &tvp_reg_init_13;
538
                        break;
539
                case 1024:
540
                        init = &tvp_reg_init_17;
541
                        break;
542
                case 1152:
543
                        init = &tvp_reg_init_18;
544
                        break;
545
                case 1280:
546
                        init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
547
                        break;
548
                default:
549
                        return NULL;
550
        }
551
        par->init = *init;
552
        return init;
553
}
554
 
555
static struct imstt_regvals *
556
compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
557
{
558
        if (par->ramdac == IBM)
559
                return compute_imstt_regvals_ibm(par, xres, yres);
560
        else
561
                return compute_imstt_regvals_tvp(par, xres, yres);
562
}
563
 
564
static void
565
set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
566
{
567
        struct imstt_regvals *init = &par->init;
568
        __u8 pformat = (bpp >> 3) + 2;
569
 
570
        par->cmap_regs[PIDXHI] = 0;              eieio();
571
        par->cmap_regs[PIDXLO] = PIXM0;         eieio();
572
        par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
573
        par->cmap_regs[PIDXLO] = PIXN0;         eieio();
574
        par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
575
        par->cmap_regs[PIDXLO] = PIXP0;         eieio();
576
        par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
577
        par->cmap_regs[PIDXLO] = PIXC0;         eieio();
578
        par->cmap_regs[PIDXDATA] = 0x02;        eieio();
579
 
580
        par->cmap_regs[PIDXLO] = PIXFMT;        eieio();
581
        par->cmap_regs[PIDXDATA] = pformat;     eieio();
582
}
583
 
584
static void
585
set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
586
{
587
        struct imstt_regvals *init = &par->init;
588
        __u8 tcc, mxc, lckl_n, mic;
589
        __u8 mlc, lckl_p;
590
 
591
        switch (bpp) {
592
                default:
593
                case 8:
594
                        tcc = 0x80;
595
                        mxc = 0x4d;
596
                        lckl_n = 0xc1;
597
                        mlc = init->mlc[0];
598
                        lckl_p = init->lckl_p[0];
599
                        break;
600
                case 16:
601
                        tcc = 0x44;
602
                        mxc = 0x55;
603
                        lckl_n = 0xe1;
604
                        mlc = init->mlc[1];
605
                        lckl_p = init->lckl_p[1];
606
                        break;
607
                case 24:
608
                        tcc = 0x5e;
609
                        mxc = 0x5d;
610
                        lckl_n = 0xf1;
611
                        mlc = init->mlc[2];
612
                        lckl_p = init->lckl_p[2];
613
                        break;
614
                case 32:
615
                        tcc = 0x46;
616
                        mxc = 0x5d;
617
                        lckl_n = 0xf1;
618
                        mlc = init->mlc[2];
619
                        lckl_p = init->lckl_p[2];
620
                        break;
621
        }
622
        mic = 0x08;
623
 
624
        par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
625
        par->cmap_regs[TVPIDATA] = 0x00;                eieio();
626
        par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
627
        par->cmap_regs[TVPIDATA] = init->pclk_m;        eieio();
628
        par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
629
        par->cmap_regs[TVPIDATA] = init->pclk_n;        eieio();
630
        par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
631
        par->cmap_regs[TVPIDATA] = init->pclk_p;        eieio();
632
 
633
        par->cmap_regs[TVPADDRW] = TVPIRTCC;            eieio();
634
        par->cmap_regs[TVPIDATA] = tcc;                 eieio();
635
        par->cmap_regs[TVPADDRW] = TVPIRMXC;            eieio();
636
        par->cmap_regs[TVPIDATA] = mxc;                 eieio();
637
        par->cmap_regs[TVPADDRW] = TVPIRMIC;            eieio();
638
        par->cmap_regs[TVPIDATA] = mic;                 eieio();
639
 
640
        par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
641
        par->cmap_regs[TVPIDATA] = 0x00;                eieio();
642
        par->cmap_regs[TVPADDRW] = TVPIRLPD;            eieio();
643
        par->cmap_regs[TVPIDATA] = lckl_n;              eieio();
644
 
645
        par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
646
        par->cmap_regs[TVPIDATA] = 0x15;                eieio();
647
        par->cmap_regs[TVPADDRW] = TVPIRMLC;            eieio();
648
        par->cmap_regs[TVPIDATA] = mlc;                 eieio();
649
 
650
        par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
651
        par->cmap_regs[TVPIDATA] = 0x2a;                eieio();
652
        par->cmap_regs[TVPADDRW] = TVPIRLPD;            eieio();
653
        par->cmap_regs[TVPIDATA] = lckl_p;              eieio();
654
}
655
 
656
static void
657
set_imstt_regvals (struct fb_info *info, u_int bpp)
658
{
659
        struct imstt_par *par = info->par;
660
        struct imstt_regvals *init = &par->init;
661
        __u32 ctl, pitch, byteswap, scr;
662
 
663
        if (par->ramdac == IBM)
664
                set_imstt_regvals_ibm(par, bpp);
665
        else
666
                set_imstt_regvals_tvp(par, bpp);
667
 
668
  /*
669
   * From what I (jsk) can gather poking around with MacsBug,
670
   * bits 8 and 9 in the SCR register control endianness
671
   * correction (byte swapping).  These bits must be set according
672
   * to the color depth as follows:
673
   *     Color depth    Bit 9   Bit 8
674
   *     ==========     =====   =====
675
   *        8bpp          0       0
676
   *       16bpp          0       1
677
   *       32bpp          1       1
678
   */
679
        switch (bpp) {
680
                default:
681
                case 8:
682
                        ctl = 0x17b1;
683
                        pitch = init->pitch >> 2;
684
                        byteswap = 0x000;
685
                        break;
686
                case 16:
687
                        ctl = 0x17b3;
688
                        pitch = init->pitch >> 1;
689
                        byteswap = 0x100;
690
                        break;
691
                case 24:
692
                        ctl = 0x17b9;
693
                        pitch = init->pitch - (init->pitch >> 2);
694
                        byteswap = 0x200;
695
                        break;
696
                case 32:
697
                        ctl = 0x17b5;
698
                        pitch = init->pitch;
699
                        byteswap = 0x300;
700
                        break;
701
        }
702
        if (par->ramdac == TVP)
703
                ctl -= 0x30;
704
 
705
        write_reg_le32(par->dc_regs, HES, init->hes);
706
        write_reg_le32(par->dc_regs, HEB, init->heb);
707
        write_reg_le32(par->dc_regs, HSB, init->hsb);
708
        write_reg_le32(par->dc_regs, HT, init->ht);
709
        write_reg_le32(par->dc_regs, VES, init->ves);
710
        write_reg_le32(par->dc_regs, VEB, init->veb);
711
        write_reg_le32(par->dc_regs, VSB, init->vsb);
712
        write_reg_le32(par->dc_regs, VT, init->vt);
713
        write_reg_le32(par->dc_regs, VIL, init->vil);
714
        write_reg_le32(par->dc_regs, HCIV, 1);
715
        write_reg_le32(par->dc_regs, VCIV, 1);
716
        write_reg_le32(par->dc_regs, TCDR, 4);
717
        write_reg_le32(par->dc_regs, RRCIV, 1);
718
        write_reg_le32(par->dc_regs, RRSC, 0x980);
719
        write_reg_le32(par->dc_regs, RRCR, 0x11);
720
 
721
        if (par->ramdac == IBM) {
722
                write_reg_le32(par->dc_regs, HRIR, 0x0100);
723
                write_reg_le32(par->dc_regs, CMR, 0x00ff);
724
                write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
725
        } else {
726
                write_reg_le32(par->dc_regs, HRIR, 0x0200);
727
                write_reg_le32(par->dc_regs, CMR, 0x01ff);
728
                write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
729
        }
730
 
731
        switch (info->fix.smem_len) {
732
                case 0x200000:
733
                        scr = 0x059d | byteswap;
734
                        break;
735
                /* case 0x400000:
736
                   case 0x800000: */
737
                default:
738
                        pitch >>= 1;
739
                        scr = 0x150dd | byteswap;
740
                        break;
741
        }
742
 
743
        write_reg_le32(par->dc_regs, SCR, scr);
744
        write_reg_le32(par->dc_regs, SPR, pitch);
745
        write_reg_le32(par->dc_regs, STGCTL, ctl);
746
}
747
 
748
static inline void
749
set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
750
{
751
        struct imstt_par *par = info->par;
752
        __u32 off = var->yoffset * (info->fix.line_length >> 3)
753
                    + ((var->xoffset * (var->bits_per_pixel >> 3)) >> 3);
754
        write_reg_le32(par->dc_regs, SSR, off);
755
}
756
 
757
static inline void
758
set_555 (struct imstt_par *par)
759
{
760
        if (par->ramdac == IBM) {
761
                par->cmap_regs[PIDXHI] = 0;              eieio();
762
                par->cmap_regs[PIDXLO] = BPP16;         eieio();
763
                par->cmap_regs[PIDXDATA] = 0x01;        eieio();
764
        } else {
765
                par->cmap_regs[TVPADDRW] = TVPIRTCC;    eieio();
766
                par->cmap_regs[TVPIDATA] = 0x44;        eieio();
767
        }
768
}
769
 
770
static inline void
771
set_565 (struct imstt_par *par)
772
{
773
        if (par->ramdac == IBM) {
774
                par->cmap_regs[PIDXHI] = 0;              eieio();
775
                par->cmap_regs[PIDXLO] = BPP16;         eieio();
776
                par->cmap_regs[PIDXDATA] = 0x03;        eieio();
777
        } else {
778
                par->cmap_regs[TVPADDRW] = TVPIRTCC;    eieio();
779
                par->cmap_regs[TVPIDATA] = 0x45;        eieio();
780
        }
781
}
782
 
783
static int
784
imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
785
{
786
        if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
787
            && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
788
            || var->xres_virtual < var->xres || var->yres_virtual < var->yres
789
            || var->nonstd
790
            || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
791
                return -EINVAL;
792
 
793
        if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
794
            || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
795
                return -EINVAL;
796
 
797
        switch (var->bits_per_pixel) {
798
                case 8:
799
                        var->red.offset = 0;
800
                        var->red.length = 8;
801
                        var->green.offset = 0;
802
                        var->green.length = 8;
803
                        var->blue.offset = 0;
804
                        var->blue.length = 8;
805
                        var->transp.offset = 0;
806
                        var->transp.length = 0;
807
                        break;
808
                case 16:        /* RGB 555 or 565 */
809
                        if (var->green.length != 6)
810
                                var->red.offset = 10;
811
                        var->red.length = 5;
812
                        var->green.offset = 5;
813
                        if (var->green.length != 6)
814
                                var->green.length = 5;
815
                        var->blue.offset = 0;
816
                        var->blue.length = 5;
817
                        var->transp.offset = 0;
818
                        var->transp.length = 0;
819
                        break;
820
                case 24:        /* RGB 888 */
821
                        var->red.offset = 16;
822
                        var->red.length = 8;
823
                        var->green.offset = 8;
824
                        var->green.length = 8;
825
                        var->blue.offset = 0;
826
                        var->blue.length = 8;
827
                        var->transp.offset = 0;
828
                        var->transp.length = 0;
829
                        break;
830
                case 32:        /* RGBA 8888 */
831
                        var->red.offset = 16;
832
                        var->red.length = 8;
833
                        var->green.offset = 8;
834
                        var->green.length = 8;
835
                        var->blue.offset = 0;
836
                        var->blue.length = 8;
837
                        var->transp.offset = 24;
838
                        var->transp.length = 8;
839
                        break;
840
        }
841
 
842
        if (var->yres == var->yres_virtual) {
843
                __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
844
                var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
845
                if (var->yres_virtual < var->yres)
846
                        var->yres_virtual = var->yres;
847
        }
848
 
849
        var->red.msb_right = 0;
850
        var->green.msb_right = 0;
851
        var->blue.msb_right = 0;
852
        var->transp.msb_right = 0;
853
        var->height = -1;
854
        var->width = -1;
855
        var->vmode = FB_VMODE_NONINTERLACED;
856
        var->left_margin = var->right_margin = 16;
857
        var->upper_margin = var->lower_margin = 16;
858
        var->hsync_len = var->vsync_len = 8;
859
        return 0;
860
}
861
 
862
static int
863
imsttfb_set_par(struct fb_info *info)
864
{
865
        struct imstt_par *par = info->par;
866
 
867
        if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
868
                return -EINVAL;
869
 
870
        if (info->var.green.length == 6)
871
                set_565(par);
872
        else
873
                set_555(par);
874
        set_imstt_regvals(info, info->var.bits_per_pixel);
875
        info->var.pixclock = 1000000 / getclkMHz(par);
876
        return 0;
877
}
878
 
879
static int
880
imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
881
                   u_int transp, struct fb_info *info)
882
{
883
        struct imstt_par *par = info->par;
884
        u_int bpp = info->var.bits_per_pixel;
885
 
886
        if (regno > 255)
887
                return 1;
888
 
889
        red >>= 8;
890
        green >>= 8;
891
        blue >>= 8;
892
 
893
        /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
894
        if (0 && bpp == 16)      /* screws up X */
895
                par->cmap_regs[PADDRW] = regno << 3;
896
        else
897
                par->cmap_regs[PADDRW] = regno;
898
        eieio();
899
 
900
        par->cmap_regs[PDATA] = red;    eieio();
901
        par->cmap_regs[PDATA] = green;  eieio();
902
        par->cmap_regs[PDATA] = blue;   eieio();
903
 
904
        if (regno < 16)
905
                switch (bpp) {
906
                        case 16:
907
                                par->palette[regno] =
908
                                        (regno << (info->var.green.length ==
909
                                        5 ? 10 : 11)) | (regno << 5) | regno;
910
                                break;
911
                        case 24:
912
                                par->palette[regno] =
913
                                        (regno << 16) | (regno << 8) | regno;
914
                                break;
915
                        case 32: {
916
                                int i = (regno << 8) | regno;
917
                                par->palette[regno] = (i << 16) |i;
918
                                break;
919
                        }
920
                }
921
        return 0;
922
}
923
 
924
static int
925
imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
926
{
927
        if (var->xoffset + info->var.xres > info->var.xres_virtual
928
            || var->yoffset + info->var.yres > info->var.yres_virtual)
929
                return -EINVAL;
930
 
931
        info->var.xoffset = var->xoffset;
932
        info->var.yoffset = var->yoffset;
933
        set_offset(var, info);
934
        return 0;
935
}
936
 
937
static int
938
imsttfb_blank(int blank, struct fb_info *info)
939
{
940
        struct imstt_par *par = info->par;
941
        __u32 ctrl;
942
 
943
        ctrl = read_reg_le32(par->dc_regs, STGCTL);
944
        if (blank > 0) {
945
                switch (blank) {
946
                case FB_BLANK_NORMAL:
947
                case FB_BLANK_POWERDOWN:
948
                        ctrl &= ~0x00000380;
949
                        if (par->ramdac == IBM) {
950
                                par->cmap_regs[PIDXHI] = 0;              eieio();
951
                                par->cmap_regs[PIDXLO] = MISCTL2;       eieio();
952
                                par->cmap_regs[PIDXDATA] = 0x55;        eieio();
953
                                par->cmap_regs[PIDXLO] = MISCTL1;       eieio();
954
                                par->cmap_regs[PIDXDATA] = 0x11;        eieio();
955
                                par->cmap_regs[PIDXLO] = SYNCCTL;       eieio();
956
                                par->cmap_regs[PIDXDATA] = 0x0f;        eieio();
957
                                par->cmap_regs[PIDXLO] = PWRMNGMT;      eieio();
958
                                par->cmap_regs[PIDXDATA] = 0x1f;        eieio();
959
                                par->cmap_regs[PIDXLO] = CLKCTL;        eieio();
960
                                par->cmap_regs[PIDXDATA] = 0xc0;
961
                        }
962
                        break;
963
                case FB_BLANK_VSYNC_SUSPEND:
964
                        ctrl &= ~0x00000020;
965
                        break;
966
                case FB_BLANK_HSYNC_SUSPEND:
967
                        ctrl &= ~0x00000010;
968
                        break;
969
                }
970
        } else {
971
                if (par->ramdac == IBM) {
972
                        ctrl |= 0x000017b0;
973
                        par->cmap_regs[PIDXHI] = 0;              eieio();
974
                        par->cmap_regs[PIDXLO] = CLKCTL;        eieio();
975
                        par->cmap_regs[PIDXDATA] = 0x01;        eieio();
976
                        par->cmap_regs[PIDXLO] = PWRMNGMT;      eieio();
977
                        par->cmap_regs[PIDXDATA] = 0x00;        eieio();
978
                        par->cmap_regs[PIDXLO] = SYNCCTL;       eieio();
979
                        par->cmap_regs[PIDXDATA] = 0x00;        eieio();
980
                        par->cmap_regs[PIDXLO] = MISCTL1;       eieio();
981
                        par->cmap_regs[PIDXDATA] = 0x01;        eieio();
982
                        par->cmap_regs[PIDXLO] = MISCTL2;       eieio();
983
                        par->cmap_regs[PIDXDATA] = 0x45;        eieio();
984
                } else
985
                        ctrl |= 0x00001780;
986
        }
987
        write_reg_le32(par->dc_regs, STGCTL, ctrl);
988
        return 0;
989
}
990
 
991
static void
992
imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
993
{
994
        struct imstt_par *par = info->par;
995
        __u32 Bpp, line_pitch, bgc, dx, dy, width, height;
996
 
997
        bgc = rect->color;
998
        bgc |= (bgc << 8);
999
        bgc |= (bgc << 16);
1000
 
1001
        Bpp = info->var.bits_per_pixel >> 3,
1002
        line_pitch = info->fix.line_length;
1003
 
1004
        dy = rect->dy * line_pitch;
1005
        dx = rect->dx * Bpp;
1006
        height = rect->height;
1007
        height--;
1008
        width = rect->width * Bpp;
1009
        width--;
1010
 
1011
        if (rect->rop == ROP_COPY) {
1012
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1013
                write_reg_le32(par->dc_regs, DSA, dy + dx);
1014
                write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1015
                write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1016
                write_reg_le32(par->dc_regs, BI, 0xffffffff);
1017
                write_reg_le32(par->dc_regs, MBC, 0xffffffff);
1018
                write_reg_le32(par->dc_regs, CLR, bgc);
1019
                write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
1020
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1021
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1022
        } else {
1023
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1024
                write_reg_le32(par->dc_regs, DSA, dy + dx);
1025
                write_reg_le32(par->dc_regs, S1SA, dy + dx);
1026
                write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1027
                write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1028
                write_reg_le32(par->dc_regs, SP, line_pitch);
1029
                write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
1030
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1031
                while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1032
        }
1033
}
1034
 
1035
static void
1036
imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1037
{
1038
        struct imstt_par *par = info->par;
1039
        __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
1040
        __u32 cnt, bltctl, sx, sy, dx, dy, height, width;
1041
 
1042
        Bpp = info->var.bits_per_pixel >> 3,
1043
 
1044
        sx = area->sx * Bpp;
1045
        sy = area->sy;
1046
        dx = area->dx * Bpp;
1047
        dy = area->dy;
1048
        height = area->height;
1049
        height--;
1050
        width = area->width * Bpp;
1051
        width--;
1052
 
1053
        line_pitch = info->fix.line_length;
1054
        bltctl = 0x05;
1055
        sp = line_pitch << 16;
1056
        cnt = height << 16;
1057
 
1058
        if (sy < dy) {
1059
                sy += height;
1060
                dy += height;
1061
                sp |= -(line_pitch) & 0xffff;
1062
                dp_octl = -(line_pitch) & 0xffff;
1063
        } else {
1064
                sp |= line_pitch;
1065
                dp_octl = line_pitch;
1066
        }
1067
        if (sx < dx) {
1068
                sx += width;
1069
                dx += width;
1070
                bltctl |= 0x80;
1071
                cnt |= -(width) & 0xffff;
1072
        } else {
1073
                cnt |= width;
1074
        }
1075
        fb_offset_old = sy * line_pitch + sx;
1076
        fb_offset_new = dy * line_pitch + dx;
1077
 
1078
        while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1079
        write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
1080
        write_reg_le32(par->dc_regs, SP, sp);
1081
        write_reg_le32(par->dc_regs, DSA, fb_offset_new);
1082
        write_reg_le32(par->dc_regs, CNT, cnt);
1083
        write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
1084
        write_reg_le32(par->dc_regs, BLTCTL, bltctl);
1085
        while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1086
        while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1087
}
1088
 
1089
#if 0
1090
static int
1091
imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
1092
{
1093
        u_int x, y;
1094
 
1095
        if (width > 32 || height > 32)
1096
                return -EINVAL;
1097
 
1098
        if (par->ramdac == IBM) {
1099
                par->cmap_regs[PIDXHI] = 1;     eieio();
1100
                for (x = 0; x < 0x100; x++) {
1101
                        par->cmap_regs[PIDXLO] = x;             eieio();
1102
                        par->cmap_regs[PIDXDATA] = 0x00;        eieio();
1103
                }
1104
                par->cmap_regs[PIDXHI] = 1;     eieio();
1105
                for (y = 0; y < height; y++)
1106
                        for (x = 0; x < width >> 2; x++) {
1107
                                par->cmap_regs[PIDXLO] = x + y * 8;     eieio();
1108
                                par->cmap_regs[PIDXDATA] = 0xff;        eieio();
1109
                        }
1110
                par->cmap_regs[PIDXHI] = 0;              eieio();
1111
                par->cmap_regs[PIDXLO] = CURS1R;        eieio();
1112
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1113
                par->cmap_regs[PIDXLO] = CURS1G;        eieio();
1114
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1115
                par->cmap_regs[PIDXLO] = CURS1B;        eieio();
1116
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1117
                par->cmap_regs[PIDXLO] = CURS2R;        eieio();
1118
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1119
                par->cmap_regs[PIDXLO] = CURS2G;        eieio();
1120
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1121
                par->cmap_regs[PIDXLO] = CURS2B;        eieio();
1122
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1123
                par->cmap_regs[PIDXLO] = CURS3R;        eieio();
1124
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1125
                par->cmap_regs[PIDXLO] = CURS3G;        eieio();
1126
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1127
                par->cmap_regs[PIDXLO] = CURS3B;        eieio();
1128
                par->cmap_regs[PIDXDATA] = fgc;         eieio();
1129
        } else {
1130
                par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1131
                par->cmap_regs[TVPIDATA] &= 0x03;       eieio();
1132
                par->cmap_regs[TVPADDRW] = 0;            eieio();
1133
                for (x = 0; x < 0x200; x++) {
1134
                        par->cmap_regs[TVPCRDAT] = 0x00;        eieio();
1135
                }
1136
                for (x = 0; x < 0x200; x++) {
1137
                        par->cmap_regs[TVPCRDAT] = 0xff;        eieio();
1138
                }
1139
                par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1140
                par->cmap_regs[TVPIDATA] &= 0x03;       eieio();
1141
                for (y = 0; y < height; y++)
1142
                        for (x = 0; x < width >> 3; x++) {
1143
                                par->cmap_regs[TVPADDRW] = x + y * 8;   eieio();
1144
                                par->cmap_regs[TVPCRDAT] = 0xff;                eieio();
1145
                        }
1146
                par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1147
                par->cmap_regs[TVPIDATA] |= 0x08;       eieio();
1148
                for (y = 0; y < height; y++)
1149
                        for (x = 0; x < width >> 3; x++) {
1150
                                par->cmap_regs[TVPADDRW] = x + y * 8;   eieio();
1151
                                par->cmap_regs[TVPCRDAT] = 0xff;                eieio();
1152
                        }
1153
                par->cmap_regs[TVPCADRW] = 0x00;        eieio();
1154
                for (x = 0; x < 12; x++)
1155
                        par->cmap_regs[TVPCDATA] = fgc; eieio();
1156
        }
1157
        return 1;
1158
}
1159
 
1160
static void
1161
imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
1162
{
1163
        if (par->ramdac == IBM) {
1164
                par->cmap_regs[PIDXHI] = 0;      eieio();
1165
                if (!on) {
1166
                        par->cmap_regs[PIDXLO] = CURSCTL;       eieio();
1167
                        par->cmap_regs[PIDXDATA] = 0x00;        eieio();
1168
                } else {
1169
                        par->cmap_regs[PIDXLO] = CURSXHI;       eieio();
1170
                        par->cmap_regs[PIDXDATA] = d->dx >> 8;  eieio();
1171
                        par->cmap_regs[PIDXLO] = CURSXLO;       eieio();
1172
                        par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
1173
                        par->cmap_regs[PIDXLO] = CURSYHI;       eieio();
1174
                        par->cmap_regs[PIDXDATA] = d->dy >> 8;  eieio();
1175
                        par->cmap_regs[PIDXLO] = CURSYLO;       eieio();
1176
                        par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
1177
                        par->cmap_regs[PIDXLO] = CURSCTL;       eieio();
1178
                        par->cmap_regs[PIDXDATA] = 0x02;        eieio();
1179
                }
1180
        } else {
1181
                if (!on) {
1182
                        par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1183
                        par->cmap_regs[TVPIDATA] = 0x00;        eieio();
1184
                } else {
1185
                        __u16 x = d->dx + 0x40, y = d->dy + 0x40;
1186
 
1187
                        par->cmap_regs[TVPCXPOH] = x >> 8;      eieio();
1188
                        par->cmap_regs[TVPCXPOL] = x & 0xff;    eieio();
1189
                        par->cmap_regs[TVPCYPOH] = y >> 8;      eieio();
1190
                        par->cmap_regs[TVPCYPOL] = y & 0xff;    eieio();
1191
                        par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1192
                        par->cmap_regs[TVPIDATA] = 0x02;        eieio();
1193
                }
1194
        }
1195
}
1196
 
1197
static int
1198
imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1199
{
1200
        struct imstt_par *par = info->par;
1201
        u32 flags = cursor->set, fg, bg, xx, yy;
1202
 
1203
        if (cursor->dest == NULL && cursor->rop == ROP_XOR)
1204
                return 1;
1205
 
1206
        imstt_set_cursor(info, cursor, 0);
1207
 
1208
        if (flags & FB_CUR_SETPOS) {
1209
                xx = cursor->image.dx - info->var.xoffset;
1210
                yy = cursor->image.dy - info->var.yoffset;
1211
        }
1212
 
1213
        if (flags & FB_CUR_SETSIZE) {
1214
        }
1215
 
1216
        if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
1217
                int fg_idx = cursor->image.fg_color;
1218
                int width = (cursor->image.width+7)/8;
1219
                u8 *dat = (u8 *) cursor->image.data;
1220
                u8 *dst = (u8 *) cursor->dest;
1221
                u8 *msk = (u8 *) cursor->mask;
1222
 
1223
                switch (cursor->rop) {
1224
                case ROP_XOR:
1225
                        for (i = 0; i < cursor->image.height; i++) {
1226
                                for (j = 0; j < width; j++) {
1227
                                        d_idx = i * MAX_CURS/8  + j;
1228
                                        data[d_idx] =  byte_rev[dat[s_idx] ^
1229
                                                                dst[s_idx]];
1230
                                        mask[d_idx] = byte_rev[msk[s_idx]];
1231
                                        s_idx++;
1232
                                }
1233
                        }
1234
                        break;
1235
                case ROP_COPY:
1236
                default:
1237
                        for (i = 0; i < cursor->image.height; i++) {
1238
                                for (j = 0; j < width; j++) {
1239
                                        d_idx = i * MAX_CURS/8 + j;
1240
                                        data[d_idx] = byte_rev[dat[s_idx]];
1241
                                        mask[d_idx] = byte_rev[msk[s_idx]];
1242
                                        s_idx++;
1243
                                }
1244
                        }
1245
                        break;
1246
                }
1247
 
1248
                fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1249
                     ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1250
                     ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1251
 
1252
                imsttfb_load_cursor_image(par, xx, yy, fgc);
1253
        }
1254
        if (cursor->enable)
1255
                imstt_set_cursor(info, cursor, 1);
1256
        return 0;
1257
}
1258
#endif
1259
 
1260
#define FBIMSTT_SETREG          0x545401
1261
#define FBIMSTT_GETREG          0x545402
1262
#define FBIMSTT_SETCMAPREG      0x545403
1263
#define FBIMSTT_GETCMAPREG      0x545404
1264
#define FBIMSTT_SETIDXREG       0x545405
1265
#define FBIMSTT_GETIDXREG       0x545406
1266
 
1267
static int
1268
imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1269
{
1270
        struct imstt_par *par = info->par;
1271
        void __user *argp = (void __user *)arg;
1272
        __u32 reg[2];
1273
        __u8 idx[2];
1274
 
1275
        switch (cmd) {
1276
                case FBIMSTT_SETREG:
1277
                        if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1278
                                return -EFAULT;
1279
                        write_reg_le32(par->dc_regs, reg[0], reg[1]);
1280
                        return 0;
1281
                case FBIMSTT_GETREG:
1282
                        if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1283
                                return -EFAULT;
1284
                        reg[1] = read_reg_le32(par->dc_regs, reg[0]);
1285
                        if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1286
                                return -EFAULT;
1287
                        return 0;
1288
                case FBIMSTT_SETCMAPREG:
1289
                        if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1290
                                return -EFAULT;
1291
                        write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
1292
                        return 0;
1293
                case FBIMSTT_GETCMAPREG:
1294
                        if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1295
                                return -EFAULT;
1296
                        reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
1297
                        if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1298
                                return -EFAULT;
1299
                        return 0;
1300
                case FBIMSTT_SETIDXREG:
1301
                        if (copy_from_user(idx, argp, 2))
1302
                                return -EFAULT;
1303
                        par->cmap_regs[PIDXHI] = 0;              eieio();
1304
                        par->cmap_regs[PIDXLO] = idx[0]; eieio();
1305
                        par->cmap_regs[PIDXDATA] = idx[1];      eieio();
1306
                        return 0;
1307
                case FBIMSTT_GETIDXREG:
1308
                        if (copy_from_user(idx, argp, 1))
1309
                                return -EFAULT;
1310
                        par->cmap_regs[PIDXHI] = 0;              eieio();
1311
                        par->cmap_regs[PIDXLO] = idx[0]; eieio();
1312
                        idx[1] = par->cmap_regs[PIDXDATA];
1313
                        if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
1314
                                return -EFAULT;
1315
                        return 0;
1316
                default:
1317
                        return -ENOIOCTLCMD;
1318
        }
1319
}
1320
 
1321
static struct pci_device_id imsttfb_pci_tbl[] = {
1322
        { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
1323
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
1324
        { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
1325
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
1326
        { 0, }
1327
};
1328
 
1329
MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
1330
 
1331
static struct pci_driver imsttfb_pci_driver = {
1332
        .name =         "imsttfb",
1333
        .id_table =     imsttfb_pci_tbl,
1334
        .probe =        imsttfb_probe,
1335
        .remove =       __devexit_p(imsttfb_remove),
1336
};
1337
 
1338
static struct fb_ops imsttfb_ops = {
1339
        .owner          = THIS_MODULE,
1340
        .fb_check_var   = imsttfb_check_var,
1341
        .fb_set_par     = imsttfb_set_par,
1342
        .fb_setcolreg   = imsttfb_setcolreg,
1343
        .fb_pan_display = imsttfb_pan_display,
1344
        .fb_blank       = imsttfb_blank,
1345
        .fb_fillrect    = imsttfb_fillrect,
1346
        .fb_copyarea    = imsttfb_copyarea,
1347
        .fb_imageblit   = cfb_imageblit,
1348
        .fb_ioctl       = imsttfb_ioctl,
1349
};
1350
 
1351
static void __devinit
1352
init_imstt(struct fb_info *info)
1353
{
1354
        struct imstt_par *par = info->par;
1355
        __u32 i, tmp, *ip, *end;
1356
 
1357
        tmp = read_reg_le32(par->dc_regs, PRC);
1358
        if (par->ramdac == IBM)
1359
                info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
1360
        else
1361
                info->fix.smem_len = 0x800000;
1362
 
1363
        ip = (__u32 *)info->screen_base;
1364
        end = (__u32 *)(info->screen_base + info->fix.smem_len);
1365
        while (ip < end)
1366
                *ip++ = 0;
1367
 
1368
        /* initialize the card */
1369
        tmp = read_reg_le32(par->dc_regs, STGCTL);
1370
        write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
1371
        write_reg_le32(par->dc_regs, SSR, 0);
1372
 
1373
        /* set default values for DAC registers */
1374
        if (par->ramdac == IBM) {
1375
                par->cmap_regs[PPMASK] = 0xff;
1376
                eieio();
1377
                par->cmap_regs[PIDXHI] = 0;
1378
                eieio();
1379
                for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
1380
                        par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
1381
                        eieio();
1382
                        par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
1383
                        eieio();
1384
                }
1385
        } else {
1386
                for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
1387
                        par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
1388
                        eieio();
1389
                        par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
1390
                        eieio();
1391
                }
1392
        }
1393
 
1394
#if USE_NV_MODES && defined(CONFIG_PPC32)
1395
        {
1396
                int vmode = init_vmode, cmode = init_cmode;
1397
 
1398
                if (vmode == -1) {
1399
                        vmode = nvram_read_byte(NV_VMODE);
1400
                        if (vmode <= 0 || vmode > VMODE_MAX)
1401
                                vmode = VMODE_640_480_67;
1402
                }
1403
                if (cmode == -1) {
1404
                        cmode = nvram_read_byte(NV_CMODE);
1405
                        if (cmode < CMODE_8 || cmode > CMODE_32)
1406
                                cmode = CMODE_8;
1407
                }
1408
                if (mac_vmode_to_var(vmode, cmode, &info->var)) {
1409
                        info->var.xres = info->var.xres_virtual = INIT_XRES;
1410
                        info->var.yres = info->var.yres_virtual = INIT_YRES;
1411
                        info->var.bits_per_pixel = INIT_BPP;
1412
                }
1413
        }
1414
#else
1415
        info->var.xres = info->var.xres_virtual = INIT_XRES;
1416
        info->var.yres = info->var.yres_virtual = INIT_YRES;
1417
        info->var.bits_per_pixel = INIT_BPP;
1418
#endif
1419
 
1420
        if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
1421
            || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
1422
                printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
1423
                framebuffer_release(info);
1424
                return;
1425
        }
1426
 
1427
        sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
1428
        info->fix.mmio_len = 0x1000;
1429
        info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1430
        info->fix.type = FB_TYPE_PACKED_PIXELS;
1431
        info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1432
                                                        : FB_VISUAL_DIRECTCOLOR;
1433
        info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
1434
        info->fix.xpanstep = 8;
1435
        info->fix.ypanstep = 1;
1436
        info->fix.ywrapstep = 0;
1437
 
1438
        info->var.accel_flags = FB_ACCELF_TEXT;
1439
 
1440
//      if (par->ramdac == IBM)
1441
//              imstt_cursor_init(info);
1442
        if (info->var.green.length == 6)
1443
                set_565(par);
1444
        else
1445
                set_555(par);
1446
        set_imstt_regvals(info, info->var.bits_per_pixel);
1447
 
1448
        info->var.pixclock = 1000000 / getclkMHz(par);
1449
 
1450
        info->fbops = &imsttfb_ops;
1451
        info->flags = FBINFO_DEFAULT |
1452
                      FBINFO_HWACCEL_COPYAREA |
1453
                      FBINFO_HWACCEL_FILLRECT |
1454
                      FBINFO_HWACCEL_YPAN;
1455
 
1456
        fb_alloc_cmap(&info->cmap, 0, 0);
1457
 
1458
        if (register_framebuffer(info) < 0) {
1459
                framebuffer_release(info);
1460
                return;
1461
        }
1462
 
1463
        tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
1464
        printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1465
                info->node, info->fix.id, info->fix.smem_len >> 20, tmp);
1466
}
1467
 
1468
static int __devinit
1469
imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1470
{
1471
        unsigned long addr, size;
1472
        struct imstt_par *par;
1473
        struct fb_info *info;
1474
#ifdef CONFIG_PPC_OF
1475
        struct device_node *dp;
1476
 
1477
        dp = pci_device_to_OF_node(pdev);
1478
        if(dp)
1479
                printk(KERN_INFO "%s: OF name %s\n",__FUNCTION__, dp->name);
1480
        else
1481
                printk(KERN_ERR "imsttfb: no OF node for pci device\n");
1482
#endif /* CONFIG_PPC_OF */
1483
 
1484
        info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev);
1485
 
1486
        if (!info) {
1487
                printk(KERN_ERR "imsttfb: Can't allocate memory\n");
1488
                return -ENOMEM;
1489
        }
1490
 
1491
        par = info->par;
1492
 
1493
        addr = pci_resource_start (pdev, 0);
1494
        size = pci_resource_len (pdev, 0);
1495
 
1496
        if (!request_mem_region(addr, size, "imsttfb")) {
1497
                printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
1498
                framebuffer_release(info);
1499
                return -ENODEV;
1500
        }
1501
 
1502
        switch (pdev->device) {
1503
                case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
1504
                        par->ramdac = IBM;
1505
#ifdef CONFIG_PPC_OF
1506
                        if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) ||
1507
                                   (strcmp(dp->name, "IMS,tt128mb8A") == 0)))
1508
                                par->ramdac = TVP;
1509
#endif /* CONFIG_PPC_OF */
1510
                        break;
1511
                case PCI_DEVICE_ID_IMS_TT3D:  /* IMS,tt3d */
1512
                        par->ramdac = TVP;
1513
                        break;
1514
                default:
1515
                        printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
1516
                                         "contact maintainer.\n", pdev->device);
1517
                        release_mem_region(addr, size);
1518
                        framebuffer_release(info);
1519
                        return -ENODEV;
1520
        }
1521
 
1522
        info->fix.smem_start = addr;
1523
        info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
1524
                                            0x400000 : 0x800000);
1525
        info->fix.mmio_start = addr + 0x800000;
1526
        par->dc_regs = ioremap(addr + 0x800000, 0x1000);
1527
        par->cmap_regs_phys = addr + 0x840000;
1528
        par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1529
        info->pseudo_palette = par->palette;
1530
        init_imstt(info);
1531
 
1532
        pci_set_drvdata(pdev, info);
1533
        return 0;
1534
}
1535
 
1536
static void __devexit
1537
imsttfb_remove(struct pci_dev *pdev)
1538
{
1539
        struct fb_info *info = pci_get_drvdata(pdev);
1540
        struct imstt_par *par = info->par;
1541
        int size = pci_resource_len(pdev, 0);
1542
 
1543
        unregister_framebuffer(info);
1544
        iounmap(par->cmap_regs);
1545
        iounmap(par->dc_regs);
1546
        iounmap(info->screen_base);
1547
        release_mem_region(info->fix.smem_start, size);
1548
        framebuffer_release(info);
1549
}
1550
 
1551
#ifndef MODULE
1552
static int __init
1553
imsttfb_setup(char *options)
1554
{
1555
        char *this_opt;
1556
 
1557
        if (!options || !*options)
1558
                return 0;
1559
 
1560
        while ((this_opt = strsep(&options, ",")) != NULL) {
1561
                if (!strncmp(this_opt, "font:", 5)) {
1562
                        char *p;
1563
                        int i;
1564
 
1565
                        p = this_opt + 5;
1566
                        for (i = 0; i < sizeof(fontname) - 1; i++)
1567
                                if (!*p || *p == ' ' || *p == ',')
1568
                                        break;
1569
                        memcpy(fontname, this_opt + 5, i);
1570
                        fontname[i] = 0;
1571
                } else if (!strncmp(this_opt, "inverse", 7)) {
1572
                        inverse = 1;
1573
                        fb_invert_cmaps();
1574
                }
1575
#if defined(CONFIG_PPC)
1576
                else if (!strncmp(this_opt, "vmode:", 6)) {
1577
                        int vmode = simple_strtoul(this_opt+6, NULL, 0);
1578
                        if (vmode > 0 && vmode <= VMODE_MAX)
1579
                                init_vmode = vmode;
1580
                } else if (!strncmp(this_opt, "cmode:", 6)) {
1581
                        int cmode = simple_strtoul(this_opt+6, NULL, 0);
1582
                        switch (cmode) {
1583
                                case CMODE_8:
1584
                                case 8:
1585
                                        init_cmode = CMODE_8;
1586
                                        break;
1587
                                case CMODE_16:
1588
                                case 15:
1589
                                case 16:
1590
                                        init_cmode = CMODE_16;
1591
                                        break;
1592
                                case CMODE_32:
1593
                                case 24:
1594
                                case 32:
1595
                                        init_cmode = CMODE_32;
1596
                                        break;
1597
                        }
1598
                }
1599
#endif
1600
        }
1601
        return 0;
1602
}
1603
 
1604
#endif /* MODULE */
1605
 
1606
static int __init imsttfb_init(void)
1607
{
1608
#ifndef MODULE
1609
        char *option = NULL;
1610
 
1611
        if (fb_get_options("imsttfb", &option))
1612
                return -ENODEV;
1613
 
1614
        imsttfb_setup(option);
1615
#endif
1616
        return pci_register_driver(&imsttfb_pci_driver);
1617
}
1618
 
1619
static void __exit imsttfb_exit(void)
1620
{
1621
        pci_unregister_driver(&imsttfb_pci_driver);
1622
}
1623
 
1624
MODULE_LICENSE("GPL");
1625
 
1626
module_init(imsttfb_init);
1627
module_exit(imsttfb_exit);
1628
 

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