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/*

 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge

 *

 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file COPYING in the main directory of this archive for

 * more details.

 *

 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)

 * which is based on the code of neofb.

 */

#include <linux/version.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/errno.h>

#include <linux/string.h>

#include <linux/mm.h>

#include <linux/tty.h>

#include <linux/slab.h>

#include <linux/delay.h>

#include <linux/fb.h>

#include <linux/svga.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */

#include <video/vga.h>

#ifdef CONFIG_MTRR

#include <asm/mtrr.h>

#endif

struct s3fb_info {

        int chip, rev, mclk_freq;

        int mtrr_reg;

        struct vgastate state;

        struct mutex open_lock;

        unsigned int ref_count;

        u32 pseudo_palette[16];

};

/* ------------------------------------------------------------------------- */

static const struct svga_fb_format s3fb_formats[] = {

        { 0,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,

                FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4,   FB_VISUAL_PSEUDOCOLOR, 8, 16},

        { 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_PSEUDOCOLOR, 8, 16},

        { 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 1,

                FB_TYPE_INTERLEAVED_PLANES, 1,          FB_VISUAL_PSEUDOCOLOR, 8, 16},

        { 8,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_PSEUDOCOLOR, 4, 8},

        {16,  {10, 5, 0}, {5, 5, 0},  {0, 5, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_TRUECOLOR, 2, 4},

        {16,  {11, 5, 0}, {5, 6, 0},  {0, 5, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_TRUECOLOR, 2, 4},

        {24,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_TRUECOLOR, 1, 2},

        {32,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,

                FB_TYPE_PACKED_PIXELS, 0,                FB_VISUAL_TRUECOLOR, 1, 2},

        SVGA_FORMAT_END

};

static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,

        35000, 240000, 14318};

static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};

static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",

                        "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",

                        "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",

                        "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",

                        "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};

#define CHIP_UNKNOWN            0x00

#define CHIP_732_TRIO32         0x01

#define CHIP_764_TRIO64         0x02

#define CHIP_765_TRIO64VP       0x03

#define CHIP_767_TRIO64UVP      0x04

#define CHIP_775_TRIO64V2_DX    0x05

#define CHIP_785_TRIO64V2_GX    0x06

#define CHIP_551_PLATO_PX       0x07

#define CHIP_M65_AURORA64VP     0x08

#define CHIP_325_VIRGE          0x09

#define CHIP_988_VIRGE_VX       0x0A

#define CHIP_375_VIRGE_DX       0x0B

#define CHIP_385_VIRGE_GX       0x0C

#define CHIP_356_VIRGE_GX2      0x0D

#define CHIP_357_VIRGE_GX2P     0x0E

#define CHIP_359_VIRGE_GX2P     0x0F

#define CHIP_XXX_TRIO           0x80

#define CHIP_XXX_TRIO64V2_DXGX  0x81

#define CHIP_XXX_VIRGE_DXGX     0x82

#define CHIP_UNDECIDED_FLAG     0x80

#define CHIP_MASK               0xFF

/* CRT timing register sets */

static const struct vga_regset s3_h_total_regs[]        = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};

static const struct vga_regset s3_h_display_regs[]      = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};

static const struct vga_regset s3_h_blank_start_regs[]  = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};

static const struct vga_regset s3_h_blank_end_regs[]    = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};

static const struct vga_regset s3_h_sync_start_regs[]   = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};

static const struct vga_regset s3_h_sync_end_regs[]     = {{0x05, 0, 4}, VGA_REGSET_END};

static const struct vga_regset s3_v_total_regs[]        = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};

static const struct vga_regset s3_v_display_regs[]      = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};

static const struct vga_regset s3_v_blank_start_regs[]  = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};

static const struct vga_regset s3_v_blank_end_regs[]    = {{0x16, 0, 7}, VGA_REGSET_END};

static const struct vga_regset s3_v_sync_start_regs[]   = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};

static const struct vga_regset s3_v_sync_end_regs[]     = {{0x11, 0, 3}, VGA_REGSET_END};

static const struct vga_regset s3_line_compare_regs[]   = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};

static const struct vga_regset s3_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};

static const struct vga_regset s3_offset_regs[]         = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */

static const struct svga_timing_regs s3_timing_regs     = {

        s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,

        s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,

        s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,

        s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,

};

/* ------------------------------------------------------------------------- */

/* Module parameters */

static char *mode = "640x480-8@60";

#ifdef CONFIG_MTRR

static int mtrr = 1;

#endif

static int fasttext = 1;

MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");

MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");

module_param(mode, charp, 0444);

MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");

#ifdef CONFIG_MTRR

module_param(mtrr, int, 0444);

MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");

#endif

module_param(fasttext, int, 0644);

MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");

/* ------------------------------------------------------------------------- */

/* Set font in S3 fast text mode */

static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)

{

        const u8 *font = map->data;

        u8 __iomem *fb = (u8 __iomem *) info->screen_base;

        int i, c;

        if ((map->width != 8) || (map->height != 16) ||

            (map->depth != 1) || (map->length != 256)) {

                printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",

                        info->node, map->width, map->height, map->depth, map->length);

                return;

        }

        fb += 2;

        for (i = 0; i < map->height; i++) {

                for (c = 0; c < map->length; c++) {

                        fb_writeb(font[c * map->height + i], fb + c * 4);

                }

                fb += 1024;

        }

}

static struct fb_tile_ops s3fb_tile_ops = {

        .fb_settile     = svga_settile,

        .fb_tilecopy    = svga_tilecopy,

        .fb_tilefill    = svga_tilefill,

        .fb_tileblit    = svga_tileblit,

        .fb_tilecursor  = svga_tilecursor,

        .fb_get_tilemax = svga_get_tilemax,

};

static struct fb_tile_ops s3fb_fast_tile_ops = {

        .fb_settile     = s3fb_settile_fast,

        .fb_tilecopy    = svga_tilecopy,

        .fb_tilefill    = svga_tilefill,

        .fb_tileblit    = svga_tileblit,

        .fb_tilecursor  = svga_tilecursor,

        .fb_get_tilemax = svga_get_tilemax,

};

/* ------------------------------------------------------------------------- */

/* image data is MSB-first, fb structure is MSB-first too */

static inline u32 expand_color(u32 c)

{

        return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;

}

/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */

static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)

{

        u32 fg = expand_color(image->fg_color);

        u32 bg = expand_color(image->bg_color);

        const u8 *src1, *src;

        u8 __iomem *dst1;

        u32 __iomem *dst;

        u32 val;

        int x, y;

        src1 = image->data;

        dst1 = info->screen_base + (image->dy * info->fix.line_length)

                 + ((image->dx / 8) * 4);

        for (y = 0; y < image->height; y++) {

                src = src1;

                dst = (u32 __iomem *) dst1;

                for (x = 0; x < image->width; x += 8) {

                        val = *(src++) * 0x01010101;

                        val = (val & fg) | (~val & bg);

                        fb_writel(val, dst++);

                }

                src1 += image->width / 8;

                dst1 += info->fix.line_length;

        }

}

/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */

static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)

{

        u32 fg = expand_color(rect->color);

        u8 __iomem *dst1;

        u32 __iomem *dst;

        int x, y;

        dst1 = info->screen_base + (rect->dy * info->fix.line_length)

                 + ((rect->dx / 8) * 4);

        for (y = 0; y < rect->height; y++) {

                dst = (u32 __iomem *) dst1;

                for (x = 0; x < rect->width; x += 8) {

                        fb_writel(fg, dst++);

                }

                dst1 += info->fix.line_length;

        }

}

/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */

static inline u32 expand_pixel(u32 c)

{

        return (((c &  1) << 24) | ((c &  2) << 27) | ((c &  4) << 14) | ((c &   8) << 17) |

                ((c & 16) <<  4) | ((c & 32) <<  7) | ((c & 64) >>  6) | ((c & 128) >>  3)) * 0xF;

}

/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */

static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)

{

        u32 fg = image->fg_color * 0x11111111;

        u32 bg = image->bg_color * 0x11111111;

        const u8 *src1, *src;

        u8 __iomem *dst1;

        u32 __iomem *dst;

        u32 val;

        int x, y;

        src1 = image->data;

        dst1 = info->screen_base + (image->dy * info->fix.line_length)

                 + ((image->dx / 8) * 4);

        for (y = 0; y < image->height; y++) {

                src = src1;

                dst = (u32 __iomem *) dst1;

                for (x = 0; x < image->width; x += 8) {

                        val = expand_pixel(*(src++));

                        val = (val & fg) | (~val & bg);

                        fb_writel(val, dst++);

                }

                src1 += image->width / 8;

                dst1 += info->fix.line_length;

        }

}

static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)

{

        if ((info->var.bits_per_pixel == 4) && (image->depth == 1)

            && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {

                if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)

                        s3fb_iplan_imageblit(info, image);

                else

                        s3fb_cfb4_imageblit(info, image);

        } else

                cfb_imageblit(info, image);

}

static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)

{

        if ((info->var.bits_per_pixel == 4)

            && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)

            && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))

                s3fb_iplan_fillrect(info, rect);

         else

                cfb_fillrect(info, rect);

}

/* ------------------------------------------------------------------------- */

static void s3_set_pixclock(struct fb_info *info, u32 pixclock)

{

        u16 m, n, r;

        u8 regval;

        int rv;

        rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);

        if (rv < 0) {

                printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);

                return;

        }

        /* Set VGA misc register  */

        regval = vga_r(NULL, VGA_MIS_R);

        vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);

        /* Set S3 clock registers */

        vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));

        vga_wseq(NULL, 0x13, m - 2);

        udelay(1000);

        /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */

        regval = vga_rseq (NULL, 0x15); /* | 0x80; */

        vga_wseq(NULL, 0x15, regval & ~(1<<5));

        vga_wseq(NULL, 0x15, regval |  (1<<5));

        vga_wseq(NULL, 0x15, regval & ~(1<<5));

}

/* Open framebuffer */

static int s3fb_open(struct fb_info *info, int user)

{

        struct s3fb_info *par = info->par;

        mutex_lock(&(par->open_lock));

        if (par->ref_count == 0) {

                memset(&(par->state), 0, sizeof(struct vgastate));

                par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;

                par->state.num_crtc = 0x70;

                par->state.num_seq = 0x20;

                save_vga(&(par->state));

        }

        par->ref_count++;

        mutex_unlock(&(par->open_lock));

        return 0;

}

/* Close framebuffer */

static int s3fb_release(struct fb_info *info, int user)

{

        struct s3fb_info *par = info->par;

        mutex_lock(&(par->open_lock));

        if (par->ref_count == 0) {

                mutex_unlock(&(par->open_lock));

                return -EINVAL;

        }

        if (par->ref_count == 1)

                restore_vga(&(par->state));

        par->ref_count--;

        mutex_unlock(&(par->open_lock));

        return 0;

}

/* Validate passed in var */

static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)

{

        struct s3fb_info *par = info->par;

        int rv, mem, step;

        u16 m, n, r;

        /* Find appropriate format */

        rv = svga_match_format (s3fb_formats, var, NULL);

        /* 32bpp mode is not supported on VIRGE VX,

           24bpp is not supported on others */

        if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))

                rv = -EINVAL;

        if (rv < 0) {

                printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);

                return rv;

        }

        /* Do not allow to have real resoulution larger than virtual */

        if (var->xres > var->xres_virtual)

                var->xres_virtual = var->xres;

        if (var->yres > var->yres_virtual)

                var->yres_virtual = var->yres;

        /* Round up xres_virtual to have proper alignment of lines */

        step = s3fb_formats[rv].xresstep - 1;

        var->xres_virtual = (var->xres_virtual+step) & ~step;

        /* Check whether have enough memory */

        mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;

        if (mem > info->screen_size) {

                printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",

                        info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));

                return -EINVAL;

        }

        rv = svga_check_timings (&s3_timing_regs, var, info->node);

        if (rv < 0) {

                printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);

                return rv;

        }

        rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,

                                info->node);

        if (rv < 0) {

                printk(KERN_ERR "fb%d: invalid pixclock value requested\n",

                        info->node);

                return rv;

        }

        return 0;

}

/* Set video mode from par */

static int s3fb_set_par(struct fb_info *info)

{

        struct s3fb_info *par = info->par;

        u32 value, mode, hmul, offset_value, screen_size, multiplex;

        u32 bpp = info->var.bits_per_pixel;

        if (bpp != 0) {

                info->fix.ypanstep = 1;

                info->fix.line_length = (info->var.xres_virtual * bpp) / 8;

                info->flags &= ~FBINFO_MISC_TILEBLITTING;

                info->tileops = NULL;

                /* in 4bpp supports 8p wide tiles only, any tiles otherwise */

                info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);

                info->pixmap.blit_y = ~(u32)0;

                offset_value = (info->var.xres_virtual * bpp) / 64;

                screen_size = info->var.yres_virtual * info->fix.line_length;

        } else {

                info->fix.ypanstep = 16;

                info->fix.line_length = 0;

                info->flags |= FBINFO_MISC_TILEBLITTING;

                info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;

                /* supports 8x16 tiles only */

                info->pixmap.blit_x = 1 << (8 - 1);

                info->pixmap.blit_y = 1 << (16 - 1);

                offset_value = info->var.xres_virtual / 16;

                screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;

        }

        info->var.xoffset = 0;

        info->var.yoffset = 0;

        info->var.activate = FB_ACTIVATE_NOW;

        /* Unlock registers */

        vga_wcrt(NULL, 0x38, 0x48);

        vga_wcrt(NULL, 0x39, 0xA5);

        vga_wseq(NULL, 0x08, 0x06);

        svga_wcrt_mask(0x11, 0x00, 0x80);

        /* Blank screen and turn off sync */

        svga_wseq_mask(0x01, 0x20, 0x20);

        svga_wcrt_mask(0x17, 0x00, 0x80);

        /* Set default values */

        svga_set_default_gfx_regs();

        svga_set_default_atc_regs();

        svga_set_default_seq_regs();

        svga_set_default_crt_regs();

        svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);

        svga_wcrt_multi(s3_start_address_regs, 0);

        /* S3 specific initialization */

        svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */

        svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */

/*      svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ?   */

/*      svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ?   */

        svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ?   */

        svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ?   */

        svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits

/*      svga_wcrt_mask(0x58, 0x03, 0x03); */

/*      svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */

/*      svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */

        /* Set the offset register */

        pr_debug("fb%d: offset register       : %d\n", info->node, offset_value);

        svga_wcrt_multi(s3_offset_regs, offset_value);

        vga_wcrt(NULL, 0x54, 0x18); /* M parameter */

        vga_wcrt(NULL, 0x60, 0xff); /* N parameter */

        vga_wcrt(NULL, 0x61, 0xff); /* L parameter */

        vga_wcrt(NULL, 0x62, 0xff); /* L parameter */

        vga_wcrt(NULL, 0x3A, 0x35);

        svga_wattr(0x33, 0x00);

        if (info->var.vmode & FB_VMODE_DOUBLE)

                svga_wcrt_mask(0x09, 0x80, 0x80);

        else

                svga_wcrt_mask(0x09, 0x00, 0x80);

        if (info->var.vmode & FB_VMODE_INTERLACED)

                svga_wcrt_mask(0x42, 0x20, 0x20);

        else

                svga_wcrt_mask(0x42, 0x00, 0x20);