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[/] [test_project/] [trunk/] [linux_sd_driver/] [include/] [linux/] [atmel-ssc.h] - Blame information for rev 81

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1 62 marcus.erl 
#ifndef __INCLUDE_ATMEL_SSC_H
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#define __INCLUDE_ATMEL_SSC_H
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#include <linux/platform_device.h>
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#include <linux/list.h>
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struct ssc_device {
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        struct list_head        list;
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        void __iomem            *regs;
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        struct platform_device  *pdev;
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        struct clk              *clk;
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        int                     user;
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        int                     irq;
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};
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struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
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void ssc_free(struct ssc_device *ssc);
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/* SSC register offsets */
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/* SSC Control Register */
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#define SSC_CR                          0x00000000
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#define SSC_CR_RXDIS_SIZE                        1
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#define SSC_CR_RXDIS_OFFSET                      1
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#define SSC_CR_RXEN_SIZE                         1
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#define SSC_CR_RXEN_OFFSET                       0
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#define SSC_CR_SWRST_SIZE                        1
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#define SSC_CR_SWRST_OFFSET                     15
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#define SSC_CR_TXDIS_SIZE                        1
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#define SSC_CR_TXDIS_OFFSET                      9
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#define SSC_CR_TXEN_SIZE                         1
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#define SSC_CR_TXEN_OFFSET                       8
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/* SSC Clock Mode Register */
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#define SSC_CMR                         0x00000004
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#define SSC_CMR_DIV_SIZE                        12
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#define SSC_CMR_DIV_OFFSET                       0
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/* SSC Receive Clock Mode Register */
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#define SSC_RCMR                        0x00000010
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#define SSC_RCMR_CKG_SIZE                        2
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#define SSC_RCMR_CKG_OFFSET                      6
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#define SSC_RCMR_CKI_SIZE                        1
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#define SSC_RCMR_CKI_OFFSET                      5
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#define SSC_RCMR_CKO_SIZE                        3
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#define SSC_RCMR_CKO_OFFSET                      2
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#define SSC_RCMR_CKS_SIZE                        2
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#define SSC_RCMR_CKS_OFFSET                      0
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#define SSC_RCMR_PERIOD_SIZE                     8
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#define SSC_RCMR_PERIOD_OFFSET                  24
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#define SSC_RCMR_START_SIZE                      4
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#define SSC_RCMR_START_OFFSET                    8
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#define SSC_RCMR_STOP_SIZE                       1
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#define SSC_RCMR_STOP_OFFSET                    12
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#define SSC_RCMR_STTDLY_SIZE                     8
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#define SSC_RCMR_STTDLY_OFFSET                  16
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/* SSC Receive Frame Mode Register */
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#define SSC_RFMR                        0x00000014
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#define SSC_RFMR_DATLEN_SIZE                     5
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#define SSC_RFMR_DATLEN_OFFSET                   0
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#define SSC_RFMR_DATNB_SIZE                      4
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#define SSC_RFMR_DATNB_OFFSET                    8
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#define SSC_RFMR_FSEDGE_SIZE                     1
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#define SSC_RFMR_FSEDGE_OFFSET                  24
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#define SSC_RFMR_FSLEN_SIZE                      4
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#define SSC_RFMR_FSLEN_OFFSET                   16
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#define SSC_RFMR_FSOS_SIZE                       4
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#define SSC_RFMR_FSOS_OFFSET                    20
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#define SSC_RFMR_LOOP_SIZE                       1
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#define SSC_RFMR_LOOP_OFFSET                     5
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#define SSC_RFMR_MSBF_SIZE                       1
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#define SSC_RFMR_MSBF_OFFSET                     7
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/* SSC Transmit Clock Mode Register */
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#define SSC_TCMR                        0x00000018
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#define SSC_TCMR_CKG_SIZE                        2
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#define SSC_TCMR_CKG_OFFSET                      6
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#define SSC_TCMR_CKI_SIZE                        1
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#define SSC_TCMR_CKI_OFFSET                      5
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#define SSC_TCMR_CKO_SIZE                        3
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#define SSC_TCMR_CKO_OFFSET                      2
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#define SSC_TCMR_CKS_SIZE                        2
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#define SSC_TCMR_CKS_OFFSET                      0
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#define SSC_TCMR_PERIOD_SIZE                     8
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#define SSC_TCMR_PERIOD_OFFSET                  24
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#define SSC_TCMR_START_SIZE                      4
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#define SSC_TCMR_START_OFFSET                    8
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#define SSC_TCMR_STTDLY_SIZE                     8
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#define SSC_TCMR_STTDLY_OFFSET                  16
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/* SSC Transmit Frame Mode Register */
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#define SSC_TFMR                        0x0000001c
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#define SSC_TFMR_DATDEF_SIZE                     1
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#define SSC_TFMR_DATDEF_OFFSET                   5
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#define SSC_TFMR_DATLEN_SIZE                     5
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#define SSC_TFMR_DATLEN_OFFSET                   0
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#define SSC_TFMR_DATNB_SIZE                      4
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#define SSC_TFMR_DATNB_OFFSET                    8
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#define SSC_TFMR_FSDEN_SIZE                      1
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#define SSC_TFMR_FSDEN_OFFSET                   23
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#define SSC_TFMR_FSEDGE_SIZE                     1
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#define SSC_TFMR_FSEDGE_OFFSET                  24
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#define SSC_TFMR_FSLEN_SIZE                      4
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#define SSC_TFMR_FSLEN_OFFSET                   16
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#define SSC_TFMR_FSOS_SIZE                       3
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#define SSC_TFMR_FSOS_OFFSET                    20
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#define SSC_TFMR_MSBF_SIZE                       1
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#define SSC_TFMR_MSBF_OFFSET                     7
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/* SSC Receive Hold Register */
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#define SSC_RHR                         0x00000020
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#define SSC_RHR_RDAT_SIZE                       32
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#define SSC_RHR_RDAT_OFFSET                      0
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/* SSC Transmit Hold Register */
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#define SSC_THR                         0x00000024
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#define SSC_THR_TDAT_SIZE                       32
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#define SSC_THR_TDAT_OFFSET                      0
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121 
/* SSC Receive Sync. Holding Register */
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#define SSC_RSHR                        0x00000030
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#define SSC_RSHR_RSDAT_SIZE                     16
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#define SSC_RSHR_RSDAT_OFFSET                    0
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/* SSC Transmit Sync. Holding Register */
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#define SSC_TSHR                        0x00000034
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#define SSC_TSHR_TSDAT_SIZE                     16
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#define SSC_TSHR_RSDAT_OFFSET                    0
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/* SSC Receive Compare 0 Register */
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#define SSC_RC0R                        0x00000038
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#define SSC_RC0R_CP0_SIZE                       16
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#define SSC_RC0R_CP0_OFFSET                      0
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/* SSC Receive Compare 1 Register */
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#define SSC_RC1R                        0x0000003c
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#define SSC_RC1R_CP1_SIZE                       16
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#define SSC_RC1R_CP1_OFFSET                      0
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141 
/* SSC Status Register */
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#define SSC_SR                          0x00000040
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#define SSC_SR_CP0_SIZE                          1
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#define SSC_SR_CP0_OFFSET                        8
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#define SSC_SR_CP1_SIZE                          1
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#define SSC_SR_CP1_OFFSET                        9
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#define SSC_SR_ENDRX_SIZE                        1
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#define SSC_SR_ENDRX_OFFSET                      6
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#define SSC_SR_ENDTX_SIZE                        1
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#define SSC_SR_ENDTX_OFFSET                      2
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#define SSC_SR_OVRUN_SIZE                        1
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#define SSC_SR_OVRUN_OFFSET                      5
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#define SSC_SR_RXBUFF_SIZE                       1
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#define SSC_SR_RXBUFF_OFFSET                     7
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#define SSC_SR_RXEN_SIZE                         1
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#define SSC_SR_RXEN_OFFSET                      17
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#define SSC_SR_RXRDY_SIZE                        1
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#define SSC_SR_RXRDY_OFFSET                      4
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#define SSC_SR_RXSYN_SIZE                        1
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#define SSC_SR_RXSYN_OFFSET                     11
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#define SSC_SR_TXBUFE_SIZE                       1
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#define SSC_SR_TXBUFE_OFFSET                     3
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#define SSC_SR_TXEMPTY_SIZE                      1
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#define SSC_SR_TXEMPTY_OFFSET                    1
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#define SSC_SR_TXEN_SIZE                         1
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#define SSC_SR_TXEN_OFFSET                      16
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#define SSC_SR_TXRDY_SIZE                        1
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#define SSC_SR_TXRDY_OFFSET                      0
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#define SSC_SR_TXSYN_SIZE                        1
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#define SSC_SR_TXSYN_OFFSET                     10
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/* SSC Interrupt Enable Register */
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#define SSC_IER                         0x00000044
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#define SSC_IER_CP0_SIZE                         1
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#define SSC_IER_CP0_OFFSET                       8
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#define SSC_IER_CP1_SIZE                         1
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#define SSC_IER_CP1_OFFSET                       9
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#define SSC_IER_ENDRX_SIZE                       1
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#define SSC_IER_ENDRX_OFFSET                     6
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#define SSC_IER_ENDTX_SIZE                       1
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#define SSC_IER_ENDTX_OFFSET                     2
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#define SSC_IER_OVRUN_SIZE                       1
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#define SSC_IER_OVRUN_OFFSET                     5
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#define SSC_IER_RXBUFF_SIZE                      1
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#define SSC_IER_RXBUFF_OFFSET                    7
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#define SSC_IER_RXRDY_SIZE                       1
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#define SSC_IER_RXRDY_OFFSET                     4
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#define SSC_IER_RXSYN_SIZE                       1
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#define SSC_IER_RXSYN_OFFSET                    11
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#define SSC_IER_TXBUFE_SIZE                      1
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#define SSC_IER_TXBUFE_OFFSET                    3
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#define SSC_IER_TXEMPTY_SIZE                     1
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#define SSC_IER_TXEMPTY_OFFSET                   1
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#define SSC_IER_TXRDY_SIZE                       1
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#define SSC_IER_TXRDY_OFFSET                     0
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#define SSC_IER_TXSYN_SIZE                       1
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#define SSC_IER_TXSYN_OFFSET                    10
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/* SSC Interrupt Disable Register */
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#define SSC_IDR                         0x00000048
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#define SSC_IDR_CP0_SIZE                         1
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#define SSC_IDR_CP0_OFFSET                       8
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#define SSC_IDR_CP1_SIZE                         1
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#define SSC_IDR_CP1_OFFSET                       9
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#define SSC_IDR_ENDRX_SIZE                       1
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#define SSC_IDR_ENDRX_OFFSET                     6
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#define SSC_IDR_ENDTX_SIZE                       1
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#define SSC_IDR_ENDTX_OFFSET                     2
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#define SSC_IDR_OVRUN_SIZE                       1
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#define SSC_IDR_OVRUN_OFFSET                     5
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#define SSC_IDR_RXBUFF_SIZE                      1
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#define SSC_IDR_RXBUFF_OFFSET                    7
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#define SSC_IDR_RXRDY_SIZE                       1
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#define SSC_IDR_RXRDY_OFFSET                     4
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#define SSC_IDR_RXSYN_SIZE                       1
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#define SSC_IDR_RXSYN_OFFSET                    11
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#define SSC_IDR_TXBUFE_SIZE                      1
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#define SSC_IDR_TXBUFE_OFFSET                    3
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#define SSC_IDR_TXEMPTY_SIZE                     1
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#define SSC_IDR_TXEMPTY_OFFSET                   1
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#define SSC_IDR_TXRDY_SIZE                       1
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#define SSC_IDR_TXRDY_OFFSET                     0
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#define SSC_IDR_TXSYN_SIZE                       1
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#define SSC_IDR_TXSYN_OFFSET                    10
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/* SSC Interrupt Mask Register */
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#define SSC_IMR                         0x0000004c
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#define SSC_IMR_CP0_SIZE                         1
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#define SSC_IMR_CP0_OFFSET                       8
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#define SSC_IMR_CP1_SIZE                         1
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#define SSC_IMR_CP1_OFFSET                       9
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#define SSC_IMR_ENDRX_SIZE                       1
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#define SSC_IMR_ENDRX_OFFSET                     6
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#define SSC_IMR_ENDTX_SIZE                       1
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#define SSC_IMR_ENDTX_OFFSET                     2
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#define SSC_IMR_OVRUN_SIZE                       1
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#define SSC_IMR_OVRUN_OFFSET                     5
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#define SSC_IMR_RXBUFF_SIZE                      1
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#define SSC_IMR_RXBUFF_OFFSET                    7
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#define SSC_IMR_RXRDY_SIZE                       1
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#define SSC_IMR_RXRDY_OFFSET                     4
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#define SSC_IMR_RXSYN_SIZE                       1
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#define SSC_IMR_RXSYN_OFFSET                    11
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#define SSC_IMR_TXBUFE_SIZE                      1
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#define SSC_IMR_TXBUFE_OFFSET                    3
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#define SSC_IMR_TXEMPTY_SIZE                     1
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#define SSC_IMR_TXEMPTY_OFFSET                   1
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#define SSC_IMR_TXRDY_SIZE                       1
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#define SSC_IMR_TXRDY_OFFSET                     0
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#define SSC_IMR_TXSYN_SIZE                       1
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#define SSC_IMR_TXSYN_OFFSET                    10
252 
 
253 
/* SSC PDC Receive Pointer Register */
254 
#define SSC_PDC_RPR                     0x00000100
255 
 
256 
/* SSC PDC Receive Counter Register */
257 
#define SSC_PDC_RCR                     0x00000104
258 
 
259 
/* SSC PDC Transmit Pointer Register */
260 
#define SSC_PDC_TPR                     0x00000108
261 
 
262 
/* SSC PDC Receive Next Pointer Register */
263 
#define SSC_PDC_RNPR                    0x00000110
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265 
/* SSC PDC Receive Next Counter Register */
266 
#define SSC_PDC_RNCR                    0x00000114
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268 
/* SSC PDC Transmit Counter Register */
269 
#define SSC_PDC_TCR                     0x0000010c
270 
 
271 
/* SSC PDC Transmit Next Pointer Register */
272 
#define SSC_PDC_TNPR                    0x00000118
273 
 
274 
/* SSC PDC Transmit Next Counter Register */
275 
#define SSC_PDC_TNCR                    0x0000011c
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277 
/* SSC PDC Transfer Control Register */
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#define SSC_PDC_PTCR                    0x00000120
279 
#define SSC_PDC_PTCR_RXTDIS_SIZE                 1
280 
#define SSC_PDC_PTCR_RXTDIS_OFFSET               1
281 
#define SSC_PDC_PTCR_RXTEN_SIZE                  1
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#define SSC_PDC_PTCR_RXTEN_OFFSET                0
283 
#define SSC_PDC_PTCR_TXTDIS_SIZE                 1
284 
#define SSC_PDC_PTCR_TXTDIS_OFFSET               9
285 
#define SSC_PDC_PTCR_TXTEN_SIZE                  1
286 
#define SSC_PDC_PTCR_TXTEN_OFFSET                8
287 
 
288 
/* SSC PDC Transfer Status Register */
289 
#define SSC_PDC_PTSR                    0x00000124
290 
#define SSC_PDC_PTSR_RXTEN_SIZE                  1
291 
#define SSC_PDC_PTSR_RXTEN_OFFSET                0
292 
#define SSC_PDC_PTSR_TXTEN_SIZE                  1
293 
#define SSC_PDC_PTSR_TXTEN_OFFSET                8
294 
 
295 
/* Bit manipulation macros */
296 
#define SSC_BIT(name)                                   \
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        (1 << SSC_##name##_OFFSET)
298 
#define SSC_BF(name, value)                             \
299 
        (((value) & ((1 << SSC_##name##_SIZE) - 1))     \
300 
         << SSC_##name##_OFFSET)
301 
#define SSC_BFEXT(name, value)                          \
302 
        (((value) >> SSC_##name##_OFFSET)               \
303 
         & ((1 << SSC_##name##_SIZE) - 1))
304 
#define SSC_BFINS(name, value, old)                     \
305 
        (((old) & ~(((1 << SSC_##name##_SIZE) - 1)      \
306 
        << SSC_##name##_OFFSET)) | SSC_BF(name, value))
307 
 
308 
/* Register access macros */
309 
#define ssc_readl(base, reg)            __raw_readl(base + SSC_##reg)
310 
#define ssc_writel(base, reg, value)    __raw_writel((value), base + SSC_##reg)
311 
 
312 
#endif /* __INCLUDE_ATMEL_SSC_H */

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