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[/] [test_project/] [trunk/] [linux_sd_driver/] [include/] [linux/] [mlx4/] [qp.h] - Blame information for rev 62

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/*
 * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
 
#ifndef MLX4_QP_H
#define MLX4_QP_H
 
#include <linux/types.h>
 
#include <linux/mlx4/device.h>
 
#define MLX4_INVALID_LKEY       0x100
 
enum mlx4_qp_optpar {
        MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
        MLX4_QP_OPTPAR_RRE                      = 1 << 1,
        MLX4_QP_OPTPAR_RAE                      = 1 << 2,
        MLX4_QP_OPTPAR_RWE                      = 1 << 3,
        MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
        MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
        MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
        MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
        MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
        MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
        MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
        MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
        MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
        MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
        MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16
};
 
enum mlx4_qp_state {
        MLX4_QP_STATE_RST                       = 0,
        MLX4_QP_STATE_INIT                      = 1,
        MLX4_QP_STATE_RTR                       = 2,
        MLX4_QP_STATE_RTS                       = 3,
        MLX4_QP_STATE_SQER                      = 4,
        MLX4_QP_STATE_SQD                       = 5,
        MLX4_QP_STATE_ERR                       = 6,
        MLX4_QP_STATE_SQ_DRAINING               = 7,
        MLX4_QP_NUM_STATE
};
 
enum {
        MLX4_QP_ST_RC                           = 0x0,
        MLX4_QP_ST_UC                           = 0x1,
        MLX4_QP_ST_RD                           = 0x2,
        MLX4_QP_ST_UD                           = 0x3,
        MLX4_QP_ST_MLX                          = 0x7
};
 
enum {
        MLX4_QP_PM_MIGRATED                     = 0x3,
        MLX4_QP_PM_ARMED                        = 0x0,
        MLX4_QP_PM_REARM                        = 0x1
};
 
enum {
        /* params1 */
        MLX4_QP_BIT_SRE                         = 1 << 15,
        MLX4_QP_BIT_SWE                         = 1 << 14,
        MLX4_QP_BIT_SAE                         = 1 << 13,
        /* params2 */
        MLX4_QP_BIT_RRE                         = 1 << 15,
        MLX4_QP_BIT_RWE                         = 1 << 14,
        MLX4_QP_BIT_RAE                         = 1 << 13,
        MLX4_QP_BIT_RIC                         = 1 <<  4,
};
 
struct mlx4_qp_path {
        u8                      fl;
        u8                      reserved1[2];
        u8                      pkey_index;
        u8                      reserved2;
        u8                      grh_mylmc;
        __be16                  rlid;
        u8                      ackto;
        u8                      mgid_index;
        u8                      static_rate;
        u8                      hop_limit;
        __be32                  tclass_flowlabel;
        u8                      rgid[16];
        u8                      sched_queue;
        u8                      snooper_flags;
        u8                      reserved3[2];
        u8                      counter_index;
        u8                      reserved4[7];
};
 
struct mlx4_qp_context {
        __be32                  flags;
        __be32                  pd;
        u8                      mtu_msgmax;
        u8                      rq_size_stride;
        u8                      sq_size_stride;
        u8                      rlkey;
        __be32                  usr_page;
        __be32                  local_qpn;
        __be32                  remote_qpn;
        struct                  mlx4_qp_path pri_path;
        struct                  mlx4_qp_path alt_path;
        __be32                  params1;
        u32                     reserved1;
        __be32                  next_send_psn;
        __be32                  cqn_send;
        u32                     reserved2[2];
        __be32                  last_acked_psn;
        __be32                  ssn;
        __be32                  params2;
        __be32                  rnr_nextrecvpsn;
        __be32                  srcd;
        __be32                  cqn_recv;
        __be64                  db_rec_addr;
        __be32                  qkey;
        __be32                  srqn;
        __be32                  msn;
        __be16                  rq_wqe_counter;
        __be16                  sq_wqe_counter;
        u32                     reserved3[2];
        __be32                  param3;
        __be32                  nummmcpeers_basemkey;
        u8                      log_page_size;
        u8                      reserved4[2];
        u8                      mtt_base_addr_h;
        __be32                  mtt_base_addr_l;
        u32                     reserved5[10];
};
 
enum {
        MLX4_WQE_CTRL_FENCE     = 1 << 6,
        MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
        MLX4_WQE_CTRL_SOLICITED = 1 << 1,
};
 
struct mlx4_wqe_ctrl_seg {
        __be32                  owner_opcode;
        u8                      reserved2[3];
        u8                      fence_size;
        /*
         * High 24 bits are SRC remote buffer; low 8 bits are flags:
         * [7]   SO (strong ordering)
         * [5]   TCP/UDP checksum
         * [4]   IP checksum
         * [3:2] C (generate completion queue entry)
         * [1]   SE (solicited event)
         */
        __be32                  srcrb_flags;
        /*
         * imm is immediate data for send/RDMA write w/ immediate;
         * also invalidation key for send with invalidate; input
         * modifier for WQEs on CCQs.
         */
        __be32                  imm;
};
 
enum {
        MLX4_WQE_MLX_VL15       = 1 << 17,
        MLX4_WQE_MLX_SLR        = 1 << 16
};
 
struct mlx4_wqe_mlx_seg {
        u8                      owner;
        u8                      reserved1[2];
        u8                      opcode;
        u8                      reserved2[3];
        u8                      size;
        /*
         * [17]    VL15
         * [16]    SLR
         * [15:12] static rate
         * [11:8]  SL
         * [4]     ICRC
         * [3:2]   C
         * [0]     FL (force loopback)
         */
        __be32                  flags;
        __be16                  rlid;
        u16                     reserved3;
};
 
struct mlx4_wqe_datagram_seg {
        __be32                  av[8];
        __be32                  dqpn;
        __be32                  qkey;
        __be32                  reservd[2];
};
 
struct mlx4_wqe_bind_seg {
        __be32                  flags1;
        __be32                  flags2;
        __be32                  new_rkey;
        __be32                  lkey;
        __be64                  addr;
        __be64                  length;
};
 
struct mlx4_wqe_fmr_seg {
        __be32                  flags;
        __be32                  mem_key;
        __be64                  buf_list;
        __be64                  start_addr;
        __be64                  reg_len;
        __be32                  offset;
        __be32                  page_size;
        u32                     reserved[2];
};
 
struct mlx4_wqe_fmr_ext_seg {
        u8                      flags;
        u8                      reserved;
        __be16                  app_mask;
        __be16                  wire_app_tag;
        __be16                  mem_app_tag;
        __be32                  wire_ref_tag_base;
        __be32                  mem_ref_tag_base;
};
 
struct mlx4_wqe_local_inval_seg {
        u8                      flags;
        u8                      reserved1[3];
        __be32                  mem_key;
        u8                      reserved2[3];
        u8                      guest_id;
        __be64                  pa;
};
 
struct mlx4_wqe_raddr_seg {
        __be64                  raddr;
        __be32                  rkey;
        u32                     reserved;
};
 
struct mlx4_wqe_atomic_seg {
        __be64                  swap_add;
        __be64                  compare;
};
 
struct mlx4_wqe_data_seg {
        __be32                  byte_count;
        __be32                  lkey;
        __be64                  addr;
};
 
enum {
        MLX4_INLINE_ALIGN       = 64,
};
 
struct mlx4_wqe_inline_seg {
        __be32                  byte_count;
};
 
int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
                   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
                   struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
                   int sqd_event, struct mlx4_qp *qp);
 
int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
                  struct mlx4_qp_context *context);
 
static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
{
        return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
}
 
void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 
#endif /* MLX4_QP_H */

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[/] [test_project/] [trunk/] [linux_sd_driver/] [include/] [linux/] [mlx4/] [qp.h] - Blame information for rev 62

Line No.	Rev	Author	Line
1	62	marcus.erl	`/*`
2			`* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.`
3			`*`
4			`* This software is available to you under a choice of one of two`
5			`* licenses. You may choose to be licensed under the terms of the GNU`
6			`* General Public License (GPL) Version 2, available from the file`
7			`* COPYING in the main directory of this source tree, or the`
8			`* OpenIB.org BSD license below:`
9			`*`
10			`* Redistribution and use in source and binary forms, with or`
11			`* without modification, are permitted provided that the following`
12			`* conditions are met:`
13			`*`
14			`* - Redistributions of source code must retain the above`
15			`* copyright notice, this list of conditions and the following`
16			`* disclaimer.`
17			`*`
18			`* - Redistributions in binary form must reproduce the above`
19			`* copyright notice, this list of conditions and the following`
20			`* disclaimer in the documentation and/or other materials`
21			`* provided with the distribution.`
22			`*`
23			`* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,`
24			`* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF`
25			`* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND`
26			`* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS`
27			`* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN`
28			`* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN`
29			`* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
30			`* SOFTWARE.`
31			`*/`
32
33			`#ifndef MLX4_QP_H`
34			`#define MLX4_QP_H`
35
36			`#include <linux/types.h>`
37
38			`#include <linux/mlx4/device.h>`
39
40			`#define MLX4_INVALID_LKEY 0x100`
41
42			`enum mlx4_qp_optpar {`
43			`MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,`
44			`MLX4_QP_OPTPAR_RRE = 1 << 1,`
45			`MLX4_QP_OPTPAR_RAE = 1 << 2,`
46			`MLX4_QP_OPTPAR_RWE = 1 << 3,`
47			`MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,`
48			`MLX4_QP_OPTPAR_Q_KEY = 1 << 5,`
49			`MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,`
50			`MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,`
51			`MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,`
52			`MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,`
53			`MLX4_QP_OPTPAR_PM_STATE = 1 << 10,`
54			`MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,`
55			`MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,`
56			`MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,`
57			`MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16`
58			`};`
59
60			`enum mlx4_qp_state {`
61			`MLX4_QP_STATE_RST = 0,`
62			`MLX4_QP_STATE_INIT = 1,`
63			`MLX4_QP_STATE_RTR = 2,`
64			`MLX4_QP_STATE_RTS = 3,`
65			`MLX4_QP_STATE_SQER = 4,`
66			`MLX4_QP_STATE_SQD = 5,`
67			`MLX4_QP_STATE_ERR = 6,`
68			`MLX4_QP_STATE_SQ_DRAINING = 7,`
69			`MLX4_QP_NUM_STATE`
70			`};`
71
72			`enum {`
73			`MLX4_QP_ST_RC = 0x0,`
74			`MLX4_QP_ST_UC = 0x1,`
75			`MLX4_QP_ST_RD = 0x2,`
76			`MLX4_QP_ST_UD = 0x3,`
77			`MLX4_QP_ST_MLX = 0x7`
78			`};`
79
80			`enum {`
81			`MLX4_QP_PM_MIGRATED = 0x3,`
82			`MLX4_QP_PM_ARMED = 0x0,`
83			`MLX4_QP_PM_REARM = 0x1`
84			`};`
85
86			`enum {`
87			`/* params1 */`
88			`MLX4_QP_BIT_SRE = 1 << 15,`
89			`MLX4_QP_BIT_SWE = 1 << 14,`
90			`MLX4_QP_BIT_SAE = 1 << 13,`
91			`/* params2 */`
92			`MLX4_QP_BIT_RRE = 1 << 15,`
93			`MLX4_QP_BIT_RWE = 1 << 14,`
94			`MLX4_QP_BIT_RAE = 1 << 13,`
95			`MLX4_QP_BIT_RIC = 1 << 4,`
96			`};`
97
98			`struct mlx4_qp_path {`
99			`u8 fl;`
100			`u8 reserved1[2];`
101			`u8 pkey_index;`
102			`u8 reserved2;`
103			`u8 grh_mylmc;`
104			`__be16 rlid;`
105			`u8 ackto;`
106			`u8 mgid_index;`
107			`u8 static_rate;`
108			`u8 hop_limit;`
109			`__be32 tclass_flowlabel;`
110			`u8 rgid[16];`
111			`u8 sched_queue;`
112			`u8 snooper_flags;`
113			`u8 reserved3[2];`
114			`u8 counter_index;`
115			`u8 reserved4[7];`
116			`};`
117
118			`struct mlx4_qp_context {`
119			`__be32 flags;`
120			`__be32 pd;`
121			`u8 mtu_msgmax;`
122			`u8 rq_size_stride;`
123			`u8 sq_size_stride;`
124			`u8 rlkey;`
125			`__be32 usr_page;`
126			`__be32 local_qpn;`
127			`__be32 remote_qpn;`
128			`struct mlx4_qp_path pri_path;`
129			`struct mlx4_qp_path alt_path;`
130			`__be32 params1;`
131			`u32 reserved1;`
132			`__be32 next_send_psn;`
133			`__be32 cqn_send;`
134			`u32 reserved2[2];`
135			`__be32 last_acked_psn;`
136			`__be32 ssn;`
137			`__be32 params2;`
138			`__be32 rnr_nextrecvpsn;`
139			`__be32 srcd;`
140			`__be32 cqn_recv;`
141			`__be64 db_rec_addr;`
142			`__be32 qkey;`
143			`__be32 srqn;`
144			`__be32 msn;`
145			`__be16 rq_wqe_counter;`
146			`__be16 sq_wqe_counter;`
147			`u32 reserved3[2];`
148			`__be32 param3;`
149			`__be32 nummmcpeers_basemkey;`
150			`u8 log_page_size;`
151			`u8 reserved4[2];`
152			`u8 mtt_base_addr_h;`
153			`__be32 mtt_base_addr_l;`
154			`u32 reserved5[10];`
155			`};`
156
157			`enum {`
158			`MLX4_WQE_CTRL_FENCE = 1 << 6,`
159			`MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,`
160			`MLX4_WQE_CTRL_SOLICITED = 1 << 1,`
161			`};`
162
163			`struct mlx4_wqe_ctrl_seg {`
164			`__be32 owner_opcode;`
165			`u8 reserved2[3];`
166			`u8 fence_size;`
167			`/*`
168			`* High 24 bits are SRC remote buffer; low 8 bits are flags:`
169			`* [7] SO (strong ordering)`
170			`* [5] TCP/UDP checksum`
171			`* [4] IP checksum`
172			`* [3:2] C (generate completion queue entry)`
173			`* [1] SE (solicited event)`
174			`*/`
175			`__be32 srcrb_flags;`
176			`/*`
177			`* imm is immediate data for send/RDMA write w/ immediate;`
178			`* also invalidation key for send with invalidate; input`
179			`* modifier for WQEs on CCQs.`
180			`*/`
181			`__be32 imm;`
182			`};`
183
184			`enum {`
185			`MLX4_WQE_MLX_VL15 = 1 << 17,`
186			`MLX4_WQE_MLX_SLR = 1 << 16`
187			`};`
188
189			`struct mlx4_wqe_mlx_seg {`
190			`u8 owner;`
191			`u8 reserved1[2];`
192			`u8 opcode;`
193			`u8 reserved2[3];`
194			`u8 size;`
195			`/*`
196			`* [17] VL15`
197			`* [16] SLR`
198			`* [15:12] static rate`
199			`* [11:8] SL`
200			`* [4] ICRC`
201			`* [3:2] C`
202			`* [0] FL (force loopback)`
203			`*/`
204			`__be32 flags;`
205			`__be16 rlid;`
206			`u16 reserved3;`
207			`};`
208
209			`struct mlx4_wqe_datagram_seg {`
210			`__be32 av[8];`
211			`__be32 dqpn;`
212			`__be32 qkey;`
213			`__be32 reservd[2];`
214			`};`
215
216			`struct mlx4_wqe_bind_seg {`
217			`__be32 flags1;`
218			`__be32 flags2;`
219			`__be32 new_rkey;`
220			`__be32 lkey;`
221			`__be64 addr;`
222			`__be64 length;`
223			`};`
224
225			`struct mlx4_wqe_fmr_seg {`
226			`__be32 flags;`
227			`__be32 mem_key;`
228			`__be64 buf_list;`
229			`__be64 start_addr;`
230			`__be64 reg_len;`
231			`__be32 offset;`
232			`__be32 page_size;`
233			`u32 reserved[2];`
234			`};`
235
236			`struct mlx4_wqe_fmr_ext_seg {`
237			`u8 flags;`
238			`u8 reserved;`
239			`__be16 app_mask;`
240			`__be16 wire_app_tag;`
241			`__be16 mem_app_tag;`
242			`__be32 wire_ref_tag_base;`
243			`__be32 mem_ref_tag_base;`
244			`};`
245
246			`struct mlx4_wqe_local_inval_seg {`
247			`u8 flags;`
248			`u8 reserved1[3];`
249			`__be32 mem_key;`
250			`u8 reserved2[3];`
251			`u8 guest_id;`
252			`__be64 pa;`
253			`};`
254
255			`struct mlx4_wqe_raddr_seg {`
256			`__be64 raddr;`
257			`__be32 rkey;`
258			`u32 reserved;`
259			`};`
260
261			`struct mlx4_wqe_atomic_seg {`
262			`__be64 swap_add;`
263			`__be64 compare;`
264			`};`
265
266			`struct mlx4_wqe_data_seg {`
267			`__be32 byte_count;`
268			`__be32 lkey;`
269			`__be64 addr;`
270			`};`
271
272			`enum {`
273			`MLX4_INLINE_ALIGN = 64,`
274			`};`
275
276			`struct mlx4_wqe_inline_seg {`
277			`__be32 byte_count;`
278			`};`
279
280			`int mlx4_qp_modify(struct mlx4_dev dev, struct mlx4_mtt mtt,`
281			`enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,`
282			`struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,`
283			`int sqd_event, struct mlx4_qp *qp);`
284
285			`int mlx4_qp_query(struct mlx4_dev dev, struct mlx4_qp qp,`
286			`struct mlx4_qp_context *context);`
287
288			`static inline struct mlx4_qp __mlx4_qp_lookup(struct mlx4_dev dev, u32 qpn)`
289			`{`
290			`return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));`
291			`}`
292
293			`void mlx4_qp_remove(struct mlx4_dev dev, struct mlx4_qp qp);`
294
295			`#endif /* MLX4_QP_H */`