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[/] [test_project/] [trunk/] [linux_sd_driver/] [include/] [linux/] [synclink.h] - Blame information for rev 62

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1 62 marcus.erl
/*
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 * SyncLink Multiprotocol Serial Adapter Driver
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 *
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 * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $
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 *
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 * Copyright (C) 1998-2000 by Microgate Corporation
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 *
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 * Redistribution of this file is permitted under
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 * the terms of the GNU Public License (GPL)
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 */
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#ifndef _SYNCLINK_H_
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#define _SYNCLINK_H_
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#define SYNCLINK_H_VERSION 3.6
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#define BOOLEAN int
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#define TRUE 1
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#define FALSE 0
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#define BIT0    0x0001
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#define BIT1    0x0002
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#define BIT2    0x0004
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#define BIT3    0x0008
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#define BIT4    0x0010
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#define BIT5    0x0020
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#define BIT6    0x0040
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#define BIT7    0x0080
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#define BIT8    0x0100
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#define BIT9    0x0200
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#define BIT10   0x0400
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#define BIT11   0x0800
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#define BIT12   0x1000
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#define BIT13   0x2000
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#define BIT14   0x4000
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#define BIT15   0x8000
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#define BIT16   0x00010000
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#define BIT17   0x00020000
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#define BIT18   0x00040000
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#define BIT19   0x00080000
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#define BIT20   0x00100000
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#define BIT21   0x00200000
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#define BIT22   0x00400000
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#define BIT23   0x00800000
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#define BIT24   0x01000000
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#define BIT25   0x02000000
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#define BIT26   0x04000000
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#define BIT27   0x08000000
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#define BIT28   0x10000000
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#define BIT29   0x20000000
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#define BIT30   0x40000000
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#define BIT31   0x80000000
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#define HDLC_MAX_FRAME_SIZE     65535
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#define MAX_ASYNC_TRANSMIT      4096
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#define MAX_ASYNC_BUFFER_SIZE   4096
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#define ASYNC_PARITY_NONE               0
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#define ASYNC_PARITY_EVEN               1
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#define ASYNC_PARITY_ODD                2
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#define ASYNC_PARITY_SPACE              3
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#define HDLC_FLAG_UNDERRUN_ABORT7       0x0000
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#define HDLC_FLAG_UNDERRUN_ABORT15      0x0001
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#define HDLC_FLAG_UNDERRUN_FLAG         0x0002
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#define HDLC_FLAG_UNDERRUN_CRC          0x0004
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#define HDLC_FLAG_SHARE_ZERO            0x0010
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#define HDLC_FLAG_AUTO_CTS              0x0020
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#define HDLC_FLAG_AUTO_DCD              0x0040
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#define HDLC_FLAG_AUTO_RTS              0x0080
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#define HDLC_FLAG_RXC_DPLL              0x0100
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#define HDLC_FLAG_RXC_BRG               0x0200
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#define HDLC_FLAG_RXC_TXCPIN            0x8000
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#define HDLC_FLAG_RXC_RXCPIN            0x0000
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#define HDLC_FLAG_TXC_DPLL              0x0400
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#define HDLC_FLAG_TXC_BRG               0x0800
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#define HDLC_FLAG_TXC_TXCPIN            0x0000
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#define HDLC_FLAG_TXC_RXCPIN            0x0008
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#define HDLC_FLAG_DPLL_DIV8             0x1000
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#define HDLC_FLAG_DPLL_DIV16            0x2000
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#define HDLC_FLAG_DPLL_DIV32            0x0000
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#define HDLC_FLAG_HDLC_LOOPMODE         0x4000
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#define HDLC_CRC_NONE                   0
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#define HDLC_CRC_16_CCITT               1
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#define HDLC_CRC_32_CCITT               2
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#define HDLC_CRC_MASK                   0x00ff
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#define HDLC_CRC_RETURN_EX              0x8000
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#define RX_OK                           0
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#define RX_CRC_ERROR                    1
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#define HDLC_TXIDLE_FLAGS               0
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#define HDLC_TXIDLE_ALT_ZEROS_ONES      1
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#define HDLC_TXIDLE_ZEROS               2
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#define HDLC_TXIDLE_ONES                3
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#define HDLC_TXIDLE_ALT_MARK_SPACE      4
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#define HDLC_TXIDLE_SPACE               5
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#define HDLC_TXIDLE_MARK                6
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#define HDLC_TXIDLE_CUSTOM_8            0x10000000
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#define HDLC_TXIDLE_CUSTOM_16           0x20000000
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#define HDLC_ENCODING_NRZ                       0
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#define HDLC_ENCODING_NRZB                      1
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#define HDLC_ENCODING_NRZI_MARK                 2
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#define HDLC_ENCODING_NRZI_SPACE                3
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#define HDLC_ENCODING_NRZI                      HDLC_ENCODING_NRZI_SPACE
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#define HDLC_ENCODING_BIPHASE_MARK              4
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#define HDLC_ENCODING_BIPHASE_SPACE             5
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#define HDLC_ENCODING_BIPHASE_LEVEL             6
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#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL        7
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#define HDLC_PREAMBLE_LENGTH_8BITS      0
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#define HDLC_PREAMBLE_LENGTH_16BITS     1
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#define HDLC_PREAMBLE_LENGTH_32BITS     2
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#define HDLC_PREAMBLE_LENGTH_64BITS     3
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#define HDLC_PREAMBLE_PATTERN_NONE      0
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#define HDLC_PREAMBLE_PATTERN_ZEROS     1
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#define HDLC_PREAMBLE_PATTERN_FLAGS     2
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#define HDLC_PREAMBLE_PATTERN_10        3
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#define HDLC_PREAMBLE_PATTERN_01        4
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#define HDLC_PREAMBLE_PATTERN_ONES      5
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#define MGSL_MODE_ASYNC         1
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#define MGSL_MODE_HDLC          2
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#define MGSL_MODE_MONOSYNC      3
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#define MGSL_MODE_BISYNC        4
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#define MGSL_MODE_RAW           6
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#define MGSL_BUS_TYPE_ISA       1
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#define MGSL_BUS_TYPE_EISA      2
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#define MGSL_BUS_TYPE_PCI       5
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#define MGSL_INTERFACE_MASK     0xf
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#define MGSL_INTERFACE_DISABLE  0
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#define MGSL_INTERFACE_RS232    1
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#define MGSL_INTERFACE_V35      2
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#define MGSL_INTERFACE_RS422    3
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#define MGSL_INTERFACE_RTS_EN   0x10
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#define MGSL_INTERFACE_LL       0x20
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#define MGSL_INTERFACE_RL       0x40
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typedef struct _MGSL_PARAMS
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{
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        /* Common */
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        unsigned long   mode;           /* Asynchronous or HDLC */
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        unsigned char   loopback;       /* internal loopback mode */
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        /* HDLC Only */
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        unsigned short  flags;
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        unsigned char   encoding;       /* NRZ, NRZI, etc. */
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        unsigned long   clock_speed;    /* external clock speed in bits per second */
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        unsigned char   addr_filter;    /* receive HDLC address filter, 0xFF = disable */
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        unsigned short  crc_type;       /* None, CRC16-CCITT, or CRC32-CCITT */
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        unsigned char   preamble_length;
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        unsigned char   preamble;
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        /* Async Only */
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        unsigned long   data_rate;      /* bits per second */
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        unsigned char   data_bits;      /* 7 or 8 data bits */
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        unsigned char   stop_bits;      /* 1 or 2 stop bits */
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        unsigned char   parity;         /* none, even, or odd */
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} MGSL_PARAMS, *PMGSL_PARAMS;
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#define MICROGATE_VENDOR_ID 0x13c0
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#define SYNCLINK_DEVICE_ID 0x0010
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#define MGSCC_DEVICE_ID 0x0020
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#define SYNCLINK_SCA_DEVICE_ID 0x0030
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#define SYNCLINK_GT_DEVICE_ID 0x0070
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#define SYNCLINK_GT4_DEVICE_ID 0x0080
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#define SYNCLINK_AC_DEVICE_ID  0x0090
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#define SYNCLINK_GT2_DEVICE_ID 0x00A0
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#define MGSL_MAX_SERIAL_NUMBER 30
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180
/*
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** device diagnostics status
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*/
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#define DiagStatus_OK                           0
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#define DiagStatus_AddressFailure               1
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#define DiagStatus_AddressConflict              2
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#define DiagStatus_IrqFailure                   3
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#define DiagStatus_IrqConflict                  4
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#define DiagStatus_DmaFailure                   5
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#define DiagStatus_DmaConflict                  6
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#define DiagStatus_PciAdapterNotFound           7
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#define DiagStatus_CantAssignPciResources       8
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#define DiagStatus_CantAssignPciMemAddr         9
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#define DiagStatus_CantAssignPciIoAddr          10
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#define DiagStatus_CantAssignPciIrq             11
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#define DiagStatus_MemoryError                  12
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#define SerialSignal_DCD            0x01     /* Data Carrier Detect */
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#define SerialSignal_TXD            0x02     /* Transmit Data */
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#define SerialSignal_RI             0x04     /* Ring Indicator */
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#define SerialSignal_RXD            0x08     /* Receive Data */
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#define SerialSignal_CTS            0x10     /* Clear to Send */
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#define SerialSignal_RTS            0x20     /* Request to Send */
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#define SerialSignal_DSR            0x40     /* Data Set Ready */
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#define SerialSignal_DTR            0x80     /* Data Terminal Ready */
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/*
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 * Counters of the input lines (CTS, DSR, RI, CD) interrupts
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 */
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struct mgsl_icount {
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        __u32   cts, dsr, rng, dcd, tx, rx;
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        __u32   frame, parity, overrun, brk;
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        __u32   buf_overrun;
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        __u32   txok;
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        __u32   txunder;
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        __u32   txabort;
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        __u32   txtimeout;
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        __u32   rxshort;
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        __u32   rxlong;
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        __u32   rxabort;
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        __u32   rxover;
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        __u32   rxcrc;
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        __u32   rxok;
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        __u32   exithunt;
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        __u32   rxidle;
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};
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struct gpio_desc {
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        __u32 state;
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        __u32 smask;
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        __u32 dir;
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        __u32 dmask;
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};
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#define DEBUG_LEVEL_DATA        1
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#define DEBUG_LEVEL_ERROR       2
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#define DEBUG_LEVEL_INFO        3
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#define DEBUG_LEVEL_BH          4
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#define DEBUG_LEVEL_ISR         5
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242
/*
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** Event bit flags for use with MgslWaitEvent
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*/
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#define MgslEvent_DsrActive     0x0001
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#define MgslEvent_DsrInactive   0x0002
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#define MgslEvent_Dsr           0x0003
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#define MgslEvent_CtsActive     0x0004
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#define MgslEvent_CtsInactive   0x0008
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#define MgslEvent_Cts           0x000c
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#define MgslEvent_DcdActive     0x0010
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#define MgslEvent_DcdInactive   0x0020
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#define MgslEvent_Dcd           0x0030
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#define MgslEvent_RiActive      0x0040
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#define MgslEvent_RiInactive    0x0080
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#define MgslEvent_Ri            0x00c0
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#define MgslEvent_ExitHuntMode  0x0100
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#define MgslEvent_IdleReceived  0x0200
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/* Private IOCTL codes:
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 *
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 * MGSL_IOCSPARAMS      set MGSL_PARAMS structure values
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 * MGSL_IOCGPARAMS      get current MGSL_PARAMS structure values
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 * MGSL_IOCSTXIDLE      set current transmit idle mode
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 * MGSL_IOCGTXIDLE      get current transmit idle mode
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 * MGSL_IOCTXENABLE     enable or disable transmitter
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 * MGSL_IOCRXENABLE     enable or disable receiver
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 * MGSL_IOCTXABORT      abort transmitting frame (HDLC)
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 * MGSL_IOCGSTATS       return current statistics
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 * MGSL_IOCWAITEVENT    wait for specified event to occur
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 * MGSL_LOOPTXDONE      transmit in HDLC LoopMode done
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 * MGSL_IOCSIF          set the serial interface type
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 * MGSL_IOCGIF          get the serial interface type
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 */
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#define MGSL_MAGIC_IOC  'm'
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#define MGSL_IOCSPARAMS         _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS)
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#define MGSL_IOCGPARAMS         _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS)
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#define MGSL_IOCSTXIDLE         _IO(MGSL_MAGIC_IOC,2)
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#define MGSL_IOCGTXIDLE         _IO(MGSL_MAGIC_IOC,3)
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#define MGSL_IOCTXENABLE        _IO(MGSL_MAGIC_IOC,4)
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#define MGSL_IOCRXENABLE        _IO(MGSL_MAGIC_IOC,5)
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#define MGSL_IOCTXABORT         _IO(MGSL_MAGIC_IOC,6)
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#define MGSL_IOCGSTATS          _IO(MGSL_MAGIC_IOC,7)
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#define MGSL_IOCWAITEVENT       _IOWR(MGSL_MAGIC_IOC,8,int)
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#define MGSL_IOCCLRMODCOUNT     _IO(MGSL_MAGIC_IOC,15)
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#define MGSL_IOCLOOPTXDONE      _IO(MGSL_MAGIC_IOC,9)
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#define MGSL_IOCSIF             _IO(MGSL_MAGIC_IOC,10)
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#define MGSL_IOCGIF             _IO(MGSL_MAGIC_IOC,11)
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#define MGSL_IOCSGPIO           _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc)
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#define MGSL_IOCGGPIO           _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc)
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#define MGSL_IOCWAITGPIO        _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc)
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294
#ifdef __KERNEL__
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/* provide 32 bit ioctl compatibility on 64 bit systems */
296
#ifdef CONFIG_COMPAT
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#include <linux/compat.h>
298
struct MGSL_PARAMS32 {
299
        compat_ulong_t  mode;
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        unsigned char   loopback;
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        unsigned short  flags;
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        unsigned char   encoding;
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        compat_ulong_t  clock_speed;
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        unsigned char   addr_filter;
305
        unsigned short  crc_type;
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        unsigned char   preamble_length;
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        unsigned char   preamble;
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        compat_ulong_t  data_rate;
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        unsigned char   data_bits;
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        unsigned char   stop_bits;
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        unsigned char   parity;
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};
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#define MGSL_IOCSPARAMS32 _IOW(MGSL_MAGIC_IOC,0,struct MGSL_PARAMS32)
314
#define MGSL_IOCGPARAMS32 _IOR(MGSL_MAGIC_IOC,1,struct MGSL_PARAMS32)
315
#endif
316
#endif
317
 
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#endif /* _SYNCLINK_H_ */

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