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marcus.erl |
/*
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* ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
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* interfaces
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*
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* Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
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*
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* Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
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* code.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <sound/driver.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/moduleparam.h>
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#include <sound/core.h>
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#include <sound/info.h>
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#include <sound/control.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/asoundef.h>
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#include <sound/initval.h>
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#include <asm/io.h>
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/* note, two last pcis should be equal, it is not a bug */
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MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
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MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
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"Digi96/8 PAD");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
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"{RME,Digi96/8},"
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"{RME,Digi96/8 PRO},"
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"{RME,Digi96/8 PST},"
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"{RME,Digi96/8 PAD}}");
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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
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static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
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static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
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module_param_array(enable, bool, NULL, 0444);
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MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
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/*
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* Defines for RME Digi96 series, from internal RME reference documents
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* dated 12.01.00
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*/
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#define RME96_SPDIF_NCHANNELS 2
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/* Playback and capture buffer size */
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#define RME96_BUFFER_SIZE 0x10000
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/* IO area size */
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#define RME96_IO_SIZE 0x60000
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/* IO area offsets */
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#define RME96_IO_PLAY_BUFFER 0x0
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#define RME96_IO_REC_BUFFER 0x10000
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#define RME96_IO_CONTROL_REGISTER 0x20000
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#define RME96_IO_ADDITIONAL_REG 0x20004
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#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
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#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
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#define RME96_IO_SET_PLAY_POS 0x40000
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#define RME96_IO_RESET_PLAY_POS 0x4FFFC
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#define RME96_IO_SET_REC_POS 0x50000
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#define RME96_IO_RESET_REC_POS 0x5FFFC
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#define RME96_IO_GET_PLAY_POS 0x20000
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#define RME96_IO_GET_REC_POS 0x30000
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/* Write control register bits */
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#define RME96_WCR_START (1 << 0)
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#define RME96_WCR_START_2 (1 << 1)
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#define RME96_WCR_GAIN_0 (1 << 2)
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#define RME96_WCR_GAIN_1 (1 << 3)
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#define RME96_WCR_MODE24 (1 << 4)
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#define RME96_WCR_MODE24_2 (1 << 5)
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#define RME96_WCR_BM (1 << 6)
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#define RME96_WCR_BM_2 (1 << 7)
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#define RME96_WCR_ADAT (1 << 8)
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#define RME96_WCR_FREQ_0 (1 << 9)
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#define RME96_WCR_FREQ_1 (1 << 10)
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#define RME96_WCR_DS (1 << 11)
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#define RME96_WCR_PRO (1 << 12)
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#define RME96_WCR_EMP (1 << 13)
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#define RME96_WCR_SEL (1 << 14)
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#define RME96_WCR_MASTER (1 << 15)
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#define RME96_WCR_PD (1 << 16)
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#define RME96_WCR_INP_0 (1 << 17)
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#define RME96_WCR_INP_1 (1 << 18)
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#define RME96_WCR_THRU_0 (1 << 19)
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#define RME96_WCR_THRU_1 (1 << 20)
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#define RME96_WCR_THRU_2 (1 << 21)
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#define RME96_WCR_THRU_3 (1 << 22)
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#define RME96_WCR_THRU_4 (1 << 23)
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#define RME96_WCR_THRU_5 (1 << 24)
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#define RME96_WCR_THRU_6 (1 << 25)
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#define RME96_WCR_THRU_7 (1 << 26)
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#define RME96_WCR_DOLBY (1 << 27)
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#define RME96_WCR_MONITOR_0 (1 << 28)
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#define RME96_WCR_MONITOR_1 (1 << 29)
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#define RME96_WCR_ISEL (1 << 30)
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#define RME96_WCR_IDIS (1 << 31)
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#define RME96_WCR_BITPOS_GAIN_0 2
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#define RME96_WCR_BITPOS_GAIN_1 3
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#define RME96_WCR_BITPOS_FREQ_0 9
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#define RME96_WCR_BITPOS_FREQ_1 10
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#define RME96_WCR_BITPOS_INP_0 17
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#define RME96_WCR_BITPOS_INP_1 18
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#define RME96_WCR_BITPOS_MONITOR_0 28
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#define RME96_WCR_BITPOS_MONITOR_1 29
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/* Read control register bits */
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#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
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#define RME96_RCR_IRQ_2 (1 << 16)
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#define RME96_RCR_T_OUT (1 << 17)
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#define RME96_RCR_DEV_ID_0 (1 << 21)
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#define RME96_RCR_DEV_ID_1 (1 << 22)
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#define RME96_RCR_LOCK (1 << 23)
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#define RME96_RCR_VERF (1 << 26)
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#define RME96_RCR_F0 (1 << 27)
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#define RME96_RCR_F1 (1 << 28)
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#define RME96_RCR_F2 (1 << 29)
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#define RME96_RCR_AUTOSYNC (1 << 30)
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#define RME96_RCR_IRQ (1 << 31)
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#define RME96_RCR_BITPOS_F0 27
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#define RME96_RCR_BITPOS_F1 28
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#define RME96_RCR_BITPOS_F2 29
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/* Additonal register bits */
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#define RME96_AR_WSEL (1 << 0)
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#define RME96_AR_ANALOG (1 << 1)
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#define RME96_AR_FREQPAD_0 (1 << 2)
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#define RME96_AR_FREQPAD_1 (1 << 3)
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#define RME96_AR_FREQPAD_2 (1 << 4)
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#define RME96_AR_PD2 (1 << 5)
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#define RME96_AR_DAC_EN (1 << 6)
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#define RME96_AR_CLATCH (1 << 7)
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#define RME96_AR_CCLK (1 << 8)
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#define RME96_AR_CDATA (1 << 9)
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#define RME96_AR_BITPOS_F0 2
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#define RME96_AR_BITPOS_F1 3
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#define RME96_AR_BITPOS_F2 4
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/* Monitor tracks */
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#define RME96_MONITOR_TRACKS_1_2 0
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#define RME96_MONITOR_TRACKS_3_4 1
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#define RME96_MONITOR_TRACKS_5_6 2
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#define RME96_MONITOR_TRACKS_7_8 3
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/* Attenuation */
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#define RME96_ATTENUATION_0 0
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#define RME96_ATTENUATION_6 1
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#define RME96_ATTENUATION_12 2
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#define RME96_ATTENUATION_18 3
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/* Input types */
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#define RME96_INPUT_OPTICAL 0
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#define RME96_INPUT_COAXIAL 1
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#define RME96_INPUT_INTERNAL 2
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#define RME96_INPUT_XLR 3
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#define RME96_INPUT_ANALOG 4
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/* Clock modes */
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#define RME96_CLOCKMODE_SLAVE 0
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#define RME96_CLOCKMODE_MASTER 1
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#define RME96_CLOCKMODE_WORDCLOCK 2
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/* Block sizes in bytes */
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#define RME96_SMALL_BLOCK_SIZE 2048
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#define RME96_LARGE_BLOCK_SIZE 8192
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/* Volume control */
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#define RME96_AD1852_VOL_BITS 14
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#define RME96_AD1855_VOL_BITS 10
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struct rme96 {
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spinlock_t lock;
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int irq;
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unsigned long port;
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void __iomem *iobase;
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u32 wcreg; /* cached write control register value */
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u32 wcreg_spdif; /* S/PDIF setup */
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u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
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u32 rcreg; /* cached read control register value */
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u32 areg; /* cached additional register value */
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u16 vol[2]; /* cached volume of analog output */
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u8 rev; /* card revision number */
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struct snd_pcm_substream *playback_substream;
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struct snd_pcm_substream *capture_substream;
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int playback_frlog; /* log2 of framesize */
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int capture_frlog;
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size_t playback_periodsize; /* in bytes, zero if not used */
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size_t capture_periodsize; /* in bytes, zero if not used */
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struct snd_card *card;
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struct snd_pcm *spdif_pcm;
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struct snd_pcm *adat_pcm;
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struct pci_dev *pci;
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struct snd_kcontrol *spdif_ctl;
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};
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static struct pci_device_id snd_rme96_ids[] = {
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{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
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{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
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{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
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{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
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#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
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#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
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#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
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#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
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(rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
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#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
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#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
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((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
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#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
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static int
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snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
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static int
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snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
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static int
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snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
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int cmd);
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static int
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snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
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int cmd);
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static snd_pcm_uframes_t
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snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
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static snd_pcm_uframes_t
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snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
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static void __devinit
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snd_rme96_proc_init(struct rme96 *rme96);
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static int
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snd_rme96_create_switches(struct snd_card *card,
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struct rme96 *rme96);
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static int
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snd_rme96_getinputtype(struct rme96 *rme96);
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static inline unsigned int
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snd_rme96_playback_ptr(struct rme96 *rme96)
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{
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return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
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& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
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}
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static inline unsigned int
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snd_rme96_capture_ptr(struct rme96 *rme96)
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{
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return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
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& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
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}
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static int
|
304 |
|
|
snd_rme96_playback_silence(struct snd_pcm_substream *substream,
|
305 |
|
|
int channel, /* not used (interleaved data) */
|
306 |
|
|
snd_pcm_uframes_t pos,
|
307 |
|
|
snd_pcm_uframes_t count)
|
308 |
|
|
{
|
309 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
310 |
|
|
count <<= rme96->playback_frlog;
|
311 |
|
|
pos <<= rme96->playback_frlog;
|
312 |
|
|
memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
|
313 |
|
|
0, count);
|
314 |
|
|
return 0;
|
315 |
|
|
}
|
316 |
|
|
|
317 |
|
|
static int
|
318 |
|
|
snd_rme96_playback_copy(struct snd_pcm_substream *substream,
|
319 |
|
|
int channel, /* not used (interleaved data) */
|
320 |
|
|
snd_pcm_uframes_t pos,
|
321 |
|
|
void __user *src,
|
322 |
|
|
snd_pcm_uframes_t count)
|
323 |
|
|
{
|
324 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
325 |
|
|
count <<= rme96->playback_frlog;
|
326 |
|
|
pos <<= rme96->playback_frlog;
|
327 |
|
|
copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
|
328 |
|
|
count);
|
329 |
|
|
return 0;
|
330 |
|
|
}
|
331 |
|
|
|
332 |
|
|
static int
|
333 |
|
|
snd_rme96_capture_copy(struct snd_pcm_substream *substream,
|
334 |
|
|
int channel, /* not used (interleaved data) */
|
335 |
|
|
snd_pcm_uframes_t pos,
|
336 |
|
|
void __user *dst,
|
337 |
|
|
snd_pcm_uframes_t count)
|
338 |
|
|
{
|
339 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
340 |
|
|
count <<= rme96->capture_frlog;
|
341 |
|
|
pos <<= rme96->capture_frlog;
|
342 |
|
|
copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
|
343 |
|
|
count);
|
344 |
|
|
return 0;
|
345 |
|
|
}
|
346 |
|
|
|
347 |
|
|
/*
|
348 |
|
|
* Digital output capabilities (S/PDIF)
|
349 |
|
|
*/
|
350 |
|
|
static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
|
351 |
|
|
{
|
352 |
|
|
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
|
353 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
354 |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
355 |
|
|
SNDRV_PCM_INFO_PAUSE),
|
356 |
|
|
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
357 |
|
|
SNDRV_PCM_FMTBIT_S32_LE),
|
358 |
|
|
.rates = (SNDRV_PCM_RATE_32000 |
|
359 |
|
|
SNDRV_PCM_RATE_44100 |
|
360 |
|
|
SNDRV_PCM_RATE_48000 |
|
361 |
|
|
SNDRV_PCM_RATE_64000 |
|
362 |
|
|
SNDRV_PCM_RATE_88200 |
|
363 |
|
|
SNDRV_PCM_RATE_96000),
|
364 |
|
|
.rate_min = 32000,
|
365 |
|
|
.rate_max = 96000,
|
366 |
|
|
.channels_min = 2,
|
367 |
|
|
.channels_max = 2,
|
368 |
|
|
.buffer_bytes_max = RME96_BUFFER_SIZE,
|
369 |
|
|
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
|
370 |
|
|
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
|
371 |
|
|
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
|
372 |
|
|
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
|
373 |
|
|
.fifo_size = 0,
|
374 |
|
|
};
|
375 |
|
|
|
376 |
|
|
/*
|
377 |
|
|
* Digital input capabilities (S/PDIF)
|
378 |
|
|
*/
|
379 |
|
|
static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
|
380 |
|
|
{
|
381 |
|
|
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
|
382 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
383 |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
384 |
|
|
SNDRV_PCM_INFO_PAUSE),
|
385 |
|
|
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
386 |
|
|
SNDRV_PCM_FMTBIT_S32_LE),
|
387 |
|
|
.rates = (SNDRV_PCM_RATE_32000 |
|
388 |
|
|
SNDRV_PCM_RATE_44100 |
|
389 |
|
|
SNDRV_PCM_RATE_48000 |
|
390 |
|
|
SNDRV_PCM_RATE_64000 |
|
391 |
|
|
SNDRV_PCM_RATE_88200 |
|
392 |
|
|
SNDRV_PCM_RATE_96000),
|
393 |
|
|
.rate_min = 32000,
|
394 |
|
|
.rate_max = 96000,
|
395 |
|
|
.channels_min = 2,
|
396 |
|
|
.channels_max = 2,
|
397 |
|
|
.buffer_bytes_max = RME96_BUFFER_SIZE,
|
398 |
|
|
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
|
399 |
|
|
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
|
400 |
|
|
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
|
401 |
|
|
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
|
402 |
|
|
.fifo_size = 0,
|
403 |
|
|
};
|
404 |
|
|
|
405 |
|
|
/*
|
406 |
|
|
* Digital output capabilities (ADAT)
|
407 |
|
|
*/
|
408 |
|
|
static struct snd_pcm_hardware snd_rme96_playback_adat_info =
|
409 |
|
|
{
|
410 |
|
|
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
|
411 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
412 |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
413 |
|
|
SNDRV_PCM_INFO_PAUSE),
|
414 |
|
|
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
415 |
|
|
SNDRV_PCM_FMTBIT_S32_LE),
|
416 |
|
|
.rates = (SNDRV_PCM_RATE_44100 |
|
417 |
|
|
SNDRV_PCM_RATE_48000),
|
418 |
|
|
.rate_min = 44100,
|
419 |
|
|
.rate_max = 48000,
|
420 |
|
|
.channels_min = 8,
|
421 |
|
|
.channels_max = 8,
|
422 |
|
|
.buffer_bytes_max = RME96_BUFFER_SIZE,
|
423 |
|
|
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
|
424 |
|
|
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
|
425 |
|
|
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
|
426 |
|
|
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
|
427 |
|
|
.fifo_size = 0,
|
428 |
|
|
};
|
429 |
|
|
|
430 |
|
|
/*
|
431 |
|
|
* Digital input capabilities (ADAT)
|
432 |
|
|
*/
|
433 |
|
|
static struct snd_pcm_hardware snd_rme96_capture_adat_info =
|
434 |
|
|
{
|
435 |
|
|
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
|
436 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
437 |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
438 |
|
|
SNDRV_PCM_INFO_PAUSE),
|
439 |
|
|
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
440 |
|
|
SNDRV_PCM_FMTBIT_S32_LE),
|
441 |
|
|
.rates = (SNDRV_PCM_RATE_44100 |
|
442 |
|
|
SNDRV_PCM_RATE_48000),
|
443 |
|
|
.rate_min = 44100,
|
444 |
|
|
.rate_max = 48000,
|
445 |
|
|
.channels_min = 8,
|
446 |
|
|
.channels_max = 8,
|
447 |
|
|
.buffer_bytes_max = RME96_BUFFER_SIZE,
|
448 |
|
|
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
|
449 |
|
|
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
|
450 |
|
|
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
|
451 |
|
|
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
|
452 |
|
|
.fifo_size = 0,
|
453 |
|
|
};
|
454 |
|
|
|
455 |
|
|
/*
|
456 |
|
|
* The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
|
457 |
|
|
* of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
|
458 |
|
|
* on the falling edge of CCLK and be stable on the rising edge. The rising
|
459 |
|
|
* edge of CLATCH after the last data bit clocks in the whole data word.
|
460 |
|
|
* A fast processor could probably drive the SPI interface faster than the
|
461 |
|
|
* DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
|
462 |
|
|
* limits the data rate to 500KHz and only causes a delay of 33 microsecs.
|
463 |
|
|
*
|
464 |
|
|
* NOTE: increased delay from 1 to 10, since there where problems setting
|
465 |
|
|
* the volume.
|
466 |
|
|
*/
|
467 |
|
|
static void
|
468 |
|
|
snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
|
469 |
|
|
{
|
470 |
|
|
int i;
|
471 |
|
|
|
472 |
|
|
for (i = 0; i < 16; i++) {
|
473 |
|
|
if (val & 0x8000) {
|
474 |
|
|
rme96->areg |= RME96_AR_CDATA;
|
475 |
|
|
} else {
|
476 |
|
|
rme96->areg &= ~RME96_AR_CDATA;
|
477 |
|
|
}
|
478 |
|
|
rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
|
479 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
480 |
|
|
udelay(10);
|
481 |
|
|
rme96->areg |= RME96_AR_CCLK;
|
482 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
483 |
|
|
udelay(10);
|
484 |
|
|
val <<= 1;
|
485 |
|
|
}
|
486 |
|
|
rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
|
487 |
|
|
rme96->areg |= RME96_AR_CLATCH;
|
488 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
489 |
|
|
udelay(10);
|
490 |
|
|
rme96->areg &= ~RME96_AR_CLATCH;
|
491 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
492 |
|
|
}
|
493 |
|
|
|
494 |
|
|
static void
|
495 |
|
|
snd_rme96_apply_dac_volume(struct rme96 *rme96)
|
496 |
|
|
{
|
497 |
|
|
if (RME96_DAC_IS_1852(rme96)) {
|
498 |
|
|
snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
|
499 |
|
|
snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
|
500 |
|
|
} else if (RME96_DAC_IS_1855(rme96)) {
|
501 |
|
|
snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
|
502 |
|
|
snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
|
503 |
|
|
}
|
504 |
|
|
}
|
505 |
|
|
|
506 |
|
|
static void
|
507 |
|
|
snd_rme96_reset_dac(struct rme96 *rme96)
|
508 |
|
|
{
|
509 |
|
|
writel(rme96->wcreg | RME96_WCR_PD,
|
510 |
|
|
rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
511 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
512 |
|
|
}
|
513 |
|
|
|
514 |
|
|
static int
|
515 |
|
|
snd_rme96_getmontracks(struct rme96 *rme96)
|
516 |
|
|
{
|
517 |
|
|
return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
|
518 |
|
|
(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
|
519 |
|
|
}
|
520 |
|
|
|
521 |
|
|
static int
|
522 |
|
|
snd_rme96_setmontracks(struct rme96 *rme96,
|
523 |
|
|
int montracks)
|
524 |
|
|
{
|
525 |
|
|
if (montracks & 1) {
|
526 |
|
|
rme96->wcreg |= RME96_WCR_MONITOR_0;
|
527 |
|
|
} else {
|
528 |
|
|
rme96->wcreg &= ~RME96_WCR_MONITOR_0;
|
529 |
|
|
}
|
530 |
|
|
if (montracks & 2) {
|
531 |
|
|
rme96->wcreg |= RME96_WCR_MONITOR_1;
|
532 |
|
|
} else {
|
533 |
|
|
rme96->wcreg &= ~RME96_WCR_MONITOR_1;
|
534 |
|
|
}
|
535 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
536 |
|
|
return 0;
|
537 |
|
|
}
|
538 |
|
|
|
539 |
|
|
static int
|
540 |
|
|
snd_rme96_getattenuation(struct rme96 *rme96)
|
541 |
|
|
{
|
542 |
|
|
return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
|
543 |
|
|
(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
|
544 |
|
|
}
|
545 |
|
|
|
546 |
|
|
static int
|
547 |
|
|
snd_rme96_setattenuation(struct rme96 *rme96,
|
548 |
|
|
int attenuation)
|
549 |
|
|
{
|
550 |
|
|
switch (attenuation) {
|
551 |
|
|
case 0:
|
552 |
|
|
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
|
553 |
|
|
~RME96_WCR_GAIN_1;
|
554 |
|
|
break;
|
555 |
|
|
case 1:
|
556 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
|
557 |
|
|
~RME96_WCR_GAIN_1;
|
558 |
|
|
break;
|
559 |
|
|
case 2:
|
560 |
|
|
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
|
561 |
|
|
RME96_WCR_GAIN_1;
|
562 |
|
|
break;
|
563 |
|
|
case 3:
|
564 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
|
565 |
|
|
RME96_WCR_GAIN_1;
|
566 |
|
|
break;
|
567 |
|
|
default:
|
568 |
|
|
return -EINVAL;
|
569 |
|
|
}
|
570 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
571 |
|
|
return 0;
|
572 |
|
|
}
|
573 |
|
|
|
574 |
|
|
static int
|
575 |
|
|
snd_rme96_capture_getrate(struct rme96 *rme96,
|
576 |
|
|
int *is_adat)
|
577 |
|
|
{
|
578 |
|
|
int n, rate;
|
579 |
|
|
|
580 |
|
|
*is_adat = 0;
|
581 |
|
|
if (rme96->areg & RME96_AR_ANALOG) {
|
582 |
|
|
/* Analog input, overrides S/PDIF setting */
|
583 |
|
|
n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
|
584 |
|
|
(((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
|
585 |
|
|
switch (n) {
|
586 |
|
|
case 1:
|
587 |
|
|
rate = 32000;
|
588 |
|
|
break;
|
589 |
|
|
case 2:
|
590 |
|
|
rate = 44100;
|
591 |
|
|
break;
|
592 |
|
|
case 3:
|
593 |
|
|
rate = 48000;
|
594 |
|
|
break;
|
595 |
|
|
default:
|
596 |
|
|
return -1;
|
597 |
|
|
}
|
598 |
|
|
return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
|
599 |
|
|
}
|
600 |
|
|
|
601 |
|
|
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
602 |
|
|
if (rme96->rcreg & RME96_RCR_LOCK) {
|
603 |
|
|
/* ADAT rate */
|
604 |
|
|
*is_adat = 1;
|
605 |
|
|
if (rme96->rcreg & RME96_RCR_T_OUT) {
|
606 |
|
|
return 48000;
|
607 |
|
|
}
|
608 |
|
|
return 44100;
|
609 |
|
|
}
|
610 |
|
|
|
611 |
|
|
if (rme96->rcreg & RME96_RCR_VERF) {
|
612 |
|
|
return -1;
|
613 |
|
|
}
|
614 |
|
|
|
615 |
|
|
/* S/PDIF rate */
|
616 |
|
|
n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
|
617 |
|
|
(((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
|
618 |
|
|
(((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
|
619 |
|
|
|
620 |
|
|
switch (n) {
|
621 |
|
|
case 0:
|
622 |
|
|
if (rme96->rcreg & RME96_RCR_T_OUT) {
|
623 |
|
|
return 64000;
|
624 |
|
|
}
|
625 |
|
|
return -1;
|
626 |
|
|
case 3: return 96000;
|
627 |
|
|
case 4: return 88200;
|
628 |
|
|
case 5: return 48000;
|
629 |
|
|
case 6: return 44100;
|
630 |
|
|
case 7: return 32000;
|
631 |
|
|
default:
|
632 |
|
|
break;
|
633 |
|
|
}
|
634 |
|
|
return -1;
|
635 |
|
|
}
|
636 |
|
|
|
637 |
|
|
static int
|
638 |
|
|
snd_rme96_playback_getrate(struct rme96 *rme96)
|
639 |
|
|
{
|
640 |
|
|
int rate, dummy;
|
641 |
|
|
|
642 |
|
|
if (!(rme96->wcreg & RME96_WCR_MASTER) &&
|
643 |
|
|
snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
|
644 |
|
|
(rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
|
645 |
|
|
{
|
646 |
|
|
/* slave clock */
|
647 |
|
|
return rate;
|
648 |
|
|
}
|
649 |
|
|
rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
|
650 |
|
|
(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
|
651 |
|
|
switch (rate) {
|
652 |
|
|
case 1:
|
653 |
|
|
rate = 32000;
|
654 |
|
|
break;
|
655 |
|
|
case 2:
|
656 |
|
|
rate = 44100;
|
657 |
|
|
break;
|
658 |
|
|
case 3:
|
659 |
|
|
rate = 48000;
|
660 |
|
|
break;
|
661 |
|
|
default:
|
662 |
|
|
return -1;
|
663 |
|
|
}
|
664 |
|
|
return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
|
665 |
|
|
}
|
666 |
|
|
|
667 |
|
|
static int
|
668 |
|
|
snd_rme96_playback_setrate(struct rme96 *rme96,
|
669 |
|
|
int rate)
|
670 |
|
|
{
|
671 |
|
|
int ds;
|
672 |
|
|
|
673 |
|
|
ds = rme96->wcreg & RME96_WCR_DS;
|
674 |
|
|
switch (rate) {
|
675 |
|
|
case 32000:
|
676 |
|
|
rme96->wcreg &= ~RME96_WCR_DS;
|
677 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
|
678 |
|
|
~RME96_WCR_FREQ_1;
|
679 |
|
|
break;
|
680 |
|
|
case 44100:
|
681 |
|
|
rme96->wcreg &= ~RME96_WCR_DS;
|
682 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
|
683 |
|
|
~RME96_WCR_FREQ_0;
|
684 |
|
|
break;
|
685 |
|
|
case 48000:
|
686 |
|
|
rme96->wcreg &= ~RME96_WCR_DS;
|
687 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
|
688 |
|
|
RME96_WCR_FREQ_1;
|
689 |
|
|
break;
|
690 |
|
|
case 64000:
|
691 |
|
|
rme96->wcreg |= RME96_WCR_DS;
|
692 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
|
693 |
|
|
~RME96_WCR_FREQ_1;
|
694 |
|
|
break;
|
695 |
|
|
case 88200:
|
696 |
|
|
rme96->wcreg |= RME96_WCR_DS;
|
697 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
|
698 |
|
|
~RME96_WCR_FREQ_0;
|
699 |
|
|
break;
|
700 |
|
|
case 96000:
|
701 |
|
|
rme96->wcreg |= RME96_WCR_DS;
|
702 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
|
703 |
|
|
RME96_WCR_FREQ_1;
|
704 |
|
|
break;
|
705 |
|
|
default:
|
706 |
|
|
return -EINVAL;
|
707 |
|
|
}
|
708 |
|
|
if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
|
709 |
|
|
(ds && !(rme96->wcreg & RME96_WCR_DS)))
|
710 |
|
|
{
|
711 |
|
|
/* change to/from double-speed: reset the DAC (if available) */
|
712 |
|
|
snd_rme96_reset_dac(rme96);
|
713 |
|
|
} else {
|
714 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
715 |
|
|
}
|
716 |
|
|
return 0;
|
717 |
|
|
}
|
718 |
|
|
|
719 |
|
|
static int
|
720 |
|
|
snd_rme96_capture_analog_setrate(struct rme96 *rme96,
|
721 |
|
|
int rate)
|
722 |
|
|
{
|
723 |
|
|
switch (rate) {
|
724 |
|
|
case 32000:
|
725 |
|
|
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
|
726 |
|
|
~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
|
727 |
|
|
break;
|
728 |
|
|
case 44100:
|
729 |
|
|
rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
|
730 |
|
|
RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
|
731 |
|
|
break;
|
732 |
|
|
case 48000:
|
733 |
|
|
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
|
734 |
|
|
RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
|
735 |
|
|
break;
|
736 |
|
|
case 64000:
|
737 |
|
|
if (rme96->rev < 4) {
|
738 |
|
|
return -EINVAL;
|
739 |
|
|
}
|
740 |
|
|
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
|
741 |
|
|
~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
|
742 |
|
|
break;
|
743 |
|
|
case 88200:
|
744 |
|
|
if (rme96->rev < 4) {
|
745 |
|
|
return -EINVAL;
|
746 |
|
|
}
|
747 |
|
|
rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
|
748 |
|
|
RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
|
749 |
|
|
break;
|
750 |
|
|
case 96000:
|
751 |
|
|
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
|
752 |
|
|
RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
|
753 |
|
|
break;
|
754 |
|
|
default:
|
755 |
|
|
return -EINVAL;
|
756 |
|
|
}
|
757 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
758 |
|
|
return 0;
|
759 |
|
|
}
|
760 |
|
|
|
761 |
|
|
static int
|
762 |
|
|
snd_rme96_setclockmode(struct rme96 *rme96,
|
763 |
|
|
int mode)
|
764 |
|
|
{
|
765 |
|
|
switch (mode) {
|
766 |
|
|
case RME96_CLOCKMODE_SLAVE:
|
767 |
|
|
/* AutoSync */
|
768 |
|
|
rme96->wcreg &= ~RME96_WCR_MASTER;
|
769 |
|
|
rme96->areg &= ~RME96_AR_WSEL;
|
770 |
|
|
break;
|
771 |
|
|
case RME96_CLOCKMODE_MASTER:
|
772 |
|
|
/* Internal */
|
773 |
|
|
rme96->wcreg |= RME96_WCR_MASTER;
|
774 |
|
|
rme96->areg &= ~RME96_AR_WSEL;
|
775 |
|
|
break;
|
776 |
|
|
case RME96_CLOCKMODE_WORDCLOCK:
|
777 |
|
|
/* Word clock is a master mode */
|
778 |
|
|
rme96->wcreg |= RME96_WCR_MASTER;
|
779 |
|
|
rme96->areg |= RME96_AR_WSEL;
|
780 |
|
|
break;
|
781 |
|
|
default:
|
782 |
|
|
return -EINVAL;
|
783 |
|
|
}
|
784 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
785 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
786 |
|
|
return 0;
|
787 |
|
|
}
|
788 |
|
|
|
789 |
|
|
static int
|
790 |
|
|
snd_rme96_getclockmode(struct rme96 *rme96)
|
791 |
|
|
{
|
792 |
|
|
if (rme96->areg & RME96_AR_WSEL) {
|
793 |
|
|
return RME96_CLOCKMODE_WORDCLOCK;
|
794 |
|
|
}
|
795 |
|
|
return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
|
796 |
|
|
RME96_CLOCKMODE_SLAVE;
|
797 |
|
|
}
|
798 |
|
|
|
799 |
|
|
static int
|
800 |
|
|
snd_rme96_setinputtype(struct rme96 *rme96,
|
801 |
|
|
int type)
|
802 |
|
|
{
|
803 |
|
|
int n;
|
804 |
|
|
|
805 |
|
|
switch (type) {
|
806 |
|
|
case RME96_INPUT_OPTICAL:
|
807 |
|
|
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
|
808 |
|
|
~RME96_WCR_INP_1;
|
809 |
|
|
break;
|
810 |
|
|
case RME96_INPUT_COAXIAL:
|
811 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
|
812 |
|
|
~RME96_WCR_INP_1;
|
813 |
|
|
break;
|
814 |
|
|
case RME96_INPUT_INTERNAL:
|
815 |
|
|
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
|
816 |
|
|
RME96_WCR_INP_1;
|
817 |
|
|
break;
|
818 |
|
|
case RME96_INPUT_XLR:
|
819 |
|
|
if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
|
820 |
|
|
rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
|
821 |
|
|
(rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
|
822 |
|
|
rme96->rev > 4))
|
823 |
|
|
{
|
824 |
|
|
/* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
|
825 |
|
|
return -EINVAL;
|
826 |
|
|
}
|
827 |
|
|
rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
|
828 |
|
|
RME96_WCR_INP_1;
|
829 |
|
|
break;
|
830 |
|
|
case RME96_INPUT_ANALOG:
|
831 |
|
|
if (!RME96_HAS_ANALOG_IN(rme96)) {
|
832 |
|
|
return -EINVAL;
|
833 |
|
|
}
|
834 |
|
|
rme96->areg |= RME96_AR_ANALOG;
|
835 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
836 |
|
|
if (rme96->rev < 4) {
|
837 |
|
|
/*
|
838 |
|
|
* Revision less than 004 does not support 64 and
|
839 |
|
|
* 88.2 kHz
|
840 |
|
|
*/
|
841 |
|
|
if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
|
842 |
|
|
snd_rme96_capture_analog_setrate(rme96, 44100);
|
843 |
|
|
}
|
844 |
|
|
if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
|
845 |
|
|
snd_rme96_capture_analog_setrate(rme96, 32000);
|
846 |
|
|
}
|
847 |
|
|
}
|
848 |
|
|
return 0;
|
849 |
|
|
default:
|
850 |
|
|
return -EINVAL;
|
851 |
|
|
}
|
852 |
|
|
if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
|
853 |
|
|
rme96->areg &= ~RME96_AR_ANALOG;
|
854 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
855 |
|
|
}
|
856 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
857 |
|
|
return 0;
|
858 |
|
|
}
|
859 |
|
|
|
860 |
|
|
static int
|
861 |
|
|
snd_rme96_getinputtype(struct rme96 *rme96)
|
862 |
|
|
{
|
863 |
|
|
if (rme96->areg & RME96_AR_ANALOG) {
|
864 |
|
|
return RME96_INPUT_ANALOG;
|
865 |
|
|
}
|
866 |
|
|
return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
|
867 |
|
|
(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
|
868 |
|
|
}
|
869 |
|
|
|
870 |
|
|
static void
|
871 |
|
|
snd_rme96_setframelog(struct rme96 *rme96,
|
872 |
|
|
int n_channels,
|
873 |
|
|
int is_playback)
|
874 |
|
|
{
|
875 |
|
|
int frlog;
|
876 |
|
|
|
877 |
|
|
if (n_channels == 2) {
|
878 |
|
|
frlog = 1;
|
879 |
|
|
} else {
|
880 |
|
|
/* assume 8 channels */
|
881 |
|
|
frlog = 3;
|
882 |
|
|
}
|
883 |
|
|
if (is_playback) {
|
884 |
|
|
frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
|
885 |
|
|
rme96->playback_frlog = frlog;
|
886 |
|
|
} else {
|
887 |
|
|
frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
|
888 |
|
|
rme96->capture_frlog = frlog;
|
889 |
|
|
}
|
890 |
|
|
}
|
891 |
|
|
|
892 |
|
|
static int
|
893 |
|
|
snd_rme96_playback_setformat(struct rme96 *rme96,
|
894 |
|
|
int format)
|
895 |
|
|
{
|
896 |
|
|
switch (format) {
|
897 |
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
898 |
|
|
rme96->wcreg &= ~RME96_WCR_MODE24;
|
899 |
|
|
break;
|
900 |
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
901 |
|
|
rme96->wcreg |= RME96_WCR_MODE24;
|
902 |
|
|
break;
|
903 |
|
|
default:
|
904 |
|
|
return -EINVAL;
|
905 |
|
|
}
|
906 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
907 |
|
|
return 0;
|
908 |
|
|
}
|
909 |
|
|
|
910 |
|
|
static int
|
911 |
|
|
snd_rme96_capture_setformat(struct rme96 *rme96,
|
912 |
|
|
int format)
|
913 |
|
|
{
|
914 |
|
|
switch (format) {
|
915 |
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
916 |
|
|
rme96->wcreg &= ~RME96_WCR_MODE24_2;
|
917 |
|
|
break;
|
918 |
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
919 |
|
|
rme96->wcreg |= RME96_WCR_MODE24_2;
|
920 |
|
|
break;
|
921 |
|
|
default:
|
922 |
|
|
return -EINVAL;
|
923 |
|
|
}
|
924 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
925 |
|
|
return 0;
|
926 |
|
|
}
|
927 |
|
|
|
928 |
|
|
static void
|
929 |
|
|
snd_rme96_set_period_properties(struct rme96 *rme96,
|
930 |
|
|
size_t period_bytes)
|
931 |
|
|
{
|
932 |
|
|
switch (period_bytes) {
|
933 |
|
|
case RME96_LARGE_BLOCK_SIZE:
|
934 |
|
|
rme96->wcreg &= ~RME96_WCR_ISEL;
|
935 |
|
|
break;
|
936 |
|
|
case RME96_SMALL_BLOCK_SIZE:
|
937 |
|
|
rme96->wcreg |= RME96_WCR_ISEL;
|
938 |
|
|
break;
|
939 |
|
|
default:
|
940 |
|
|
snd_BUG();
|
941 |
|
|
break;
|
942 |
|
|
}
|
943 |
|
|
rme96->wcreg &= ~RME96_WCR_IDIS;
|
944 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
945 |
|
|
}
|
946 |
|
|
|
947 |
|
|
static int
|
948 |
|
|
snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
|
949 |
|
|
struct snd_pcm_hw_params *params)
|
950 |
|
|
{
|
951 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
952 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
953 |
|
|
int err, rate, dummy;
|
954 |
|
|
|
955 |
|
|
runtime->dma_area = (void __force *)(rme96->iobase +
|
956 |
|
|
RME96_IO_PLAY_BUFFER);
|
957 |
|
|
runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
|
958 |
|
|
runtime->dma_bytes = RME96_BUFFER_SIZE;
|
959 |
|
|
|
960 |
|
|
spin_lock_irq(&rme96->lock);
|
961 |
|
|
if (!(rme96->wcreg & RME96_WCR_MASTER) &&
|
962 |
|
|
snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
|
963 |
|
|
(rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
|
964 |
|
|
{
|
965 |
|
|
/* slave clock */
|
966 |
|
|
if ((int)params_rate(params) != rate) {
|
967 |
|
|
spin_unlock_irq(&rme96->lock);
|
968 |
|
|
return -EIO;
|
969 |
|
|
}
|
970 |
|
|
} else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
|
971 |
|
|
spin_unlock_irq(&rme96->lock);
|
972 |
|
|
return err;
|
973 |
|
|
}
|
974 |
|
|
if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
|
975 |
|
|
spin_unlock_irq(&rme96->lock);
|
976 |
|
|
return err;
|
977 |
|
|
}
|
978 |
|
|
snd_rme96_setframelog(rme96, params_channels(params), 1);
|
979 |
|
|
if (rme96->capture_periodsize != 0) {
|
980 |
|
|
if (params_period_size(params) << rme96->playback_frlog !=
|
981 |
|
|
rme96->capture_periodsize)
|
982 |
|
|
{
|
983 |
|
|
spin_unlock_irq(&rme96->lock);
|
984 |
|
|
return -EBUSY;
|
985 |
|
|
}
|
986 |
|
|
}
|
987 |
|
|
rme96->playback_periodsize =
|
988 |
|
|
params_period_size(params) << rme96->playback_frlog;
|
989 |
|
|
snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
|
990 |
|
|
/* S/PDIF setup */
|
991 |
|
|
if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
|
992 |
|
|
rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
|
993 |
|
|
writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
994 |
|
|
}
|
995 |
|
|
spin_unlock_irq(&rme96->lock);
|
996 |
|
|
|
997 |
|
|
return 0;
|
998 |
|
|
}
|
999 |
|
|
|
1000 |
|
|
static int
|
1001 |
|
|
snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
|
1002 |
|
|
struct snd_pcm_hw_params *params)
|
1003 |
|
|
{
|
1004 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1005 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
1006 |
|
|
int err, isadat, rate;
|
1007 |
|
|
|
1008 |
|
|
runtime->dma_area = (void __force *)(rme96->iobase +
|
1009 |
|
|
RME96_IO_REC_BUFFER);
|
1010 |
|
|
runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
|
1011 |
|
|
runtime->dma_bytes = RME96_BUFFER_SIZE;
|
1012 |
|
|
|
1013 |
|
|
spin_lock_irq(&rme96->lock);
|
1014 |
|
|
if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
|
1015 |
|
|
spin_unlock_irq(&rme96->lock);
|
1016 |
|
|
return err;
|
1017 |
|
|
}
|
1018 |
|
|
if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
|
1019 |
|
|
if ((err = snd_rme96_capture_analog_setrate(rme96,
|
1020 |
|
|
params_rate(params))) < 0)
|
1021 |
|
|
{
|
1022 |
|
|
spin_unlock_irq(&rme96->lock);
|
1023 |
|
|
return err;
|
1024 |
|
|
}
|
1025 |
|
|
} else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
|
1026 |
|
|
if ((int)params_rate(params) != rate) {
|
1027 |
|
|
spin_unlock_irq(&rme96->lock);
|
1028 |
|
|
return -EIO;
|
1029 |
|
|
}
|
1030 |
|
|
if ((isadat && runtime->hw.channels_min == 2) ||
|
1031 |
|
|
(!isadat && runtime->hw.channels_min == 8))
|
1032 |
|
|
{
|
1033 |
|
|
spin_unlock_irq(&rme96->lock);
|
1034 |
|
|
return -EIO;
|
1035 |
|
|
}
|
1036 |
|
|
}
|
1037 |
|
|
snd_rme96_setframelog(rme96, params_channels(params), 0);
|
1038 |
|
|
if (rme96->playback_periodsize != 0) {
|
1039 |
|
|
if (params_period_size(params) << rme96->capture_frlog !=
|
1040 |
|
|
rme96->playback_periodsize)
|
1041 |
|
|
{
|
1042 |
|
|
spin_unlock_irq(&rme96->lock);
|
1043 |
|
|
return -EBUSY;
|
1044 |
|
|
}
|
1045 |
|
|
}
|
1046 |
|
|
rme96->capture_periodsize =
|
1047 |
|
|
params_period_size(params) << rme96->capture_frlog;
|
1048 |
|
|
snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
|
1049 |
|
|
spin_unlock_irq(&rme96->lock);
|
1050 |
|
|
|
1051 |
|
|
return 0;
|
1052 |
|
|
}
|
1053 |
|
|
|
1054 |
|
|
static void
|
1055 |
|
|
snd_rme96_playback_start(struct rme96 *rme96,
|
1056 |
|
|
int from_pause)
|
1057 |
|
|
{
|
1058 |
|
|
if (!from_pause) {
|
1059 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
|
1060 |
|
|
}
|
1061 |
|
|
|
1062 |
|
|
rme96->wcreg |= RME96_WCR_START;
|
1063 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1064 |
|
|
}
|
1065 |
|
|
|
1066 |
|
|
static void
|
1067 |
|
|
snd_rme96_capture_start(struct rme96 *rme96,
|
1068 |
|
|
int from_pause)
|
1069 |
|
|
{
|
1070 |
|
|
if (!from_pause) {
|
1071 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
|
1072 |
|
|
}
|
1073 |
|
|
|
1074 |
|
|
rme96->wcreg |= RME96_WCR_START_2;
|
1075 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1076 |
|
|
}
|
1077 |
|
|
|
1078 |
|
|
static void
|
1079 |
|
|
snd_rme96_playback_stop(struct rme96 *rme96)
|
1080 |
|
|
{
|
1081 |
|
|
/*
|
1082 |
|
|
* Check if there is an unconfirmed IRQ, if so confirm it, or else
|
1083 |
|
|
* the hardware will not stop generating interrupts
|
1084 |
|
|
*/
|
1085 |
|
|
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1086 |
|
|
if (rme96->rcreg & RME96_RCR_IRQ) {
|
1087 |
|
|
writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
|
1088 |
|
|
}
|
1089 |
|
|
rme96->wcreg &= ~RME96_WCR_START;
|
1090 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1091 |
|
|
}
|
1092 |
|
|
|
1093 |
|
|
static void
|
1094 |
|
|
snd_rme96_capture_stop(struct rme96 *rme96)
|
1095 |
|
|
{
|
1096 |
|
|
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1097 |
|
|
if (rme96->rcreg & RME96_RCR_IRQ_2) {
|
1098 |
|
|
writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
|
1099 |
|
|
}
|
1100 |
|
|
rme96->wcreg &= ~RME96_WCR_START_2;
|
1101 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1102 |
|
|
}
|
1103 |
|
|
|
1104 |
|
|
static irqreturn_t
|
1105 |
|
|
snd_rme96_interrupt(int irq,
|
1106 |
|
|
void *dev_id)
|
1107 |
|
|
{
|
1108 |
|
|
struct rme96 *rme96 = (struct rme96 *)dev_id;
|
1109 |
|
|
|
1110 |
|
|
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1111 |
|
|
/* fastpath out, to ease interrupt sharing */
|
1112 |
|
|
if (!((rme96->rcreg & RME96_RCR_IRQ) ||
|
1113 |
|
|
(rme96->rcreg & RME96_RCR_IRQ_2)))
|
1114 |
|
|
{
|
1115 |
|
|
return IRQ_NONE;
|
1116 |
|
|
}
|
1117 |
|
|
|
1118 |
|
|
if (rme96->rcreg & RME96_RCR_IRQ) {
|
1119 |
|
|
/* playback */
|
1120 |
|
|
snd_pcm_period_elapsed(rme96->playback_substream);
|
1121 |
|
|
writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
|
1122 |
|
|
}
|
1123 |
|
|
if (rme96->rcreg & RME96_RCR_IRQ_2) {
|
1124 |
|
|
/* capture */
|
1125 |
|
|
snd_pcm_period_elapsed(rme96->capture_substream);
|
1126 |
|
|
writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
|
1127 |
|
|
}
|
1128 |
|
|
return IRQ_HANDLED;
|
1129 |
|
|
}
|
1130 |
|
|
|
1131 |
|
|
static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
|
1132 |
|
|
|
1133 |
|
|
static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
|
1134 |
|
|
.count = ARRAY_SIZE(period_bytes),
|
1135 |
|
|
.list = period_bytes,
|
1136 |
|
|
.mask = 0
|
1137 |
|
|
};
|
1138 |
|
|
|
1139 |
|
|
static void
|
1140 |
|
|
rme96_set_buffer_size_constraint(struct rme96 *rme96,
|
1141 |
|
|
struct snd_pcm_runtime *runtime)
|
1142 |
|
|
{
|
1143 |
|
|
unsigned int size;
|
1144 |
|
|
|
1145 |
|
|
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
|
1146 |
|
|
RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
|
1147 |
|
|
if ((size = rme96->playback_periodsize) != 0 ||
|
1148 |
|
|
(size = rme96->capture_periodsize) != 0)
|
1149 |
|
|
snd_pcm_hw_constraint_minmax(runtime,
|
1150 |
|
|
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
|
1151 |
|
|
size, size);
|
1152 |
|
|
else
|
1153 |
|
|
snd_pcm_hw_constraint_list(runtime, 0,
|
1154 |
|
|
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
|
1155 |
|
|
&hw_constraints_period_bytes);
|
1156 |
|
|
}
|
1157 |
|
|
|
1158 |
|
|
static int
|
1159 |
|
|
snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
|
1160 |
|
|
{
|
1161 |
|
|
int rate, dummy;
|
1162 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1163 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
1164 |
|
|
|
1165 |
|
|
spin_lock_irq(&rme96->lock);
|
1166 |
|
|
if (rme96->playback_substream != NULL) {
|
1167 |
|
|
spin_unlock_irq(&rme96->lock);
|
1168 |
|
|
return -EBUSY;
|
1169 |
|
|
}
|
1170 |
|
|
rme96->wcreg &= ~RME96_WCR_ADAT;
|
1171 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1172 |
|
|
rme96->playback_substream = substream;
|
1173 |
|
|
spin_unlock_irq(&rme96->lock);
|
1174 |
|
|
|
1175 |
|
|
runtime->hw = snd_rme96_playback_spdif_info;
|
1176 |
|
|
if (!(rme96->wcreg & RME96_WCR_MASTER) &&
|
1177 |
|
|
snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
|
1178 |
|
|
(rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
|
1179 |
|
|
{
|
1180 |
|
|
/* slave clock */
|
1181 |
|
|
runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
|
1182 |
|
|
runtime->hw.rate_min = rate;
|
1183 |
|
|
runtime->hw.rate_max = rate;
|
1184 |
|
|
}
|
1185 |
|
|
rme96_set_buffer_size_constraint(rme96, runtime);
|
1186 |
|
|
|
1187 |
|
|
rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
|
1188 |
|
|
rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
|
1189 |
|
|
snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
|
1190 |
|
|
SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
|
1191 |
|
|
return 0;
|
1192 |
|
|
}
|
1193 |
|
|
|
1194 |
|
|
static int
|
1195 |
|
|
snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
|
1196 |
|
|
{
|
1197 |
|
|
int isadat, rate;
|
1198 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1199 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
1200 |
|
|
|
1201 |
|
|
runtime->hw = snd_rme96_capture_spdif_info;
|
1202 |
|
|
if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
|
1203 |
|
|
(rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
|
1204 |
|
|
{
|
1205 |
|
|
if (isadat) {
|
1206 |
|
|
return -EIO;
|
1207 |
|
|
}
|
1208 |
|
|
runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
|
1209 |
|
|
runtime->hw.rate_min = rate;
|
1210 |
|
|
runtime->hw.rate_max = rate;
|
1211 |
|
|
}
|
1212 |
|
|
|
1213 |
|
|
spin_lock_irq(&rme96->lock);
|
1214 |
|
|
if (rme96->capture_substream != NULL) {
|
1215 |
|
|
spin_unlock_irq(&rme96->lock);
|
1216 |
|
|
return -EBUSY;
|
1217 |
|
|
}
|
1218 |
|
|
rme96->capture_substream = substream;
|
1219 |
|
|
spin_unlock_irq(&rme96->lock);
|
1220 |
|
|
|
1221 |
|
|
rme96_set_buffer_size_constraint(rme96, runtime);
|
1222 |
|
|
return 0;
|
1223 |
|
|
}
|
1224 |
|
|
|
1225 |
|
|
static int
|
1226 |
|
|
snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
|
1227 |
|
|
{
|
1228 |
|
|
int rate, dummy;
|
1229 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1230 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
1231 |
|
|
|
1232 |
|
|
spin_lock_irq(&rme96->lock);
|
1233 |
|
|
if (rme96->playback_substream != NULL) {
|
1234 |
|
|
spin_unlock_irq(&rme96->lock);
|
1235 |
|
|
return -EBUSY;
|
1236 |
|
|
}
|
1237 |
|
|
rme96->wcreg |= RME96_WCR_ADAT;
|
1238 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1239 |
|
|
rme96->playback_substream = substream;
|
1240 |
|
|
spin_unlock_irq(&rme96->lock);
|
1241 |
|
|
|
1242 |
|
|
runtime->hw = snd_rme96_playback_adat_info;
|
1243 |
|
|
if (!(rme96->wcreg & RME96_WCR_MASTER) &&
|
1244 |
|
|
snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
|
1245 |
|
|
(rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
|
1246 |
|
|
{
|
1247 |
|
|
/* slave clock */
|
1248 |
|
|
runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
|
1249 |
|
|
runtime->hw.rate_min = rate;
|
1250 |
|
|
runtime->hw.rate_max = rate;
|
1251 |
|
|
}
|
1252 |
|
|
rme96_set_buffer_size_constraint(rme96, runtime);
|
1253 |
|
|
return 0;
|
1254 |
|
|
}
|
1255 |
|
|
|
1256 |
|
|
static int
|
1257 |
|
|
snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
|
1258 |
|
|
{
|
1259 |
|
|
int isadat, rate;
|
1260 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1261 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
1262 |
|
|
|
1263 |
|
|
runtime->hw = snd_rme96_capture_adat_info;
|
1264 |
|
|
if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
|
1265 |
|
|
/* makes no sense to use analog input. Note that analog
|
1266 |
|
|
expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
|
1267 |
|
|
return -EIO;
|
1268 |
|
|
}
|
1269 |
|
|
if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
|
1270 |
|
|
if (!isadat) {
|
1271 |
|
|
return -EIO;
|
1272 |
|
|
}
|
1273 |
|
|
runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
|
1274 |
|
|
runtime->hw.rate_min = rate;
|
1275 |
|
|
runtime->hw.rate_max = rate;
|
1276 |
|
|
}
|
1277 |
|
|
|
1278 |
|
|
spin_lock_irq(&rme96->lock);
|
1279 |
|
|
if (rme96->capture_substream != NULL) {
|
1280 |
|
|
spin_unlock_irq(&rme96->lock);
|
1281 |
|
|
return -EBUSY;
|
1282 |
|
|
}
|
1283 |
|
|
rme96->capture_substream = substream;
|
1284 |
|
|
spin_unlock_irq(&rme96->lock);
|
1285 |
|
|
|
1286 |
|
|
rme96_set_buffer_size_constraint(rme96, runtime);
|
1287 |
|
|
return 0;
|
1288 |
|
|
}
|
1289 |
|
|
|
1290 |
|
|
static int
|
1291 |
|
|
snd_rme96_playback_close(struct snd_pcm_substream *substream)
|
1292 |
|
|
{
|
1293 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1294 |
|
|
int spdif = 0;
|
1295 |
|
|
|
1296 |
|
|
spin_lock_irq(&rme96->lock);
|
1297 |
|
|
if (RME96_ISPLAYING(rme96)) {
|
1298 |
|
|
snd_rme96_playback_stop(rme96);
|
1299 |
|
|
}
|
1300 |
|
|
rme96->playback_substream = NULL;
|
1301 |
|
|
rme96->playback_periodsize = 0;
|
1302 |
|
|
spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
|
1303 |
|
|
spin_unlock_irq(&rme96->lock);
|
1304 |
|
|
if (spdif) {
|
1305 |
|
|
rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
|
1306 |
|
|
snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
|
1307 |
|
|
SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
|
1308 |
|
|
}
|
1309 |
|
|
return 0;
|
1310 |
|
|
}
|
1311 |
|
|
|
1312 |
|
|
static int
|
1313 |
|
|
snd_rme96_capture_close(struct snd_pcm_substream *substream)
|
1314 |
|
|
{
|
1315 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1316 |
|
|
|
1317 |
|
|
spin_lock_irq(&rme96->lock);
|
1318 |
|
|
if (RME96_ISRECORDING(rme96)) {
|
1319 |
|
|
snd_rme96_capture_stop(rme96);
|
1320 |
|
|
}
|
1321 |
|
|
rme96->capture_substream = NULL;
|
1322 |
|
|
rme96->capture_periodsize = 0;
|
1323 |
|
|
spin_unlock_irq(&rme96->lock);
|
1324 |
|
|
return 0;
|
1325 |
|
|
}
|
1326 |
|
|
|
1327 |
|
|
static int
|
1328 |
|
|
snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
|
1329 |
|
|
{
|
1330 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1331 |
|
|
|
1332 |
|
|
spin_lock_irq(&rme96->lock);
|
1333 |
|
|
if (RME96_ISPLAYING(rme96)) {
|
1334 |
|
|
snd_rme96_playback_stop(rme96);
|
1335 |
|
|
}
|
1336 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
|
1337 |
|
|
spin_unlock_irq(&rme96->lock);
|
1338 |
|
|
return 0;
|
1339 |
|
|
}
|
1340 |
|
|
|
1341 |
|
|
static int
|
1342 |
|
|
snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
|
1343 |
|
|
{
|
1344 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1345 |
|
|
|
1346 |
|
|
spin_lock_irq(&rme96->lock);
|
1347 |
|
|
if (RME96_ISRECORDING(rme96)) {
|
1348 |
|
|
snd_rme96_capture_stop(rme96);
|
1349 |
|
|
}
|
1350 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
|
1351 |
|
|
spin_unlock_irq(&rme96->lock);
|
1352 |
|
|
return 0;
|
1353 |
|
|
}
|
1354 |
|
|
|
1355 |
|
|
static int
|
1356 |
|
|
snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
|
1357 |
|
|
int cmd)
|
1358 |
|
|
{
|
1359 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1360 |
|
|
|
1361 |
|
|
switch (cmd) {
|
1362 |
|
|
case SNDRV_PCM_TRIGGER_START:
|
1363 |
|
|
if (!RME96_ISPLAYING(rme96)) {
|
1364 |
|
|
if (substream != rme96->playback_substream) {
|
1365 |
|
|
return -EBUSY;
|
1366 |
|
|
}
|
1367 |
|
|
snd_rme96_playback_start(rme96, 0);
|
1368 |
|
|
}
|
1369 |
|
|
break;
|
1370 |
|
|
|
1371 |
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
1372 |
|
|
if (RME96_ISPLAYING(rme96)) {
|
1373 |
|
|
if (substream != rme96->playback_substream) {
|
1374 |
|
|
return -EBUSY;
|
1375 |
|
|
}
|
1376 |
|
|
snd_rme96_playback_stop(rme96);
|
1377 |
|
|
}
|
1378 |
|
|
break;
|
1379 |
|
|
|
1380 |
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
1381 |
|
|
if (RME96_ISPLAYING(rme96)) {
|
1382 |
|
|
snd_rme96_playback_stop(rme96);
|
1383 |
|
|
}
|
1384 |
|
|
break;
|
1385 |
|
|
|
1386 |
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
1387 |
|
|
if (!RME96_ISPLAYING(rme96)) {
|
1388 |
|
|
snd_rme96_playback_start(rme96, 1);
|
1389 |
|
|
}
|
1390 |
|
|
break;
|
1391 |
|
|
|
1392 |
|
|
default:
|
1393 |
|
|
return -EINVAL;
|
1394 |
|
|
}
|
1395 |
|
|
return 0;
|
1396 |
|
|
}
|
1397 |
|
|
|
1398 |
|
|
static int
|
1399 |
|
|
snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
|
1400 |
|
|
int cmd)
|
1401 |
|
|
{
|
1402 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1403 |
|
|
|
1404 |
|
|
switch (cmd) {
|
1405 |
|
|
case SNDRV_PCM_TRIGGER_START:
|
1406 |
|
|
if (!RME96_ISRECORDING(rme96)) {
|
1407 |
|
|
if (substream != rme96->capture_substream) {
|
1408 |
|
|
return -EBUSY;
|
1409 |
|
|
}
|
1410 |
|
|
snd_rme96_capture_start(rme96, 0);
|
1411 |
|
|
}
|
1412 |
|
|
break;
|
1413 |
|
|
|
1414 |
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
1415 |
|
|
if (RME96_ISRECORDING(rme96)) {
|
1416 |
|
|
if (substream != rme96->capture_substream) {
|
1417 |
|
|
return -EBUSY;
|
1418 |
|
|
}
|
1419 |
|
|
snd_rme96_capture_stop(rme96);
|
1420 |
|
|
}
|
1421 |
|
|
break;
|
1422 |
|
|
|
1423 |
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
1424 |
|
|
if (RME96_ISRECORDING(rme96)) {
|
1425 |
|
|
snd_rme96_capture_stop(rme96);
|
1426 |
|
|
}
|
1427 |
|
|
break;
|
1428 |
|
|
|
1429 |
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
1430 |
|
|
if (!RME96_ISRECORDING(rme96)) {
|
1431 |
|
|
snd_rme96_capture_start(rme96, 1);
|
1432 |
|
|
}
|
1433 |
|
|
break;
|
1434 |
|
|
|
1435 |
|
|
default:
|
1436 |
|
|
return -EINVAL;
|
1437 |
|
|
}
|
1438 |
|
|
|
1439 |
|
|
return 0;
|
1440 |
|
|
}
|
1441 |
|
|
|
1442 |
|
|
static snd_pcm_uframes_t
|
1443 |
|
|
snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
|
1444 |
|
|
{
|
1445 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1446 |
|
|
return snd_rme96_playback_ptr(rme96);
|
1447 |
|
|
}
|
1448 |
|
|
|
1449 |
|
|
static snd_pcm_uframes_t
|
1450 |
|
|
snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
|
1451 |
|
|
{
|
1452 |
|
|
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
|
1453 |
|
|
return snd_rme96_capture_ptr(rme96);
|
1454 |
|
|
}
|
1455 |
|
|
|
1456 |
|
|
static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
|
1457 |
|
|
.open = snd_rme96_playback_spdif_open,
|
1458 |
|
|
.close = snd_rme96_playback_close,
|
1459 |
|
|
.ioctl = snd_pcm_lib_ioctl,
|
1460 |
|
|
.hw_params = snd_rme96_playback_hw_params,
|
1461 |
|
|
.prepare = snd_rme96_playback_prepare,
|
1462 |
|
|
.trigger = snd_rme96_playback_trigger,
|
1463 |
|
|
.pointer = snd_rme96_playback_pointer,
|
1464 |
|
|
.copy = snd_rme96_playback_copy,
|
1465 |
|
|
.silence = snd_rme96_playback_silence,
|
1466 |
|
|
.mmap = snd_pcm_lib_mmap_iomem,
|
1467 |
|
|
};
|
1468 |
|
|
|
1469 |
|
|
static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
|
1470 |
|
|
.open = snd_rme96_capture_spdif_open,
|
1471 |
|
|
.close = snd_rme96_capture_close,
|
1472 |
|
|
.ioctl = snd_pcm_lib_ioctl,
|
1473 |
|
|
.hw_params = snd_rme96_capture_hw_params,
|
1474 |
|
|
.prepare = snd_rme96_capture_prepare,
|
1475 |
|
|
.trigger = snd_rme96_capture_trigger,
|
1476 |
|
|
.pointer = snd_rme96_capture_pointer,
|
1477 |
|
|
.copy = snd_rme96_capture_copy,
|
1478 |
|
|
.mmap = snd_pcm_lib_mmap_iomem,
|
1479 |
|
|
};
|
1480 |
|
|
|
1481 |
|
|
static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
|
1482 |
|
|
.open = snd_rme96_playback_adat_open,
|
1483 |
|
|
.close = snd_rme96_playback_close,
|
1484 |
|
|
.ioctl = snd_pcm_lib_ioctl,
|
1485 |
|
|
.hw_params = snd_rme96_playback_hw_params,
|
1486 |
|
|
.prepare = snd_rme96_playback_prepare,
|
1487 |
|
|
.trigger = snd_rme96_playback_trigger,
|
1488 |
|
|
.pointer = snd_rme96_playback_pointer,
|
1489 |
|
|
.copy = snd_rme96_playback_copy,
|
1490 |
|
|
.silence = snd_rme96_playback_silence,
|
1491 |
|
|
.mmap = snd_pcm_lib_mmap_iomem,
|
1492 |
|
|
};
|
1493 |
|
|
|
1494 |
|
|
static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
|
1495 |
|
|
.open = snd_rme96_capture_adat_open,
|
1496 |
|
|
.close = snd_rme96_capture_close,
|
1497 |
|
|
.ioctl = snd_pcm_lib_ioctl,
|
1498 |
|
|
.hw_params = snd_rme96_capture_hw_params,
|
1499 |
|
|
.prepare = snd_rme96_capture_prepare,
|
1500 |
|
|
.trigger = snd_rme96_capture_trigger,
|
1501 |
|
|
.pointer = snd_rme96_capture_pointer,
|
1502 |
|
|
.copy = snd_rme96_capture_copy,
|
1503 |
|
|
.mmap = snd_pcm_lib_mmap_iomem,
|
1504 |
|
|
};
|
1505 |
|
|
|
1506 |
|
|
static void
|
1507 |
|
|
snd_rme96_free(void *private_data)
|
1508 |
|
|
{
|
1509 |
|
|
struct rme96 *rme96 = (struct rme96 *)private_data;
|
1510 |
|
|
|
1511 |
|
|
if (rme96 == NULL) {
|
1512 |
|
|
return;
|
1513 |
|
|
}
|
1514 |
|
|
if (rme96->irq >= 0) {
|
1515 |
|
|
snd_rme96_playback_stop(rme96);
|
1516 |
|
|
snd_rme96_capture_stop(rme96);
|
1517 |
|
|
rme96->areg &= ~RME96_AR_DAC_EN;
|
1518 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
1519 |
|
|
free_irq(rme96->irq, (void *)rme96);
|
1520 |
|
|
rme96->irq = -1;
|
1521 |
|
|
}
|
1522 |
|
|
if (rme96->iobase) {
|
1523 |
|
|
iounmap(rme96->iobase);
|
1524 |
|
|
rme96->iobase = NULL;
|
1525 |
|
|
}
|
1526 |
|
|
if (rme96->port) {
|
1527 |
|
|
pci_release_regions(rme96->pci);
|
1528 |
|
|
rme96->port = 0;
|
1529 |
|
|
}
|
1530 |
|
|
pci_disable_device(rme96->pci);
|
1531 |
|
|
}
|
1532 |
|
|
|
1533 |
|
|
static void
|
1534 |
|
|
snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
|
1535 |
|
|
{
|
1536 |
|
|
struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
|
1537 |
|
|
rme96->spdif_pcm = NULL;
|
1538 |
|
|
}
|
1539 |
|
|
|
1540 |
|
|
static void
|
1541 |
|
|
snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
|
1542 |
|
|
{
|
1543 |
|
|
struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
|
1544 |
|
|
rme96->adat_pcm = NULL;
|
1545 |
|
|
}
|
1546 |
|
|
|
1547 |
|
|
static int __devinit
|
1548 |
|
|
snd_rme96_create(struct rme96 *rme96)
|
1549 |
|
|
{
|
1550 |
|
|
struct pci_dev *pci = rme96->pci;
|
1551 |
|
|
int err;
|
1552 |
|
|
|
1553 |
|
|
rme96->irq = -1;
|
1554 |
|
|
spin_lock_init(&rme96->lock);
|
1555 |
|
|
|
1556 |
|
|
if ((err = pci_enable_device(pci)) < 0)
|
1557 |
|
|
return err;
|
1558 |
|
|
|
1559 |
|
|
if ((err = pci_request_regions(pci, "RME96")) < 0)
|
1560 |
|
|
return err;
|
1561 |
|
|
rme96->port = pci_resource_start(rme96->pci, 0);
|
1562 |
|
|
|
1563 |
|
|
if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
|
1564 |
|
|
snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
|
1565 |
|
|
return -ENOMEM;
|
1566 |
|
|
}
|
1567 |
|
|
|
1568 |
|
|
if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
|
1569 |
|
|
"RME96", rme96)) {
|
1570 |
|
|
snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
|
1571 |
|
|
return -EBUSY;
|
1572 |
|
|
}
|
1573 |
|
|
rme96->irq = pci->irq;
|
1574 |
|
|
|
1575 |
|
|
/* read the card's revision number */
|
1576 |
|
|
pci_read_config_byte(pci, 8, &rme96->rev);
|
1577 |
|
|
|
1578 |
|
|
/* set up ALSA pcm device for S/PDIF */
|
1579 |
|
|
if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
|
1580 |
|
|
1, 1, &rme96->spdif_pcm)) < 0)
|
1581 |
|
|
{
|
1582 |
|
|
return err;
|
1583 |
|
|
}
|
1584 |
|
|
rme96->spdif_pcm->private_data = rme96;
|
1585 |
|
|
rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
|
1586 |
|
|
strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
|
1587 |
|
|
snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
|
1588 |
|
|
snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
|
1589 |
|
|
|
1590 |
|
|
rme96->spdif_pcm->info_flags = 0;
|
1591 |
|
|
|
1592 |
|
|
/* set up ALSA pcm device for ADAT */
|
1593 |
|
|
if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
|
1594 |
|
|
/* ADAT is not available on the base model */
|
1595 |
|
|
rme96->adat_pcm = NULL;
|
1596 |
|
|
} else {
|
1597 |
|
|
if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
|
1598 |
|
|
1, 1, &rme96->adat_pcm)) < 0)
|
1599 |
|
|
{
|
1600 |
|
|
return err;
|
1601 |
|
|
}
|
1602 |
|
|
rme96->adat_pcm->private_data = rme96;
|
1603 |
|
|
rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
|
1604 |
|
|
strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
|
1605 |
|
|
snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
|
1606 |
|
|
snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
|
1607 |
|
|
|
1608 |
|
|
rme96->adat_pcm->info_flags = 0;
|
1609 |
|
|
}
|
1610 |
|
|
|
1611 |
|
|
rme96->playback_periodsize = 0;
|
1612 |
|
|
rme96->capture_periodsize = 0;
|
1613 |
|
|
|
1614 |
|
|
/* make sure playback/capture is stopped, if by some reason active */
|
1615 |
|
|
snd_rme96_playback_stop(rme96);
|
1616 |
|
|
snd_rme96_capture_stop(rme96);
|
1617 |
|
|
|
1618 |
|
|
/* set default values in registers */
|
1619 |
|
|
rme96->wcreg =
|
1620 |
|
|
RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
|
1621 |
|
|
RME96_WCR_SEL | /* normal playback */
|
1622 |
|
|
RME96_WCR_MASTER | /* set to master clock mode */
|
1623 |
|
|
RME96_WCR_INP_0; /* set coaxial input */
|
1624 |
|
|
|
1625 |
|
|
rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
|
1626 |
|
|
|
1627 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1628 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
1629 |
|
|
|
1630 |
|
|
/* reset the ADC */
|
1631 |
|
|
writel(rme96->areg | RME96_AR_PD2,
|
1632 |
|
|
rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
1633 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
1634 |
|
|
|
1635 |
|
|
/* reset and enable the DAC (order is important). */
|
1636 |
|
|
snd_rme96_reset_dac(rme96);
|
1637 |
|
|
rme96->areg |= RME96_AR_DAC_EN;
|
1638 |
|
|
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
|
1639 |
|
|
|
1640 |
|
|
/* reset playback and record buffer pointers */
|
1641 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
|
1642 |
|
|
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
|
1643 |
|
|
|
1644 |
|
|
/* reset volume */
|
1645 |
|
|
rme96->vol[0] = rme96->vol[1] = 0;
|
1646 |
|
|
if (RME96_HAS_ANALOG_OUT(rme96)) {
|
1647 |
|
|
snd_rme96_apply_dac_volume(rme96);
|
1648 |
|
|
}
|
1649 |
|
|
|
1650 |
|
|
/* init switch interface */
|
1651 |
|
|
if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
|
1652 |
|
|
return err;
|
1653 |
|
|
}
|
1654 |
|
|
|
1655 |
|
|
/* init proc interface */
|
1656 |
|
|
snd_rme96_proc_init(rme96);
|
1657 |
|
|
|
1658 |
|
|
return 0;
|
1659 |
|
|
}
|
1660 |
|
|
|
1661 |
|
|
/*
|
1662 |
|
|
* proc interface
|
1663 |
|
|
*/
|
1664 |
|
|
|
1665 |
|
|
static void
|
1666 |
|
|
snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
|
1667 |
|
|
{
|
1668 |
|
|
int n;
|
1669 |
|
|
struct rme96 *rme96 = (struct rme96 *)entry->private_data;
|
1670 |
|
|
|
1671 |
|
|
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1672 |
|
|
|
1673 |
|
|
snd_iprintf(buffer, rme96->card->longname);
|
1674 |
|
|
snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
|
1675 |
|
|
|
1676 |
|
|
snd_iprintf(buffer, "\nGeneral settings\n");
|
1677 |
|
|
if (rme96->wcreg & RME96_WCR_IDIS) {
|
1678 |
|
|
snd_iprintf(buffer, " period size: N/A (interrupts "
|
1679 |
|
|
"disabled)\n");
|
1680 |
|
|
} else if (rme96->wcreg & RME96_WCR_ISEL) {
|
1681 |
|
|
snd_iprintf(buffer, " period size: 2048 bytes\n");
|
1682 |
|
|
} else {
|
1683 |
|
|
snd_iprintf(buffer, " period size: 8192 bytes\n");
|
1684 |
|
|
}
|
1685 |
|
|
snd_iprintf(buffer, "\nInput settings\n");
|
1686 |
|
|
switch (snd_rme96_getinputtype(rme96)) {
|
1687 |
|
|
case RME96_INPUT_OPTICAL:
|
1688 |
|
|
snd_iprintf(buffer, " input: optical");
|
1689 |
|
|
break;
|
1690 |
|
|
case RME96_INPUT_COAXIAL:
|
1691 |
|
|
snd_iprintf(buffer, " input: coaxial");
|
1692 |
|
|
break;
|
1693 |
|
|
case RME96_INPUT_INTERNAL:
|
1694 |
|
|
snd_iprintf(buffer, " input: internal");
|
1695 |
|
|
break;
|
1696 |
|
|
case RME96_INPUT_XLR:
|
1697 |
|
|
snd_iprintf(buffer, " input: XLR");
|
1698 |
|
|
break;
|
1699 |
|
|
case RME96_INPUT_ANALOG:
|
1700 |
|
|
snd_iprintf(buffer, " input: analog");
|
1701 |
|
|
break;
|
1702 |
|
|
}
|
1703 |
|
|
if (snd_rme96_capture_getrate(rme96, &n) < 0) {
|
1704 |
|
|
snd_iprintf(buffer, "\n sample rate: no valid signal\n");
|
1705 |
|
|
} else {
|
1706 |
|
|
if (n) {
|
1707 |
|
|
snd_iprintf(buffer, " (8 channels)\n");
|
1708 |
|
|
} else {
|
1709 |
|
|
snd_iprintf(buffer, " (2 channels)\n");
|
1710 |
|
|
}
|
1711 |
|
|
snd_iprintf(buffer, " sample rate: %d Hz\n",
|
1712 |
|
|
snd_rme96_capture_getrate(rme96, &n));
|
1713 |
|
|
}
|
1714 |
|
|
if (rme96->wcreg & RME96_WCR_MODE24_2) {
|
1715 |
|
|
snd_iprintf(buffer, " sample format: 24 bit\n");
|
1716 |
|
|
} else {
|
1717 |
|
|
snd_iprintf(buffer, " sample format: 16 bit\n");
|
1718 |
|
|
}
|
1719 |
|
|
|
1720 |
|
|
snd_iprintf(buffer, "\nOutput settings\n");
|
1721 |
|
|
if (rme96->wcreg & RME96_WCR_SEL) {
|
1722 |
|
|
snd_iprintf(buffer, " output signal: normal playback\n");
|
1723 |
|
|
} else {
|
1724 |
|
|
snd_iprintf(buffer, " output signal: same as input\n");
|
1725 |
|
|
}
|
1726 |
|
|
snd_iprintf(buffer, " sample rate: %d Hz\n",
|
1727 |
|
|
snd_rme96_playback_getrate(rme96));
|
1728 |
|
|
if (rme96->wcreg & RME96_WCR_MODE24) {
|
1729 |
|
|
snd_iprintf(buffer, " sample format: 24 bit\n");
|
1730 |
|
|
} else {
|
1731 |
|
|
snd_iprintf(buffer, " sample format: 16 bit\n");
|
1732 |
|
|
}
|
1733 |
|
|
if (rme96->areg & RME96_AR_WSEL) {
|
1734 |
|
|
snd_iprintf(buffer, " sample clock source: word clock\n");
|
1735 |
|
|
} else if (rme96->wcreg & RME96_WCR_MASTER) {
|
1736 |
|
|
snd_iprintf(buffer, " sample clock source: internal\n");
|
1737 |
|
|
} else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
|
1738 |
|
|
snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
|
1739 |
|
|
} else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
|
1740 |
|
|
snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
|
1741 |
|
|
} else {
|
1742 |
|
|
snd_iprintf(buffer, " sample clock source: autosync\n");
|
1743 |
|
|
}
|
1744 |
|
|
if (rme96->wcreg & RME96_WCR_PRO) {
|
1745 |
|
|
snd_iprintf(buffer, " format: AES/EBU (professional)\n");
|
1746 |
|
|
} else {
|
1747 |
|
|
snd_iprintf(buffer, " format: IEC958 (consumer)\n");
|
1748 |
|
|
}
|
1749 |
|
|
if (rme96->wcreg & RME96_WCR_EMP) {
|
1750 |
|
|
snd_iprintf(buffer, " emphasis: on\n");
|
1751 |
|
|
} else {
|
1752 |
|
|
snd_iprintf(buffer, " emphasis: off\n");
|
1753 |
|
|
}
|
1754 |
|
|
if (rme96->wcreg & RME96_WCR_DOLBY) {
|
1755 |
|
|
snd_iprintf(buffer, " non-audio (dolby): on\n");
|
1756 |
|
|
} else {
|
1757 |
|
|
snd_iprintf(buffer, " non-audio (dolby): off\n");
|
1758 |
|
|
}
|
1759 |
|
|
if (RME96_HAS_ANALOG_IN(rme96)) {
|
1760 |
|
|
snd_iprintf(buffer, "\nAnalog output settings\n");
|
1761 |
|
|
switch (snd_rme96_getmontracks(rme96)) {
|
1762 |
|
|
case RME96_MONITOR_TRACKS_1_2:
|
1763 |
|
|
snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
|
1764 |
|
|
break;
|
1765 |
|
|
case RME96_MONITOR_TRACKS_3_4:
|
1766 |
|
|
snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
|
1767 |
|
|
break;
|
1768 |
|
|
case RME96_MONITOR_TRACKS_5_6:
|
1769 |
|
|
snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
|
1770 |
|
|
break;
|
1771 |
|
|
case RME96_MONITOR_TRACKS_7_8:
|
1772 |
|
|
snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
|
1773 |
|
|
break;
|
1774 |
|
|
}
|
1775 |
|
|
switch (snd_rme96_getattenuation(rme96)) {
|
1776 |
|
|
case RME96_ATTENUATION_0:
|
1777 |
|
|
snd_iprintf(buffer, " attenuation: 0 dB\n");
|
1778 |
|
|
break;
|
1779 |
|
|
case RME96_ATTENUATION_6:
|
1780 |
|
|
snd_iprintf(buffer, " attenuation: -6 dB\n");
|
1781 |
|
|
break;
|
1782 |
|
|
case RME96_ATTENUATION_12:
|
1783 |
|
|
snd_iprintf(buffer, " attenuation: -12 dB\n");
|
1784 |
|
|
break;
|
1785 |
|
|
case RME96_ATTENUATION_18:
|
1786 |
|
|
snd_iprintf(buffer, " attenuation: -18 dB\n");
|
1787 |
|
|
break;
|
1788 |
|
|
}
|
1789 |
|
|
snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
|
1790 |
|
|
snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
|
1791 |
|
|
}
|
1792 |
|
|
}
|
1793 |
|
|
|
1794 |
|
|
static void __devinit
|
1795 |
|
|
snd_rme96_proc_init(struct rme96 *rme96)
|
1796 |
|
|
{
|
1797 |
|
|
struct snd_info_entry *entry;
|
1798 |
|
|
|
1799 |
|
|
if (! snd_card_proc_new(rme96->card, "rme96", &entry))
|
1800 |
|
|
snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
|
1801 |
|
|
}
|
1802 |
|
|
|
1803 |
|
|
/*
|
1804 |
|
|
* control interface
|
1805 |
|
|
*/
|
1806 |
|
|
|
1807 |
|
|
#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
|
1808 |
|
|
|
1809 |
|
|
static int
|
1810 |
|
|
snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1811 |
|
|
{
|
1812 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1813 |
|
|
|
1814 |
|
|
spin_lock_irq(&rme96->lock);
|
1815 |
|
|
ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
|
1816 |
|
|
spin_unlock_irq(&rme96->lock);
|
1817 |
|
|
return 0;
|
1818 |
|
|
}
|
1819 |
|
|
static int
|
1820 |
|
|
snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1821 |
|
|
{
|
1822 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1823 |
|
|
unsigned int val;
|
1824 |
|
|
int change;
|
1825 |
|
|
|
1826 |
|
|
val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
|
1827 |
|
|
spin_lock_irq(&rme96->lock);
|
1828 |
|
|
val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
|
1829 |
|
|
change = val != rme96->wcreg;
|
1830 |
|
|
rme96->wcreg = val;
|
1831 |
|
|
writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
1832 |
|
|
spin_unlock_irq(&rme96->lock);
|
1833 |
|
|
return change;
|
1834 |
|
|
}
|
1835 |
|
|
|
1836 |
|
|
static int
|
1837 |
|
|
snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1838 |
|
|
{
|
1839 |
|
|
static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
|
1840 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1841 |
|
|
char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
|
1842 |
|
|
|
1843 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1844 |
|
|
uinfo->count = 1;
|
1845 |
|
|
switch (rme96->pci->device) {
|
1846 |
|
|
case PCI_DEVICE_ID_RME_DIGI96:
|
1847 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8:
|
1848 |
|
|
uinfo->value.enumerated.items = 3;
|
1849 |
|
|
break;
|
1850 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
|
1851 |
|
|
uinfo->value.enumerated.items = 4;
|
1852 |
|
|
break;
|
1853 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
|
1854 |
|
|
if (rme96->rev > 4) {
|
1855 |
|
|
/* PST */
|
1856 |
|
|
uinfo->value.enumerated.items = 4;
|
1857 |
|
|
texts[3] = _texts[4]; /* Analog instead of XLR */
|
1858 |
|
|
} else {
|
1859 |
|
|
/* PAD */
|
1860 |
|
|
uinfo->value.enumerated.items = 5;
|
1861 |
|
|
}
|
1862 |
|
|
break;
|
1863 |
|
|
default:
|
1864 |
|
|
snd_BUG();
|
1865 |
|
|
break;
|
1866 |
|
|
}
|
1867 |
|
|
if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
|
1868 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
1869 |
|
|
}
|
1870 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1871 |
|
|
return 0;
|
1872 |
|
|
}
|
1873 |
|
|
static int
|
1874 |
|
|
snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1875 |
|
|
{
|
1876 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1877 |
|
|
unsigned int items = 3;
|
1878 |
|
|
|
1879 |
|
|
spin_lock_irq(&rme96->lock);
|
1880 |
|
|
ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
|
1881 |
|
|
|
1882 |
|
|
switch (rme96->pci->device) {
|
1883 |
|
|
case PCI_DEVICE_ID_RME_DIGI96:
|
1884 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8:
|
1885 |
|
|
items = 3;
|
1886 |
|
|
break;
|
1887 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
|
1888 |
|
|
items = 4;
|
1889 |
|
|
break;
|
1890 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
|
1891 |
|
|
if (rme96->rev > 4) {
|
1892 |
|
|
/* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
|
1893 |
|
|
if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
|
1894 |
|
|
ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
|
1895 |
|
|
}
|
1896 |
|
|
items = 4;
|
1897 |
|
|
} else {
|
1898 |
|
|
items = 5;
|
1899 |
|
|
}
|
1900 |
|
|
break;
|
1901 |
|
|
default:
|
1902 |
|
|
snd_BUG();
|
1903 |
|
|
break;
|
1904 |
|
|
}
|
1905 |
|
|
if (ucontrol->value.enumerated.item[0] >= items) {
|
1906 |
|
|
ucontrol->value.enumerated.item[0] = items - 1;
|
1907 |
|
|
}
|
1908 |
|
|
|
1909 |
|
|
spin_unlock_irq(&rme96->lock);
|
1910 |
|
|
return 0;
|
1911 |
|
|
}
|
1912 |
|
|
static int
|
1913 |
|
|
snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1914 |
|
|
{
|
1915 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1916 |
|
|
unsigned int val;
|
1917 |
|
|
int change, items = 3;
|
1918 |
|
|
|
1919 |
|
|
switch (rme96->pci->device) {
|
1920 |
|
|
case PCI_DEVICE_ID_RME_DIGI96:
|
1921 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8:
|
1922 |
|
|
items = 3;
|
1923 |
|
|
break;
|
1924 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
|
1925 |
|
|
items = 4;
|
1926 |
|
|
break;
|
1927 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
|
1928 |
|
|
if (rme96->rev > 4) {
|
1929 |
|
|
items = 4;
|
1930 |
|
|
} else {
|
1931 |
|
|
items = 5;
|
1932 |
|
|
}
|
1933 |
|
|
break;
|
1934 |
|
|
default:
|
1935 |
|
|
snd_BUG();
|
1936 |
|
|
break;
|
1937 |
|
|
}
|
1938 |
|
|
val = ucontrol->value.enumerated.item[0] % items;
|
1939 |
|
|
|
1940 |
|
|
/* special case for PST */
|
1941 |
|
|
if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
|
1942 |
|
|
if (val == RME96_INPUT_XLR) {
|
1943 |
|
|
val = RME96_INPUT_ANALOG;
|
1944 |
|
|
}
|
1945 |
|
|
}
|
1946 |
|
|
|
1947 |
|
|
spin_lock_irq(&rme96->lock);
|
1948 |
|
|
change = (int)val != snd_rme96_getinputtype(rme96);
|
1949 |
|
|
snd_rme96_setinputtype(rme96, val);
|
1950 |
|
|
spin_unlock_irq(&rme96->lock);
|
1951 |
|
|
return change;
|
1952 |
|
|
}
|
1953 |
|
|
|
1954 |
|
|
static int
|
1955 |
|
|
snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1956 |
|
|
{
|
1957 |
|
|
static char *texts[3] = { "AutoSync", "Internal", "Word" };
|
1958 |
|
|
|
1959 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1960 |
|
|
uinfo->count = 1;
|
1961 |
|
|
uinfo->value.enumerated.items = 3;
|
1962 |
|
|
if (uinfo->value.enumerated.item > 2) {
|
1963 |
|
|
uinfo->value.enumerated.item = 2;
|
1964 |
|
|
}
|
1965 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1966 |
|
|
return 0;
|
1967 |
|
|
}
|
1968 |
|
|
static int
|
1969 |
|
|
snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1970 |
|
|
{
|
1971 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1972 |
|
|
|
1973 |
|
|
spin_lock_irq(&rme96->lock);
|
1974 |
|
|
ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
|
1975 |
|
|
spin_unlock_irq(&rme96->lock);
|
1976 |
|
|
return 0;
|
1977 |
|
|
}
|
1978 |
|
|
static int
|
1979 |
|
|
snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1980 |
|
|
{
|
1981 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
1982 |
|
|
unsigned int val;
|
1983 |
|
|
int change;
|
1984 |
|
|
|
1985 |
|
|
val = ucontrol->value.enumerated.item[0] % 3;
|
1986 |
|
|
spin_lock_irq(&rme96->lock);
|
1987 |
|
|
change = (int)val != snd_rme96_getclockmode(rme96);
|
1988 |
|
|
snd_rme96_setclockmode(rme96, val);
|
1989 |
|
|
spin_unlock_irq(&rme96->lock);
|
1990 |
|
|
return change;
|
1991 |
|
|
}
|
1992 |
|
|
|
1993 |
|
|
static int
|
1994 |
|
|
snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1995 |
|
|
{
|
1996 |
|
|
static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
|
1997 |
|
|
|
1998 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1999 |
|
|
uinfo->count = 1;
|
2000 |
|
|
uinfo->value.enumerated.items = 4;
|
2001 |
|
|
if (uinfo->value.enumerated.item > 3) {
|
2002 |
|
|
uinfo->value.enumerated.item = 3;
|
2003 |
|
|
}
|
2004 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2005 |
|
|
return 0;
|
2006 |
|
|
}
|
2007 |
|
|
static int
|
2008 |
|
|
snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2009 |
|
|
{
|
2010 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2011 |
|
|
|
2012 |
|
|
spin_lock_irq(&rme96->lock);
|
2013 |
|
|
ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
|
2014 |
|
|
spin_unlock_irq(&rme96->lock);
|
2015 |
|
|
return 0;
|
2016 |
|
|
}
|
2017 |
|
|
static int
|
2018 |
|
|
snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2019 |
|
|
{
|
2020 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2021 |
|
|
unsigned int val;
|
2022 |
|
|
int change;
|
2023 |
|
|
|
2024 |
|
|
val = ucontrol->value.enumerated.item[0] % 4;
|
2025 |
|
|
spin_lock_irq(&rme96->lock);
|
2026 |
|
|
|
2027 |
|
|
change = (int)val != snd_rme96_getattenuation(rme96);
|
2028 |
|
|
snd_rme96_setattenuation(rme96, val);
|
2029 |
|
|
spin_unlock_irq(&rme96->lock);
|
2030 |
|
|
return change;
|
2031 |
|
|
}
|
2032 |
|
|
|
2033 |
|
|
static int
|
2034 |
|
|
snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2035 |
|
|
{
|
2036 |
|
|
static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
|
2037 |
|
|
|
2038 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2039 |
|
|
uinfo->count = 1;
|
2040 |
|
|
uinfo->value.enumerated.items = 4;
|
2041 |
|
|
if (uinfo->value.enumerated.item > 3) {
|
2042 |
|
|
uinfo->value.enumerated.item = 3;
|
2043 |
|
|
}
|
2044 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2045 |
|
|
return 0;
|
2046 |
|
|
}
|
2047 |
|
|
static int
|
2048 |
|
|
snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2049 |
|
|
{
|
2050 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2051 |
|
|
|
2052 |
|
|
spin_lock_irq(&rme96->lock);
|
2053 |
|
|
ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
|
2054 |
|
|
spin_unlock_irq(&rme96->lock);
|
2055 |
|
|
return 0;
|
2056 |
|
|
}
|
2057 |
|
|
static int
|
2058 |
|
|
snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2059 |
|
|
{
|
2060 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2061 |
|
|
unsigned int val;
|
2062 |
|
|
int change;
|
2063 |
|
|
|
2064 |
|
|
val = ucontrol->value.enumerated.item[0] % 4;
|
2065 |
|
|
spin_lock_irq(&rme96->lock);
|
2066 |
|
|
change = (int)val != snd_rme96_getmontracks(rme96);
|
2067 |
|
|
snd_rme96_setmontracks(rme96, val);
|
2068 |
|
|
spin_unlock_irq(&rme96->lock);
|
2069 |
|
|
return change;
|
2070 |
|
|
}
|
2071 |
|
|
|
2072 |
|
|
static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
|
2073 |
|
|
{
|
2074 |
|
|
u32 val = 0;
|
2075 |
|
|
val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
|
2076 |
|
|
val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
|
2077 |
|
|
if (val & RME96_WCR_PRO)
|
2078 |
|
|
val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
|
2079 |
|
|
else
|
2080 |
|
|
val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
|
2081 |
|
|
return val;
|
2082 |
|
|
}
|
2083 |
|
|
|
2084 |
|
|
static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
|
2085 |
|
|
{
|
2086 |
|
|
aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
|
2087 |
|
|
((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
|
2088 |
|
|
if (val & RME96_WCR_PRO)
|
2089 |
|
|
aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
|
2090 |
|
|
else
|
2091 |
|
|
aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
|
2092 |
|
|
}
|
2093 |
|
|
|
2094 |
|
|
static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2095 |
|
|
{
|
2096 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
2097 |
|
|
uinfo->count = 1;
|
2098 |
|
|
return 0;
|
2099 |
|
|
}
|
2100 |
|
|
|
2101 |
|
|
static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2102 |
|
|
{
|
2103 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2104 |
|
|
|
2105 |
|
|
snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
|
2106 |
|
|
return 0;
|
2107 |
|
|
}
|
2108 |
|
|
|
2109 |
|
|
static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2110 |
|
|
{
|
2111 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2112 |
|
|
int change;
|
2113 |
|
|
u32 val;
|
2114 |
|
|
|
2115 |
|
|
val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
|
2116 |
|
|
spin_lock_irq(&rme96->lock);
|
2117 |
|
|
change = val != rme96->wcreg_spdif;
|
2118 |
|
|
rme96->wcreg_spdif = val;
|
2119 |
|
|
spin_unlock_irq(&rme96->lock);
|
2120 |
|
|
return change;
|
2121 |
|
|
}
|
2122 |
|
|
|
2123 |
|
|
static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2124 |
|
|
{
|
2125 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
2126 |
|
|
uinfo->count = 1;
|
2127 |
|
|
return 0;
|
2128 |
|
|
}
|
2129 |
|
|
|
2130 |
|
|
static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2131 |
|
|
{
|
2132 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2133 |
|
|
|
2134 |
|
|
snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
|
2135 |
|
|
return 0;
|
2136 |
|
|
}
|
2137 |
|
|
|
2138 |
|
|
static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2139 |
|
|
{
|
2140 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2141 |
|
|
int change;
|
2142 |
|
|
u32 val;
|
2143 |
|
|
|
2144 |
|
|
val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
|
2145 |
|
|
spin_lock_irq(&rme96->lock);
|
2146 |
|
|
change = val != rme96->wcreg_spdif_stream;
|
2147 |
|
|
rme96->wcreg_spdif_stream = val;
|
2148 |
|
|
rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
|
2149 |
|
|
rme96->wcreg |= val;
|
2150 |
|
|
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
|
2151 |
|
|
spin_unlock_irq(&rme96->lock);
|
2152 |
|
|
return change;
|
2153 |
|
|
}
|
2154 |
|
|
|
2155 |
|
|
static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2156 |
|
|
{
|
2157 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
2158 |
|
|
uinfo->count = 1;
|
2159 |
|
|
return 0;
|
2160 |
|
|
}
|
2161 |
|
|
|
2162 |
|
|
static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2163 |
|
|
{
|
2164 |
|
|
ucontrol->value.iec958.status[0] = kcontrol->private_value;
|
2165 |
|
|
return 0;
|
2166 |
|
|
}
|
2167 |
|
|
|
2168 |
|
|
static int
|
2169 |
|
|
snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2170 |
|
|
{
|
2171 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2172 |
|
|
|
2173 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
2174 |
|
|
uinfo->count = 2;
|
2175 |
|
|
uinfo->value.integer.min = 0;
|
2176 |
|
|
uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
|
2177 |
|
|
return 0;
|
2178 |
|
|
}
|
2179 |
|
|
|
2180 |
|
|
static int
|
2181 |
|
|
snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
|
2182 |
|
|
{
|
2183 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2184 |
|
|
|
2185 |
|
|
spin_lock_irq(&rme96->lock);
|
2186 |
|
|
u->value.integer.value[0] = rme96->vol[0];
|
2187 |
|
|
u->value.integer.value[1] = rme96->vol[1];
|
2188 |
|
|
spin_unlock_irq(&rme96->lock);
|
2189 |
|
|
|
2190 |
|
|
return 0;
|
2191 |
|
|
}
|
2192 |
|
|
|
2193 |
|
|
static int
|
2194 |
|
|
snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
|
2195 |
|
|
{
|
2196 |
|
|
struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
|
2197 |
|
|
int change = 0;
|
2198 |
|
|
|
2199 |
|
|
if (!RME96_HAS_ANALOG_OUT(rme96)) {
|
2200 |
|
|
return -EINVAL;
|
2201 |
|
|
}
|
2202 |
|
|
spin_lock_irq(&rme96->lock);
|
2203 |
|
|
if (u->value.integer.value[0] != rme96->vol[0]) {
|
2204 |
|
|
rme96->vol[0] = u->value.integer.value[0];
|
2205 |
|
|
change = 1;
|
2206 |
|
|
}
|
2207 |
|
|
if (u->value.integer.value[1] != rme96->vol[1]) {
|
2208 |
|
|
rme96->vol[1] = u->value.integer.value[1];
|
2209 |
|
|
change = 1;
|
2210 |
|
|
}
|
2211 |
|
|
if (change) {
|
2212 |
|
|
snd_rme96_apply_dac_volume(rme96);
|
2213 |
|
|
}
|
2214 |
|
|
spin_unlock_irq(&rme96->lock);
|
2215 |
|
|
|
2216 |
|
|
return change;
|
2217 |
|
|
}
|
2218 |
|
|
|
2219 |
|
|
static struct snd_kcontrol_new snd_rme96_controls[] = {
|
2220 |
|
|
{
|
2221 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
2222 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
|
2223 |
|
|
.info = snd_rme96_control_spdif_info,
|
2224 |
|
|
.get = snd_rme96_control_spdif_get,
|
2225 |
|
|
.put = snd_rme96_control_spdif_put
|
2226 |
|
|
},
|
2227 |
|
|
{
|
2228 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
|
2229 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
2230 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
|
2231 |
|
|
.info = snd_rme96_control_spdif_stream_info,
|
2232 |
|
|
.get = snd_rme96_control_spdif_stream_get,
|
2233 |
|
|
.put = snd_rme96_control_spdif_stream_put
|
2234 |
|
|
},
|
2235 |
|
|
{
|
2236 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ,
|
2237 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
2238 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
|
2239 |
|
|
.info = snd_rme96_control_spdif_mask_info,
|
2240 |
|
|
.get = snd_rme96_control_spdif_mask_get,
|
2241 |
|
|
.private_value = IEC958_AES0_NONAUDIO |
|
2242 |
|
|
IEC958_AES0_PROFESSIONAL |
|
2243 |
|
|
IEC958_AES0_CON_EMPHASIS
|
2244 |
|
|
},
|
2245 |
|
|
{
|
2246 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ,
|
2247 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
2248 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
|
2249 |
|
|
.info = snd_rme96_control_spdif_mask_info,
|
2250 |
|
|
.get = snd_rme96_control_spdif_mask_get,
|
2251 |
|
|
.private_value = IEC958_AES0_NONAUDIO |
|
2252 |
|
|
IEC958_AES0_PROFESSIONAL |
|
2253 |
|
|
IEC958_AES0_PRO_EMPHASIS
|
2254 |
|
|
},
|
2255 |
|
|
{
|
2256 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2257 |
|
|
.name = "Input Connector",
|
2258 |
|
|
.info = snd_rme96_info_inputtype_control,
|
2259 |
|
|
.get = snd_rme96_get_inputtype_control,
|
2260 |
|
|
.put = snd_rme96_put_inputtype_control
|
2261 |
|
|
},
|
2262 |
|
|
{
|
2263 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2264 |
|
|
.name = "Loopback Input",
|
2265 |
|
|
.info = snd_rme96_info_loopback_control,
|
2266 |
|
|
.get = snd_rme96_get_loopback_control,
|
2267 |
|
|
.put = snd_rme96_put_loopback_control
|
2268 |
|
|
},
|
2269 |
|
|
{
|
2270 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2271 |
|
|
.name = "Sample Clock Source",
|
2272 |
|
|
.info = snd_rme96_info_clockmode_control,
|
2273 |
|
|
.get = snd_rme96_get_clockmode_control,
|
2274 |
|
|
.put = snd_rme96_put_clockmode_control
|
2275 |
|
|
},
|
2276 |
|
|
{
|
2277 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2278 |
|
|
.name = "Monitor Tracks",
|
2279 |
|
|
.info = snd_rme96_info_montracks_control,
|
2280 |
|
|
.get = snd_rme96_get_montracks_control,
|
2281 |
|
|
.put = snd_rme96_put_montracks_control
|
2282 |
|
|
},
|
2283 |
|
|
{
|
2284 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2285 |
|
|
.name = "Attenuation",
|
2286 |
|
|
.info = snd_rme96_info_attenuation_control,
|
2287 |
|
|
.get = snd_rme96_get_attenuation_control,
|
2288 |
|
|
.put = snd_rme96_put_attenuation_control
|
2289 |
|
|
},
|
2290 |
|
|
{
|
2291 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
2292 |
|
|
.name = "DAC Playback Volume",
|
2293 |
|
|
.info = snd_rme96_dac_volume_info,
|
2294 |
|
|
.get = snd_rme96_dac_volume_get,
|
2295 |
|
|
.put = snd_rme96_dac_volume_put
|
2296 |
|
|
}
|
2297 |
|
|
};
|
2298 |
|
|
|
2299 |
|
|
static int
|
2300 |
|
|
snd_rme96_create_switches(struct snd_card *card,
|
2301 |
|
|
struct rme96 *rme96)
|
2302 |
|
|
{
|
2303 |
|
|
int idx, err;
|
2304 |
|
|
struct snd_kcontrol *kctl;
|
2305 |
|
|
|
2306 |
|
|
for (idx = 0; idx < 7; idx++) {
|
2307 |
|
|
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
|
2308 |
|
|
return err;
|
2309 |
|
|
if (idx == 1) /* IEC958 (S/PDIF) Stream */
|
2310 |
|
|
rme96->spdif_ctl = kctl;
|
2311 |
|
|
}
|
2312 |
|
|
|
2313 |
|
|
if (RME96_HAS_ANALOG_OUT(rme96)) {
|
2314 |
|
|
for (idx = 7; idx < 10; idx++)
|
2315 |
|
|
if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
|
2316 |
|
|
return err;
|
2317 |
|
|
}
|
2318 |
|
|
|
2319 |
|
|
return 0;
|
2320 |
|
|
}
|
2321 |
|
|
|
2322 |
|
|
/*
|
2323 |
|
|
* Card initialisation
|
2324 |
|
|
*/
|
2325 |
|
|
|
2326 |
|
|
static void snd_rme96_card_free(struct snd_card *card)
|
2327 |
|
|
{
|
2328 |
|
|
snd_rme96_free(card->private_data);
|
2329 |
|
|
}
|
2330 |
|
|
|
2331 |
|
|
static int __devinit
|
2332 |
|
|
snd_rme96_probe(struct pci_dev *pci,
|
2333 |
|
|
const struct pci_device_id *pci_id)
|
2334 |
|
|
{
|
2335 |
|
|
static int dev;
|
2336 |
|
|
struct rme96 *rme96;
|
2337 |
|
|
struct snd_card *card;
|
2338 |
|
|
int err;
|
2339 |
|
|
u8 val;
|
2340 |
|
|
|
2341 |
|
|
if (dev >= SNDRV_CARDS) {
|
2342 |
|
|
return -ENODEV;
|
2343 |
|
|
}
|
2344 |
|
|
if (!enable[dev]) {
|
2345 |
|
|
dev++;
|
2346 |
|
|
return -ENOENT;
|
2347 |
|
|
}
|
2348 |
|
|
if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
|
2349 |
|
|
sizeof(struct rme96))) == NULL)
|
2350 |
|
|
return -ENOMEM;
|
2351 |
|
|
card->private_free = snd_rme96_card_free;
|
2352 |
|
|
rme96 = (struct rme96 *)card->private_data;
|
2353 |
|
|
rme96->card = card;
|
2354 |
|
|
rme96->pci = pci;
|
2355 |
|
|
snd_card_set_dev(card, &pci->dev);
|
2356 |
|
|
if ((err = snd_rme96_create(rme96)) < 0) {
|
2357 |
|
|
snd_card_free(card);
|
2358 |
|
|
return err;
|
2359 |
|
|
}
|
2360 |
|
|
|
2361 |
|
|
strcpy(card->driver, "Digi96");
|
2362 |
|
|
switch (rme96->pci->device) {
|
2363 |
|
|
case PCI_DEVICE_ID_RME_DIGI96:
|
2364 |
|
|
strcpy(card->shortname, "RME Digi96");
|
2365 |
|
|
break;
|
2366 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8:
|
2367 |
|
|
strcpy(card->shortname, "RME Digi96/8");
|
2368 |
|
|
break;
|
2369 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
|
2370 |
|
|
strcpy(card->shortname, "RME Digi96/8 PRO");
|
2371 |
|
|
break;
|
2372 |
|
|
case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
|
2373 |
|
|
pci_read_config_byte(rme96->pci, 8, &val);
|
2374 |
|
|
if (val < 5) {
|
2375 |
|
|
strcpy(card->shortname, "RME Digi96/8 PAD");
|
2376 |
|
|
} else {
|
2377 |
|
|
strcpy(card->shortname, "RME Digi96/8 PST");
|
2378 |
|
|
}
|
2379 |
|
|
break;
|
2380 |
|
|
}
|
2381 |
|
|
sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
|
2382 |
|
|
rme96->port, rme96->irq);
|
2383 |
|
|
|
2384 |
|
|
if ((err = snd_card_register(card)) < 0) {
|
2385 |
|
|
snd_card_free(card);
|
2386 |
|
|
return err;
|
2387 |
|
|
}
|
2388 |
|
|
pci_set_drvdata(pci, card);
|
2389 |
|
|
dev++;
|
2390 |
|
|
return 0;
|
2391 |
|
|
}
|
2392 |
|
|
|
2393 |
|
|
static void __devexit snd_rme96_remove(struct pci_dev *pci)
|
2394 |
|
|
{
|
2395 |
|
|
snd_card_free(pci_get_drvdata(pci));
|
2396 |
|
|
pci_set_drvdata(pci, NULL);
|
2397 |
|
|
}
|
2398 |
|
|
|
2399 |
|
|
static struct pci_driver driver = {
|
2400 |
|
|
.name = "RME Digi96",
|
2401 |
|
|
.id_table = snd_rme96_ids,
|
2402 |
|
|
.probe = snd_rme96_probe,
|
2403 |
|
|
.remove = __devexit_p(snd_rme96_remove),
|
2404 |
|
|
};
|
2405 |
|
|
|
2406 |
|
|
static int __init alsa_card_rme96_init(void)
|
2407 |
|
|
{
|
2408 |
|
|
return pci_register_driver(&driver);
|
2409 |
|
|
}
|
2410 |
|
|
|
2411 |
|
|
static void __exit alsa_card_rme96_exit(void)
|
2412 |
|
|
{
|
2413 |
|
|
pci_unregister_driver(&driver);
|
2414 |
|
|
}
|
2415 |
|
|
|
2416 |
|
|
module_init(alsa_card_rme96_init)
|
2417 |
|
|
module_exit(alsa_card_rme96_exit)
|