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marcus.erl |
/*
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* ALSA driver for RME Hammerfall DSP audio interface(s)
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*
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* Copyright (c) 2002 Paul Davis
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* Marcus Andersson
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* Thomas Charbonnel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <sound/driver.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include <linux/moduleparam.h>
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#include <sound/core.h>
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#include <sound/control.h>
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#include <sound/pcm.h>
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#include <sound/info.h>
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#include <sound/asoundef.h>
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#include <sound/rawmidi.h>
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#include <sound/hwdep.h>
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#include <sound/initval.h>
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#include <sound/hdsp.h>
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#include <asm/byteorder.h>
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#include <asm/current.h>
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#include <asm/io.h>
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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
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static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
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static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
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module_param_array(enable, bool, NULL, 0444);
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MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
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MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
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MODULE_DESCRIPTION("RME Hammerfall DSP");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
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"{RME HDSP-9652},"
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"{RME HDSP-9632}}");
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#ifdef HDSP_FW_LOADER
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MODULE_FIRMWARE("multiface_firmware.bin");
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MODULE_FIRMWARE("multiface_firmware_rev11.bin");
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MODULE_FIRMWARE("digiface_firmware.bin");
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MODULE_FIRMWARE("digiface_firmware_rev11.bin");
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#endif
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#define HDSP_MAX_CHANNELS 26
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#define HDSP_MAX_DS_CHANNELS 14
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#define HDSP_MAX_QS_CHANNELS 8
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#define DIGIFACE_SS_CHANNELS 26
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#define DIGIFACE_DS_CHANNELS 14
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#define MULTIFACE_SS_CHANNELS 18
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#define MULTIFACE_DS_CHANNELS 14
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#define H9652_SS_CHANNELS 26
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#define H9652_DS_CHANNELS 14
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/* This does not include possible Analog Extension Boards
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AEBs are detected at card initialization
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*/
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#define H9632_SS_CHANNELS 12
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#define H9632_DS_CHANNELS 8
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#define H9632_QS_CHANNELS 4
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/* Write registers. These are defined as byte-offsets from the iobase value.
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*/
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#define HDSP_resetPointer 0
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#define HDSP_freqReg 0
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#define HDSP_outputBufferAddress 32
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#define HDSP_inputBufferAddress 36
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#define HDSP_controlRegister 64
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#define HDSP_interruptConfirmation 96
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#define HDSP_outputEnable 128
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#define HDSP_control2Reg 256
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#define HDSP_midiDataOut0 352
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#define HDSP_midiDataOut1 356
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#define HDSP_fifoData 368
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#define HDSP_inputEnable 384
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/* Read registers. These are defined as byte-offsets from the iobase value
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*/
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#define HDSP_statusRegister 0
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#define HDSP_timecode 128
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#define HDSP_status2Register 192
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#define HDSP_midiDataOut0 352
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#define HDSP_midiDataOut1 356
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#define HDSP_midiDataIn0 360
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#define HDSP_midiDataIn1 364
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#define HDSP_midiStatusOut0 384
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#define HDSP_midiStatusOut1 388
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#define HDSP_midiStatusIn0 392
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#define HDSP_midiStatusIn1 396
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#define HDSP_fifoStatus 400
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/* the meters are regular i/o-mapped registers, but offset
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considerably from the rest. the peak registers are reset
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when read; the least-significant 4 bits are full-scale counters;
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the actual peak value is in the most-significant 24 bits.
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*/
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#define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
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#define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
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#define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
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#define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
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#define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
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/* This is for H9652 cards
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Peak values are read downward from the base
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Rms values are read upward
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There are rms values for the outputs too
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26*3 values are read in ss mode
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14*3 in ds mode, with no gap between values
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*/
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#define HDSP_9652_peakBase 7164
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#define HDSP_9652_rmsBase 4096
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/* c.f. the hdsp_9632_meters_t struct */
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#define HDSP_9632_metersBase 4096
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#define HDSP_IO_EXTENT 7168
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/* control2 register bits */
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#define HDSP_TMS 0x01
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#define HDSP_TCK 0x02
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#define HDSP_TDI 0x04
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#define HDSP_JTAG 0x08
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#define HDSP_PWDN 0x10
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#define HDSP_PROGRAM 0x020
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#define HDSP_CONFIG_MODE_0 0x040
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#define HDSP_CONFIG_MODE_1 0x080
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#define HDSP_VERSION_BIT 0x100
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#define HDSP_BIGENDIAN_MODE 0x200
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#define HDSP_RD_MULTIPLE 0x400
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#define HDSP_9652_ENABLE_MIXER 0x800
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#define HDSP_TDO 0x10000000
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#define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
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#define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
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/* Control Register bits */
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#define HDSP_Start (1<<0) /* start engine */
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#define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
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#define HDSP_Latency1 (1<<2) /* [ see above ] */
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#define HDSP_Latency2 (1<<3) /* [ see above ] */
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#define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
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#define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
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#define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
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#define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
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#define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
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#define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
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#define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
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#define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
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#define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
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#define HDSP_SyncRef2 (1<<13)
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#define HDSP_SPDIFInputSelect0 (1<<14)
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#define HDSP_SPDIFInputSelect1 (1<<15)
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#define HDSP_SyncRef0 (1<<16)
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#define HDSP_SyncRef1 (1<<17)
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#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
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#define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
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#define HDSP_Midi0InterruptEnable (1<<22)
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#define HDSP_Midi1InterruptEnable (1<<23)
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#define HDSP_LineOut (1<<24)
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#define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
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#define HDSP_ADGain1 (1<<26)
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#define HDSP_DAGain0 (1<<27)
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#define HDSP_DAGain1 (1<<28)
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#define HDSP_PhoneGain0 (1<<29)
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#define HDSP_PhoneGain1 (1<<30)
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#define HDSP_QuadSpeed (1<<31)
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#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
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#define HDSP_ADGainMinus10dBV HDSP_ADGainMask
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#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
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#define HDSP_ADGainLowGain 0
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#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
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#define HDSP_DAGainHighGain HDSP_DAGainMask
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#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
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#define HDSP_DAGainMinus10dBV 0
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#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
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#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
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#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
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#define HDSP_PhoneGainMinus12dB 0
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#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
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#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
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#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
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#define HDSP_SPDIFInputADAT1 0
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#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
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#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
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#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
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#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
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#define HDSP_SyncRef_ADAT1 0
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#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
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#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
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#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
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#define HDSP_SyncRef_WORD (HDSP_SyncRef2)
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#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
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/* Sample Clock Sources */
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#define HDSP_CLOCK_SOURCE_AUTOSYNC 0
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#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
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#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
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#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
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#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
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#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
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#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
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#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
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#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
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#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
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/* Preferred sync reference choices - used by "pref_sync_ref" control switch */
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#define HDSP_SYNC_FROM_WORD 0
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#define HDSP_SYNC_FROM_SPDIF 1
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#define HDSP_SYNC_FROM_ADAT1 2
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#define HDSP_SYNC_FROM_ADAT_SYNC 3
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#define HDSP_SYNC_FROM_ADAT2 4
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#define HDSP_SYNC_FROM_ADAT3 5
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/* SyncCheck status */
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#define HDSP_SYNC_CHECK_NO_LOCK 0
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#define HDSP_SYNC_CHECK_LOCK 1
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#define HDSP_SYNC_CHECK_SYNC 2
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/* AutoSync references - used by "autosync_ref" control switch */
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#define HDSP_AUTOSYNC_FROM_WORD 0
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#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
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#define HDSP_AUTOSYNC_FROM_SPDIF 2
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#define HDSP_AUTOSYNC_FROM_NONE 3
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#define HDSP_AUTOSYNC_FROM_ADAT1 4
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#define HDSP_AUTOSYNC_FROM_ADAT2 5
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#define HDSP_AUTOSYNC_FROM_ADAT3 6
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/* Possible sources of S/PDIF input */
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#define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
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#define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
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#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
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#define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
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#define HDSP_Frequency32KHz HDSP_Frequency0
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#define HDSP_Frequency44_1KHz HDSP_Frequency1
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#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
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#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
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#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
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#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
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/* For H9632 cards */
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#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
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#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
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#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
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/* RME says n = 104857600000000, but in the windows MADI driver, I see:
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return 104857600000000 / rate; // 100 MHz
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return 110100480000000 / rate; // 105 MHz
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*/
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#define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
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#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
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#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
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#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
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#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
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/* Status Register bits */
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#define HDSP_audioIRQPending (1<<0)
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|
|
#define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
|
300 |
|
|
#define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
|
301 |
|
|
#define HDSP_Lock1 (1<<2)
|
302 |
|
|
#define HDSP_Lock0 (1<<3)
|
303 |
|
|
#define HDSP_SPDIFSync (1<<4)
|
304 |
|
|
#define HDSP_TimecodeLock (1<<5)
|
305 |
|
|
#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
|
306 |
|
|
#define HDSP_Sync2 (1<<16)
|
307 |
|
|
#define HDSP_Sync1 (1<<17)
|
308 |
|
|
#define HDSP_Sync0 (1<<18)
|
309 |
|
|
#define HDSP_DoubleSpeedStatus (1<<19)
|
310 |
|
|
#define HDSP_ConfigError (1<<20)
|
311 |
|
|
#define HDSP_DllError (1<<21)
|
312 |
|
|
#define HDSP_spdifFrequency0 (1<<22)
|
313 |
|
|
#define HDSP_spdifFrequency1 (1<<23)
|
314 |
|
|
#define HDSP_spdifFrequency2 (1<<24)
|
315 |
|
|
#define HDSP_SPDIFErrorFlag (1<<25)
|
316 |
|
|
#define HDSP_BufferID (1<<26)
|
317 |
|
|
#define HDSP_TimecodeSync (1<<27)
|
318 |
|
|
#define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
|
319 |
|
|
#define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
|
320 |
|
|
#define HDSP_midi0IRQPending (1<<30)
|
321 |
|
|
#define HDSP_midi1IRQPending (1<<31)
|
322 |
|
|
|
323 |
|
|
#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
|
324 |
|
|
|
325 |
|
|
#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
|
326 |
|
|
#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
|
327 |
|
|
#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
|
328 |
|
|
|
329 |
|
|
#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
|
330 |
|
|
#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
|
331 |
|
|
#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
|
332 |
|
|
|
333 |
|
|
/* This is for H9632 cards */
|
334 |
|
|
#define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
|
335 |
|
|
#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
|
336 |
|
|
#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
|
337 |
|
|
|
338 |
|
|
/* Status2 Register bits */
|
339 |
|
|
|
340 |
|
|
#define HDSP_version0 (1<<0)
|
341 |
|
|
#define HDSP_version1 (1<<1)
|
342 |
|
|
#define HDSP_version2 (1<<2)
|
343 |
|
|
#define HDSP_wc_lock (1<<3)
|
344 |
|
|
#define HDSP_wc_sync (1<<4)
|
345 |
|
|
#define HDSP_inp_freq0 (1<<5)
|
346 |
|
|
#define HDSP_inp_freq1 (1<<6)
|
347 |
|
|
#define HDSP_inp_freq2 (1<<7)
|
348 |
|
|
#define HDSP_SelSyncRef0 (1<<8)
|
349 |
|
|
#define HDSP_SelSyncRef1 (1<<9)
|
350 |
|
|
#define HDSP_SelSyncRef2 (1<<10)
|
351 |
|
|
|
352 |
|
|
#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
|
353 |
|
|
|
354 |
|
|
#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
|
355 |
|
|
#define HDSP_systemFrequency32 (HDSP_inp_freq0)
|
356 |
|
|
#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
|
357 |
|
|
#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
|
358 |
|
|
#define HDSP_systemFrequency64 (HDSP_inp_freq2)
|
359 |
|
|
#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
|
360 |
|
|
#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
|
361 |
|
|
/* FIXME : more values for 9632 cards ? */
|
362 |
|
|
|
363 |
|
|
#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
|
364 |
|
|
#define HDSP_SelSyncRef_ADAT1 0
|
365 |
|
|
#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
|
366 |
|
|
#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
|
367 |
|
|
#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
|
368 |
|
|
#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
|
369 |
|
|
#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
|
370 |
|
|
|
371 |
|
|
/* Card state flags */
|
372 |
|
|
|
373 |
|
|
#define HDSP_InitializationComplete (1<<0)
|
374 |
|
|
#define HDSP_FirmwareLoaded (1<<1)
|
375 |
|
|
#define HDSP_FirmwareCached (1<<2)
|
376 |
|
|
|
377 |
|
|
/* FIFO wait times, defined in terms of 1/10ths of msecs */
|
378 |
|
|
|
379 |
|
|
#define HDSP_LONG_WAIT 5000
|
380 |
|
|
#define HDSP_SHORT_WAIT 30
|
381 |
|
|
|
382 |
|
|
#define UNITY_GAIN 32768
|
383 |
|
|
#define MINUS_INFINITY_GAIN 0
|
384 |
|
|
|
385 |
|
|
/* the size of a substream (1 mono data stream) */
|
386 |
|
|
|
387 |
|
|
#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
|
388 |
|
|
#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
|
389 |
|
|
|
390 |
|
|
/* the size of the area we need to allocate for DMA transfers. the
|
391 |
|
|
size is the same regardless of the number of channels - the
|
392 |
|
|
Multiface still uses the same memory area.
|
393 |
|
|
|
394 |
|
|
Note that we allocate 1 more channel than is apparently needed
|
395 |
|
|
because the h/w seems to write 1 byte beyond the end of the last
|
396 |
|
|
page. Sigh.
|
397 |
|
|
*/
|
398 |
|
|
|
399 |
|
|
#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
|
400 |
|
|
#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
|
401 |
|
|
|
402 |
|
|
/* use hotplug firmeare loader? */
|
403 |
|
|
#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
|
404 |
|
|
#if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP)
|
405 |
|
|
#define HDSP_FW_LOADER
|
406 |
|
|
#endif
|
407 |
|
|
#endif
|
408 |
|
|
|
409 |
|
|
struct hdsp_9632_meters {
|
410 |
|
|
u32 input_peak[16];
|
411 |
|
|
u32 playback_peak[16];
|
412 |
|
|
u32 output_peak[16];
|
413 |
|
|
u32 xxx_peak[16];
|
414 |
|
|
u32 padding[64];
|
415 |
|
|
u32 input_rms_low[16];
|
416 |
|
|
u32 playback_rms_low[16];
|
417 |
|
|
u32 output_rms_low[16];
|
418 |
|
|
u32 xxx_rms_low[16];
|
419 |
|
|
u32 input_rms_high[16];
|
420 |
|
|
u32 playback_rms_high[16];
|
421 |
|
|
u32 output_rms_high[16];
|
422 |
|
|
u32 xxx_rms_high[16];
|
423 |
|
|
};
|
424 |
|
|
|
425 |
|
|
struct hdsp_midi {
|
426 |
|
|
struct hdsp *hdsp;
|
427 |
|
|
int id;
|
428 |
|
|
struct snd_rawmidi *rmidi;
|
429 |
|
|
struct snd_rawmidi_substream *input;
|
430 |
|
|
struct snd_rawmidi_substream *output;
|
431 |
|
|
char istimer; /* timer in use */
|
432 |
|
|
struct timer_list timer;
|
433 |
|
|
spinlock_t lock;
|
434 |
|
|
int pending;
|
435 |
|
|
};
|
436 |
|
|
|
437 |
|
|
struct hdsp {
|
438 |
|
|
spinlock_t lock;
|
439 |
|
|
struct snd_pcm_substream *capture_substream;
|
440 |
|
|
struct snd_pcm_substream *playback_substream;
|
441 |
|
|
struct hdsp_midi midi[2];
|
442 |
|
|
struct tasklet_struct midi_tasklet;
|
443 |
|
|
int use_midi_tasklet;
|
444 |
|
|
int precise_ptr;
|
445 |
|
|
u32 control_register; /* cached value */
|
446 |
|
|
u32 control2_register; /* cached value */
|
447 |
|
|
u32 creg_spdif;
|
448 |
|
|
u32 creg_spdif_stream;
|
449 |
|
|
int clock_source_locked;
|
450 |
|
|
char *card_name; /* digiface/multiface */
|
451 |
|
|
enum HDSP_IO_Type io_type; /* ditto, but for code use */
|
452 |
|
|
unsigned short firmware_rev;
|
453 |
|
|
unsigned short state; /* stores state bits */
|
454 |
|
|
u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
|
455 |
|
|
size_t period_bytes; /* guess what this is */
|
456 |
|
|
unsigned char max_channels;
|
457 |
|
|
unsigned char qs_in_channels; /* quad speed mode for H9632 */
|
458 |
|
|
unsigned char ds_in_channels;
|
459 |
|
|
unsigned char ss_in_channels; /* different for multiface/digiface */
|
460 |
|
|
unsigned char qs_out_channels;
|
461 |
|
|
unsigned char ds_out_channels;
|
462 |
|
|
unsigned char ss_out_channels;
|
463 |
|
|
|
464 |
|
|
struct snd_dma_buffer capture_dma_buf;
|
465 |
|
|
struct snd_dma_buffer playback_dma_buf;
|
466 |
|
|
unsigned char *capture_buffer; /* suitably aligned address */
|
467 |
|
|
unsigned char *playback_buffer; /* suitably aligned address */
|
468 |
|
|
|
469 |
|
|
pid_t capture_pid;
|
470 |
|
|
pid_t playback_pid;
|
471 |
|
|
int running;
|
472 |
|
|
int system_sample_rate;
|
473 |
|
|
char *channel_map;
|
474 |
|
|
int dev;
|
475 |
|
|
int irq;
|
476 |
|
|
unsigned long port;
|
477 |
|
|
void __iomem *iobase;
|
478 |
|
|
struct snd_card *card;
|
479 |
|
|
struct snd_pcm *pcm;
|
480 |
|
|
struct snd_hwdep *hwdep;
|
481 |
|
|
struct pci_dev *pci;
|
482 |
|
|
struct snd_kcontrol *spdif_ctl;
|
483 |
|
|
unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
|
484 |
|
|
unsigned int dds_value; /* last value written to freq register */
|
485 |
|
|
};
|
486 |
|
|
|
487 |
|
|
/* These tables map the ALSA channels 1..N to the channels that we
|
488 |
|
|
need to use in order to find the relevant channel buffer. RME
|
489 |
|
|
refer to this kind of mapping as between "the ADAT channel and
|
490 |
|
|
the DMA channel." We index it using the logical audio channel,
|
491 |
|
|
and the value is the DMA channel (i.e. channel buffer number)
|
492 |
|
|
where the data for that channel can be read/written from/to.
|
493 |
|
|
*/
|
494 |
|
|
|
495 |
|
|
static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
|
496 |
|
|
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
|
497 |
|
|
18, 19, 20, 21, 22, 23, 24, 25
|
498 |
|
|
};
|
499 |
|
|
|
500 |
|
|
static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
|
501 |
|
|
/* Analog */
|
502 |
|
|
0, 1, 2, 3, 4, 5, 6, 7,
|
503 |
|
|
/* ADAT 2 */
|
504 |
|
|
16, 17, 18, 19, 20, 21, 22, 23,
|
505 |
|
|
/* SPDIF */
|
506 |
|
|
24, 25,
|
507 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1
|
508 |
|
|
};
|
509 |
|
|
|
510 |
|
|
static char channel_map_ds[HDSP_MAX_CHANNELS] = {
|
511 |
|
|
/* ADAT channels are remapped */
|
512 |
|
|
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
|
513 |
|
|
/* channels 12 and 13 are S/PDIF */
|
514 |
|
|
24, 25,
|
515 |
|
|
/* others don't exist */
|
516 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
|
517 |
|
|
};
|
518 |
|
|
|
519 |
|
|
static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
|
520 |
|
|
/* ADAT channels */
|
521 |
|
|
0, 1, 2, 3, 4, 5, 6, 7,
|
522 |
|
|
/* SPDIF */
|
523 |
|
|
8, 9,
|
524 |
|
|
/* Analog */
|
525 |
|
|
10, 11,
|
526 |
|
|
/* AO4S-192 and AI4S-192 extension boards */
|
527 |
|
|
12, 13, 14, 15,
|
528 |
|
|
/* others don't exist */
|
529 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1,
|
530 |
|
|
-1, -1
|
531 |
|
|
};
|
532 |
|
|
|
533 |
|
|
static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
|
534 |
|
|
/* ADAT */
|
535 |
|
|
1, 3, 5, 7,
|
536 |
|
|
/* SPDIF */
|
537 |
|
|
8, 9,
|
538 |
|
|
/* Analog */
|
539 |
|
|
10, 11,
|
540 |
|
|
/* AO4S-192 and AI4S-192 extension boards */
|
541 |
|
|
12, 13, 14, 15,
|
542 |
|
|
/* others don't exist */
|
543 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1,
|
544 |
|
|
-1, -1, -1, -1, -1, -1
|
545 |
|
|
};
|
546 |
|
|
|
547 |
|
|
static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
|
548 |
|
|
/* ADAT is disabled in this mode */
|
549 |
|
|
/* SPDIF */
|
550 |
|
|
8, 9,
|
551 |
|
|
/* Analog */
|
552 |
|
|
10, 11,
|
553 |
|
|
/* AO4S-192 and AI4S-192 extension boards */
|
554 |
|
|
12, 13, 14, 15,
|
555 |
|
|
/* others don't exist */
|
556 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1,
|
557 |
|
|
-1, -1, -1, -1, -1, -1, -1, -1,
|
558 |
|
|
-1, -1
|
559 |
|
|
};
|
560 |
|
|
|
561 |
|
|
static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
|
562 |
|
|
{
|
563 |
|
|
dmab->dev.type = SNDRV_DMA_TYPE_DEV;
|
564 |
|
|
dmab->dev.dev = snd_dma_pci_data(pci);
|
565 |
|
|
if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
|
566 |
|
|
if (dmab->bytes >= size)
|
567 |
|
|
return 0;
|
568 |
|
|
}
|
569 |
|
|
if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
|
570 |
|
|
size, dmab) < 0)
|
571 |
|
|
return -ENOMEM;
|
572 |
|
|
return 0;
|
573 |
|
|
}
|
574 |
|
|
|
575 |
|
|
static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
|
576 |
|
|
{
|
577 |
|
|
if (dmab->area) {
|
578 |
|
|
dmab->dev.dev = NULL; /* make it anonymous */
|
579 |
|
|
snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
|
580 |
|
|
}
|
581 |
|
|
}
|
582 |
|
|
|
583 |
|
|
|
584 |
|
|
static struct pci_device_id snd_hdsp_ids[] = {
|
585 |
|
|
{
|
586 |
|
|
.vendor = PCI_VENDOR_ID_XILINX,
|
587 |
|
|
.device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
|
588 |
|
|
.subvendor = PCI_ANY_ID,
|
589 |
|
|
.subdevice = PCI_ANY_ID,
|
590 |
|
|
}, /* RME Hammerfall-DSP */
|
591 |
|
|
{ 0, },
|
592 |
|
|
};
|
593 |
|
|
|
594 |
|
|
MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
|
595 |
|
|
|
596 |
|
|
/* prototypes */
|
597 |
|
|
static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
|
598 |
|
|
static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
|
599 |
|
|
static int snd_hdsp_enable_io (struct hdsp *hdsp);
|
600 |
|
|
static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
|
601 |
|
|
static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
|
602 |
|
|
static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
|
603 |
|
|
static int hdsp_autosync_ref(struct hdsp *hdsp);
|
604 |
|
|
static int snd_hdsp_set_defaults(struct hdsp *hdsp);
|
605 |
|
|
static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
|
606 |
|
|
|
607 |
|
|
static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
|
608 |
|
|
{
|
609 |
|
|
switch (hdsp->io_type) {
|
610 |
|
|
case Multiface:
|
611 |
|
|
case Digiface:
|
612 |
|
|
default:
|
613 |
|
|
return (64 * out) + (32 + (in));
|
614 |
|
|
case H9632:
|
615 |
|
|
return (32 * out) + (16 + (in));
|
616 |
|
|
case H9652:
|
617 |
|
|
return (52 * out) + (26 + (in));
|
618 |
|
|
}
|
619 |
|
|
}
|
620 |
|
|
|
621 |
|
|
static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
|
622 |
|
|
{
|
623 |
|
|
switch (hdsp->io_type) {
|
624 |
|
|
case Multiface:
|
625 |
|
|
case Digiface:
|
626 |
|
|
default:
|
627 |
|
|
return (64 * out) + in;
|
628 |
|
|
case H9632:
|
629 |
|
|
return (32 * out) + in;
|
630 |
|
|
case H9652:
|
631 |
|
|
return (52 * out) + in;
|
632 |
|
|
}
|
633 |
|
|
}
|
634 |
|
|
|
635 |
|
|
static void hdsp_write(struct hdsp *hdsp, int reg, int val)
|
636 |
|
|
{
|
637 |
|
|
writel(val, hdsp->iobase + reg);
|
638 |
|
|
}
|
639 |
|
|
|
640 |
|
|
static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
|
641 |
|
|
{
|
642 |
|
|
return readl (hdsp->iobase + reg);
|
643 |
|
|
}
|
644 |
|
|
|
645 |
|
|
static int hdsp_check_for_iobox (struct hdsp *hdsp)
|
646 |
|
|
{
|
647 |
|
|
|
648 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
|
649 |
|
|
if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
|
650 |
|
|
snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
|
651 |
|
|
hdsp->state &= ~HDSP_FirmwareLoaded;
|
652 |
|
|
return -EIO;
|
653 |
|
|
}
|
654 |
|
|
return 0;
|
655 |
|
|
|
656 |
|
|
}
|
657 |
|
|
|
658 |
|
|
static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
|
659 |
|
|
|
660 |
|
|
int i;
|
661 |
|
|
unsigned long flags;
|
662 |
|
|
|
663 |
|
|
if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
|
664 |
|
|
|
665 |
|
|
snd_printk ("Hammerfall-DSP: loading firmware\n");
|
666 |
|
|
|
667 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
|
668 |
|
|
hdsp_write (hdsp, HDSP_fifoData, 0);
|
669 |
|
|
|
670 |
|
|
if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
|
671 |
|
|
snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
|
672 |
|
|
return -EIO;
|
673 |
|
|
}
|
674 |
|
|
|
675 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
|
676 |
|
|
|
677 |
|
|
for (i = 0; i < 24413; ++i) {
|
678 |
|
|
hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
|
679 |
|
|
if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
|
680 |
|
|
snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
|
681 |
|
|
return -EIO;
|
682 |
|
|
}
|
683 |
|
|
}
|
684 |
|
|
|
685 |
|
|
ssleep(3);
|
686 |
|
|
|
687 |
|
|
if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
|
688 |
|
|
snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
|
689 |
|
|
return -EIO;
|
690 |
|
|
}
|
691 |
|
|
|
692 |
|
|
#ifdef SNDRV_BIG_ENDIAN
|
693 |
|
|
hdsp->control2_register = HDSP_BIGENDIAN_MODE;
|
694 |
|
|
#else
|
695 |
|
|
hdsp->control2_register = 0;
|
696 |
|
|
#endif
|
697 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
|
698 |
|
|
snd_printk ("Hammerfall-DSP: finished firmware loading\n");
|
699 |
|
|
|
700 |
|
|
}
|
701 |
|
|
if (hdsp->state & HDSP_InitializationComplete) {
|
702 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
|
703 |
|
|
spin_lock_irqsave(&hdsp->lock, flags);
|
704 |
|
|
snd_hdsp_set_defaults(hdsp);
|
705 |
|
|
spin_unlock_irqrestore(&hdsp->lock, flags);
|
706 |
|
|
}
|
707 |
|
|
|
708 |
|
|
hdsp->state |= HDSP_FirmwareLoaded;
|
709 |
|
|
|
710 |
|
|
return 0;
|
711 |
|
|
}
|
712 |
|
|
|
713 |
|
|
static int hdsp_get_iobox_version (struct hdsp *hdsp)
|
714 |
|
|
{
|
715 |
|
|
if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
|
716 |
|
|
|
717 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
|
718 |
|
|
hdsp_write (hdsp, HDSP_fifoData, 0);
|
719 |
|
|
if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
|
720 |
|
|
return -EIO;
|
721 |
|
|
|
722 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
|
723 |
|
|
hdsp_write (hdsp, HDSP_fifoData, 0);
|
724 |
|
|
|
725 |
|
|
if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
|
726 |
|
|
hdsp->io_type = Multiface;
|
727 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
|
728 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
|
729 |
|
|
hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
|
730 |
|
|
} else {
|
731 |
|
|
hdsp->io_type = Digiface;
|
732 |
|
|
}
|
733 |
|
|
} else {
|
734 |
|
|
/* firmware was already loaded, get iobox type */
|
735 |
|
|
if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
|
736 |
|
|
hdsp->io_type = Multiface;
|
737 |
|
|
else
|
738 |
|
|
hdsp->io_type = Digiface;
|
739 |
|
|
}
|
740 |
|
|
return 0;
|
741 |
|
|
}
|
742 |
|
|
|
743 |
|
|
|
744 |
|
|
#ifdef HDSP_FW_LOADER
|
745 |
|
|
static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp);
|
746 |
|
|
#endif
|
747 |
|
|
|
748 |
|
|
static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
|
749 |
|
|
{
|
750 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
|
751 |
|
|
return 0;
|
752 |
|
|
if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
|
753 |
|
|
hdsp->state &= ~HDSP_FirmwareLoaded;
|
754 |
|
|
if (! load_on_demand)
|
755 |
|
|
return -EIO;
|
756 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
|
757 |
|
|
/* try to load firmware */
|
758 |
|
|
if (! (hdsp->state & HDSP_FirmwareCached)) {
|
759 |
|
|
#ifdef HDSP_FW_LOADER
|
760 |
|
|
if (! hdsp_request_fw_loader(hdsp))
|
761 |
|
|
return 0;
|
762 |
|
|
#endif
|
763 |
|
|
snd_printk(KERN_ERR
|
764 |
|
|
"Hammerfall-DSP: No firmware loaded nor "
|
765 |
|
|
"cached, please upload firmware.\n");
|
766 |
|
|
return -EIO;
|
767 |
|
|
}
|
768 |
|
|
if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
|
769 |
|
|
snd_printk(KERN_ERR
|
770 |
|
|
"Hammerfall-DSP: Firmware loading from "
|
771 |
|
|
"cache failed, please upload manually.\n");
|
772 |
|
|
return -EIO;
|
773 |
|
|
}
|
774 |
|
|
}
|
775 |
|
|
return 0;
|
776 |
|
|
}
|
777 |
|
|
|
778 |
|
|
|
779 |
|
|
static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
|
780 |
|
|
{
|
781 |
|
|
int i;
|
782 |
|
|
|
783 |
|
|
/* the fifoStatus registers reports on how many words
|
784 |
|
|
are available in the command FIFO.
|
785 |
|
|
*/
|
786 |
|
|
|
787 |
|
|
for (i = 0; i < timeout; i++) {
|
788 |
|
|
|
789 |
|
|
if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
|
790 |
|
|
return 0;
|
791 |
|
|
|
792 |
|
|
/* not very friendly, but we only do this during a firmware
|
793 |
|
|
load and changing the mixer, so we just put up with it.
|
794 |
|
|
*/
|
795 |
|
|
|
796 |
|
|
udelay (100);
|
797 |
|
|
}
|
798 |
|
|
|
799 |
|
|
snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
|
800 |
|
|
count, timeout);
|
801 |
|
|
return -1;
|
802 |
|
|
}
|
803 |
|
|
|
804 |
|
|
static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
|
805 |
|
|
{
|
806 |
|
|
if (addr >= HDSP_MATRIX_MIXER_SIZE)
|
807 |
|
|
return 0;
|
808 |
|
|
|
809 |
|
|
return hdsp->mixer_matrix[addr];
|
810 |
|
|
}
|
811 |
|
|
|
812 |
|
|
static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
|
813 |
|
|
{
|
814 |
|
|
unsigned int ad;
|
815 |
|
|
|
816 |
|
|
if (addr >= HDSP_MATRIX_MIXER_SIZE)
|
817 |
|
|
return -1;
|
818 |
|
|
|
819 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
|
820 |
|
|
|
821 |
|
|
/* from martin bjornsen:
|
822 |
|
|
|
823 |
|
|
"You can only write dwords to the
|
824 |
|
|
mixer memory which contain two
|
825 |
|
|
mixer values in the low and high
|
826 |
|
|
word. So if you want to change
|
827 |
|
|
value 0 you have to read value 1
|
828 |
|
|
from the cache and write both to
|
829 |
|
|
the first dword in the mixer
|
830 |
|
|
memory."
|
831 |
|
|
*/
|
832 |
|
|
|
833 |
|
|
if (hdsp->io_type == H9632 && addr >= 512)
|
834 |
|
|
return 0;
|
835 |
|
|
|
836 |
|
|
if (hdsp->io_type == H9652 && addr >= 1352)
|
837 |
|
|
return 0;
|
838 |
|
|
|
839 |
|
|
hdsp->mixer_matrix[addr] = data;
|
840 |
|
|
|
841 |
|
|
|
842 |
|
|
/* `addr' addresses a 16-bit wide address, but
|
843 |
|
|
the address space accessed via hdsp_write
|
844 |
|
|
uses byte offsets. put another way, addr
|
845 |
|
|
varies from 0 to 1351, but to access the
|
846 |
|
|
corresponding memory location, we need
|
847 |
|
|
to access 0 to 2703 ...
|
848 |
|
|
*/
|
849 |
|
|
ad = addr/2;
|
850 |
|
|
|
851 |
|
|
hdsp_write (hdsp, 4096 + (ad*4),
|
852 |
|
|
(hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
|
853 |
|
|
hdsp->mixer_matrix[addr&0x7fe]);
|
854 |
|
|
|
855 |
|
|
return 0;
|
856 |
|
|
|
857 |
|
|
} else {
|
858 |
|
|
|
859 |
|
|
ad = (addr << 16) + data;
|
860 |
|
|
|
861 |
|
|
if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
|
862 |
|
|
return -1;
|
863 |
|
|
|
864 |
|
|
hdsp_write (hdsp, HDSP_fifoData, ad);
|
865 |
|
|
hdsp->mixer_matrix[addr] = data;
|
866 |
|
|
|
867 |
|
|
}
|
868 |
|
|
|
869 |
|
|
return 0;
|
870 |
|
|
}
|
871 |
|
|
|
872 |
|
|
static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
|
873 |
|
|
{
|
874 |
|
|
unsigned long flags;
|
875 |
|
|
int ret = 1;
|
876 |
|
|
|
877 |
|
|
spin_lock_irqsave(&hdsp->lock, flags);
|
878 |
|
|
if ((hdsp->playback_pid != hdsp->capture_pid) &&
|
879 |
|
|
(hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
|
880 |
|
|
ret = 0;
|
881 |
|
|
spin_unlock_irqrestore(&hdsp->lock, flags);
|
882 |
|
|
return ret;
|
883 |
|
|
}
|
884 |
|
|
|
885 |
|
|
static int hdsp_external_sample_rate (struct hdsp *hdsp)
|
886 |
|
|
{
|
887 |
|
|
unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
|
888 |
|
|
unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
|
889 |
|
|
|
890 |
|
|
switch (rate_bits) {
|
891 |
|
|
case HDSP_systemFrequency32: return 32000;
|
892 |
|
|
case HDSP_systemFrequency44_1: return 44100;
|
893 |
|
|
case HDSP_systemFrequency48: return 48000;
|
894 |
|
|
case HDSP_systemFrequency64: return 64000;
|
895 |
|
|
case HDSP_systemFrequency88_2: return 88200;
|
896 |
|
|
case HDSP_systemFrequency96: return 96000;
|
897 |
|
|
default:
|
898 |
|
|
return 0;
|
899 |
|
|
}
|
900 |
|
|
}
|
901 |
|
|
|
902 |
|
|
static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
|
903 |
|
|
{
|
904 |
|
|
unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
|
905 |
|
|
unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
|
906 |
|
|
|
907 |
|
|
if (status & HDSP_SPDIFErrorFlag)
|
908 |
|
|
return 0;
|
909 |
|
|
|
910 |
|
|
switch (rate_bits) {
|
911 |
|
|
case HDSP_spdifFrequency32KHz: return 32000;
|
912 |
|
|
case HDSP_spdifFrequency44_1KHz: return 44100;
|
913 |
|
|
case HDSP_spdifFrequency48KHz: return 48000;
|
914 |
|
|
case HDSP_spdifFrequency64KHz: return 64000;
|
915 |
|
|
case HDSP_spdifFrequency88_2KHz: return 88200;
|
916 |
|
|
case HDSP_spdifFrequency96KHz: return 96000;
|
917 |
|
|
case HDSP_spdifFrequency128KHz:
|
918 |
|
|
if (hdsp->io_type == H9632) return 128000;
|
919 |
|
|
break;
|
920 |
|
|
case HDSP_spdifFrequency176_4KHz:
|
921 |
|
|
if (hdsp->io_type == H9632) return 176400;
|
922 |
|
|
break;
|
923 |
|
|
case HDSP_spdifFrequency192KHz:
|
924 |
|
|
if (hdsp->io_type == H9632) return 192000;
|
925 |
|
|
break;
|
926 |
|
|
default:
|
927 |
|
|
break;
|
928 |
|
|
}
|
929 |
|
|
snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
|
930 |
|
|
return 0;
|
931 |
|
|
}
|
932 |
|
|
|
933 |
|
|
static void hdsp_compute_period_size(struct hdsp *hdsp)
|
934 |
|
|
{
|
935 |
|
|
hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
|
936 |
|
|
}
|
937 |
|
|
|
938 |
|
|
static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
|
939 |
|
|
{
|
940 |
|
|
int position;
|
941 |
|
|
|
942 |
|
|
position = hdsp_read(hdsp, HDSP_statusRegister);
|
943 |
|
|
|
944 |
|
|
if (!hdsp->precise_ptr)
|
945 |
|
|
return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
|
946 |
|
|
|
947 |
|
|
position &= HDSP_BufferPositionMask;
|
948 |
|
|
position /= 4;
|
949 |
|
|
position &= (hdsp->period_bytes/2) - 1;
|
950 |
|
|
return position;
|
951 |
|
|
}
|
952 |
|
|
|
953 |
|
|
static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
|
954 |
|
|
{
|
955 |
|
|
hdsp_write (hdsp, HDSP_resetPointer, 0);
|
956 |
|
|
if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
|
957 |
|
|
/* HDSP_resetPointer = HDSP_freqReg, which is strange and
|
958 |
|
|
* requires (?) to write again DDS value after a reset pointer
|
959 |
|
|
* (at least, it works like this) */
|
960 |
|
|
hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
|
961 |
|
|
}
|
962 |
|
|
|
963 |
|
|
static void hdsp_start_audio(struct hdsp *s)
|
964 |
|
|
{
|
965 |
|
|
s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
|
966 |
|
|
hdsp_write(s, HDSP_controlRegister, s->control_register);
|
967 |
|
|
}
|
968 |
|
|
|
969 |
|
|
static void hdsp_stop_audio(struct hdsp *s)
|
970 |
|
|
{
|
971 |
|
|
s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
|
972 |
|
|
hdsp_write(s, HDSP_controlRegister, s->control_register);
|
973 |
|
|
}
|
974 |
|
|
|
975 |
|
|
static void hdsp_silence_playback(struct hdsp *hdsp)
|
976 |
|
|
{
|
977 |
|
|
memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
|
978 |
|
|
}
|
979 |
|
|
|
980 |
|
|
static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
|
981 |
|
|
{
|
982 |
|
|
int n;
|
983 |
|
|
|
984 |
|
|
spin_lock_irq(&s->lock);
|
985 |
|
|
|
986 |
|
|
frames >>= 7;
|
987 |
|
|
n = 0;
|
988 |
|
|
while (frames) {
|
989 |
|
|
n++;
|
990 |
|
|
frames >>= 1;
|
991 |
|
|
}
|
992 |
|
|
|
993 |
|
|
s->control_register &= ~HDSP_LatencyMask;
|
994 |
|
|
s->control_register |= hdsp_encode_latency(n);
|
995 |
|
|
|
996 |
|
|
hdsp_write(s, HDSP_controlRegister, s->control_register);
|
997 |
|
|
|
998 |
|
|
hdsp_compute_period_size(s);
|
999 |
|
|
|
1000 |
|
|
spin_unlock_irq(&s->lock);
|
1001 |
|
|
|
1002 |
|
|
return 0;
|
1003 |
|
|
}
|
1004 |
|
|
|
1005 |
|
|
static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
|
1006 |
|
|
{
|
1007 |
|
|
u64 n;
|
1008 |
|
|
u32 r;
|
1009 |
|
|
|
1010 |
|
|
if (rate >= 112000)
|
1011 |
|
|
rate /= 4;
|
1012 |
|
|
else if (rate >= 56000)
|
1013 |
|
|
rate /= 2;
|
1014 |
|
|
|
1015 |
|
|
n = DDS_NUMERATOR;
|
1016 |
|
|
div64_32(&n, rate, &r);
|
1017 |
|
|
/* n should be less than 2^32 for being written to FREQ register */
|
1018 |
|
|
snd_assert((n >> 32) == 0);
|
1019 |
|
|
/* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
|
1020 |
|
|
value to write it after a reset */
|
1021 |
|
|
hdsp->dds_value = n;
|
1022 |
|
|
hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
|
1023 |
|
|
}
|
1024 |
|
|
|
1025 |
|
|
static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
|
1026 |
|
|
{
|
1027 |
|
|
int reject_if_open = 0;
|
1028 |
|
|
int current_rate;
|
1029 |
|
|
int rate_bits;
|
1030 |
|
|
|
1031 |
|
|
/* ASSUMPTION: hdsp->lock is either held, or
|
1032 |
|
|
there is no need for it (e.g. during module
|
1033 |
|
|
initialization).
|
1034 |
|
|
*/
|
1035 |
|
|
|
1036 |
|
|
if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
|
1037 |
|
|
if (called_internally) {
|
1038 |
|
|
/* request from ctl or card initialization */
|
1039 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
|
1040 |
|
|
return -1;
|
1041 |
|
|
} else {
|
1042 |
|
|
/* hw_param request while in AutoSync mode */
|
1043 |
|
|
int external_freq = hdsp_external_sample_rate(hdsp);
|
1044 |
|
|
int spdif_freq = hdsp_spdif_sample_rate(hdsp);
|
1045 |
|
|
|
1046 |
|
|
if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
|
1047 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
|
1048 |
|
|
else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
|
1049 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
|
1050 |
|
|
else if (rate != external_freq) {
|
1051 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
|
1052 |
|
|
return -1;
|
1053 |
|
|
}
|
1054 |
|
|
}
|
1055 |
|
|
}
|
1056 |
|
|
|
1057 |
|
|
current_rate = hdsp->system_sample_rate;
|
1058 |
|
|
|
1059 |
|
|
/* Changing from a "single speed" to a "double speed" rate is
|
1060 |
|
|
not allowed if any substreams are open. This is because
|
1061 |
|
|
such a change causes a shift in the location of
|
1062 |
|
|
the DMA buffers and a reduction in the number of available
|
1063 |
|
|
buffers.
|
1064 |
|
|
|
1065 |
|
|
Note that a similar but essentially insoluble problem
|
1066 |
|
|
exists for externally-driven rate changes. All we can do
|
1067 |
|
|
is to flag rate changes in the read/write routines. */
|
1068 |
|
|
|
1069 |
|
|
if (rate > 96000 && hdsp->io_type != H9632)
|
1070 |
|
|
return -EINVAL;
|
1071 |
|
|
|
1072 |
|
|
switch (rate) {
|
1073 |
|
|
case 32000:
|
1074 |
|
|
if (current_rate > 48000)
|
1075 |
|
|
reject_if_open = 1;
|
1076 |
|
|
rate_bits = HDSP_Frequency32KHz;
|
1077 |
|
|
break;
|
1078 |
|
|
case 44100:
|
1079 |
|
|
if (current_rate > 48000)
|
1080 |
|
|
reject_if_open = 1;
|
1081 |
|
|
rate_bits = HDSP_Frequency44_1KHz;
|
1082 |
|
|
break;
|
1083 |
|
|
case 48000:
|
1084 |
|
|
if (current_rate > 48000)
|
1085 |
|
|
reject_if_open = 1;
|
1086 |
|
|
rate_bits = HDSP_Frequency48KHz;
|
1087 |
|
|
break;
|
1088 |
|
|
case 64000:
|
1089 |
|
|
if (current_rate <= 48000 || current_rate > 96000)
|
1090 |
|
|
reject_if_open = 1;
|
1091 |
|
|
rate_bits = HDSP_Frequency64KHz;
|
1092 |
|
|
break;
|
1093 |
|
|
case 88200:
|
1094 |
|
|
if (current_rate <= 48000 || current_rate > 96000)
|
1095 |
|
|
reject_if_open = 1;
|
1096 |
|
|
rate_bits = HDSP_Frequency88_2KHz;
|
1097 |
|
|
break;
|
1098 |
|
|
case 96000:
|
1099 |
|
|
if (current_rate <= 48000 || current_rate > 96000)
|
1100 |
|
|
reject_if_open = 1;
|
1101 |
|
|
rate_bits = HDSP_Frequency96KHz;
|
1102 |
|
|
break;
|
1103 |
|
|
case 128000:
|
1104 |
|
|
if (current_rate < 128000)
|
1105 |
|
|
reject_if_open = 1;
|
1106 |
|
|
rate_bits = HDSP_Frequency128KHz;
|
1107 |
|
|
break;
|
1108 |
|
|
case 176400:
|
1109 |
|
|
if (current_rate < 128000)
|
1110 |
|
|
reject_if_open = 1;
|
1111 |
|
|
rate_bits = HDSP_Frequency176_4KHz;
|
1112 |
|
|
break;
|
1113 |
|
|
case 192000:
|
1114 |
|
|
if (current_rate < 128000)
|
1115 |
|
|
reject_if_open = 1;
|
1116 |
|
|
rate_bits = HDSP_Frequency192KHz;
|
1117 |
|
|
break;
|
1118 |
|
|
default:
|
1119 |
|
|
return -EINVAL;
|
1120 |
|
|
}
|
1121 |
|
|
|
1122 |
|
|
if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
|
1123 |
|
|
snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
|
1124 |
|
|
hdsp->capture_pid,
|
1125 |
|
|
hdsp->playback_pid);
|
1126 |
|
|
return -EBUSY;
|
1127 |
|
|
}
|
1128 |
|
|
|
1129 |
|
|
hdsp->control_register &= ~HDSP_FrequencyMask;
|
1130 |
|
|
hdsp->control_register |= rate_bits;
|
1131 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1132 |
|
|
|
1133 |
|
|
/* For HDSP9632 rev 152, need to set DDS value in FREQ register */
|
1134 |
|
|
if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
|
1135 |
|
|
hdsp_set_dds_value(hdsp, rate);
|
1136 |
|
|
|
1137 |
|
|
if (rate >= 128000) {
|
1138 |
|
|
hdsp->channel_map = channel_map_H9632_qs;
|
1139 |
|
|
} else if (rate > 48000) {
|
1140 |
|
|
if (hdsp->io_type == H9632)
|
1141 |
|
|
hdsp->channel_map = channel_map_H9632_ds;
|
1142 |
|
|
else
|
1143 |
|
|
hdsp->channel_map = channel_map_ds;
|
1144 |
|
|
} else {
|
1145 |
|
|
switch (hdsp->io_type) {
|
1146 |
|
|
case Multiface:
|
1147 |
|
|
hdsp->channel_map = channel_map_mf_ss;
|
1148 |
|
|
break;
|
1149 |
|
|
case Digiface:
|
1150 |
|
|
case H9652:
|
1151 |
|
|
hdsp->channel_map = channel_map_df_ss;
|
1152 |
|
|
break;
|
1153 |
|
|
case H9632:
|
1154 |
|
|
hdsp->channel_map = channel_map_H9632_ss;
|
1155 |
|
|
break;
|
1156 |
|
|
default:
|
1157 |
|
|
/* should never happen */
|
1158 |
|
|
break;
|
1159 |
|
|
}
|
1160 |
|
|
}
|
1161 |
|
|
|
1162 |
|
|
hdsp->system_sample_rate = rate;
|
1163 |
|
|
|
1164 |
|
|
return 0;
|
1165 |
|
|
}
|
1166 |
|
|
|
1167 |
|
|
/*----------------------------------------------------------------------------
|
1168 |
|
|
MIDI
|
1169 |
|
|
----------------------------------------------------------------------------*/
|
1170 |
|
|
|
1171 |
|
|
static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
|
1172 |
|
|
{
|
1173 |
|
|
/* the hardware already does the relevant bit-mask with 0xff */
|
1174 |
|
|
if (id)
|
1175 |
|
|
return hdsp_read(hdsp, HDSP_midiDataIn1);
|
1176 |
|
|
else
|
1177 |
|
|
return hdsp_read(hdsp, HDSP_midiDataIn0);
|
1178 |
|
|
}
|
1179 |
|
|
|
1180 |
|
|
static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
|
1181 |
|
|
{
|
1182 |
|
|
/* the hardware already does the relevant bit-mask with 0xff */
|
1183 |
|
|
if (id)
|
1184 |
|
|
hdsp_write(hdsp, HDSP_midiDataOut1, val);
|
1185 |
|
|
else
|
1186 |
|
|
hdsp_write(hdsp, HDSP_midiDataOut0, val);
|
1187 |
|
|
}
|
1188 |
|
|
|
1189 |
|
|
static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
|
1190 |
|
|
{
|
1191 |
|
|
if (id)
|
1192 |
|
|
return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
|
1193 |
|
|
else
|
1194 |
|
|
return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
|
1195 |
|
|
}
|
1196 |
|
|
|
1197 |
|
|
static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
|
1198 |
|
|
{
|
1199 |
|
|
int fifo_bytes_used;
|
1200 |
|
|
|
1201 |
|
|
if (id)
|
1202 |
|
|
fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
|
1203 |
|
|
else
|
1204 |
|
|
fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
|
1205 |
|
|
|
1206 |
|
|
if (fifo_bytes_used < 128)
|
1207 |
|
|
return 128 - fifo_bytes_used;
|
1208 |
|
|
else
|
1209 |
|
|
return 0;
|
1210 |
|
|
}
|
1211 |
|
|
|
1212 |
|
|
static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
|
1213 |
|
|
{
|
1214 |
|
|
while (snd_hdsp_midi_input_available (hdsp, id))
|
1215 |
|
|
snd_hdsp_midi_read_byte (hdsp, id);
|
1216 |
|
|
}
|
1217 |
|
|
|
1218 |
|
|
static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
|
1219 |
|
|
{
|
1220 |
|
|
unsigned long flags;
|
1221 |
|
|
int n_pending;
|
1222 |
|
|
int to_write;
|
1223 |
|
|
int i;
|
1224 |
|
|
unsigned char buf[128];
|
1225 |
|
|
|
1226 |
|
|
/* Output is not interrupt driven */
|
1227 |
|
|
|
1228 |
|
|
spin_lock_irqsave (&hmidi->lock, flags);
|
1229 |
|
|
if (hmidi->output) {
|
1230 |
|
|
if (!snd_rawmidi_transmit_empty (hmidi->output)) {
|
1231 |
|
|
if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
|
1232 |
|
|
if (n_pending > (int)sizeof (buf))
|
1233 |
|
|
n_pending = sizeof (buf);
|
1234 |
|
|
|
1235 |
|
|
if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
|
1236 |
|
|
for (i = 0; i < to_write; ++i)
|
1237 |
|
|
snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
|
1238 |
|
|
}
|
1239 |
|
|
}
|
1240 |
|
|
}
|
1241 |
|
|
}
|
1242 |
|
|
spin_unlock_irqrestore (&hmidi->lock, flags);
|
1243 |
|
|
return 0;
|
1244 |
|
|
}
|
1245 |
|
|
|
1246 |
|
|
static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
|
1247 |
|
|
{
|
1248 |
|
|
unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
|
1249 |
|
|
unsigned long flags;
|
1250 |
|
|
int n_pending;
|
1251 |
|
|
int i;
|
1252 |
|
|
|
1253 |
|
|
spin_lock_irqsave (&hmidi->lock, flags);
|
1254 |
|
|
if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
|
1255 |
|
|
if (hmidi->input) {
|
1256 |
|
|
if (n_pending > (int)sizeof (buf))
|
1257 |
|
|
n_pending = sizeof (buf);
|
1258 |
|
|
for (i = 0; i < n_pending; ++i)
|
1259 |
|
|
buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
|
1260 |
|
|
if (n_pending)
|
1261 |
|
|
snd_rawmidi_receive (hmidi->input, buf, n_pending);
|
1262 |
|
|
} else {
|
1263 |
|
|
/* flush the MIDI input FIFO */
|
1264 |
|
|
while (--n_pending)
|
1265 |
|
|
snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
|
1266 |
|
|
}
|
1267 |
|
|
}
|
1268 |
|
|
hmidi->pending = 0;
|
1269 |
|
|
if (hmidi->id)
|
1270 |
|
|
hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
|
1271 |
|
|
else
|
1272 |
|
|
hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
|
1273 |
|
|
hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
|
1274 |
|
|
spin_unlock_irqrestore (&hmidi->lock, flags);
|
1275 |
|
|
return snd_hdsp_midi_output_write (hmidi);
|
1276 |
|
|
}
|
1277 |
|
|
|
1278 |
|
|
static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
|
1279 |
|
|
{
|
1280 |
|
|
struct hdsp *hdsp;
|
1281 |
|
|
struct hdsp_midi *hmidi;
|
1282 |
|
|
unsigned long flags;
|
1283 |
|
|
u32 ie;
|
1284 |
|
|
|
1285 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1286 |
|
|
hdsp = hmidi->hdsp;
|
1287 |
|
|
ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
|
1288 |
|
|
spin_lock_irqsave (&hdsp->lock, flags);
|
1289 |
|
|
if (up) {
|
1290 |
|
|
if (!(hdsp->control_register & ie)) {
|
1291 |
|
|
snd_hdsp_flush_midi_input (hdsp, hmidi->id);
|
1292 |
|
|
hdsp->control_register |= ie;
|
1293 |
|
|
}
|
1294 |
|
|
} else {
|
1295 |
|
|
hdsp->control_register &= ~ie;
|
1296 |
|
|
tasklet_kill(&hdsp->midi_tasklet);
|
1297 |
|
|
}
|
1298 |
|
|
|
1299 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1300 |
|
|
spin_unlock_irqrestore (&hdsp->lock, flags);
|
1301 |
|
|
}
|
1302 |
|
|
|
1303 |
|
|
static void snd_hdsp_midi_output_timer(unsigned long data)
|
1304 |
|
|
{
|
1305 |
|
|
struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
|
1306 |
|
|
unsigned long flags;
|
1307 |
|
|
|
1308 |
|
|
snd_hdsp_midi_output_write(hmidi);
|
1309 |
|
|
spin_lock_irqsave (&hmidi->lock, flags);
|
1310 |
|
|
|
1311 |
|
|
/* this does not bump hmidi->istimer, because the
|
1312 |
|
|
kernel automatically removed the timer when it
|
1313 |
|
|
expired, and we are now adding it back, thus
|
1314 |
|
|
leaving istimer wherever it was set before.
|
1315 |
|
|
*/
|
1316 |
|
|
|
1317 |
|
|
if (hmidi->istimer) {
|
1318 |
|
|
hmidi->timer.expires = 1 + jiffies;
|
1319 |
|
|
add_timer(&hmidi->timer);
|
1320 |
|
|
}
|
1321 |
|
|
|
1322 |
|
|
spin_unlock_irqrestore (&hmidi->lock, flags);
|
1323 |
|
|
}
|
1324 |
|
|
|
1325 |
|
|
static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
|
1326 |
|
|
{
|
1327 |
|
|
struct hdsp_midi *hmidi;
|
1328 |
|
|
unsigned long flags;
|
1329 |
|
|
|
1330 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1331 |
|
|
spin_lock_irqsave (&hmidi->lock, flags);
|
1332 |
|
|
if (up) {
|
1333 |
|
|
if (!hmidi->istimer) {
|
1334 |
|
|
init_timer(&hmidi->timer);
|
1335 |
|
|
hmidi->timer.function = snd_hdsp_midi_output_timer;
|
1336 |
|
|
hmidi->timer.data = (unsigned long) hmidi;
|
1337 |
|
|
hmidi->timer.expires = 1 + jiffies;
|
1338 |
|
|
add_timer(&hmidi->timer);
|
1339 |
|
|
hmidi->istimer++;
|
1340 |
|
|
}
|
1341 |
|
|
} else {
|
1342 |
|
|
if (hmidi->istimer && --hmidi->istimer <= 0)
|
1343 |
|
|
del_timer (&hmidi->timer);
|
1344 |
|
|
}
|
1345 |
|
|
spin_unlock_irqrestore (&hmidi->lock, flags);
|
1346 |
|
|
if (up)
|
1347 |
|
|
snd_hdsp_midi_output_write(hmidi);
|
1348 |
|
|
}
|
1349 |
|
|
|
1350 |
|
|
static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
|
1351 |
|
|
{
|
1352 |
|
|
struct hdsp_midi *hmidi;
|
1353 |
|
|
|
1354 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1355 |
|
|
spin_lock_irq (&hmidi->lock);
|
1356 |
|
|
snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
|
1357 |
|
|
hmidi->input = substream;
|
1358 |
|
|
spin_unlock_irq (&hmidi->lock);
|
1359 |
|
|
|
1360 |
|
|
return 0;
|
1361 |
|
|
}
|
1362 |
|
|
|
1363 |
|
|
static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
|
1364 |
|
|
{
|
1365 |
|
|
struct hdsp_midi *hmidi;
|
1366 |
|
|
|
1367 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1368 |
|
|
spin_lock_irq (&hmidi->lock);
|
1369 |
|
|
hmidi->output = substream;
|
1370 |
|
|
spin_unlock_irq (&hmidi->lock);
|
1371 |
|
|
|
1372 |
|
|
return 0;
|
1373 |
|
|
}
|
1374 |
|
|
|
1375 |
|
|
static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
|
1376 |
|
|
{
|
1377 |
|
|
struct hdsp_midi *hmidi;
|
1378 |
|
|
|
1379 |
|
|
snd_hdsp_midi_input_trigger (substream, 0);
|
1380 |
|
|
|
1381 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1382 |
|
|
spin_lock_irq (&hmidi->lock);
|
1383 |
|
|
hmidi->input = NULL;
|
1384 |
|
|
spin_unlock_irq (&hmidi->lock);
|
1385 |
|
|
|
1386 |
|
|
return 0;
|
1387 |
|
|
}
|
1388 |
|
|
|
1389 |
|
|
static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
|
1390 |
|
|
{
|
1391 |
|
|
struct hdsp_midi *hmidi;
|
1392 |
|
|
|
1393 |
|
|
snd_hdsp_midi_output_trigger (substream, 0);
|
1394 |
|
|
|
1395 |
|
|
hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
|
1396 |
|
|
spin_lock_irq (&hmidi->lock);
|
1397 |
|
|
hmidi->output = NULL;
|
1398 |
|
|
spin_unlock_irq (&hmidi->lock);
|
1399 |
|
|
|
1400 |
|
|
return 0;
|
1401 |
|
|
}
|
1402 |
|
|
|
1403 |
|
|
static struct snd_rawmidi_ops snd_hdsp_midi_output =
|
1404 |
|
|
{
|
1405 |
|
|
.open = snd_hdsp_midi_output_open,
|
1406 |
|
|
.close = snd_hdsp_midi_output_close,
|
1407 |
|
|
.trigger = snd_hdsp_midi_output_trigger,
|
1408 |
|
|
};
|
1409 |
|
|
|
1410 |
|
|
static struct snd_rawmidi_ops snd_hdsp_midi_input =
|
1411 |
|
|
{
|
1412 |
|
|
.open = snd_hdsp_midi_input_open,
|
1413 |
|
|
.close = snd_hdsp_midi_input_close,
|
1414 |
|
|
.trigger = snd_hdsp_midi_input_trigger,
|
1415 |
|
|
};
|
1416 |
|
|
|
1417 |
|
|
static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
|
1418 |
|
|
{
|
1419 |
|
|
char buf[32];
|
1420 |
|
|
|
1421 |
|
|
hdsp->midi[id].id = id;
|
1422 |
|
|
hdsp->midi[id].rmidi = NULL;
|
1423 |
|
|
hdsp->midi[id].input = NULL;
|
1424 |
|
|
hdsp->midi[id].output = NULL;
|
1425 |
|
|
hdsp->midi[id].hdsp = hdsp;
|
1426 |
|
|
hdsp->midi[id].istimer = 0;
|
1427 |
|
|
hdsp->midi[id].pending = 0;
|
1428 |
|
|
spin_lock_init (&hdsp->midi[id].lock);
|
1429 |
|
|
|
1430 |
|
|
sprintf (buf, "%s MIDI %d", card->shortname, id+1);
|
1431 |
|
|
if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
|
1432 |
|
|
return -1;
|
1433 |
|
|
|
1434 |
|
|
sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
|
1435 |
|
|
hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
|
1436 |
|
|
|
1437 |
|
|
snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
|
1438 |
|
|
snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
|
1439 |
|
|
|
1440 |
|
|
hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
|
1441 |
|
|
SNDRV_RAWMIDI_INFO_INPUT |
|
1442 |
|
|
SNDRV_RAWMIDI_INFO_DUPLEX;
|
1443 |
|
|
|
1444 |
|
|
return 0;
|
1445 |
|
|
}
|
1446 |
|
|
|
1447 |
|
|
/*-----------------------------------------------------------------------------
|
1448 |
|
|
Control Interface
|
1449 |
|
|
----------------------------------------------------------------------------*/
|
1450 |
|
|
|
1451 |
|
|
static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
|
1452 |
|
|
{
|
1453 |
|
|
u32 val = 0;
|
1454 |
|
|
val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
|
1455 |
|
|
val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
|
1456 |
|
|
if (val & HDSP_SPDIFProfessional)
|
1457 |
|
|
val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
|
1458 |
|
|
else
|
1459 |
|
|
val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
|
1460 |
|
|
return val;
|
1461 |
|
|
}
|
1462 |
|
|
|
1463 |
|
|
static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
|
1464 |
|
|
{
|
1465 |
|
|
aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
|
1466 |
|
|
((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
|
1467 |
|
|
if (val & HDSP_SPDIFProfessional)
|
1468 |
|
|
aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
|
1469 |
|
|
else
|
1470 |
|
|
aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
|
1471 |
|
|
}
|
1472 |
|
|
|
1473 |
|
|
static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1474 |
|
|
{
|
1475 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
1476 |
|
|
uinfo->count = 1;
|
1477 |
|
|
return 0;
|
1478 |
|
|
}
|
1479 |
|
|
|
1480 |
|
|
static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1481 |
|
|
{
|
1482 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1483 |
|
|
|
1484 |
|
|
snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
|
1485 |
|
|
return 0;
|
1486 |
|
|
}
|
1487 |
|
|
|
1488 |
|
|
static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1489 |
|
|
{
|
1490 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1491 |
|
|
int change;
|
1492 |
|
|
u32 val;
|
1493 |
|
|
|
1494 |
|
|
val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
|
1495 |
|
|
spin_lock_irq(&hdsp->lock);
|
1496 |
|
|
change = val != hdsp->creg_spdif;
|
1497 |
|
|
hdsp->creg_spdif = val;
|
1498 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1499 |
|
|
return change;
|
1500 |
|
|
}
|
1501 |
|
|
|
1502 |
|
|
static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1503 |
|
|
{
|
1504 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
1505 |
|
|
uinfo->count = 1;
|
1506 |
|
|
return 0;
|
1507 |
|
|
}
|
1508 |
|
|
|
1509 |
|
|
static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1510 |
|
|
{
|
1511 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1512 |
|
|
|
1513 |
|
|
snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
|
1514 |
|
|
return 0;
|
1515 |
|
|
}
|
1516 |
|
|
|
1517 |
|
|
static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1518 |
|
|
{
|
1519 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1520 |
|
|
int change;
|
1521 |
|
|
u32 val;
|
1522 |
|
|
|
1523 |
|
|
val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
|
1524 |
|
|
spin_lock_irq(&hdsp->lock);
|
1525 |
|
|
change = val != hdsp->creg_spdif_stream;
|
1526 |
|
|
hdsp->creg_spdif_stream = val;
|
1527 |
|
|
hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
|
1528 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
|
1529 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1530 |
|
|
return change;
|
1531 |
|
|
}
|
1532 |
|
|
|
1533 |
|
|
static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1534 |
|
|
{
|
1535 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
|
1536 |
|
|
uinfo->count = 1;
|
1537 |
|
|
return 0;
|
1538 |
|
|
}
|
1539 |
|
|
|
1540 |
|
|
static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1541 |
|
|
{
|
1542 |
|
|
ucontrol->value.iec958.status[0] = kcontrol->private_value;
|
1543 |
|
|
return 0;
|
1544 |
|
|
}
|
1545 |
|
|
|
1546 |
|
|
#define HDSP_SPDIF_IN(xname, xindex) \
|
1547 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1548 |
|
|
.name = xname, \
|
1549 |
|
|
.index = xindex, \
|
1550 |
|
|
.info = snd_hdsp_info_spdif_in, \
|
1551 |
|
|
.get = snd_hdsp_get_spdif_in, \
|
1552 |
|
|
.put = snd_hdsp_put_spdif_in }
|
1553 |
|
|
|
1554 |
|
|
static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
|
1555 |
|
|
{
|
1556 |
|
|
return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
|
1557 |
|
|
}
|
1558 |
|
|
|
1559 |
|
|
static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
|
1560 |
|
|
{
|
1561 |
|
|
hdsp->control_register &= ~HDSP_SPDIFInputMask;
|
1562 |
|
|
hdsp->control_register |= hdsp_encode_spdif_in(in);
|
1563 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1564 |
|
|
return 0;
|
1565 |
|
|
}
|
1566 |
|
|
|
1567 |
|
|
static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1568 |
|
|
{
|
1569 |
|
|
static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
|
1570 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1571 |
|
|
|
1572 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1573 |
|
|
uinfo->count = 1;
|
1574 |
|
|
uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
|
1575 |
|
|
if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
|
1576 |
|
|
uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
|
1577 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1578 |
|
|
return 0;
|
1579 |
|
|
}
|
1580 |
|
|
|
1581 |
|
|
static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1582 |
|
|
{
|
1583 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1584 |
|
|
|
1585 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
|
1586 |
|
|
return 0;
|
1587 |
|
|
}
|
1588 |
|
|
|
1589 |
|
|
static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1590 |
|
|
{
|
1591 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1592 |
|
|
int change;
|
1593 |
|
|
unsigned int val;
|
1594 |
|
|
|
1595 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
1596 |
|
|
return -EBUSY;
|
1597 |
|
|
val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
|
1598 |
|
|
spin_lock_irq(&hdsp->lock);
|
1599 |
|
|
change = val != hdsp_spdif_in(hdsp);
|
1600 |
|
|
if (change)
|
1601 |
|
|
hdsp_set_spdif_input(hdsp, val);
|
1602 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1603 |
|
|
return change;
|
1604 |
|
|
}
|
1605 |
|
|
|
1606 |
|
|
#define HDSP_SPDIF_OUT(xname, xindex) \
|
1607 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
|
1608 |
|
|
.info = snd_hdsp_info_spdif_bits, \
|
1609 |
|
|
.get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
|
1610 |
|
|
|
1611 |
|
|
static int hdsp_spdif_out(struct hdsp *hdsp)
|
1612 |
|
|
{
|
1613 |
|
|
return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
|
1614 |
|
|
}
|
1615 |
|
|
|
1616 |
|
|
static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
|
1617 |
|
|
{
|
1618 |
|
|
if (out)
|
1619 |
|
|
hdsp->control_register |= HDSP_SPDIFOpticalOut;
|
1620 |
|
|
else
|
1621 |
|
|
hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
|
1622 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1623 |
|
|
return 0;
|
1624 |
|
|
}
|
1625 |
|
|
|
1626 |
|
|
#define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
|
1627 |
|
|
|
1628 |
|
|
static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1629 |
|
|
{
|
1630 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1631 |
|
|
|
1632 |
|
|
ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
|
1633 |
|
|
return 0;
|
1634 |
|
|
}
|
1635 |
|
|
|
1636 |
|
|
static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1637 |
|
|
{
|
1638 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1639 |
|
|
int change;
|
1640 |
|
|
unsigned int val;
|
1641 |
|
|
|
1642 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
1643 |
|
|
return -EBUSY;
|
1644 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
1645 |
|
|
spin_lock_irq(&hdsp->lock);
|
1646 |
|
|
change = (int)val != hdsp_spdif_out(hdsp);
|
1647 |
|
|
hdsp_set_spdif_output(hdsp, val);
|
1648 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1649 |
|
|
return change;
|
1650 |
|
|
}
|
1651 |
|
|
|
1652 |
|
|
#define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
|
1653 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
|
1654 |
|
|
.info = snd_hdsp_info_spdif_bits, \
|
1655 |
|
|
.get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
|
1656 |
|
|
|
1657 |
|
|
static int hdsp_spdif_professional(struct hdsp *hdsp)
|
1658 |
|
|
{
|
1659 |
|
|
return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
|
1660 |
|
|
}
|
1661 |
|
|
|
1662 |
|
|
static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
|
1663 |
|
|
{
|
1664 |
|
|
if (val)
|
1665 |
|
|
hdsp->control_register |= HDSP_SPDIFProfessional;
|
1666 |
|
|
else
|
1667 |
|
|
hdsp->control_register &= ~HDSP_SPDIFProfessional;
|
1668 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1669 |
|
|
return 0;
|
1670 |
|
|
}
|
1671 |
|
|
|
1672 |
|
|
static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1673 |
|
|
{
|
1674 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1675 |
|
|
|
1676 |
|
|
ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
|
1677 |
|
|
return 0;
|
1678 |
|
|
}
|
1679 |
|
|
|
1680 |
|
|
static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1681 |
|
|
{
|
1682 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1683 |
|
|
int change;
|
1684 |
|
|
unsigned int val;
|
1685 |
|
|
|
1686 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
1687 |
|
|
return -EBUSY;
|
1688 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
1689 |
|
|
spin_lock_irq(&hdsp->lock);
|
1690 |
|
|
change = (int)val != hdsp_spdif_professional(hdsp);
|
1691 |
|
|
hdsp_set_spdif_professional(hdsp, val);
|
1692 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1693 |
|
|
return change;
|
1694 |
|
|
}
|
1695 |
|
|
|
1696 |
|
|
#define HDSP_SPDIF_EMPHASIS(xname, xindex) \
|
1697 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
|
1698 |
|
|
.info = snd_hdsp_info_spdif_bits, \
|
1699 |
|
|
.get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
|
1700 |
|
|
|
1701 |
|
|
static int hdsp_spdif_emphasis(struct hdsp *hdsp)
|
1702 |
|
|
{
|
1703 |
|
|
return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
|
1704 |
|
|
}
|
1705 |
|
|
|
1706 |
|
|
static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
|
1707 |
|
|
{
|
1708 |
|
|
if (val)
|
1709 |
|
|
hdsp->control_register |= HDSP_SPDIFEmphasis;
|
1710 |
|
|
else
|
1711 |
|
|
hdsp->control_register &= ~HDSP_SPDIFEmphasis;
|
1712 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1713 |
|
|
return 0;
|
1714 |
|
|
}
|
1715 |
|
|
|
1716 |
|
|
static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1717 |
|
|
{
|
1718 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1719 |
|
|
|
1720 |
|
|
ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
|
1721 |
|
|
return 0;
|
1722 |
|
|
}
|
1723 |
|
|
|
1724 |
|
|
static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1725 |
|
|
{
|
1726 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1727 |
|
|
int change;
|
1728 |
|
|
unsigned int val;
|
1729 |
|
|
|
1730 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
1731 |
|
|
return -EBUSY;
|
1732 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
1733 |
|
|
spin_lock_irq(&hdsp->lock);
|
1734 |
|
|
change = (int)val != hdsp_spdif_emphasis(hdsp);
|
1735 |
|
|
hdsp_set_spdif_emphasis(hdsp, val);
|
1736 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1737 |
|
|
return change;
|
1738 |
|
|
}
|
1739 |
|
|
|
1740 |
|
|
#define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
|
1741 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
|
1742 |
|
|
.info = snd_hdsp_info_spdif_bits, \
|
1743 |
|
|
.get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
|
1744 |
|
|
|
1745 |
|
|
static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
|
1746 |
|
|
{
|
1747 |
|
|
return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
|
1748 |
|
|
}
|
1749 |
|
|
|
1750 |
|
|
static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
|
1751 |
|
|
{
|
1752 |
|
|
if (val)
|
1753 |
|
|
hdsp->control_register |= HDSP_SPDIFNonAudio;
|
1754 |
|
|
else
|
1755 |
|
|
hdsp->control_register &= ~HDSP_SPDIFNonAudio;
|
1756 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
1757 |
|
|
return 0;
|
1758 |
|
|
}
|
1759 |
|
|
|
1760 |
|
|
static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1761 |
|
|
{
|
1762 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1763 |
|
|
|
1764 |
|
|
ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
|
1765 |
|
|
return 0;
|
1766 |
|
|
}
|
1767 |
|
|
|
1768 |
|
|
static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1769 |
|
|
{
|
1770 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1771 |
|
|
int change;
|
1772 |
|
|
unsigned int val;
|
1773 |
|
|
|
1774 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
1775 |
|
|
return -EBUSY;
|
1776 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
1777 |
|
|
spin_lock_irq(&hdsp->lock);
|
1778 |
|
|
change = (int)val != hdsp_spdif_nonaudio(hdsp);
|
1779 |
|
|
hdsp_set_spdif_nonaudio(hdsp, val);
|
1780 |
|
|
spin_unlock_irq(&hdsp->lock);
|
1781 |
|
|
return change;
|
1782 |
|
|
}
|
1783 |
|
|
|
1784 |
|
|
#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
|
1785 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1786 |
|
|
.name = xname, \
|
1787 |
|
|
.index = xindex, \
|
1788 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
|
1789 |
|
|
.info = snd_hdsp_info_spdif_sample_rate, \
|
1790 |
|
|
.get = snd_hdsp_get_spdif_sample_rate \
|
1791 |
|
|
}
|
1792 |
|
|
|
1793 |
|
|
static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1794 |
|
|
{
|
1795 |
|
|
static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
|
1796 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1797 |
|
|
|
1798 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1799 |
|
|
uinfo->count = 1;
|
1800 |
|
|
uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
|
1801 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
1802 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
1803 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1804 |
|
|
return 0;
|
1805 |
|
|
}
|
1806 |
|
|
|
1807 |
|
|
static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1808 |
|
|
{
|
1809 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1810 |
|
|
|
1811 |
|
|
switch (hdsp_spdif_sample_rate(hdsp)) {
|
1812 |
|
|
case 32000:
|
1813 |
|
|
ucontrol->value.enumerated.item[0] = 0;
|
1814 |
|
|
break;
|
1815 |
|
|
case 44100:
|
1816 |
|
|
ucontrol->value.enumerated.item[0] = 1;
|
1817 |
|
|
break;
|
1818 |
|
|
case 48000:
|
1819 |
|
|
ucontrol->value.enumerated.item[0] = 2;
|
1820 |
|
|
break;
|
1821 |
|
|
case 64000:
|
1822 |
|
|
ucontrol->value.enumerated.item[0] = 3;
|
1823 |
|
|
break;
|
1824 |
|
|
case 88200:
|
1825 |
|
|
ucontrol->value.enumerated.item[0] = 4;
|
1826 |
|
|
break;
|
1827 |
|
|
case 96000:
|
1828 |
|
|
ucontrol->value.enumerated.item[0] = 5;
|
1829 |
|
|
break;
|
1830 |
|
|
case 128000:
|
1831 |
|
|
ucontrol->value.enumerated.item[0] = 7;
|
1832 |
|
|
break;
|
1833 |
|
|
case 176400:
|
1834 |
|
|
ucontrol->value.enumerated.item[0] = 8;
|
1835 |
|
|
break;
|
1836 |
|
|
case 192000:
|
1837 |
|
|
ucontrol->value.enumerated.item[0] = 9;
|
1838 |
|
|
break;
|
1839 |
|
|
default:
|
1840 |
|
|
ucontrol->value.enumerated.item[0] = 6;
|
1841 |
|
|
}
|
1842 |
|
|
return 0;
|
1843 |
|
|
}
|
1844 |
|
|
|
1845 |
|
|
#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
|
1846 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1847 |
|
|
.name = xname, \
|
1848 |
|
|
.index = xindex, \
|
1849 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
|
1850 |
|
|
.info = snd_hdsp_info_system_sample_rate, \
|
1851 |
|
|
.get = snd_hdsp_get_system_sample_rate \
|
1852 |
|
|
}
|
1853 |
|
|
|
1854 |
|
|
static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1855 |
|
|
{
|
1856 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
1857 |
|
|
uinfo->count = 1;
|
1858 |
|
|
return 0;
|
1859 |
|
|
}
|
1860 |
|
|
|
1861 |
|
|
static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1862 |
|
|
{
|
1863 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1864 |
|
|
|
1865 |
|
|
ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
|
1866 |
|
|
return 0;
|
1867 |
|
|
}
|
1868 |
|
|
|
1869 |
|
|
#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
|
1870 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1871 |
|
|
.name = xname, \
|
1872 |
|
|
.index = xindex, \
|
1873 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
|
1874 |
|
|
.info = snd_hdsp_info_autosync_sample_rate, \
|
1875 |
|
|
.get = snd_hdsp_get_autosync_sample_rate \
|
1876 |
|
|
}
|
1877 |
|
|
|
1878 |
|
|
static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1879 |
|
|
{
|
1880 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1881 |
|
|
static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
|
1882 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1883 |
|
|
uinfo->count = 1;
|
1884 |
|
|
uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
|
1885 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
1886 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
1887 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1888 |
|
|
return 0;
|
1889 |
|
|
}
|
1890 |
|
|
|
1891 |
|
|
static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1892 |
|
|
{
|
1893 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1894 |
|
|
|
1895 |
|
|
switch (hdsp_external_sample_rate(hdsp)) {
|
1896 |
|
|
case 32000:
|
1897 |
|
|
ucontrol->value.enumerated.item[0] = 0;
|
1898 |
|
|
break;
|
1899 |
|
|
case 44100:
|
1900 |
|
|
ucontrol->value.enumerated.item[0] = 1;
|
1901 |
|
|
break;
|
1902 |
|
|
case 48000:
|
1903 |
|
|
ucontrol->value.enumerated.item[0] = 2;
|
1904 |
|
|
break;
|
1905 |
|
|
case 64000:
|
1906 |
|
|
ucontrol->value.enumerated.item[0] = 3;
|
1907 |
|
|
break;
|
1908 |
|
|
case 88200:
|
1909 |
|
|
ucontrol->value.enumerated.item[0] = 4;
|
1910 |
|
|
break;
|
1911 |
|
|
case 96000:
|
1912 |
|
|
ucontrol->value.enumerated.item[0] = 5;
|
1913 |
|
|
break;
|
1914 |
|
|
case 128000:
|
1915 |
|
|
ucontrol->value.enumerated.item[0] = 7;
|
1916 |
|
|
break;
|
1917 |
|
|
case 176400:
|
1918 |
|
|
ucontrol->value.enumerated.item[0] = 8;
|
1919 |
|
|
break;
|
1920 |
|
|
case 192000:
|
1921 |
|
|
ucontrol->value.enumerated.item[0] = 9;
|
1922 |
|
|
break;
|
1923 |
|
|
default:
|
1924 |
|
|
ucontrol->value.enumerated.item[0] = 6;
|
1925 |
|
|
}
|
1926 |
|
|
return 0;
|
1927 |
|
|
}
|
1928 |
|
|
|
1929 |
|
|
#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
|
1930 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1931 |
|
|
.name = xname, \
|
1932 |
|
|
.index = xindex, \
|
1933 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
|
1934 |
|
|
.info = snd_hdsp_info_system_clock_mode, \
|
1935 |
|
|
.get = snd_hdsp_get_system_clock_mode \
|
1936 |
|
|
}
|
1937 |
|
|
|
1938 |
|
|
static int hdsp_system_clock_mode(struct hdsp *hdsp)
|
1939 |
|
|
{
|
1940 |
|
|
if (hdsp->control_register & HDSP_ClockModeMaster)
|
1941 |
|
|
return 0;
|
1942 |
|
|
else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
|
1943 |
|
|
return 0;
|
1944 |
|
|
return 1;
|
1945 |
|
|
}
|
1946 |
|
|
|
1947 |
|
|
static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
1948 |
|
|
{
|
1949 |
|
|
static char *texts[] = {"Master", "Slave" };
|
1950 |
|
|
|
1951 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
1952 |
|
|
uinfo->count = 1;
|
1953 |
|
|
uinfo->value.enumerated.items = 2;
|
1954 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
1955 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
1956 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
1957 |
|
|
return 0;
|
1958 |
|
|
}
|
1959 |
|
|
|
1960 |
|
|
static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
1961 |
|
|
{
|
1962 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
1963 |
|
|
|
1964 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
|
1965 |
|
|
return 0;
|
1966 |
|
|
}
|
1967 |
|
|
|
1968 |
|
|
#define HDSP_CLOCK_SOURCE(xname, xindex) \
|
1969 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
1970 |
|
|
.name = xname, \
|
1971 |
|
|
.index = xindex, \
|
1972 |
|
|
.info = snd_hdsp_info_clock_source, \
|
1973 |
|
|
.get = snd_hdsp_get_clock_source, \
|
1974 |
|
|
.put = snd_hdsp_put_clock_source \
|
1975 |
|
|
}
|
1976 |
|
|
|
1977 |
|
|
static int hdsp_clock_source(struct hdsp *hdsp)
|
1978 |
|
|
{
|
1979 |
|
|
if (hdsp->control_register & HDSP_ClockModeMaster) {
|
1980 |
|
|
switch (hdsp->system_sample_rate) {
|
1981 |
|
|
case 32000:
|
1982 |
|
|
return 1;
|
1983 |
|
|
case 44100:
|
1984 |
|
|
return 2;
|
1985 |
|
|
case 48000:
|
1986 |
|
|
return 3;
|
1987 |
|
|
case 64000:
|
1988 |
|
|
return 4;
|
1989 |
|
|
case 88200:
|
1990 |
|
|
return 5;
|
1991 |
|
|
case 96000:
|
1992 |
|
|
return 6;
|
1993 |
|
|
case 128000:
|
1994 |
|
|
return 7;
|
1995 |
|
|
case 176400:
|
1996 |
|
|
return 8;
|
1997 |
|
|
case 192000:
|
1998 |
|
|
return 9;
|
1999 |
|
|
default:
|
2000 |
|
|
return 3;
|
2001 |
|
|
}
|
2002 |
|
|
} else {
|
2003 |
|
|
return 0;
|
2004 |
|
|
}
|
2005 |
|
|
}
|
2006 |
|
|
|
2007 |
|
|
static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
|
2008 |
|
|
{
|
2009 |
|
|
int rate;
|
2010 |
|
|
switch (mode) {
|
2011 |
|
|
case HDSP_CLOCK_SOURCE_AUTOSYNC:
|
2012 |
|
|
if (hdsp_external_sample_rate(hdsp) != 0) {
|
2013 |
|
|
if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
|
2014 |
|
|
hdsp->control_register &= ~HDSP_ClockModeMaster;
|
2015 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2016 |
|
|
return 0;
|
2017 |
|
|
}
|
2018 |
|
|
}
|
2019 |
|
|
return -1;
|
2020 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
|
2021 |
|
|
rate = 32000;
|
2022 |
|
|
break;
|
2023 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
|
2024 |
|
|
rate = 44100;
|
2025 |
|
|
break;
|
2026 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
|
2027 |
|
|
rate = 48000;
|
2028 |
|
|
break;
|
2029 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
|
2030 |
|
|
rate = 64000;
|
2031 |
|
|
break;
|
2032 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
|
2033 |
|
|
rate = 88200;
|
2034 |
|
|
break;
|
2035 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
|
2036 |
|
|
rate = 96000;
|
2037 |
|
|
break;
|
2038 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
|
2039 |
|
|
rate = 128000;
|
2040 |
|
|
break;
|
2041 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
|
2042 |
|
|
rate = 176400;
|
2043 |
|
|
break;
|
2044 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
|
2045 |
|
|
rate = 192000;
|
2046 |
|
|
break;
|
2047 |
|
|
default:
|
2048 |
|
|
rate = 48000;
|
2049 |
|
|
}
|
2050 |
|
|
hdsp->control_register |= HDSP_ClockModeMaster;
|
2051 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2052 |
|
|
hdsp_set_rate(hdsp, rate, 1);
|
2053 |
|
|
return 0;
|
2054 |
|
|
}
|
2055 |
|
|
|
2056 |
|
|
static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2057 |
|
|
{
|
2058 |
|
|
static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
|
2059 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2060 |
|
|
|
2061 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2062 |
|
|
uinfo->count = 1;
|
2063 |
|
|
if (hdsp->io_type == H9632)
|
2064 |
|
|
uinfo->value.enumerated.items = 10;
|
2065 |
|
|
else
|
2066 |
|
|
uinfo->value.enumerated.items = 7;
|
2067 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2068 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2069 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2070 |
|
|
return 0;
|
2071 |
|
|
}
|
2072 |
|
|
|
2073 |
|
|
static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2074 |
|
|
{
|
2075 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2076 |
|
|
|
2077 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
|
2078 |
|
|
return 0;
|
2079 |
|
|
}
|
2080 |
|
|
|
2081 |
|
|
static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2082 |
|
|
{
|
2083 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2084 |
|
|
int change;
|
2085 |
|
|
int val;
|
2086 |
|
|
|
2087 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2088 |
|
|
return -EBUSY;
|
2089 |
|
|
val = ucontrol->value.enumerated.item[0];
|
2090 |
|
|
if (val < 0) val = 0;
|
2091 |
|
|
if (hdsp->io_type == H9632) {
|
2092 |
|
|
if (val > 9)
|
2093 |
|
|
val = 9;
|
2094 |
|
|
} else {
|
2095 |
|
|
if (val > 6)
|
2096 |
|
|
val = 6;
|
2097 |
|
|
}
|
2098 |
|
|
spin_lock_irq(&hdsp->lock);
|
2099 |
|
|
if (val != hdsp_clock_source(hdsp))
|
2100 |
|
|
change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
|
2101 |
|
|
else
|
2102 |
|
|
change = 0;
|
2103 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2104 |
|
|
return change;
|
2105 |
|
|
}
|
2106 |
|
|
|
2107 |
|
|
#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
|
2108 |
|
|
|
2109 |
|
|
static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2110 |
|
|
{
|
2111 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2112 |
|
|
|
2113 |
|
|
ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
|
2114 |
|
|
return 0;
|
2115 |
|
|
}
|
2116 |
|
|
|
2117 |
|
|
static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2118 |
|
|
{
|
2119 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2120 |
|
|
int change;
|
2121 |
|
|
|
2122 |
|
|
change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
|
2123 |
|
|
if (change)
|
2124 |
|
|
hdsp->clock_source_locked = ucontrol->value.integer.value[0];
|
2125 |
|
|
return change;
|
2126 |
|
|
}
|
2127 |
|
|
|
2128 |
|
|
#define HDSP_DA_GAIN(xname, xindex) \
|
2129 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2130 |
|
|
.name = xname, \
|
2131 |
|
|
.index = xindex, \
|
2132 |
|
|
.info = snd_hdsp_info_da_gain, \
|
2133 |
|
|
.get = snd_hdsp_get_da_gain, \
|
2134 |
|
|
.put = snd_hdsp_put_da_gain \
|
2135 |
|
|
}
|
2136 |
|
|
|
2137 |
|
|
static int hdsp_da_gain(struct hdsp *hdsp)
|
2138 |
|
|
{
|
2139 |
|
|
switch (hdsp->control_register & HDSP_DAGainMask) {
|
2140 |
|
|
case HDSP_DAGainHighGain:
|
2141 |
|
|
return 0;
|
2142 |
|
|
case HDSP_DAGainPlus4dBu:
|
2143 |
|
|
return 1;
|
2144 |
|
|
case HDSP_DAGainMinus10dBV:
|
2145 |
|
|
return 2;
|
2146 |
|
|
default:
|
2147 |
|
|
return 1;
|
2148 |
|
|
}
|
2149 |
|
|
}
|
2150 |
|
|
|
2151 |
|
|
static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
|
2152 |
|
|
{
|
2153 |
|
|
hdsp->control_register &= ~HDSP_DAGainMask;
|
2154 |
|
|
switch (mode) {
|
2155 |
|
|
case 0:
|
2156 |
|
|
hdsp->control_register |= HDSP_DAGainHighGain;
|
2157 |
|
|
break;
|
2158 |
|
|
case 1:
|
2159 |
|
|
hdsp->control_register |= HDSP_DAGainPlus4dBu;
|
2160 |
|
|
break;
|
2161 |
|
|
case 2:
|
2162 |
|
|
hdsp->control_register |= HDSP_DAGainMinus10dBV;
|
2163 |
|
|
break;
|
2164 |
|
|
default:
|
2165 |
|
|
return -1;
|
2166 |
|
|
|
2167 |
|
|
}
|
2168 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2169 |
|
|
return 0;
|
2170 |
|
|
}
|
2171 |
|
|
|
2172 |
|
|
static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2173 |
|
|
{
|
2174 |
|
|
static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
|
2175 |
|
|
|
2176 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2177 |
|
|
uinfo->count = 1;
|
2178 |
|
|
uinfo->value.enumerated.items = 3;
|
2179 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2180 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2181 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2182 |
|
|
return 0;
|
2183 |
|
|
}
|
2184 |
|
|
|
2185 |
|
|
static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2186 |
|
|
{
|
2187 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2188 |
|
|
|
2189 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
|
2190 |
|
|
return 0;
|
2191 |
|
|
}
|
2192 |
|
|
|
2193 |
|
|
static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2194 |
|
|
{
|
2195 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2196 |
|
|
int change;
|
2197 |
|
|
int val;
|
2198 |
|
|
|
2199 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2200 |
|
|
return -EBUSY;
|
2201 |
|
|
val = ucontrol->value.enumerated.item[0];
|
2202 |
|
|
if (val < 0) val = 0;
|
2203 |
|
|
if (val > 2) val = 2;
|
2204 |
|
|
spin_lock_irq(&hdsp->lock);
|
2205 |
|
|
if (val != hdsp_da_gain(hdsp))
|
2206 |
|
|
change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
|
2207 |
|
|
else
|
2208 |
|
|
change = 0;
|
2209 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2210 |
|
|
return change;
|
2211 |
|
|
}
|
2212 |
|
|
|
2213 |
|
|
#define HDSP_AD_GAIN(xname, xindex) \
|
2214 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2215 |
|
|
.name = xname, \
|
2216 |
|
|
.index = xindex, \
|
2217 |
|
|
.info = snd_hdsp_info_ad_gain, \
|
2218 |
|
|
.get = snd_hdsp_get_ad_gain, \
|
2219 |
|
|
.put = snd_hdsp_put_ad_gain \
|
2220 |
|
|
}
|
2221 |
|
|
|
2222 |
|
|
static int hdsp_ad_gain(struct hdsp *hdsp)
|
2223 |
|
|
{
|
2224 |
|
|
switch (hdsp->control_register & HDSP_ADGainMask) {
|
2225 |
|
|
case HDSP_ADGainMinus10dBV:
|
2226 |
|
|
return 0;
|
2227 |
|
|
case HDSP_ADGainPlus4dBu:
|
2228 |
|
|
return 1;
|
2229 |
|
|
case HDSP_ADGainLowGain:
|
2230 |
|
|
return 2;
|
2231 |
|
|
default:
|
2232 |
|
|
return 1;
|
2233 |
|
|
}
|
2234 |
|
|
}
|
2235 |
|
|
|
2236 |
|
|
static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
|
2237 |
|
|
{
|
2238 |
|
|
hdsp->control_register &= ~HDSP_ADGainMask;
|
2239 |
|
|
switch (mode) {
|
2240 |
|
|
case 0:
|
2241 |
|
|
hdsp->control_register |= HDSP_ADGainMinus10dBV;
|
2242 |
|
|
break;
|
2243 |
|
|
case 1:
|
2244 |
|
|
hdsp->control_register |= HDSP_ADGainPlus4dBu;
|
2245 |
|
|
break;
|
2246 |
|
|
case 2:
|
2247 |
|
|
hdsp->control_register |= HDSP_ADGainLowGain;
|
2248 |
|
|
break;
|
2249 |
|
|
default:
|
2250 |
|
|
return -1;
|
2251 |
|
|
|
2252 |
|
|
}
|
2253 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2254 |
|
|
return 0;
|
2255 |
|
|
}
|
2256 |
|
|
|
2257 |
|
|
static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2258 |
|
|
{
|
2259 |
|
|
static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
|
2260 |
|
|
|
2261 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2262 |
|
|
uinfo->count = 1;
|
2263 |
|
|
uinfo->value.enumerated.items = 3;
|
2264 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2265 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2266 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2267 |
|
|
return 0;
|
2268 |
|
|
}
|
2269 |
|
|
|
2270 |
|
|
static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2271 |
|
|
{
|
2272 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2273 |
|
|
|
2274 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
|
2275 |
|
|
return 0;
|
2276 |
|
|
}
|
2277 |
|
|
|
2278 |
|
|
static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2279 |
|
|
{
|
2280 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2281 |
|
|
int change;
|
2282 |
|
|
int val;
|
2283 |
|
|
|
2284 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2285 |
|
|
return -EBUSY;
|
2286 |
|
|
val = ucontrol->value.enumerated.item[0];
|
2287 |
|
|
if (val < 0) val = 0;
|
2288 |
|
|
if (val > 2) val = 2;
|
2289 |
|
|
spin_lock_irq(&hdsp->lock);
|
2290 |
|
|
if (val != hdsp_ad_gain(hdsp))
|
2291 |
|
|
change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
|
2292 |
|
|
else
|
2293 |
|
|
change = 0;
|
2294 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2295 |
|
|
return change;
|
2296 |
|
|
}
|
2297 |
|
|
|
2298 |
|
|
#define HDSP_PHONE_GAIN(xname, xindex) \
|
2299 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2300 |
|
|
.name = xname, \
|
2301 |
|
|
.index = xindex, \
|
2302 |
|
|
.info = snd_hdsp_info_phone_gain, \
|
2303 |
|
|
.get = snd_hdsp_get_phone_gain, \
|
2304 |
|
|
.put = snd_hdsp_put_phone_gain \
|
2305 |
|
|
}
|
2306 |
|
|
|
2307 |
|
|
static int hdsp_phone_gain(struct hdsp *hdsp)
|
2308 |
|
|
{
|
2309 |
|
|
switch (hdsp->control_register & HDSP_PhoneGainMask) {
|
2310 |
|
|
case HDSP_PhoneGain0dB:
|
2311 |
|
|
return 0;
|
2312 |
|
|
case HDSP_PhoneGainMinus6dB:
|
2313 |
|
|
return 1;
|
2314 |
|
|
case HDSP_PhoneGainMinus12dB:
|
2315 |
|
|
return 2;
|
2316 |
|
|
default:
|
2317 |
|
|
return 0;
|
2318 |
|
|
}
|
2319 |
|
|
}
|
2320 |
|
|
|
2321 |
|
|
static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
|
2322 |
|
|
{
|
2323 |
|
|
hdsp->control_register &= ~HDSP_PhoneGainMask;
|
2324 |
|
|
switch (mode) {
|
2325 |
|
|
case 0:
|
2326 |
|
|
hdsp->control_register |= HDSP_PhoneGain0dB;
|
2327 |
|
|
break;
|
2328 |
|
|
case 1:
|
2329 |
|
|
hdsp->control_register |= HDSP_PhoneGainMinus6dB;
|
2330 |
|
|
break;
|
2331 |
|
|
case 2:
|
2332 |
|
|
hdsp->control_register |= HDSP_PhoneGainMinus12dB;
|
2333 |
|
|
break;
|
2334 |
|
|
default:
|
2335 |
|
|
return -1;
|
2336 |
|
|
|
2337 |
|
|
}
|
2338 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2339 |
|
|
return 0;
|
2340 |
|
|
}
|
2341 |
|
|
|
2342 |
|
|
static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2343 |
|
|
{
|
2344 |
|
|
static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
|
2345 |
|
|
|
2346 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2347 |
|
|
uinfo->count = 1;
|
2348 |
|
|
uinfo->value.enumerated.items = 3;
|
2349 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2350 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2351 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2352 |
|
|
return 0;
|
2353 |
|
|
}
|
2354 |
|
|
|
2355 |
|
|
static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2356 |
|
|
{
|
2357 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2358 |
|
|
|
2359 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
|
2360 |
|
|
return 0;
|
2361 |
|
|
}
|
2362 |
|
|
|
2363 |
|
|
static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2364 |
|
|
{
|
2365 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2366 |
|
|
int change;
|
2367 |
|
|
int val;
|
2368 |
|
|
|
2369 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2370 |
|
|
return -EBUSY;
|
2371 |
|
|
val = ucontrol->value.enumerated.item[0];
|
2372 |
|
|
if (val < 0) val = 0;
|
2373 |
|
|
if (val > 2) val = 2;
|
2374 |
|
|
spin_lock_irq(&hdsp->lock);
|
2375 |
|
|
if (val != hdsp_phone_gain(hdsp))
|
2376 |
|
|
change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
|
2377 |
|
|
else
|
2378 |
|
|
change = 0;
|
2379 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2380 |
|
|
return change;
|
2381 |
|
|
}
|
2382 |
|
|
|
2383 |
|
|
#define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
|
2384 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2385 |
|
|
.name = xname, \
|
2386 |
|
|
.index = xindex, \
|
2387 |
|
|
.info = snd_hdsp_info_xlr_breakout_cable, \
|
2388 |
|
|
.get = snd_hdsp_get_xlr_breakout_cable, \
|
2389 |
|
|
.put = snd_hdsp_put_xlr_breakout_cable \
|
2390 |
|
|
}
|
2391 |
|
|
|
2392 |
|
|
static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
|
2393 |
|
|
{
|
2394 |
|
|
if (hdsp->control_register & HDSP_XLRBreakoutCable)
|
2395 |
|
|
return 1;
|
2396 |
|
|
return 0;
|
2397 |
|
|
}
|
2398 |
|
|
|
2399 |
|
|
static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
|
2400 |
|
|
{
|
2401 |
|
|
if (mode)
|
2402 |
|
|
hdsp->control_register |= HDSP_XLRBreakoutCable;
|
2403 |
|
|
else
|
2404 |
|
|
hdsp->control_register &= ~HDSP_XLRBreakoutCable;
|
2405 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2406 |
|
|
return 0;
|
2407 |
|
|
}
|
2408 |
|
|
|
2409 |
|
|
#define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
|
2410 |
|
|
|
2411 |
|
|
static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2412 |
|
|
{
|
2413 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2414 |
|
|
|
2415 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
|
2416 |
|
|
return 0;
|
2417 |
|
|
}
|
2418 |
|
|
|
2419 |
|
|
static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2420 |
|
|
{
|
2421 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2422 |
|
|
int change;
|
2423 |
|
|
int val;
|
2424 |
|
|
|
2425 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2426 |
|
|
return -EBUSY;
|
2427 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
2428 |
|
|
spin_lock_irq(&hdsp->lock);
|
2429 |
|
|
change = (int)val != hdsp_xlr_breakout_cable(hdsp);
|
2430 |
|
|
hdsp_set_xlr_breakout_cable(hdsp, val);
|
2431 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2432 |
|
|
return change;
|
2433 |
|
|
}
|
2434 |
|
|
|
2435 |
|
|
/* (De)activates old RME Analog Extension Board
|
2436 |
|
|
These are connected to the internal ADAT connector
|
2437 |
|
|
Switching this on desactivates external ADAT
|
2438 |
|
|
*/
|
2439 |
|
|
#define HDSP_AEB(xname, xindex) \
|
2440 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2441 |
|
|
.name = xname, \
|
2442 |
|
|
.index = xindex, \
|
2443 |
|
|
.info = snd_hdsp_info_aeb, \
|
2444 |
|
|
.get = snd_hdsp_get_aeb, \
|
2445 |
|
|
.put = snd_hdsp_put_aeb \
|
2446 |
|
|
}
|
2447 |
|
|
|
2448 |
|
|
static int hdsp_aeb(struct hdsp *hdsp)
|
2449 |
|
|
{
|
2450 |
|
|
if (hdsp->control_register & HDSP_AnalogExtensionBoard)
|
2451 |
|
|
return 1;
|
2452 |
|
|
return 0;
|
2453 |
|
|
}
|
2454 |
|
|
|
2455 |
|
|
static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
|
2456 |
|
|
{
|
2457 |
|
|
if (mode)
|
2458 |
|
|
hdsp->control_register |= HDSP_AnalogExtensionBoard;
|
2459 |
|
|
else
|
2460 |
|
|
hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
|
2461 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2462 |
|
|
return 0;
|
2463 |
|
|
}
|
2464 |
|
|
|
2465 |
|
|
#define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
|
2466 |
|
|
|
2467 |
|
|
static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2468 |
|
|
{
|
2469 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2470 |
|
|
|
2471 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
|
2472 |
|
|
return 0;
|
2473 |
|
|
}
|
2474 |
|
|
|
2475 |
|
|
static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2476 |
|
|
{
|
2477 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2478 |
|
|
int change;
|
2479 |
|
|
int val;
|
2480 |
|
|
|
2481 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2482 |
|
|
return -EBUSY;
|
2483 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
2484 |
|
|
spin_lock_irq(&hdsp->lock);
|
2485 |
|
|
change = (int)val != hdsp_aeb(hdsp);
|
2486 |
|
|
hdsp_set_aeb(hdsp, val);
|
2487 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2488 |
|
|
return change;
|
2489 |
|
|
}
|
2490 |
|
|
|
2491 |
|
|
#define HDSP_PREF_SYNC_REF(xname, xindex) \
|
2492 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2493 |
|
|
.name = xname, \
|
2494 |
|
|
.index = xindex, \
|
2495 |
|
|
.info = snd_hdsp_info_pref_sync_ref, \
|
2496 |
|
|
.get = snd_hdsp_get_pref_sync_ref, \
|
2497 |
|
|
.put = snd_hdsp_put_pref_sync_ref \
|
2498 |
|
|
}
|
2499 |
|
|
|
2500 |
|
|
static int hdsp_pref_sync_ref(struct hdsp *hdsp)
|
2501 |
|
|
{
|
2502 |
|
|
/* Notice that this looks at the requested sync source,
|
2503 |
|
|
not the one actually in use.
|
2504 |
|
|
*/
|
2505 |
|
|
|
2506 |
|
|
switch (hdsp->control_register & HDSP_SyncRefMask) {
|
2507 |
|
|
case HDSP_SyncRef_ADAT1:
|
2508 |
|
|
return HDSP_SYNC_FROM_ADAT1;
|
2509 |
|
|
case HDSP_SyncRef_ADAT2:
|
2510 |
|
|
return HDSP_SYNC_FROM_ADAT2;
|
2511 |
|
|
case HDSP_SyncRef_ADAT3:
|
2512 |
|
|
return HDSP_SYNC_FROM_ADAT3;
|
2513 |
|
|
case HDSP_SyncRef_SPDIF:
|
2514 |
|
|
return HDSP_SYNC_FROM_SPDIF;
|
2515 |
|
|
case HDSP_SyncRef_WORD:
|
2516 |
|
|
return HDSP_SYNC_FROM_WORD;
|
2517 |
|
|
case HDSP_SyncRef_ADAT_SYNC:
|
2518 |
|
|
return HDSP_SYNC_FROM_ADAT_SYNC;
|
2519 |
|
|
default:
|
2520 |
|
|
return HDSP_SYNC_FROM_WORD;
|
2521 |
|
|
}
|
2522 |
|
|
return 0;
|
2523 |
|
|
}
|
2524 |
|
|
|
2525 |
|
|
static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
|
2526 |
|
|
{
|
2527 |
|
|
hdsp->control_register &= ~HDSP_SyncRefMask;
|
2528 |
|
|
switch (pref) {
|
2529 |
|
|
case HDSP_SYNC_FROM_ADAT1:
|
2530 |
|
|
hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
|
2531 |
|
|
break;
|
2532 |
|
|
case HDSP_SYNC_FROM_ADAT2:
|
2533 |
|
|
hdsp->control_register |= HDSP_SyncRef_ADAT2;
|
2534 |
|
|
break;
|
2535 |
|
|
case HDSP_SYNC_FROM_ADAT3:
|
2536 |
|
|
hdsp->control_register |= HDSP_SyncRef_ADAT3;
|
2537 |
|
|
break;
|
2538 |
|
|
case HDSP_SYNC_FROM_SPDIF:
|
2539 |
|
|
hdsp->control_register |= HDSP_SyncRef_SPDIF;
|
2540 |
|
|
break;
|
2541 |
|
|
case HDSP_SYNC_FROM_WORD:
|
2542 |
|
|
hdsp->control_register |= HDSP_SyncRef_WORD;
|
2543 |
|
|
break;
|
2544 |
|
|
case HDSP_SYNC_FROM_ADAT_SYNC:
|
2545 |
|
|
hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
|
2546 |
|
|
break;
|
2547 |
|
|
default:
|
2548 |
|
|
return -1;
|
2549 |
|
|
}
|
2550 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2551 |
|
|
return 0;
|
2552 |
|
|
}
|
2553 |
|
|
|
2554 |
|
|
static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2555 |
|
|
{
|
2556 |
|
|
static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
|
2557 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2558 |
|
|
|
2559 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2560 |
|
|
uinfo->count = 1;
|
2561 |
|
|
|
2562 |
|
|
switch (hdsp->io_type) {
|
2563 |
|
|
case Digiface:
|
2564 |
|
|
case H9652:
|
2565 |
|
|
uinfo->value.enumerated.items = 6;
|
2566 |
|
|
break;
|
2567 |
|
|
case Multiface:
|
2568 |
|
|
uinfo->value.enumerated.items = 4;
|
2569 |
|
|
break;
|
2570 |
|
|
case H9632:
|
2571 |
|
|
uinfo->value.enumerated.items = 3;
|
2572 |
|
|
break;
|
2573 |
|
|
default:
|
2574 |
|
|
uinfo->value.enumerated.items = 0;
|
2575 |
|
|
break;
|
2576 |
|
|
}
|
2577 |
|
|
|
2578 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2579 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2580 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2581 |
|
|
return 0;
|
2582 |
|
|
}
|
2583 |
|
|
|
2584 |
|
|
static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2585 |
|
|
{
|
2586 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2587 |
|
|
|
2588 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
|
2589 |
|
|
return 0;
|
2590 |
|
|
}
|
2591 |
|
|
|
2592 |
|
|
static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2593 |
|
|
{
|
2594 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2595 |
|
|
int change, max;
|
2596 |
|
|
unsigned int val;
|
2597 |
|
|
|
2598 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2599 |
|
|
return -EBUSY;
|
2600 |
|
|
|
2601 |
|
|
switch (hdsp->io_type) {
|
2602 |
|
|
case Digiface:
|
2603 |
|
|
case H9652:
|
2604 |
|
|
max = 6;
|
2605 |
|
|
break;
|
2606 |
|
|
case Multiface:
|
2607 |
|
|
max = 4;
|
2608 |
|
|
break;
|
2609 |
|
|
case H9632:
|
2610 |
|
|
max = 3;
|
2611 |
|
|
break;
|
2612 |
|
|
default:
|
2613 |
|
|
return -EIO;
|
2614 |
|
|
}
|
2615 |
|
|
|
2616 |
|
|
val = ucontrol->value.enumerated.item[0] % max;
|
2617 |
|
|
spin_lock_irq(&hdsp->lock);
|
2618 |
|
|
change = (int)val != hdsp_pref_sync_ref(hdsp);
|
2619 |
|
|
hdsp_set_pref_sync_ref(hdsp, val);
|
2620 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2621 |
|
|
return change;
|
2622 |
|
|
}
|
2623 |
|
|
|
2624 |
|
|
#define HDSP_AUTOSYNC_REF(xname, xindex) \
|
2625 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2626 |
|
|
.name = xname, \
|
2627 |
|
|
.index = xindex, \
|
2628 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
|
2629 |
|
|
.info = snd_hdsp_info_autosync_ref, \
|
2630 |
|
|
.get = snd_hdsp_get_autosync_ref, \
|
2631 |
|
|
}
|
2632 |
|
|
|
2633 |
|
|
static int hdsp_autosync_ref(struct hdsp *hdsp)
|
2634 |
|
|
{
|
2635 |
|
|
/* This looks at the autosync selected sync reference */
|
2636 |
|
|
unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
|
2637 |
|
|
|
2638 |
|
|
switch (status2 & HDSP_SelSyncRefMask) {
|
2639 |
|
|
case HDSP_SelSyncRef_WORD:
|
2640 |
|
|
return HDSP_AUTOSYNC_FROM_WORD;
|
2641 |
|
|
case HDSP_SelSyncRef_ADAT_SYNC:
|
2642 |
|
|
return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
|
2643 |
|
|
case HDSP_SelSyncRef_SPDIF:
|
2644 |
|
|
return HDSP_AUTOSYNC_FROM_SPDIF;
|
2645 |
|
|
case HDSP_SelSyncRefMask:
|
2646 |
|
|
return HDSP_AUTOSYNC_FROM_NONE;
|
2647 |
|
|
case HDSP_SelSyncRef_ADAT1:
|
2648 |
|
|
return HDSP_AUTOSYNC_FROM_ADAT1;
|
2649 |
|
|
case HDSP_SelSyncRef_ADAT2:
|
2650 |
|
|
return HDSP_AUTOSYNC_FROM_ADAT2;
|
2651 |
|
|
case HDSP_SelSyncRef_ADAT3:
|
2652 |
|
|
return HDSP_AUTOSYNC_FROM_ADAT3;
|
2653 |
|
|
default:
|
2654 |
|
|
return HDSP_AUTOSYNC_FROM_WORD;
|
2655 |
|
|
}
|
2656 |
|
|
return 0;
|
2657 |
|
|
}
|
2658 |
|
|
|
2659 |
|
|
static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2660 |
|
|
{
|
2661 |
|
|
static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
|
2662 |
|
|
|
2663 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2664 |
|
|
uinfo->count = 1;
|
2665 |
|
|
uinfo->value.enumerated.items = 7;
|
2666 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2667 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2668 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2669 |
|
|
return 0;
|
2670 |
|
|
}
|
2671 |
|
|
|
2672 |
|
|
static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2673 |
|
|
{
|
2674 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2675 |
|
|
|
2676 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
|
2677 |
|
|
return 0;
|
2678 |
|
|
}
|
2679 |
|
|
|
2680 |
|
|
#define HDSP_LINE_OUT(xname, xindex) \
|
2681 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2682 |
|
|
.name = xname, \
|
2683 |
|
|
.index = xindex, \
|
2684 |
|
|
.info = snd_hdsp_info_line_out, \
|
2685 |
|
|
.get = snd_hdsp_get_line_out, \
|
2686 |
|
|
.put = snd_hdsp_put_line_out \
|
2687 |
|
|
}
|
2688 |
|
|
|
2689 |
|
|
static int hdsp_line_out(struct hdsp *hdsp)
|
2690 |
|
|
{
|
2691 |
|
|
return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
|
2692 |
|
|
}
|
2693 |
|
|
|
2694 |
|
|
static int hdsp_set_line_output(struct hdsp *hdsp, int out)
|
2695 |
|
|
{
|
2696 |
|
|
if (out)
|
2697 |
|
|
hdsp->control_register |= HDSP_LineOut;
|
2698 |
|
|
else
|
2699 |
|
|
hdsp->control_register &= ~HDSP_LineOut;
|
2700 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
2701 |
|
|
return 0;
|
2702 |
|
|
}
|
2703 |
|
|
|
2704 |
|
|
#define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
|
2705 |
|
|
|
2706 |
|
|
static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2707 |
|
|
{
|
2708 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2709 |
|
|
|
2710 |
|
|
spin_lock_irq(&hdsp->lock);
|
2711 |
|
|
ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
|
2712 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2713 |
|
|
return 0;
|
2714 |
|
|
}
|
2715 |
|
|
|
2716 |
|
|
static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2717 |
|
|
{
|
2718 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2719 |
|
|
int change;
|
2720 |
|
|
unsigned int val;
|
2721 |
|
|
|
2722 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2723 |
|
|
return -EBUSY;
|
2724 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
2725 |
|
|
spin_lock_irq(&hdsp->lock);
|
2726 |
|
|
change = (int)val != hdsp_line_out(hdsp);
|
2727 |
|
|
hdsp_set_line_output(hdsp, val);
|
2728 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2729 |
|
|
return change;
|
2730 |
|
|
}
|
2731 |
|
|
|
2732 |
|
|
#define HDSP_PRECISE_POINTER(xname, xindex) \
|
2733 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
|
2734 |
|
|
.name = xname, \
|
2735 |
|
|
.index = xindex, \
|
2736 |
|
|
.info = snd_hdsp_info_precise_pointer, \
|
2737 |
|
|
.get = snd_hdsp_get_precise_pointer, \
|
2738 |
|
|
.put = snd_hdsp_put_precise_pointer \
|
2739 |
|
|
}
|
2740 |
|
|
|
2741 |
|
|
static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
|
2742 |
|
|
{
|
2743 |
|
|
if (precise)
|
2744 |
|
|
hdsp->precise_ptr = 1;
|
2745 |
|
|
else
|
2746 |
|
|
hdsp->precise_ptr = 0;
|
2747 |
|
|
return 0;
|
2748 |
|
|
}
|
2749 |
|
|
|
2750 |
|
|
#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
|
2751 |
|
|
|
2752 |
|
|
static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2753 |
|
|
{
|
2754 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2755 |
|
|
|
2756 |
|
|
spin_lock_irq(&hdsp->lock);
|
2757 |
|
|
ucontrol->value.integer.value[0] = hdsp->precise_ptr;
|
2758 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2759 |
|
|
return 0;
|
2760 |
|
|
}
|
2761 |
|
|
|
2762 |
|
|
static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2763 |
|
|
{
|
2764 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2765 |
|
|
int change;
|
2766 |
|
|
unsigned int val;
|
2767 |
|
|
|
2768 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2769 |
|
|
return -EBUSY;
|
2770 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
2771 |
|
|
spin_lock_irq(&hdsp->lock);
|
2772 |
|
|
change = (int)val != hdsp->precise_ptr;
|
2773 |
|
|
hdsp_set_precise_pointer(hdsp, val);
|
2774 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2775 |
|
|
return change;
|
2776 |
|
|
}
|
2777 |
|
|
|
2778 |
|
|
#define HDSP_USE_MIDI_TASKLET(xname, xindex) \
|
2779 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
|
2780 |
|
|
.name = xname, \
|
2781 |
|
|
.index = xindex, \
|
2782 |
|
|
.info = snd_hdsp_info_use_midi_tasklet, \
|
2783 |
|
|
.get = snd_hdsp_get_use_midi_tasklet, \
|
2784 |
|
|
.put = snd_hdsp_put_use_midi_tasklet \
|
2785 |
|
|
}
|
2786 |
|
|
|
2787 |
|
|
static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
|
2788 |
|
|
{
|
2789 |
|
|
if (use_tasklet)
|
2790 |
|
|
hdsp->use_midi_tasklet = 1;
|
2791 |
|
|
else
|
2792 |
|
|
hdsp->use_midi_tasklet = 0;
|
2793 |
|
|
return 0;
|
2794 |
|
|
}
|
2795 |
|
|
|
2796 |
|
|
#define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
|
2797 |
|
|
|
2798 |
|
|
static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2799 |
|
|
{
|
2800 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2801 |
|
|
|
2802 |
|
|
spin_lock_irq(&hdsp->lock);
|
2803 |
|
|
ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
|
2804 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2805 |
|
|
return 0;
|
2806 |
|
|
}
|
2807 |
|
|
|
2808 |
|
|
static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2809 |
|
|
{
|
2810 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2811 |
|
|
int change;
|
2812 |
|
|
unsigned int val;
|
2813 |
|
|
|
2814 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2815 |
|
|
return -EBUSY;
|
2816 |
|
|
val = ucontrol->value.integer.value[0] & 1;
|
2817 |
|
|
spin_lock_irq(&hdsp->lock);
|
2818 |
|
|
change = (int)val != hdsp->use_midi_tasklet;
|
2819 |
|
|
hdsp_set_use_midi_tasklet(hdsp, val);
|
2820 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2821 |
|
|
return change;
|
2822 |
|
|
}
|
2823 |
|
|
|
2824 |
|
|
#define HDSP_MIXER(xname, xindex) \
|
2825 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
|
2826 |
|
|
.name = xname, \
|
2827 |
|
|
.index = xindex, \
|
2828 |
|
|
.device = 0, \
|
2829 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
|
2830 |
|
|
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
|
2831 |
|
|
.info = snd_hdsp_info_mixer, \
|
2832 |
|
|
.get = snd_hdsp_get_mixer, \
|
2833 |
|
|
.put = snd_hdsp_put_mixer \
|
2834 |
|
|
}
|
2835 |
|
|
|
2836 |
|
|
static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2837 |
|
|
{
|
2838 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
2839 |
|
|
uinfo->count = 3;
|
2840 |
|
|
uinfo->value.integer.min = 0;
|
2841 |
|
|
uinfo->value.integer.max = 65536;
|
2842 |
|
|
uinfo->value.integer.step = 1;
|
2843 |
|
|
return 0;
|
2844 |
|
|
}
|
2845 |
|
|
|
2846 |
|
|
static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2847 |
|
|
{
|
2848 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2849 |
|
|
int source;
|
2850 |
|
|
int destination;
|
2851 |
|
|
int addr;
|
2852 |
|
|
|
2853 |
|
|
source = ucontrol->value.integer.value[0];
|
2854 |
|
|
destination = ucontrol->value.integer.value[1];
|
2855 |
|
|
|
2856 |
|
|
if (source >= hdsp->max_channels)
|
2857 |
|
|
addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
|
2858 |
|
|
else
|
2859 |
|
|
addr = hdsp_input_to_output_key(hdsp,source, destination);
|
2860 |
|
|
|
2861 |
|
|
spin_lock_irq(&hdsp->lock);
|
2862 |
|
|
ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
|
2863 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2864 |
|
|
return 0;
|
2865 |
|
|
}
|
2866 |
|
|
|
2867 |
|
|
static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2868 |
|
|
{
|
2869 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2870 |
|
|
int change;
|
2871 |
|
|
int source;
|
2872 |
|
|
int destination;
|
2873 |
|
|
int gain;
|
2874 |
|
|
int addr;
|
2875 |
|
|
|
2876 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
2877 |
|
|
return -EBUSY;
|
2878 |
|
|
|
2879 |
|
|
source = ucontrol->value.integer.value[0];
|
2880 |
|
|
destination = ucontrol->value.integer.value[1];
|
2881 |
|
|
|
2882 |
|
|
if (source >= hdsp->max_channels)
|
2883 |
|
|
addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
|
2884 |
|
|
else
|
2885 |
|
|
addr = hdsp_input_to_output_key(hdsp,source, destination);
|
2886 |
|
|
|
2887 |
|
|
gain = ucontrol->value.integer.value[2];
|
2888 |
|
|
|
2889 |
|
|
spin_lock_irq(&hdsp->lock);
|
2890 |
|
|
change = gain != hdsp_read_gain(hdsp, addr);
|
2891 |
|
|
if (change)
|
2892 |
|
|
hdsp_write_gain(hdsp, addr, gain);
|
2893 |
|
|
spin_unlock_irq(&hdsp->lock);
|
2894 |
|
|
return change;
|
2895 |
|
|
}
|
2896 |
|
|
|
2897 |
|
|
#define HDSP_WC_SYNC_CHECK(xname, xindex) \
|
2898 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2899 |
|
|
.name = xname, \
|
2900 |
|
|
.index = xindex, \
|
2901 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
|
2902 |
|
|
.info = snd_hdsp_info_sync_check, \
|
2903 |
|
|
.get = snd_hdsp_get_wc_sync_check \
|
2904 |
|
|
}
|
2905 |
|
|
|
2906 |
|
|
static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
2907 |
|
|
{
|
2908 |
|
|
static char *texts[] = {"No Lock", "Lock", "Sync" };
|
2909 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
|
2910 |
|
|
uinfo->count = 1;
|
2911 |
|
|
uinfo->value.enumerated.items = 3;
|
2912 |
|
|
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
|
2913 |
|
|
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
|
2914 |
|
|
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
|
2915 |
|
|
return 0;
|
2916 |
|
|
}
|
2917 |
|
|
|
2918 |
|
|
static int hdsp_wc_sync_check(struct hdsp *hdsp)
|
2919 |
|
|
{
|
2920 |
|
|
int status2 = hdsp_read(hdsp, HDSP_status2Register);
|
2921 |
|
|
if (status2 & HDSP_wc_lock) {
|
2922 |
|
|
if (status2 & HDSP_wc_sync)
|
2923 |
|
|
return 2;
|
2924 |
|
|
else
|
2925 |
|
|
return 1;
|
2926 |
|
|
} else
|
2927 |
|
|
return 0;
|
2928 |
|
|
return 0;
|
2929 |
|
|
}
|
2930 |
|
|
|
2931 |
|
|
static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2932 |
|
|
{
|
2933 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2934 |
|
|
|
2935 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
|
2936 |
|
|
return 0;
|
2937 |
|
|
}
|
2938 |
|
|
|
2939 |
|
|
#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
|
2940 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2941 |
|
|
.name = xname, \
|
2942 |
|
|
.index = xindex, \
|
2943 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
|
2944 |
|
|
.info = snd_hdsp_info_sync_check, \
|
2945 |
|
|
.get = snd_hdsp_get_spdif_sync_check \
|
2946 |
|
|
}
|
2947 |
|
|
|
2948 |
|
|
static int hdsp_spdif_sync_check(struct hdsp *hdsp)
|
2949 |
|
|
{
|
2950 |
|
|
int status = hdsp_read(hdsp, HDSP_statusRegister);
|
2951 |
|
|
if (status & HDSP_SPDIFErrorFlag)
|
2952 |
|
|
return 0;
|
2953 |
|
|
else {
|
2954 |
|
|
if (status & HDSP_SPDIFSync)
|
2955 |
|
|
return 2;
|
2956 |
|
|
else
|
2957 |
|
|
return 1;
|
2958 |
|
|
}
|
2959 |
|
|
return 0;
|
2960 |
|
|
}
|
2961 |
|
|
|
2962 |
|
|
static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2963 |
|
|
{
|
2964 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2965 |
|
|
|
2966 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
|
2967 |
|
|
return 0;
|
2968 |
|
|
}
|
2969 |
|
|
|
2970 |
|
|
#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
|
2971 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
2972 |
|
|
.name = xname, \
|
2973 |
|
|
.index = xindex, \
|
2974 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
|
2975 |
|
|
.info = snd_hdsp_info_sync_check, \
|
2976 |
|
|
.get = snd_hdsp_get_adatsync_sync_check \
|
2977 |
|
|
}
|
2978 |
|
|
|
2979 |
|
|
static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
|
2980 |
|
|
{
|
2981 |
|
|
int status = hdsp_read(hdsp, HDSP_statusRegister);
|
2982 |
|
|
if (status & HDSP_TimecodeLock) {
|
2983 |
|
|
if (status & HDSP_TimecodeSync)
|
2984 |
|
|
return 2;
|
2985 |
|
|
else
|
2986 |
|
|
return 1;
|
2987 |
|
|
} else
|
2988 |
|
|
return 0;
|
2989 |
|
|
}
|
2990 |
|
|
|
2991 |
|
|
static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
2992 |
|
|
{
|
2993 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
2994 |
|
|
|
2995 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
|
2996 |
|
|
return 0;
|
2997 |
|
|
}
|
2998 |
|
|
|
2999 |
|
|
#define HDSP_ADAT_SYNC_CHECK \
|
3000 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
3001 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
|
3002 |
|
|
.info = snd_hdsp_info_sync_check, \
|
3003 |
|
|
.get = snd_hdsp_get_adat_sync_check \
|
3004 |
|
|
}
|
3005 |
|
|
|
3006 |
|
|
static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
|
3007 |
|
|
{
|
3008 |
|
|
int status = hdsp_read(hdsp, HDSP_statusRegister);
|
3009 |
|
|
|
3010 |
|
|
if (status & (HDSP_Lock0>>idx)) {
|
3011 |
|
|
if (status & (HDSP_Sync0>>idx))
|
3012 |
|
|
return 2;
|
3013 |
|
|
else
|
3014 |
|
|
return 1;
|
3015 |
|
|
} else
|
3016 |
|
|
return 0;
|
3017 |
|
|
}
|
3018 |
|
|
|
3019 |
|
|
static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
3020 |
|
|
{
|
3021 |
|
|
int offset;
|
3022 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
3023 |
|
|
|
3024 |
|
|
offset = ucontrol->id.index - 1;
|
3025 |
|
|
snd_assert(offset >= 0);
|
3026 |
|
|
|
3027 |
|
|
switch (hdsp->io_type) {
|
3028 |
|
|
case Digiface:
|
3029 |
|
|
case H9652:
|
3030 |
|
|
if (offset >= 3)
|
3031 |
|
|
return -EINVAL;
|
3032 |
|
|
break;
|
3033 |
|
|
case Multiface:
|
3034 |
|
|
case H9632:
|
3035 |
|
|
if (offset >= 1)
|
3036 |
|
|
return -EINVAL;
|
3037 |
|
|
break;
|
3038 |
|
|
default:
|
3039 |
|
|
return -EIO;
|
3040 |
|
|
}
|
3041 |
|
|
|
3042 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
|
3043 |
|
|
return 0;
|
3044 |
|
|
}
|
3045 |
|
|
|
3046 |
|
|
#define HDSP_DDS_OFFSET(xname, xindex) \
|
3047 |
|
|
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
3048 |
|
|
.name = xname, \
|
3049 |
|
|
.index = xindex, \
|
3050 |
|
|
.info = snd_hdsp_info_dds_offset, \
|
3051 |
|
|
.get = snd_hdsp_get_dds_offset, \
|
3052 |
|
|
.put = snd_hdsp_put_dds_offset \
|
3053 |
|
|
}
|
3054 |
|
|
|
3055 |
|
|
static int hdsp_dds_offset(struct hdsp *hdsp)
|
3056 |
|
|
{
|
3057 |
|
|
u64 n;
|
3058 |
|
|
u32 r;
|
3059 |
|
|
unsigned int dds_value = hdsp->dds_value;
|
3060 |
|
|
int system_sample_rate = hdsp->system_sample_rate;
|
3061 |
|
|
|
3062 |
|
|
if (!dds_value)
|
3063 |
|
|
return 0;
|
3064 |
|
|
|
3065 |
|
|
n = DDS_NUMERATOR;
|
3066 |
|
|
/*
|
3067 |
|
|
* dds_value = n / rate
|
3068 |
|
|
* rate = n / dds_value
|
3069 |
|
|
*/
|
3070 |
|
|
div64_32(&n, dds_value, &r);
|
3071 |
|
|
if (system_sample_rate >= 112000)
|
3072 |
|
|
n *= 4;
|
3073 |
|
|
else if (system_sample_rate >= 56000)
|
3074 |
|
|
n *= 2;
|
3075 |
|
|
return ((int)n) - system_sample_rate;
|
3076 |
|
|
}
|
3077 |
|
|
|
3078 |
|
|
static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
|
3079 |
|
|
{
|
3080 |
|
|
int rate = hdsp->system_sample_rate + offset_hz;
|
3081 |
|
|
hdsp_set_dds_value(hdsp, rate);
|
3082 |
|
|
return 0;
|
3083 |
|
|
}
|
3084 |
|
|
|
3085 |
|
|
static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
|
3086 |
|
|
{
|
3087 |
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
3088 |
|
|
uinfo->count = 1;
|
3089 |
|
|
uinfo->value.integer.min = -5000;
|
3090 |
|
|
uinfo->value.integer.max = 5000;
|
3091 |
|
|
return 0;
|
3092 |
|
|
}
|
3093 |
|
|
|
3094 |
|
|
static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
3095 |
|
|
{
|
3096 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
3097 |
|
|
|
3098 |
|
|
ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
|
3099 |
|
|
return 0;
|
3100 |
|
|
}
|
3101 |
|
|
|
3102 |
|
|
static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
|
3103 |
|
|
{
|
3104 |
|
|
struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
|
3105 |
|
|
int change;
|
3106 |
|
|
int val;
|
3107 |
|
|
|
3108 |
|
|
if (!snd_hdsp_use_is_exclusive(hdsp))
|
3109 |
|
|
return -EBUSY;
|
3110 |
|
|
val = ucontrol->value.enumerated.item[0];
|
3111 |
|
|
spin_lock_irq(&hdsp->lock);
|
3112 |
|
|
if (val != hdsp_dds_offset(hdsp))
|
3113 |
|
|
change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
|
3114 |
|
|
else
|
3115 |
|
|
change = 0;
|
3116 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3117 |
|
|
return change;
|
3118 |
|
|
}
|
3119 |
|
|
|
3120 |
|
|
static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
|
3121 |
|
|
HDSP_DA_GAIN("DA Gain", 0),
|
3122 |
|
|
HDSP_AD_GAIN("AD Gain", 0),
|
3123 |
|
|
HDSP_PHONE_GAIN("Phones Gain", 0),
|
3124 |
|
|
HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
|
3125 |
|
|
HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
|
3126 |
|
|
};
|
3127 |
|
|
|
3128 |
|
|
static struct snd_kcontrol_new snd_hdsp_controls[] = {
|
3129 |
|
|
{
|
3130 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
3131 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
|
3132 |
|
|
.info = snd_hdsp_control_spdif_info,
|
3133 |
|
|
.get = snd_hdsp_control_spdif_get,
|
3134 |
|
|
.put = snd_hdsp_control_spdif_put,
|
3135 |
|
|
},
|
3136 |
|
|
{
|
3137 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
|
3138 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
3139 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
|
3140 |
|
|
.info = snd_hdsp_control_spdif_stream_info,
|
3141 |
|
|
.get = snd_hdsp_control_spdif_stream_get,
|
3142 |
|
|
.put = snd_hdsp_control_spdif_stream_put,
|
3143 |
|
|
},
|
3144 |
|
|
{
|
3145 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ,
|
3146 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
3147 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
|
3148 |
|
|
.info = snd_hdsp_control_spdif_mask_info,
|
3149 |
|
|
.get = snd_hdsp_control_spdif_mask_get,
|
3150 |
|
|
.private_value = IEC958_AES0_NONAUDIO |
|
3151 |
|
|
IEC958_AES0_PROFESSIONAL |
|
3152 |
|
|
IEC958_AES0_CON_EMPHASIS,
|
3153 |
|
|
},
|
3154 |
|
|
{
|
3155 |
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READ,
|
3156 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
|
3157 |
|
|
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
|
3158 |
|
|
.info = snd_hdsp_control_spdif_mask_info,
|
3159 |
|
|
.get = snd_hdsp_control_spdif_mask_get,
|
3160 |
|
|
.private_value = IEC958_AES0_NONAUDIO |
|
3161 |
|
|
IEC958_AES0_PROFESSIONAL |
|
3162 |
|
|
IEC958_AES0_PRO_EMPHASIS,
|
3163 |
|
|
},
|
3164 |
|
|
HDSP_MIXER("Mixer", 0),
|
3165 |
|
|
HDSP_SPDIF_IN("IEC958 Input Connector", 0),
|
3166 |
|
|
HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
|
3167 |
|
|
HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
|
3168 |
|
|
HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
|
3169 |
|
|
HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
|
3170 |
|
|
/* 'Sample Clock Source' complies with the alsa control naming scheme */
|
3171 |
|
|
HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
|
3172 |
|
|
{
|
3173 |
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
|
3174 |
|
|
.name = "Sample Clock Source Locking",
|
3175 |
|
|
.info = snd_hdsp_info_clock_source_lock,
|
3176 |
|
|
.get = snd_hdsp_get_clock_source_lock,
|
3177 |
|
|
.put = snd_hdsp_put_clock_source_lock,
|
3178 |
|
|
},
|
3179 |
|
|
HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
|
3180 |
|
|
HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
|
3181 |
|
|
HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
|
3182 |
|
|
HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
|
3183 |
|
|
HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
|
3184 |
|
|
/* 'External Rate' complies with the alsa control naming scheme */
|
3185 |
|
|
HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
|
3186 |
|
|
HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
|
3187 |
|
|
HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
|
3188 |
|
|
HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
|
3189 |
|
|
HDSP_LINE_OUT("Line Out", 0),
|
3190 |
|
|
HDSP_PRECISE_POINTER("Precise Pointer", 0),
|
3191 |
|
|
HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
|
3192 |
|
|
};
|
3193 |
|
|
|
3194 |
|
|
static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
|
3195 |
|
|
static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
|
3196 |
|
|
|
3197 |
|
|
static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
|
3198 |
|
|
{
|
3199 |
|
|
unsigned int idx;
|
3200 |
|
|
int err;
|
3201 |
|
|
struct snd_kcontrol *kctl;
|
3202 |
|
|
|
3203 |
|
|
for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
|
3204 |
|
|
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
|
3205 |
|
|
return err;
|
3206 |
|
|
if (idx == 1) /* IEC958 (S/PDIF) Stream */
|
3207 |
|
|
hdsp->spdif_ctl = kctl;
|
3208 |
|
|
}
|
3209 |
|
|
|
3210 |
|
|
/* ADAT SyncCheck status */
|
3211 |
|
|
snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
|
3212 |
|
|
snd_hdsp_adat_sync_check.index = 1;
|
3213 |
|
|
if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
|
3214 |
|
|
return err;
|
3215 |
|
|
if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
|
3216 |
|
|
for (idx = 1; idx < 3; ++idx) {
|
3217 |
|
|
snd_hdsp_adat_sync_check.index = idx+1;
|
3218 |
|
|
if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
|
3219 |
|
|
return err;
|
3220 |
|
|
}
|
3221 |
|
|
}
|
3222 |
|
|
|
3223 |
|
|
/* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
|
3224 |
|
|
if (hdsp->io_type == H9632) {
|
3225 |
|
|
for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
|
3226 |
|
|
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
|
3227 |
|
|
return err;
|
3228 |
|
|
}
|
3229 |
|
|
}
|
3230 |
|
|
|
3231 |
|
|
/* AEB control for H96xx card */
|
3232 |
|
|
if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
|
3233 |
|
|
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
|
3234 |
|
|
return err;
|
3235 |
|
|
}
|
3236 |
|
|
|
3237 |
|
|
return 0;
|
3238 |
|
|
}
|
3239 |
|
|
|
3240 |
|
|
/*------------------------------------------------------------
|
3241 |
|
|
/proc interface
|
3242 |
|
|
------------------------------------------------------------*/
|
3243 |
|
|
|
3244 |
|
|
static void
|
3245 |
|
|
snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
|
3246 |
|
|
{
|
3247 |
|
|
struct hdsp *hdsp = (struct hdsp *) entry->private_data;
|
3248 |
|
|
unsigned int status;
|
3249 |
|
|
unsigned int status2;
|
3250 |
|
|
char *pref_sync_ref;
|
3251 |
|
|
char *autosync_ref;
|
3252 |
|
|
char *system_clock_mode;
|
3253 |
|
|
char *clock_source;
|
3254 |
|
|
int x;
|
3255 |
|
|
|
3256 |
|
|
if (hdsp_check_for_iobox (hdsp)) {
|
3257 |
|
|
snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
|
3258 |
|
|
return;
|
3259 |
|
|
}
|
3260 |
|
|
|
3261 |
|
|
if (hdsp_check_for_firmware(hdsp, 0)) {
|
3262 |
|
|
if (hdsp->state & HDSP_FirmwareCached) {
|
3263 |
|
|
if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
|
3264 |
|
|
snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
|
3265 |
|
|
return;
|
3266 |
|
|
}
|
3267 |
|
|
} else {
|
3268 |
|
|
int err = -EINVAL;
|
3269 |
|
|
#ifdef HDSP_FW_LOADER
|
3270 |
|
|
err = hdsp_request_fw_loader(hdsp);
|
3271 |
|
|
#endif
|
3272 |
|
|
if (err < 0) {
|
3273 |
|
|
snd_iprintf(buffer,
|
3274 |
|
|
"No firmware loaded nor cached, "
|
3275 |
|
|
"please upload firmware.\n");
|
3276 |
|
|
return;
|
3277 |
|
|
}
|
3278 |
|
|
}
|
3279 |
|
|
}
|
3280 |
|
|
|
3281 |
|
|
status = hdsp_read(hdsp, HDSP_statusRegister);
|
3282 |
|
|
status2 = hdsp_read(hdsp, HDSP_status2Register);
|
3283 |
|
|
|
3284 |
|
|
snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
|
3285 |
|
|
snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
|
3286 |
|
|
hdsp->capture_buffer, hdsp->playback_buffer);
|
3287 |
|
|
snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
|
3288 |
|
|
hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
|
3289 |
|
|
snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
|
3290 |
|
|
snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
|
3291 |
|
|
snd_iprintf(buffer, "Status register: 0x%x\n", status);
|
3292 |
|
|
snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
|
3293 |
|
|
snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
|
3294 |
|
|
snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
|
3295 |
|
|
snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
|
3296 |
|
|
snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
|
3297 |
|
|
snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
|
3298 |
|
|
snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
|
3299 |
|
|
|
3300 |
|
|
snd_iprintf(buffer, "\n");
|
3301 |
|
|
|
3302 |
|
|
x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
|
3303 |
|
|
|
3304 |
|
|
snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
|
3305 |
|
|
snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
|
3306 |
|
|
snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
|
3307 |
|
|
snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
|
3308 |
|
|
|
3309 |
|
|
snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
|
3310 |
|
|
|
3311 |
|
|
snd_iprintf(buffer, "\n");
|
3312 |
|
|
|
3313 |
|
|
|
3314 |
|
|
switch (hdsp_clock_source(hdsp)) {
|
3315 |
|
|
case HDSP_CLOCK_SOURCE_AUTOSYNC:
|
3316 |
|
|
clock_source = "AutoSync";
|
3317 |
|
|
break;
|
3318 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
|
3319 |
|
|
clock_source = "Internal 32 kHz";
|
3320 |
|
|
break;
|
3321 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
|
3322 |
|
|
clock_source = "Internal 44.1 kHz";
|
3323 |
|
|
break;
|
3324 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
|
3325 |
|
|
clock_source = "Internal 48 kHz";
|
3326 |
|
|
break;
|
3327 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
|
3328 |
|
|
clock_source = "Internal 64 kHz";
|
3329 |
|
|
break;
|
3330 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
|
3331 |
|
|
clock_source = "Internal 88.2 kHz";
|
3332 |
|
|
break;
|
3333 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
|
3334 |
|
|
clock_source = "Internal 96 kHz";
|
3335 |
|
|
break;
|
3336 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
|
3337 |
|
|
clock_source = "Internal 128 kHz";
|
3338 |
|
|
break;
|
3339 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
|
3340 |
|
|
clock_source = "Internal 176.4 kHz";
|
3341 |
|
|
break;
|
3342 |
|
|
case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
|
3343 |
|
|
clock_source = "Internal 192 kHz";
|
3344 |
|
|
break;
|
3345 |
|
|
default:
|
3346 |
|
|
clock_source = "Error";
|
3347 |
|
|
}
|
3348 |
|
|
snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
|
3349 |
|
|
|
3350 |
|
|
if (hdsp_system_clock_mode(hdsp))
|
3351 |
|
|
system_clock_mode = "Slave";
|
3352 |
|
|
else
|
3353 |
|
|
system_clock_mode = "Master";
|
3354 |
|
|
|
3355 |
|
|
switch (hdsp_pref_sync_ref (hdsp)) {
|
3356 |
|
|
case HDSP_SYNC_FROM_WORD:
|
3357 |
|
|
pref_sync_ref = "Word Clock";
|
3358 |
|
|
break;
|
3359 |
|
|
case HDSP_SYNC_FROM_ADAT_SYNC:
|
3360 |
|
|
pref_sync_ref = "ADAT Sync";
|
3361 |
|
|
break;
|
3362 |
|
|
case HDSP_SYNC_FROM_SPDIF:
|
3363 |
|
|
pref_sync_ref = "SPDIF";
|
3364 |
|
|
break;
|
3365 |
|
|
case HDSP_SYNC_FROM_ADAT1:
|
3366 |
|
|
pref_sync_ref = "ADAT1";
|
3367 |
|
|
break;
|
3368 |
|
|
case HDSP_SYNC_FROM_ADAT2:
|
3369 |
|
|
pref_sync_ref = "ADAT2";
|
3370 |
|
|
break;
|
3371 |
|
|
case HDSP_SYNC_FROM_ADAT3:
|
3372 |
|
|
pref_sync_ref = "ADAT3";
|
3373 |
|
|
break;
|
3374 |
|
|
default:
|
3375 |
|
|
pref_sync_ref = "Word Clock";
|
3376 |
|
|
break;
|
3377 |
|
|
}
|
3378 |
|
|
snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
|
3379 |
|
|
|
3380 |
|
|
switch (hdsp_autosync_ref (hdsp)) {
|
3381 |
|
|
case HDSP_AUTOSYNC_FROM_WORD:
|
3382 |
|
|
autosync_ref = "Word Clock";
|
3383 |
|
|
break;
|
3384 |
|
|
case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
|
3385 |
|
|
autosync_ref = "ADAT Sync";
|
3386 |
|
|
break;
|
3387 |
|
|
case HDSP_AUTOSYNC_FROM_SPDIF:
|
3388 |
|
|
autosync_ref = "SPDIF";
|
3389 |
|
|
break;
|
3390 |
|
|
case HDSP_AUTOSYNC_FROM_NONE:
|
3391 |
|
|
autosync_ref = "None";
|
3392 |
|
|
break;
|
3393 |
|
|
case HDSP_AUTOSYNC_FROM_ADAT1:
|
3394 |
|
|
autosync_ref = "ADAT1";
|
3395 |
|
|
break;
|
3396 |
|
|
case HDSP_AUTOSYNC_FROM_ADAT2:
|
3397 |
|
|
autosync_ref = "ADAT2";
|
3398 |
|
|
break;
|
3399 |
|
|
case HDSP_AUTOSYNC_FROM_ADAT3:
|
3400 |
|
|
autosync_ref = "ADAT3";
|
3401 |
|
|
break;
|
3402 |
|
|
default:
|
3403 |
|
|
autosync_ref = "---";
|
3404 |
|
|
break;
|
3405 |
|
|
}
|
3406 |
|
|
snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
|
3407 |
|
|
|
3408 |
|
|
snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
|
3409 |
|
|
|
3410 |
|
|
snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
|
3411 |
|
|
|
3412 |
|
|
snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
|
3413 |
|
|
snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
|
3414 |
|
|
|
3415 |
|
|
snd_iprintf(buffer, "\n");
|
3416 |
|
|
|
3417 |
|
|
switch (hdsp_spdif_in(hdsp)) {
|
3418 |
|
|
case HDSP_SPDIFIN_OPTICAL:
|
3419 |
|
|
snd_iprintf(buffer, "IEC958 input: Optical\n");
|
3420 |
|
|
break;
|
3421 |
|
|
case HDSP_SPDIFIN_COAXIAL:
|
3422 |
|
|
snd_iprintf(buffer, "IEC958 input: Coaxial\n");
|
3423 |
|
|
break;
|
3424 |
|
|
case HDSP_SPDIFIN_INTERNAL:
|
3425 |
|
|
snd_iprintf(buffer, "IEC958 input: Internal\n");
|
3426 |
|
|
break;
|
3427 |
|
|
case HDSP_SPDIFIN_AES:
|
3428 |
|
|
snd_iprintf(buffer, "IEC958 input: AES\n");
|
3429 |
|
|
break;
|
3430 |
|
|
default:
|
3431 |
|
|
snd_iprintf(buffer, "IEC958 input: ???\n");
|
3432 |
|
|
break;
|
3433 |
|
|
}
|
3434 |
|
|
|
3435 |
|
|
if (hdsp->control_register & HDSP_SPDIFOpticalOut)
|
3436 |
|
|
snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
|
3437 |
|
|
else
|
3438 |
|
|
snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
|
3439 |
|
|
|
3440 |
|
|
if (hdsp->control_register & HDSP_SPDIFProfessional)
|
3441 |
|
|
snd_iprintf(buffer, "IEC958 quality: Professional\n");
|
3442 |
|
|
else
|
3443 |
|
|
snd_iprintf(buffer, "IEC958 quality: Consumer\n");
|
3444 |
|
|
|
3445 |
|
|
if (hdsp->control_register & HDSP_SPDIFEmphasis)
|
3446 |
|
|
snd_iprintf(buffer, "IEC958 emphasis: on\n");
|
3447 |
|
|
else
|
3448 |
|
|
snd_iprintf(buffer, "IEC958 emphasis: off\n");
|
3449 |
|
|
|
3450 |
|
|
if (hdsp->control_register & HDSP_SPDIFNonAudio)
|
3451 |
|
|
snd_iprintf(buffer, "IEC958 NonAudio: on\n");
|
3452 |
|
|
else
|
3453 |
|
|
snd_iprintf(buffer, "IEC958 NonAudio: off\n");
|
3454 |
|
|
if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
|
3455 |
|
|
snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
|
3456 |
|
|
else
|
3457 |
|
|
snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
|
3458 |
|
|
|
3459 |
|
|
snd_iprintf(buffer, "\n");
|
3460 |
|
|
|
3461 |
|
|
/* Sync Check */
|
3462 |
|
|
x = status & HDSP_Sync0;
|
3463 |
|
|
if (status & HDSP_Lock0)
|
3464 |
|
|
snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
|
3465 |
|
|
else
|
3466 |
|
|
snd_iprintf(buffer, "ADAT1: No Lock\n");
|
3467 |
|
|
|
3468 |
|
|
switch (hdsp->io_type) {
|
3469 |
|
|
case Digiface:
|
3470 |
|
|
case H9652:
|
3471 |
|
|
x = status & HDSP_Sync1;
|
3472 |
|
|
if (status & HDSP_Lock1)
|
3473 |
|
|
snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
|
3474 |
|
|
else
|
3475 |
|
|
snd_iprintf(buffer, "ADAT2: No Lock\n");
|
3476 |
|
|
x = status & HDSP_Sync2;
|
3477 |
|
|
if (status & HDSP_Lock2)
|
3478 |
|
|
snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
|
3479 |
|
|
else
|
3480 |
|
|
snd_iprintf(buffer, "ADAT3: No Lock\n");
|
3481 |
|
|
break;
|
3482 |
|
|
default:
|
3483 |
|
|
/* relax */
|
3484 |
|
|
break;
|
3485 |
|
|
}
|
3486 |
|
|
|
3487 |
|
|
x = status & HDSP_SPDIFSync;
|
3488 |
|
|
if (status & HDSP_SPDIFErrorFlag)
|
3489 |
|
|
snd_iprintf (buffer, "SPDIF: No Lock\n");
|
3490 |
|
|
else
|
3491 |
|
|
snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
|
3492 |
|
|
|
3493 |
|
|
x = status2 & HDSP_wc_sync;
|
3494 |
|
|
if (status2 & HDSP_wc_lock)
|
3495 |
|
|
snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
|
3496 |
|
|
else
|
3497 |
|
|
snd_iprintf (buffer, "Word Clock: No Lock\n");
|
3498 |
|
|
|
3499 |
|
|
x = status & HDSP_TimecodeSync;
|
3500 |
|
|
if (status & HDSP_TimecodeLock)
|
3501 |
|
|
snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
|
3502 |
|
|
else
|
3503 |
|
|
snd_iprintf(buffer, "ADAT Sync: No Lock\n");
|
3504 |
|
|
|
3505 |
|
|
snd_iprintf(buffer, "\n");
|
3506 |
|
|
|
3507 |
|
|
/* Informations about H9632 specific controls */
|
3508 |
|
|
if (hdsp->io_type == H9632) {
|
3509 |
|
|
char *tmp;
|
3510 |
|
|
|
3511 |
|
|
switch (hdsp_ad_gain(hdsp)) {
|
3512 |
|
|
case 0:
|
3513 |
|
|
tmp = "-10 dBV";
|
3514 |
|
|
break;
|
3515 |
|
|
case 1:
|
3516 |
|
|
tmp = "+4 dBu";
|
3517 |
|
|
break;
|
3518 |
|
|
default:
|
3519 |
|
|
tmp = "Lo Gain";
|
3520 |
|
|
break;
|
3521 |
|
|
}
|
3522 |
|
|
snd_iprintf(buffer, "AD Gain : %s\n", tmp);
|
3523 |
|
|
|
3524 |
|
|
switch (hdsp_da_gain(hdsp)) {
|
3525 |
|
|
case 0:
|
3526 |
|
|
tmp = "Hi Gain";
|
3527 |
|
|
break;
|
3528 |
|
|
case 1:
|
3529 |
|
|
tmp = "+4 dBu";
|
3530 |
|
|
break;
|
3531 |
|
|
default:
|
3532 |
|
|
tmp = "-10 dBV";
|
3533 |
|
|
break;
|
3534 |
|
|
}
|
3535 |
|
|
snd_iprintf(buffer, "DA Gain : %s\n", tmp);
|
3536 |
|
|
|
3537 |
|
|
switch (hdsp_phone_gain(hdsp)) {
|
3538 |
|
|
case 0:
|
3539 |
|
|
tmp = "0 dB";
|
3540 |
|
|
break;
|
3541 |
|
|
case 1:
|
3542 |
|
|
tmp = "-6 dB";
|
3543 |
|
|
break;
|
3544 |
|
|
default:
|
3545 |
|
|
tmp = "-12 dB";
|
3546 |
|
|
break;
|
3547 |
|
|
}
|
3548 |
|
|
snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
|
3549 |
|
|
|
3550 |
|
|
snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
|
3551 |
|
|
|
3552 |
|
|
if (hdsp->control_register & HDSP_AnalogExtensionBoard)
|
3553 |
|
|
snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
|
3554 |
|
|
else
|
3555 |
|
|
snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
|
3556 |
|
|
snd_iprintf(buffer, "\n");
|
3557 |
|
|
}
|
3558 |
|
|
|
3559 |
|
|
}
|
3560 |
|
|
|
3561 |
|
|
static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp)
|
3562 |
|
|
{
|
3563 |
|
|
struct snd_info_entry *entry;
|
3564 |
|
|
|
3565 |
|
|
if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
|
3566 |
|
|
snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
|
3567 |
|
|
}
|
3568 |
|
|
|
3569 |
|
|
static void snd_hdsp_free_buffers(struct hdsp *hdsp)
|
3570 |
|
|
{
|
3571 |
|
|
snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
|
3572 |
|
|
snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
|
3573 |
|
|
}
|
3574 |
|
|
|
3575 |
|
|
static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
|
3576 |
|
|
{
|
3577 |
|
|
unsigned long pb_bus, cb_bus;
|
3578 |
|
|
|
3579 |
|
|
if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
|
3580 |
|
|
snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
|
3581 |
|
|
if (hdsp->capture_dma_buf.area)
|
3582 |
|
|
snd_dma_free_pages(&hdsp->capture_dma_buf);
|
3583 |
|
|
printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
|
3584 |
|
|
return -ENOMEM;
|
3585 |
|
|
}
|
3586 |
|
|
|
3587 |
|
|
/* Align to bus-space 64K boundary */
|
3588 |
|
|
|
3589 |
|
|
cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
|
3590 |
|
|
pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
|
3591 |
|
|
|
3592 |
|
|
/* Tell the card where it is */
|
3593 |
|
|
|
3594 |
|
|
hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
|
3595 |
|
|
hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
|
3596 |
|
|
|
3597 |
|
|
hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
|
3598 |
|
|
hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
|
3599 |
|
|
|
3600 |
|
|
return 0;
|
3601 |
|
|
}
|
3602 |
|
|
|
3603 |
|
|
static int snd_hdsp_set_defaults(struct hdsp *hdsp)
|
3604 |
|
|
{
|
3605 |
|
|
unsigned int i;
|
3606 |
|
|
|
3607 |
|
|
/* ASSUMPTION: hdsp->lock is either held, or
|
3608 |
|
|
there is no need to hold it (e.g. during module
|
3609 |
|
|
initalization).
|
3610 |
|
|
*/
|
3611 |
|
|
|
3612 |
|
|
/* set defaults:
|
3613 |
|
|
|
3614 |
|
|
SPDIF Input via Coax
|
3615 |
|
|
Master clock mode
|
3616 |
|
|
maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
|
3617 |
|
|
which implies 2 4096 sample, 32Kbyte periods).
|
3618 |
|
|
Enable line out.
|
3619 |
|
|
*/
|
3620 |
|
|
|
3621 |
|
|
hdsp->control_register = HDSP_ClockModeMaster |
|
3622 |
|
|
HDSP_SPDIFInputCoaxial |
|
3623 |
|
|
hdsp_encode_latency(7) |
|
3624 |
|
|
HDSP_LineOut;
|
3625 |
|
|
|
3626 |
|
|
|
3627 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
3628 |
|
|
|
3629 |
|
|
#ifdef SNDRV_BIG_ENDIAN
|
3630 |
|
|
hdsp->control2_register = HDSP_BIGENDIAN_MODE;
|
3631 |
|
|
#else
|
3632 |
|
|
hdsp->control2_register = 0;
|
3633 |
|
|
#endif
|
3634 |
|
|
if (hdsp->io_type == H9652)
|
3635 |
|
|
snd_hdsp_9652_enable_mixer (hdsp);
|
3636 |
|
|
else
|
3637 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
|
3638 |
|
|
|
3639 |
|
|
hdsp_reset_hw_pointer(hdsp);
|
3640 |
|
|
hdsp_compute_period_size(hdsp);
|
3641 |
|
|
|
3642 |
|
|
/* silence everything */
|
3643 |
|
|
|
3644 |
|
|
for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
|
3645 |
|
|
hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
|
3646 |
|
|
|
3647 |
|
|
for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
|
3648 |
|
|
if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
|
3649 |
|
|
return -EIO;
|
3650 |
|
|
}
|
3651 |
|
|
|
3652 |
|
|
/* H9632 specific defaults */
|
3653 |
|
|
if (hdsp->io_type == H9632) {
|
3654 |
|
|
hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
|
3655 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
3656 |
|
|
}
|
3657 |
|
|
|
3658 |
|
|
/* set a default rate so that the channel map is set up.
|
3659 |
|
|
*/
|
3660 |
|
|
|
3661 |
|
|
hdsp_set_rate(hdsp, 48000, 1);
|
3662 |
|
|
|
3663 |
|
|
return 0;
|
3664 |
|
|
}
|
3665 |
|
|
|
3666 |
|
|
static void hdsp_midi_tasklet(unsigned long arg)
|
3667 |
|
|
{
|
3668 |
|
|
struct hdsp *hdsp = (struct hdsp *)arg;
|
3669 |
|
|
|
3670 |
|
|
if (hdsp->midi[0].pending)
|
3671 |
|
|
snd_hdsp_midi_input_read (&hdsp->midi[0]);
|
3672 |
|
|
if (hdsp->midi[1].pending)
|
3673 |
|
|
snd_hdsp_midi_input_read (&hdsp->midi[1]);
|
3674 |
|
|
}
|
3675 |
|
|
|
3676 |
|
|
static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
|
3677 |
|
|
{
|
3678 |
|
|
struct hdsp *hdsp = (struct hdsp *) dev_id;
|
3679 |
|
|
unsigned int status;
|
3680 |
|
|
int audio;
|
3681 |
|
|
int midi0;
|
3682 |
|
|
int midi1;
|
3683 |
|
|
unsigned int midi0status;
|
3684 |
|
|
unsigned int midi1status;
|
3685 |
|
|
int schedule = 0;
|
3686 |
|
|
|
3687 |
|
|
status = hdsp_read(hdsp, HDSP_statusRegister);
|
3688 |
|
|
|
3689 |
|
|
audio = status & HDSP_audioIRQPending;
|
3690 |
|
|
midi0 = status & HDSP_midi0IRQPending;
|
3691 |
|
|
midi1 = status & HDSP_midi1IRQPending;
|
3692 |
|
|
|
3693 |
|
|
if (!audio && !midi0 && !midi1)
|
3694 |
|
|
return IRQ_NONE;
|
3695 |
|
|
|
3696 |
|
|
hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
|
3697 |
|
|
|
3698 |
|
|
midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
|
3699 |
|
|
midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
|
3700 |
|
|
|
3701 |
|
|
if (audio) {
|
3702 |
|
|
if (hdsp->capture_substream)
|
3703 |
|
|
snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
|
3704 |
|
|
|
3705 |
|
|
if (hdsp->playback_substream)
|
3706 |
|
|
snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
|
3707 |
|
|
}
|
3708 |
|
|
|
3709 |
|
|
if (midi0 && midi0status) {
|
3710 |
|
|
if (hdsp->use_midi_tasklet) {
|
3711 |
|
|
/* we disable interrupts for this input until processing is done */
|
3712 |
|
|
hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
|
3713 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
3714 |
|
|
hdsp->midi[0].pending = 1;
|
3715 |
|
|
schedule = 1;
|
3716 |
|
|
} else {
|
3717 |
|
|
snd_hdsp_midi_input_read (&hdsp->midi[0]);
|
3718 |
|
|
}
|
3719 |
|
|
}
|
3720 |
|
|
if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
|
3721 |
|
|
if (hdsp->use_midi_tasklet) {
|
3722 |
|
|
/* we disable interrupts for this input until processing is done */
|
3723 |
|
|
hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
|
3724 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
|
3725 |
|
|
hdsp->midi[1].pending = 1;
|
3726 |
|
|
schedule = 1;
|
3727 |
|
|
} else {
|
3728 |
|
|
snd_hdsp_midi_input_read (&hdsp->midi[1]);
|
3729 |
|
|
}
|
3730 |
|
|
}
|
3731 |
|
|
if (hdsp->use_midi_tasklet && schedule)
|
3732 |
|
|
tasklet_hi_schedule(&hdsp->midi_tasklet);
|
3733 |
|
|
return IRQ_HANDLED;
|
3734 |
|
|
}
|
3735 |
|
|
|
3736 |
|
|
static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
|
3737 |
|
|
{
|
3738 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3739 |
|
|
return hdsp_hw_pointer(hdsp);
|
3740 |
|
|
}
|
3741 |
|
|
|
3742 |
|
|
static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
|
3743 |
|
|
int stream,
|
3744 |
|
|
int channel)
|
3745 |
|
|
|
3746 |
|
|
{
|
3747 |
|
|
int mapped_channel;
|
3748 |
|
|
|
3749 |
|
|
snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
|
3750 |
|
|
|
3751 |
|
|
if ((mapped_channel = hdsp->channel_map[channel]) < 0)
|
3752 |
|
|
return NULL;
|
3753 |
|
|
|
3754 |
|
|
if (stream == SNDRV_PCM_STREAM_CAPTURE)
|
3755 |
|
|
return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
|
3756 |
|
|
else
|
3757 |
|
|
return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
|
3758 |
|
|
}
|
3759 |
|
|
|
3760 |
|
|
static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
|
3761 |
|
|
snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
|
3762 |
|
|
{
|
3763 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3764 |
|
|
char *channel_buf;
|
3765 |
|
|
|
3766 |
|
|
snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
|
3767 |
|
|
|
3768 |
|
|
channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
|
3769 |
|
|
snd_assert(channel_buf != NULL, return -EIO);
|
3770 |
|
|
if (copy_from_user(channel_buf + pos * 4, src, count * 4))
|
3771 |
|
|
return -EFAULT;
|
3772 |
|
|
return count;
|
3773 |
|
|
}
|
3774 |
|
|
|
3775 |
|
|
static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
|
3776 |
|
|
snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
|
3777 |
|
|
{
|
3778 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3779 |
|
|
char *channel_buf;
|
3780 |
|
|
|
3781 |
|
|
snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
|
3782 |
|
|
|
3783 |
|
|
channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
|
3784 |
|
|
snd_assert(channel_buf != NULL, return -EIO);
|
3785 |
|
|
if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
|
3786 |
|
|
return -EFAULT;
|
3787 |
|
|
return count;
|
3788 |
|
|
}
|
3789 |
|
|
|
3790 |
|
|
static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
|
3791 |
|
|
snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
|
3792 |
|
|
{
|
3793 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3794 |
|
|
char *channel_buf;
|
3795 |
|
|
|
3796 |
|
|
channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
|
3797 |
|
|
snd_assert(channel_buf != NULL, return -EIO);
|
3798 |
|
|
memset(channel_buf + pos * 4, 0, count * 4);
|
3799 |
|
|
return count;
|
3800 |
|
|
}
|
3801 |
|
|
|
3802 |
|
|
static int snd_hdsp_reset(struct snd_pcm_substream *substream)
|
3803 |
|
|
{
|
3804 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
3805 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3806 |
|
|
struct snd_pcm_substream *other;
|
3807 |
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
3808 |
|
|
other = hdsp->capture_substream;
|
3809 |
|
|
else
|
3810 |
|
|
other = hdsp->playback_substream;
|
3811 |
|
|
if (hdsp->running)
|
3812 |
|
|
runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
|
3813 |
|
|
else
|
3814 |
|
|
runtime->status->hw_ptr = 0;
|
3815 |
|
|
if (other) {
|
3816 |
|
|
struct snd_pcm_substream *s;
|
3817 |
|
|
struct snd_pcm_runtime *oruntime = other->runtime;
|
3818 |
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
3819 |
|
|
if (s == other) {
|
3820 |
|
|
oruntime->status->hw_ptr = runtime->status->hw_ptr;
|
3821 |
|
|
break;
|
3822 |
|
|
}
|
3823 |
|
|
}
|
3824 |
|
|
}
|
3825 |
|
|
return 0;
|
3826 |
|
|
}
|
3827 |
|
|
|
3828 |
|
|
static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
|
3829 |
|
|
struct snd_pcm_hw_params *params)
|
3830 |
|
|
{
|
3831 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3832 |
|
|
int err;
|
3833 |
|
|
pid_t this_pid;
|
3834 |
|
|
pid_t other_pid;
|
3835 |
|
|
|
3836 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
3837 |
|
|
return -EIO;
|
3838 |
|
|
|
3839 |
|
|
if (hdsp_check_for_firmware(hdsp, 1))
|
3840 |
|
|
return -EIO;
|
3841 |
|
|
|
3842 |
|
|
spin_lock_irq(&hdsp->lock);
|
3843 |
|
|
|
3844 |
|
|
if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
3845 |
|
|
hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
|
3846 |
|
|
hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
|
3847 |
|
|
this_pid = hdsp->playback_pid;
|
3848 |
|
|
other_pid = hdsp->capture_pid;
|
3849 |
|
|
} else {
|
3850 |
|
|
this_pid = hdsp->capture_pid;
|
3851 |
|
|
other_pid = hdsp->playback_pid;
|
3852 |
|
|
}
|
3853 |
|
|
|
3854 |
|
|
if ((other_pid > 0) && (this_pid != other_pid)) {
|
3855 |
|
|
|
3856 |
|
|
/* The other stream is open, and not by the same
|
3857 |
|
|
task as this one. Make sure that the parameters
|
3858 |
|
|
that matter are the same.
|
3859 |
|
|
*/
|
3860 |
|
|
|
3861 |
|
|
if (params_rate(params) != hdsp->system_sample_rate) {
|
3862 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3863 |
|
|
_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
|
3864 |
|
|
return -EBUSY;
|
3865 |
|
|
}
|
3866 |
|
|
|
3867 |
|
|
if (params_period_size(params) != hdsp->period_bytes / 4) {
|
3868 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3869 |
|
|
_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
|
3870 |
|
|
return -EBUSY;
|
3871 |
|
|
}
|
3872 |
|
|
|
3873 |
|
|
/* We're fine. */
|
3874 |
|
|
|
3875 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3876 |
|
|
return 0;
|
3877 |
|
|
|
3878 |
|
|
} else {
|
3879 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3880 |
|
|
}
|
3881 |
|
|
|
3882 |
|
|
/* how to make sure that the rate matches an externally-set one ?
|
3883 |
|
|
*/
|
3884 |
|
|
|
3885 |
|
|
spin_lock_irq(&hdsp->lock);
|
3886 |
|
|
if (! hdsp->clock_source_locked) {
|
3887 |
|
|
if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
|
3888 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3889 |
|
|
_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
|
3890 |
|
|
return err;
|
3891 |
|
|
}
|
3892 |
|
|
}
|
3893 |
|
|
spin_unlock_irq(&hdsp->lock);
|
3894 |
|
|
|
3895 |
|
|
if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
|
3896 |
|
|
_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
|
3897 |
|
|
return err;
|
3898 |
|
|
}
|
3899 |
|
|
|
3900 |
|
|
return 0;
|
3901 |
|
|
}
|
3902 |
|
|
|
3903 |
|
|
static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
|
3904 |
|
|
struct snd_pcm_channel_info *info)
|
3905 |
|
|
{
|
3906 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3907 |
|
|
int mapped_channel;
|
3908 |
|
|
|
3909 |
|
|
snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
|
3910 |
|
|
|
3911 |
|
|
if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
|
3912 |
|
|
return -EINVAL;
|
3913 |
|
|
|
3914 |
|
|
info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
|
3915 |
|
|
info->first = 0;
|
3916 |
|
|
info->step = 32;
|
3917 |
|
|
return 0;
|
3918 |
|
|
}
|
3919 |
|
|
|
3920 |
|
|
static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
|
3921 |
|
|
unsigned int cmd, void *arg)
|
3922 |
|
|
{
|
3923 |
|
|
switch (cmd) {
|
3924 |
|
|
case SNDRV_PCM_IOCTL1_RESET:
|
3925 |
|
|
return snd_hdsp_reset(substream);
|
3926 |
|
|
case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
|
3927 |
|
|
return snd_hdsp_channel_info(substream, arg);
|
3928 |
|
|
default:
|
3929 |
|
|
break;
|
3930 |
|
|
}
|
3931 |
|
|
|
3932 |
|
|
return snd_pcm_lib_ioctl(substream, cmd, arg);
|
3933 |
|
|
}
|
3934 |
|
|
|
3935 |
|
|
static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
|
3936 |
|
|
{
|
3937 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
3938 |
|
|
struct snd_pcm_substream *other;
|
3939 |
|
|
int running;
|
3940 |
|
|
|
3941 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
3942 |
|
|
return -EIO;
|
3943 |
|
|
|
3944 |
|
|
if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
|
3945 |
|
|
return -EIO;
|
3946 |
|
|
|
3947 |
|
|
spin_lock(&hdsp->lock);
|
3948 |
|
|
running = hdsp->running;
|
3949 |
|
|
switch (cmd) {
|
3950 |
|
|
case SNDRV_PCM_TRIGGER_START:
|
3951 |
|
|
running |= 1 << substream->stream;
|
3952 |
|
|
break;
|
3953 |
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
3954 |
|
|
running &= ~(1 << substream->stream);
|
3955 |
|
|
break;
|
3956 |
|
|
default:
|
3957 |
|
|
snd_BUG();
|
3958 |
|
|
spin_unlock(&hdsp->lock);
|
3959 |
|
|
return -EINVAL;
|
3960 |
|
|
}
|
3961 |
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
3962 |
|
|
other = hdsp->capture_substream;
|
3963 |
|
|
else
|
3964 |
|
|
other = hdsp->playback_substream;
|
3965 |
|
|
|
3966 |
|
|
if (other) {
|
3967 |
|
|
struct snd_pcm_substream *s;
|
3968 |
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
3969 |
|
|
if (s == other) {
|
3970 |
|
|
snd_pcm_trigger_done(s, substream);
|
3971 |
|
|
if (cmd == SNDRV_PCM_TRIGGER_START)
|
3972 |
|
|
running |= 1 << s->stream;
|
3973 |
|
|
else
|
3974 |
|
|
running &= ~(1 << s->stream);
|
3975 |
|
|
goto _ok;
|
3976 |
|
|
}
|
3977 |
|
|
}
|
3978 |
|
|
if (cmd == SNDRV_PCM_TRIGGER_START) {
|
3979 |
|
|
if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
|
3980 |
|
|
substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
3981 |
|
|
hdsp_silence_playback(hdsp);
|
3982 |
|
|
} else {
|
3983 |
|
|
if (running &&
|
3984 |
|
|
substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
3985 |
|
|
hdsp_silence_playback(hdsp);
|
3986 |
|
|
}
|
3987 |
|
|
} else {
|
3988 |
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
3989 |
|
|
hdsp_silence_playback(hdsp);
|
3990 |
|
|
}
|
3991 |
|
|
_ok:
|
3992 |
|
|
snd_pcm_trigger_done(substream, substream);
|
3993 |
|
|
if (!hdsp->running && running)
|
3994 |
|
|
hdsp_start_audio(hdsp);
|
3995 |
|
|
else if (hdsp->running && !running)
|
3996 |
|
|
hdsp_stop_audio(hdsp);
|
3997 |
|
|
hdsp->running = running;
|
3998 |
|
|
spin_unlock(&hdsp->lock);
|
3999 |
|
|
|
4000 |
|
|
return 0;
|
4001 |
|
|
}
|
4002 |
|
|
|
4003 |
|
|
static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
|
4004 |
|
|
{
|
4005 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
4006 |
|
|
int result = 0;
|
4007 |
|
|
|
4008 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
4009 |
|
|
return -EIO;
|
4010 |
|
|
|
4011 |
|
|
if (hdsp_check_for_firmware(hdsp, 1))
|
4012 |
|
|
return -EIO;
|
4013 |
|
|
|
4014 |
|
|
spin_lock_irq(&hdsp->lock);
|
4015 |
|
|
if (!hdsp->running)
|
4016 |
|
|
hdsp_reset_hw_pointer(hdsp);
|
4017 |
|
|
spin_unlock_irq(&hdsp->lock);
|
4018 |
|
|
return result;
|
4019 |
|
|
}
|
4020 |
|
|
|
4021 |
|
|
static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
|
4022 |
|
|
{
|
4023 |
|
|
.info = (SNDRV_PCM_INFO_MMAP |
|
4024 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
4025 |
|
|
SNDRV_PCM_INFO_NONINTERLEAVED |
|
4026 |
|
|
SNDRV_PCM_INFO_SYNC_START |
|
4027 |
|
|
SNDRV_PCM_INFO_DOUBLE),
|
4028 |
|
|
#ifdef SNDRV_BIG_ENDIAN
|
4029 |
|
|
.formats = SNDRV_PCM_FMTBIT_S32_BE,
|
4030 |
|
|
#else
|
4031 |
|
|
.formats = SNDRV_PCM_FMTBIT_S32_LE,
|
4032 |
|
|
#endif
|
4033 |
|
|
.rates = (SNDRV_PCM_RATE_32000 |
|
4034 |
|
|
SNDRV_PCM_RATE_44100 |
|
4035 |
|
|
SNDRV_PCM_RATE_48000 |
|
4036 |
|
|
SNDRV_PCM_RATE_64000 |
|
4037 |
|
|
SNDRV_PCM_RATE_88200 |
|
4038 |
|
|
SNDRV_PCM_RATE_96000),
|
4039 |
|
|
.rate_min = 32000,
|
4040 |
|
|
.rate_max = 96000,
|
4041 |
|
|
.channels_min = 14,
|
4042 |
|
|
.channels_max = HDSP_MAX_CHANNELS,
|
4043 |
|
|
.buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
|
4044 |
|
|
.period_bytes_min = (64 * 4) * 10,
|
4045 |
|
|
.period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
|
4046 |
|
|
.periods_min = 2,
|
4047 |
|
|
.periods_max = 2,
|
4048 |
|
|
.fifo_size = 0
|
4049 |
|
|
};
|
4050 |
|
|
|
4051 |
|
|
static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
|
4052 |
|
|
{
|
4053 |
|
|
.info = (SNDRV_PCM_INFO_MMAP |
|
4054 |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
4055 |
|
|
SNDRV_PCM_INFO_NONINTERLEAVED |
|
4056 |
|
|
SNDRV_PCM_INFO_SYNC_START),
|
4057 |
|
|
#ifdef SNDRV_BIG_ENDIAN
|
4058 |
|
|
.formats = SNDRV_PCM_FMTBIT_S32_BE,
|
4059 |
|
|
#else
|
4060 |
|
|
.formats = SNDRV_PCM_FMTBIT_S32_LE,
|
4061 |
|
|
#endif
|
4062 |
|
|
.rates = (SNDRV_PCM_RATE_32000 |
|
4063 |
|
|
SNDRV_PCM_RATE_44100 |
|
4064 |
|
|
SNDRV_PCM_RATE_48000 |
|
4065 |
|
|
SNDRV_PCM_RATE_64000 |
|
4066 |
|
|
SNDRV_PCM_RATE_88200 |
|
4067 |
|
|
SNDRV_PCM_RATE_96000),
|
4068 |
|
|
.rate_min = 32000,
|
4069 |
|
|
.rate_max = 96000,
|
4070 |
|
|
.channels_min = 14,
|
4071 |
|
|
.channels_max = HDSP_MAX_CHANNELS,
|
4072 |
|
|
.buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
|
4073 |
|
|
.period_bytes_min = (64 * 4) * 10,
|
4074 |
|
|
.period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
|
4075 |
|
|
.periods_min = 2,
|
4076 |
|
|
.periods_max = 2,
|
4077 |
|
|
.fifo_size = 0
|
4078 |
|
|
};
|
4079 |
|
|
|
4080 |
|
|
static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
|
4081 |
|
|
|
4082 |
|
|
static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
|
4083 |
|
|
.count = ARRAY_SIZE(hdsp_period_sizes),
|
4084 |
|
|
.list = hdsp_period_sizes,
|
4085 |
|
|
.mask = 0
|
4086 |
|
|
};
|
4087 |
|
|
|
4088 |
|
|
static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
|
4089 |
|
|
|
4090 |
|
|
static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
|
4091 |
|
|
.count = ARRAY_SIZE(hdsp_9632_sample_rates),
|
4092 |
|
|
.list = hdsp_9632_sample_rates,
|
4093 |
|
|
.mask = 0
|
4094 |
|
|
};
|
4095 |
|
|
|
4096 |
|
|
static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
|
4097 |
|
|
struct snd_pcm_hw_rule *rule)
|
4098 |
|
|
{
|
4099 |
|
|
struct hdsp *hdsp = rule->private;
|
4100 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4101 |
|
|
if (hdsp->io_type == H9632) {
|
4102 |
|
|
unsigned int list[3];
|
4103 |
|
|
list[0] = hdsp->qs_in_channels;
|
4104 |
|
|
list[1] = hdsp->ds_in_channels;
|
4105 |
|
|
list[2] = hdsp->ss_in_channels;
|
4106 |
|
|
return snd_interval_list(c, 3, list, 0);
|
4107 |
|
|
} else {
|
4108 |
|
|
unsigned int list[2];
|
4109 |
|
|
list[0] = hdsp->ds_in_channels;
|
4110 |
|
|
list[1] = hdsp->ss_in_channels;
|
4111 |
|
|
return snd_interval_list(c, 2, list, 0);
|
4112 |
|
|
}
|
4113 |
|
|
}
|
4114 |
|
|
|
4115 |
|
|
static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
|
4116 |
|
|
struct snd_pcm_hw_rule *rule)
|
4117 |
|
|
{
|
4118 |
|
|
unsigned int list[3];
|
4119 |
|
|
struct hdsp *hdsp = rule->private;
|
4120 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4121 |
|
|
if (hdsp->io_type == H9632) {
|
4122 |
|
|
list[0] = hdsp->qs_out_channels;
|
4123 |
|
|
list[1] = hdsp->ds_out_channels;
|
4124 |
|
|
list[2] = hdsp->ss_out_channels;
|
4125 |
|
|
return snd_interval_list(c, 3, list, 0);
|
4126 |
|
|
} else {
|
4127 |
|
|
list[0] = hdsp->ds_out_channels;
|
4128 |
|
|
list[1] = hdsp->ss_out_channels;
|
4129 |
|
|
}
|
4130 |
|
|
return snd_interval_list(c, 2, list, 0);
|
4131 |
|
|
}
|
4132 |
|
|
|
4133 |
|
|
static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
|
4134 |
|
|
struct snd_pcm_hw_rule *rule)
|
4135 |
|
|
{
|
4136 |
|
|
struct hdsp *hdsp = rule->private;
|
4137 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4138 |
|
|
struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
|
4139 |
|
|
if (r->min > 96000 && hdsp->io_type == H9632) {
|
4140 |
|
|
struct snd_interval t = {
|
4141 |
|
|
.min = hdsp->qs_in_channels,
|
4142 |
|
|
.max = hdsp->qs_in_channels,
|
4143 |
|
|
.integer = 1,
|
4144 |
|
|
};
|
4145 |
|
|
return snd_interval_refine(c, &t);
|
4146 |
|
|
} else if (r->min > 48000 && r->max <= 96000) {
|
4147 |
|
|
struct snd_interval t = {
|
4148 |
|
|
.min = hdsp->ds_in_channels,
|
4149 |
|
|
.max = hdsp->ds_in_channels,
|
4150 |
|
|
.integer = 1,
|
4151 |
|
|
};
|
4152 |
|
|
return snd_interval_refine(c, &t);
|
4153 |
|
|
} else if (r->max < 64000) {
|
4154 |
|
|
struct snd_interval t = {
|
4155 |
|
|
.min = hdsp->ss_in_channels,
|
4156 |
|
|
.max = hdsp->ss_in_channels,
|
4157 |
|
|
.integer = 1,
|
4158 |
|
|
};
|
4159 |
|
|
return snd_interval_refine(c, &t);
|
4160 |
|
|
}
|
4161 |
|
|
return 0;
|
4162 |
|
|
}
|
4163 |
|
|
|
4164 |
|
|
static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
|
4165 |
|
|
struct snd_pcm_hw_rule *rule)
|
4166 |
|
|
{
|
4167 |
|
|
struct hdsp *hdsp = rule->private;
|
4168 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4169 |
|
|
struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
|
4170 |
|
|
if (r->min > 96000 && hdsp->io_type == H9632) {
|
4171 |
|
|
struct snd_interval t = {
|
4172 |
|
|
.min = hdsp->qs_out_channels,
|
4173 |
|
|
.max = hdsp->qs_out_channels,
|
4174 |
|
|
.integer = 1,
|
4175 |
|
|
};
|
4176 |
|
|
return snd_interval_refine(c, &t);
|
4177 |
|
|
} else if (r->min > 48000 && r->max <= 96000) {
|
4178 |
|
|
struct snd_interval t = {
|
4179 |
|
|
.min = hdsp->ds_out_channels,
|
4180 |
|
|
.max = hdsp->ds_out_channels,
|
4181 |
|
|
.integer = 1,
|
4182 |
|
|
};
|
4183 |
|
|
return snd_interval_refine(c, &t);
|
4184 |
|
|
} else if (r->max < 64000) {
|
4185 |
|
|
struct snd_interval t = {
|
4186 |
|
|
.min = hdsp->ss_out_channels,
|
4187 |
|
|
.max = hdsp->ss_out_channels,
|
4188 |
|
|
.integer = 1,
|
4189 |
|
|
};
|
4190 |
|
|
return snd_interval_refine(c, &t);
|
4191 |
|
|
}
|
4192 |
|
|
return 0;
|
4193 |
|
|
}
|
4194 |
|
|
|
4195 |
|
|
static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
|
4196 |
|
|
struct snd_pcm_hw_rule *rule)
|
4197 |
|
|
{
|
4198 |
|
|
struct hdsp *hdsp = rule->private;
|
4199 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4200 |
|
|
struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
|
4201 |
|
|
if (c->min >= hdsp->ss_out_channels) {
|
4202 |
|
|
struct snd_interval t = {
|
4203 |
|
|
.min = 32000,
|
4204 |
|
|
.max = 48000,
|
4205 |
|
|
.integer = 1,
|
4206 |
|
|
};
|
4207 |
|
|
return snd_interval_refine(r, &t);
|
4208 |
|
|
} else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
|
4209 |
|
|
struct snd_interval t = {
|
4210 |
|
|
.min = 128000,
|
4211 |
|
|
.max = 192000,
|
4212 |
|
|
.integer = 1,
|
4213 |
|
|
};
|
4214 |
|
|
return snd_interval_refine(r, &t);
|
4215 |
|
|
} else if (c->max <= hdsp->ds_out_channels) {
|
4216 |
|
|
struct snd_interval t = {
|
4217 |
|
|
.min = 64000,
|
4218 |
|
|
.max = 96000,
|
4219 |
|
|
.integer = 1,
|
4220 |
|
|
};
|
4221 |
|
|
return snd_interval_refine(r, &t);
|
4222 |
|
|
}
|
4223 |
|
|
return 0;
|
4224 |
|
|
}
|
4225 |
|
|
|
4226 |
|
|
static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
|
4227 |
|
|
struct snd_pcm_hw_rule *rule)
|
4228 |
|
|
{
|
4229 |
|
|
struct hdsp *hdsp = rule->private;
|
4230 |
|
|
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
|
4231 |
|
|
struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
|
4232 |
|
|
if (c->min >= hdsp->ss_in_channels) {
|
4233 |
|
|
struct snd_interval t = {
|
4234 |
|
|
.min = 32000,
|
4235 |
|
|
.max = 48000,
|
4236 |
|
|
.integer = 1,
|
4237 |
|
|
};
|
4238 |
|
|
return snd_interval_refine(r, &t);
|
4239 |
|
|
} else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
|
4240 |
|
|
struct snd_interval t = {
|
4241 |
|
|
.min = 128000,
|
4242 |
|
|
.max = 192000,
|
4243 |
|
|
.integer = 1,
|
4244 |
|
|
};
|
4245 |
|
|
return snd_interval_refine(r, &t);
|
4246 |
|
|
} else if (c->max <= hdsp->ds_in_channels) {
|
4247 |
|
|
struct snd_interval t = {
|
4248 |
|
|
.min = 64000,
|
4249 |
|
|
.max = 96000,
|
4250 |
|
|
.integer = 1,
|
4251 |
|
|
};
|
4252 |
|
|
return snd_interval_refine(r, &t);
|
4253 |
|
|
}
|
4254 |
|
|
return 0;
|
4255 |
|
|
}
|
4256 |
|
|
|
4257 |
|
|
static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
|
4258 |
|
|
{
|
4259 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
4260 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
4261 |
|
|
|
4262 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
4263 |
|
|
return -EIO;
|
4264 |
|
|
|
4265 |
|
|
if (hdsp_check_for_firmware(hdsp, 1))
|
4266 |
|
|
return -EIO;
|
4267 |
|
|
|
4268 |
|
|
spin_lock_irq(&hdsp->lock);
|
4269 |
|
|
|
4270 |
|
|
snd_pcm_set_sync(substream);
|
4271 |
|
|
|
4272 |
|
|
runtime->hw = snd_hdsp_playback_subinfo;
|
4273 |
|
|
runtime->dma_area = hdsp->playback_buffer;
|
4274 |
|
|
runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
|
4275 |
|
|
|
4276 |
|
|
hdsp->playback_pid = current->pid;
|
4277 |
|
|
hdsp->playback_substream = substream;
|
4278 |
|
|
|
4279 |
|
|
spin_unlock_irq(&hdsp->lock);
|
4280 |
|
|
|
4281 |
|
|
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
|
4282 |
|
|
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
|
4283 |
|
|
if (hdsp->clock_source_locked) {
|
4284 |
|
|
runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
|
4285 |
|
|
} else if (hdsp->io_type == H9632) {
|
4286 |
|
|
runtime->hw.rate_max = 192000;
|
4287 |
|
|
runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
|
4288 |
|
|
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
|
4289 |
|
|
}
|
4290 |
|
|
if (hdsp->io_type == H9632) {
|
4291 |
|
|
runtime->hw.channels_min = hdsp->qs_out_channels;
|
4292 |
|
|
runtime->hw.channels_max = hdsp->ss_out_channels;
|
4293 |
|
|
}
|
4294 |
|
|
|
4295 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
|
4296 |
|
|
snd_hdsp_hw_rule_out_channels, hdsp,
|
4297 |
|
|
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
|
4298 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
|
4299 |
|
|
snd_hdsp_hw_rule_out_channels_rate, hdsp,
|
4300 |
|
|
SNDRV_PCM_HW_PARAM_RATE, -1);
|
4301 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
|
4302 |
|
|
snd_hdsp_hw_rule_rate_out_channels, hdsp,
|
4303 |
|
|
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
|
4304 |
|
|
|
4305 |
|
|
hdsp->creg_spdif_stream = hdsp->creg_spdif;
|
4306 |
|
|
hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
|
4307 |
|
|
snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
|
4308 |
|
|
SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
|
4309 |
|
|
return 0;
|
4310 |
|
|
}
|
4311 |
|
|
|
4312 |
|
|
static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
|
4313 |
|
|
{
|
4314 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
4315 |
|
|
|
4316 |
|
|
spin_lock_irq(&hdsp->lock);
|
4317 |
|
|
|
4318 |
|
|
hdsp->playback_pid = -1;
|
4319 |
|
|
hdsp->playback_substream = NULL;
|
4320 |
|
|
|
4321 |
|
|
spin_unlock_irq(&hdsp->lock);
|
4322 |
|
|
|
4323 |
|
|
hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
|
4324 |
|
|
snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
|
4325 |
|
|
SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
|
4326 |
|
|
return 0;
|
4327 |
|
|
}
|
4328 |
|
|
|
4329 |
|
|
|
4330 |
|
|
static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
|
4331 |
|
|
{
|
4332 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
4333 |
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
4334 |
|
|
|
4335 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
4336 |
|
|
return -EIO;
|
4337 |
|
|
|
4338 |
|
|
if (hdsp_check_for_firmware(hdsp, 1))
|
4339 |
|
|
return -EIO;
|
4340 |
|
|
|
4341 |
|
|
spin_lock_irq(&hdsp->lock);
|
4342 |
|
|
|
4343 |
|
|
snd_pcm_set_sync(substream);
|
4344 |
|
|
|
4345 |
|
|
runtime->hw = snd_hdsp_capture_subinfo;
|
4346 |
|
|
runtime->dma_area = hdsp->capture_buffer;
|
4347 |
|
|
runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
|
4348 |
|
|
|
4349 |
|
|
hdsp->capture_pid = current->pid;
|
4350 |
|
|
hdsp->capture_substream = substream;
|
4351 |
|
|
|
4352 |
|
|
spin_unlock_irq(&hdsp->lock);
|
4353 |
|
|
|
4354 |
|
|
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
|
4355 |
|
|
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
|
4356 |
|
|
if (hdsp->io_type == H9632) {
|
4357 |
|
|
runtime->hw.channels_min = hdsp->qs_in_channels;
|
4358 |
|
|
runtime->hw.channels_max = hdsp->ss_in_channels;
|
4359 |
|
|
runtime->hw.rate_max = 192000;
|
4360 |
|
|
runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
|
4361 |
|
|
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
|
4362 |
|
|
}
|
4363 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
|
4364 |
|
|
snd_hdsp_hw_rule_in_channels, hdsp,
|
4365 |
|
|
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
|
4366 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
|
4367 |
|
|
snd_hdsp_hw_rule_in_channels_rate, hdsp,
|
4368 |
|
|
SNDRV_PCM_HW_PARAM_RATE, -1);
|
4369 |
|
|
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
|
4370 |
|
|
snd_hdsp_hw_rule_rate_in_channels, hdsp,
|
4371 |
|
|
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
|
4372 |
|
|
return 0;
|
4373 |
|
|
}
|
4374 |
|
|
|
4375 |
|
|
static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
|
4376 |
|
|
{
|
4377 |
|
|
struct hdsp *hdsp = snd_pcm_substream_chip(substream);
|
4378 |
|
|
|
4379 |
|
|
spin_lock_irq(&hdsp->lock);
|
4380 |
|
|
|
4381 |
|
|
hdsp->capture_pid = -1;
|
4382 |
|
|
hdsp->capture_substream = NULL;
|
4383 |
|
|
|
4384 |
|
|
spin_unlock_irq(&hdsp->lock);
|
4385 |
|
|
return 0;
|
4386 |
|
|
}
|
4387 |
|
|
|
4388 |
|
|
static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
|
4389 |
|
|
{
|
4390 |
|
|
/* we have nothing to initialize but the call is required */
|
4391 |
|
|
return 0;
|
4392 |
|
|
}
|
4393 |
|
|
|
4394 |
|
|
|
4395 |
|
|
/* helper functions for copying meter values */
|
4396 |
|
|
static inline int copy_u32_le(void __user *dest, void __iomem *src)
|
4397 |
|
|
{
|
4398 |
|
|
u32 val = readl(src);
|
4399 |
|
|
return copy_to_user(dest, &val, 4);
|
4400 |
|
|
}
|
4401 |
|
|
|
4402 |
|
|
static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
|
4403 |
|
|
{
|
4404 |
|
|
u32 rms_low, rms_high;
|
4405 |
|
|
u64 rms;
|
4406 |
|
|
rms_low = readl(src_low);
|
4407 |
|
|
rms_high = readl(src_high);
|
4408 |
|
|
rms = ((u64)rms_high << 32) | rms_low;
|
4409 |
|
|
return copy_to_user(dest, &rms, 8);
|
4410 |
|
|
}
|
4411 |
|
|
|
4412 |
|
|
static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
|
4413 |
|
|
{
|
4414 |
|
|
u32 rms_low, rms_high;
|
4415 |
|
|
u64 rms;
|
4416 |
|
|
rms_low = readl(src_low) & 0xffffff00;
|
4417 |
|
|
rms_high = readl(src_high) & 0xffffff00;
|
4418 |
|
|
rms = ((u64)rms_high << 32) | rms_low;
|
4419 |
|
|
return copy_to_user(dest, &rms, 8);
|
4420 |
|
|
}
|
4421 |
|
|
|
4422 |
|
|
static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
|
4423 |
|
|
{
|
4424 |
|
|
int doublespeed = 0;
|
4425 |
|
|
int i, j, channels, ofs;
|
4426 |
|
|
|
4427 |
|
|
if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
|
4428 |
|
|
doublespeed = 1;
|
4429 |
|
|
channels = doublespeed ? 14 : 26;
|
4430 |
|
|
for (i = 0, j = 0; i < 26; ++i) {
|
4431 |
|
|
if (doublespeed && (i & 4))
|
4432 |
|
|
continue;
|
4433 |
|
|
ofs = HDSP_9652_peakBase - j * 4;
|
4434 |
|
|
if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
|
4435 |
|
|
return -EFAULT;
|
4436 |
|
|
ofs -= channels * 4;
|
4437 |
|
|
if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
|
4438 |
|
|
return -EFAULT;
|
4439 |
|
|
ofs -= channels * 4;
|
4440 |
|
|
if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
|
4441 |
|
|
return -EFAULT;
|
4442 |
|
|
ofs = HDSP_9652_rmsBase + j * 8;
|
4443 |
|
|
if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
|
4444 |
|
|
hdsp->iobase + ofs + 4))
|
4445 |
|
|
return -EFAULT;
|
4446 |
|
|
ofs += channels * 8;
|
4447 |
|
|
if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
|
4448 |
|
|
hdsp->iobase + ofs + 4))
|
4449 |
|
|
return -EFAULT;
|
4450 |
|
|
ofs += channels * 8;
|
4451 |
|
|
if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
|
4452 |
|
|
hdsp->iobase + ofs + 4))
|
4453 |
|
|
return -EFAULT;
|
4454 |
|
|
j++;
|
4455 |
|
|
}
|
4456 |
|
|
return 0;
|
4457 |
|
|
}
|
4458 |
|
|
|
4459 |
|
|
static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
|
4460 |
|
|
{
|
4461 |
|
|
int i, j;
|
4462 |
|
|
struct hdsp_9632_meters __iomem *m;
|
4463 |
|
|
int doublespeed = 0;
|
4464 |
|
|
|
4465 |
|
|
if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
|
4466 |
|
|
doublespeed = 1;
|
4467 |
|
|
m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
|
4468 |
|
|
for (i = 0, j = 0; i < 16; ++i, ++j) {
|
4469 |
|
|
if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
|
4470 |
|
|
return -EFAULT;
|
4471 |
|
|
if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
|
4472 |
|
|
return -EFAULT;
|
4473 |
|
|
if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
|
4474 |
|
|
return -EFAULT;
|
4475 |
|
|
if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
|
4476 |
|
|
&m->input_rms_high[j]))
|
4477 |
|
|
return -EFAULT;
|
4478 |
|
|
if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
|
4479 |
|
|
&m->playback_rms_high[j]))
|
4480 |
|
|
return -EFAULT;
|
4481 |
|
|
if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
|
4482 |
|
|
&m->output_rms_high[j]))
|
4483 |
|
|
return -EFAULT;
|
4484 |
|
|
if (doublespeed && i == 3) i += 4;
|
4485 |
|
|
}
|
4486 |
|
|
return 0;
|
4487 |
|
|
}
|
4488 |
|
|
|
4489 |
|
|
static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
|
4490 |
|
|
{
|
4491 |
|
|
int i;
|
4492 |
|
|
|
4493 |
|
|
for (i = 0; i < 26; i++) {
|
4494 |
|
|
if (copy_u32_le(&peak_rms->playback_peaks[i],
|
4495 |
|
|
hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
|
4496 |
|
|
return -EFAULT;
|
4497 |
|
|
if (copy_u32_le(&peak_rms->input_peaks[i],
|
4498 |
|
|
hdsp->iobase + HDSP_inputPeakLevel + i * 4))
|
4499 |
|
|
return -EFAULT;
|
4500 |
|
|
}
|
4501 |
|
|
for (i = 0; i < 28; i++) {
|
4502 |
|
|
if (copy_u32_le(&peak_rms->output_peaks[i],
|
4503 |
|
|
hdsp->iobase + HDSP_outputPeakLevel + i * 4))
|
4504 |
|
|
return -EFAULT;
|
4505 |
|
|
}
|
4506 |
|
|
for (i = 0; i < 26; ++i) {
|
4507 |
|
|
if (copy_u64_le(&peak_rms->playback_rms[i],
|
4508 |
|
|
hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
|
4509 |
|
|
hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
|
4510 |
|
|
return -EFAULT;
|
4511 |
|
|
if (copy_u64_le(&peak_rms->input_rms[i],
|
4512 |
|
|
hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
|
4513 |
|
|
hdsp->iobase + HDSP_inputRmsLevel + i * 8))
|
4514 |
|
|
return -EFAULT;
|
4515 |
|
|
}
|
4516 |
|
|
return 0;
|
4517 |
|
|
}
|
4518 |
|
|
|
4519 |
|
|
static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
|
4520 |
|
|
{
|
4521 |
|
|
struct hdsp *hdsp = (struct hdsp *)hw->private_data;
|
4522 |
|
|
void __user *argp = (void __user *)arg;
|
4523 |
|
|
|
4524 |
|
|
switch (cmd) {
|
4525 |
|
|
case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
|
4526 |
|
|
struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
|
4527 |
|
|
|
4528 |
|
|
if (!(hdsp->state & HDSP_FirmwareLoaded)) {
|
4529 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
|
4530 |
|
|
return -EINVAL;
|
4531 |
|
|
}
|
4532 |
|
|
|
4533 |
|
|
switch (hdsp->io_type) {
|
4534 |
|
|
case H9652:
|
4535 |
|
|
return hdsp_9652_get_peak(hdsp, peak_rms);
|
4536 |
|
|
case H9632:
|
4537 |
|
|
return hdsp_9632_get_peak(hdsp, peak_rms);
|
4538 |
|
|
default:
|
4539 |
|
|
return hdsp_get_peak(hdsp, peak_rms);
|
4540 |
|
|
}
|
4541 |
|
|
}
|
4542 |
|
|
case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
|
4543 |
|
|
struct hdsp_config_info info;
|
4544 |
|
|
unsigned long flags;
|
4545 |
|
|
int i;
|
4546 |
|
|
|
4547 |
|
|
if (!(hdsp->state & HDSP_FirmwareLoaded)) {
|
4548 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
|
4549 |
|
|
return -EINVAL;
|
4550 |
|
|
}
|
4551 |
|
|
spin_lock_irqsave(&hdsp->lock, flags);
|
4552 |
|
|
info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
|
4553 |
|
|
info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
|
4554 |
|
|
if (hdsp->io_type != H9632)
|
4555 |
|
|
info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
|
4556 |
|
|
info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
|
4557 |
|
|
for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
|
4558 |
|
|
info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
|
4559 |
|
|
info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
|
4560 |
|
|
info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
|
4561 |
|
|
info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
|
4562 |
|
|
info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
|
4563 |
|
|
info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
|
4564 |
|
|
info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
|
4565 |
|
|
info.system_sample_rate = hdsp->system_sample_rate;
|
4566 |
|
|
info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
|
4567 |
|
|
info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
|
4568 |
|
|
info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
|
4569 |
|
|
info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
|
4570 |
|
|
info.line_out = (unsigned char)hdsp_line_out(hdsp);
|
4571 |
|
|
if (hdsp->io_type == H9632) {
|
4572 |
|
|
info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
|
4573 |
|
|
info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
|
4574 |
|
|
info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
|
4575 |
|
|
info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
|
4576 |
|
|
|
4577 |
|
|
}
|
4578 |
|
|
if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
|
4579 |
|
|
info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
|
4580 |
|
|
spin_unlock_irqrestore(&hdsp->lock, flags);
|
4581 |
|
|
if (copy_to_user(argp, &info, sizeof(info)))
|
4582 |
|
|
return -EFAULT;
|
4583 |
|
|
break;
|
4584 |
|
|
}
|
4585 |
|
|
case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
|
4586 |
|
|
struct hdsp_9632_aeb h9632_aeb;
|
4587 |
|
|
|
4588 |
|
|
if (hdsp->io_type != H9632) return -EINVAL;
|
4589 |
|
|
h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
|
4590 |
|
|
h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
|
4591 |
|
|
if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
|
4592 |
|
|
return -EFAULT;
|
4593 |
|
|
break;
|
4594 |
|
|
}
|
4595 |
|
|
case SNDRV_HDSP_IOCTL_GET_VERSION: {
|
4596 |
|
|
struct hdsp_version hdsp_version;
|
4597 |
|
|
int err;
|
4598 |
|
|
|
4599 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
|
4600 |
|
|
if (hdsp->io_type == Undefined) {
|
4601 |
|
|
if ((err = hdsp_get_iobox_version(hdsp)) < 0)
|
4602 |
|
|
return err;
|
4603 |
|
|
}
|
4604 |
|
|
hdsp_version.io_type = hdsp->io_type;
|
4605 |
|
|
hdsp_version.firmware_rev = hdsp->firmware_rev;
|
4606 |
|
|
if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
|
4607 |
|
|
return -EFAULT;
|
4608 |
|
|
break;
|
4609 |
|
|
}
|
4610 |
|
|
case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
|
4611 |
|
|
struct hdsp_firmware __user *firmware;
|
4612 |
|
|
u32 __user *firmware_data;
|
4613 |
|
|
int err;
|
4614 |
|
|
|
4615 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
|
4616 |
|
|
/* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
|
4617 |
|
|
if (hdsp->io_type == Undefined) return -EINVAL;
|
4618 |
|
|
|
4619 |
|
|
if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
|
4620 |
|
|
return -EBUSY;
|
4621 |
|
|
|
4622 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
|
4623 |
|
|
firmware = (struct hdsp_firmware __user *)argp;
|
4624 |
|
|
|
4625 |
|
|
if (get_user(firmware_data, &firmware->firmware_data))
|
4626 |
|
|
return -EFAULT;
|
4627 |
|
|
|
4628 |
|
|
if (hdsp_check_for_iobox (hdsp))
|
4629 |
|
|
return -EIO;
|
4630 |
|
|
|
4631 |
|
|
if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
|
4632 |
|
|
return -EFAULT;
|
4633 |
|
|
|
4634 |
|
|
hdsp->state |= HDSP_FirmwareCached;
|
4635 |
|
|
|
4636 |
|
|
if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
|
4637 |
|
|
return err;
|
4638 |
|
|
|
4639 |
|
|
if (!(hdsp->state & HDSP_InitializationComplete)) {
|
4640 |
|
|
if ((err = snd_hdsp_enable_io(hdsp)) < 0)
|
4641 |
|
|
return err;
|
4642 |
|
|
|
4643 |
|
|
snd_hdsp_initialize_channels(hdsp);
|
4644 |
|
|
snd_hdsp_initialize_midi_flush(hdsp);
|
4645 |
|
|
|
4646 |
|
|
if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
|
4647 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
|
4648 |
|
|
return err;
|
4649 |
|
|
}
|
4650 |
|
|
}
|
4651 |
|
|
break;
|
4652 |
|
|
}
|
4653 |
|
|
case SNDRV_HDSP_IOCTL_GET_MIXER: {
|
4654 |
|
|
struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
|
4655 |
|
|
if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
|
4656 |
|
|
return -EFAULT;
|
4657 |
|
|
break;
|
4658 |
|
|
}
|
4659 |
|
|
default:
|
4660 |
|
|
return -EINVAL;
|
4661 |
|
|
}
|
4662 |
|
|
return 0;
|
4663 |
|
|
}
|
4664 |
|
|
|
4665 |
|
|
static struct snd_pcm_ops snd_hdsp_playback_ops = {
|
4666 |
|
|
.open = snd_hdsp_playback_open,
|
4667 |
|
|
.close = snd_hdsp_playback_release,
|
4668 |
|
|
.ioctl = snd_hdsp_ioctl,
|
4669 |
|
|
.hw_params = snd_hdsp_hw_params,
|
4670 |
|
|
.prepare = snd_hdsp_prepare,
|
4671 |
|
|
.trigger = snd_hdsp_trigger,
|
4672 |
|
|
.pointer = snd_hdsp_hw_pointer,
|
4673 |
|
|
.copy = snd_hdsp_playback_copy,
|
4674 |
|
|
.silence = snd_hdsp_hw_silence,
|
4675 |
|
|
};
|
4676 |
|
|
|
4677 |
|
|
static struct snd_pcm_ops snd_hdsp_capture_ops = {
|
4678 |
|
|
.open = snd_hdsp_capture_open,
|
4679 |
|
|
.close = snd_hdsp_capture_release,
|
4680 |
|
|
.ioctl = snd_hdsp_ioctl,
|
4681 |
|
|
.hw_params = snd_hdsp_hw_params,
|
4682 |
|
|
.prepare = snd_hdsp_prepare,
|
4683 |
|
|
.trigger = snd_hdsp_trigger,
|
4684 |
|
|
.pointer = snd_hdsp_hw_pointer,
|
4685 |
|
|
.copy = snd_hdsp_capture_copy,
|
4686 |
|
|
};
|
4687 |
|
|
|
4688 |
|
|
static int __devinit snd_hdsp_create_hwdep(struct snd_card *card,
|
4689 |
|
|
struct hdsp *hdsp)
|
4690 |
|
|
{
|
4691 |
|
|
struct snd_hwdep *hw;
|
4692 |
|
|
int err;
|
4693 |
|
|
|
4694 |
|
|
if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
|
4695 |
|
|
return err;
|
4696 |
|
|
|
4697 |
|
|
hdsp->hwdep = hw;
|
4698 |
|
|
hw->private_data = hdsp;
|
4699 |
|
|
strcpy(hw->name, "HDSP hwdep interface");
|
4700 |
|
|
|
4701 |
|
|
hw->ops.open = snd_hdsp_hwdep_dummy_op;
|
4702 |
|
|
hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
|
4703 |
|
|
hw->ops.release = snd_hdsp_hwdep_dummy_op;
|
4704 |
|
|
|
4705 |
|
|
return 0;
|
4706 |
|
|
}
|
4707 |
|
|
|
4708 |
|
|
static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
|
4709 |
|
|
{
|
4710 |
|
|
struct snd_pcm *pcm;
|
4711 |
|
|
int err;
|
4712 |
|
|
|
4713 |
|
|
if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
|
4714 |
|
|
return err;
|
4715 |
|
|
|
4716 |
|
|
hdsp->pcm = pcm;
|
4717 |
|
|
pcm->private_data = hdsp;
|
4718 |
|
|
strcpy(pcm->name, hdsp->card_name);
|
4719 |
|
|
|
4720 |
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
|
4721 |
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
|
4722 |
|
|
|
4723 |
|
|
pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
|
4724 |
|
|
|
4725 |
|
|
return 0;
|
4726 |
|
|
}
|
4727 |
|
|
|
4728 |
|
|
static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
|
4729 |
|
|
{
|
4730 |
|
|
hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
|
4731 |
|
|
hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
|
4732 |
|
|
}
|
4733 |
|
|
|
4734 |
|
|
static int snd_hdsp_enable_io (struct hdsp *hdsp)
|
4735 |
|
|
{
|
4736 |
|
|
int i;
|
4737 |
|
|
|
4738 |
|
|
if (hdsp_fifo_wait (hdsp, 0, 100)) {
|
4739 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
|
4740 |
|
|
return -EIO;
|
4741 |
|
|
}
|
4742 |
|
|
|
4743 |
|
|
for (i = 0; i < hdsp->max_channels; ++i) {
|
4744 |
|
|
hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
|
4745 |
|
|
hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
|
4746 |
|
|
}
|
4747 |
|
|
|
4748 |
|
|
return 0;
|
4749 |
|
|
}
|
4750 |
|
|
|
4751 |
|
|
static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
|
4752 |
|
|
{
|
4753 |
|
|
int status, aebi_channels, aebo_channels;
|
4754 |
|
|
|
4755 |
|
|
switch (hdsp->io_type) {
|
4756 |
|
|
case Digiface:
|
4757 |
|
|
hdsp->card_name = "RME Hammerfall DSP + Digiface";
|
4758 |
|
|
hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
|
4759 |
|
|
hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
|
4760 |
|
|
break;
|
4761 |
|
|
|
4762 |
|
|
case H9652:
|
4763 |
|
|
hdsp->card_name = "RME Hammerfall HDSP 9652";
|
4764 |
|
|
hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
|
4765 |
|
|
hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
|
4766 |
|
|
break;
|
4767 |
|
|
|
4768 |
|
|
case H9632:
|
4769 |
|
|
status = hdsp_read(hdsp, HDSP_statusRegister);
|
4770 |
|
|
/* HDSP_AEBx bits are low when AEB are connected */
|
4771 |
|
|
aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
|
4772 |
|
|
aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
|
4773 |
|
|
hdsp->card_name = "RME Hammerfall HDSP 9632";
|
4774 |
|
|
hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
|
4775 |
|
|
hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
|
4776 |
|
|
hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
|
4777 |
|
|
hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
|
4778 |
|
|
hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
|
4779 |
|
|
hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
|
4780 |
|
|
break;
|
4781 |
|
|
|
4782 |
|
|
case Multiface:
|
4783 |
|
|
hdsp->card_name = "RME Hammerfall DSP + Multiface";
|
4784 |
|
|
hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
|
4785 |
|
|
hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
|
4786 |
|
|
break;
|
4787 |
|
|
|
4788 |
|
|
default:
|
4789 |
|
|
/* should never get here */
|
4790 |
|
|
break;
|
4791 |
|
|
}
|
4792 |
|
|
}
|
4793 |
|
|
|
4794 |
|
|
static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
|
4795 |
|
|
{
|
4796 |
|
|
snd_hdsp_flush_midi_input (hdsp, 0);
|
4797 |
|
|
snd_hdsp_flush_midi_input (hdsp, 1);
|
4798 |
|
|
}
|
4799 |
|
|
|
4800 |
|
|
static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
|
4801 |
|
|
{
|
4802 |
|
|
int err;
|
4803 |
|
|
|
4804 |
|
|
if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
|
4805 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
|
4806 |
|
|
return err;
|
4807 |
|
|
}
|
4808 |
|
|
|
4809 |
|
|
|
4810 |
|
|
if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
|
4811 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
|
4812 |
|
|
return err;
|
4813 |
|
|
}
|
4814 |
|
|
|
4815 |
|
|
if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
|
4816 |
|
|
if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
|
4817 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
|
4818 |
|
|
return err;
|
4819 |
|
|
}
|
4820 |
|
|
}
|
4821 |
|
|
|
4822 |
|
|
if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
|
4823 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
|
4824 |
|
|
return err;
|
4825 |
|
|
}
|
4826 |
|
|
|
4827 |
|
|
snd_hdsp_proc_init(hdsp);
|
4828 |
|
|
|
4829 |
|
|
hdsp->system_sample_rate = -1;
|
4830 |
|
|
hdsp->playback_pid = -1;
|
4831 |
|
|
hdsp->capture_pid = -1;
|
4832 |
|
|
hdsp->capture_substream = NULL;
|
4833 |
|
|
hdsp->playback_substream = NULL;
|
4834 |
|
|
|
4835 |
|
|
if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
|
4836 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
|
4837 |
|
|
return err;
|
4838 |
|
|
}
|
4839 |
|
|
|
4840 |
|
|
if (!(hdsp->state & HDSP_InitializationComplete)) {
|
4841 |
|
|
strcpy(card->shortname, "Hammerfall DSP");
|
4842 |
|
|
sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
|
4843 |
|
|
hdsp->port, hdsp->irq);
|
4844 |
|
|
|
4845 |
|
|
if ((err = snd_card_register(card)) < 0) {
|
4846 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
|
4847 |
|
|
return err;
|
4848 |
|
|
}
|
4849 |
|
|
hdsp->state |= HDSP_InitializationComplete;
|
4850 |
|
|
}
|
4851 |
|
|
|
4852 |
|
|
return 0;
|
4853 |
|
|
}
|
4854 |
|
|
|
4855 |
|
|
#ifdef HDSP_FW_LOADER
|
4856 |
|
|
/* load firmware via hotplug fw loader */
|
4857 |
|
|
static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp)
|
4858 |
|
|
{
|
4859 |
|
|
const char *fwfile;
|
4860 |
|
|
const struct firmware *fw;
|
4861 |
|
|
int err;
|
4862 |
|
|
|
4863 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
|
4864 |
|
|
return 0;
|
4865 |
|
|
if (hdsp->io_type == Undefined) {
|
4866 |
|
|
if ((err = hdsp_get_iobox_version(hdsp)) < 0)
|
4867 |
|
|
return err;
|
4868 |
|
|
if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
|
4869 |
|
|
return 0;
|
4870 |
|
|
}
|
4871 |
|
|
|
4872 |
|
|
/* caution: max length of firmware filename is 30! */
|
4873 |
|
|
switch (hdsp->io_type) {
|
4874 |
|
|
case Multiface:
|
4875 |
|
|
if (hdsp->firmware_rev == 0xa)
|
4876 |
|
|
fwfile = "multiface_firmware.bin";
|
4877 |
|
|
else
|
4878 |
|
|
fwfile = "multiface_firmware_rev11.bin";
|
4879 |
|
|
break;
|
4880 |
|
|
case Digiface:
|
4881 |
|
|
if (hdsp->firmware_rev == 0xa)
|
4882 |
|
|
fwfile = "digiface_firmware.bin";
|
4883 |
|
|
else
|
4884 |
|
|
fwfile = "digiface_firmware_rev11.bin";
|
4885 |
|
|
break;
|
4886 |
|
|
default:
|
4887 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
|
4888 |
|
|
return -EINVAL;
|
4889 |
|
|
}
|
4890 |
|
|
|
4891 |
|
|
if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
|
4892 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
|
4893 |
|
|
return -ENOENT;
|
4894 |
|
|
}
|
4895 |
|
|
if (fw->size < sizeof(hdsp->firmware_cache)) {
|
4896 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
|
4897 |
|
|
(int)fw->size, (int)sizeof(hdsp->firmware_cache));
|
4898 |
|
|
release_firmware(fw);
|
4899 |
|
|
return -EINVAL;
|
4900 |
|
|
}
|
4901 |
|
|
|
4902 |
|
|
memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
|
4903 |
|
|
|
4904 |
|
|
release_firmware(fw);
|
4905 |
|
|
|
4906 |
|
|
hdsp->state |= HDSP_FirmwareCached;
|
4907 |
|
|
|
4908 |
|
|
if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
|
4909 |
|
|
return err;
|
4910 |
|
|
|
4911 |
|
|
if (!(hdsp->state & HDSP_InitializationComplete)) {
|
4912 |
|
|
if ((err = snd_hdsp_enable_io(hdsp)) < 0)
|
4913 |
|
|
return err;
|
4914 |
|
|
|
4915 |
|
|
if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
|
4916 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
|
4917 |
|
|
return err;
|
4918 |
|
|
}
|
4919 |
|
|
snd_hdsp_initialize_channels(hdsp);
|
4920 |
|
|
snd_hdsp_initialize_midi_flush(hdsp);
|
4921 |
|
|
if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
|
4922 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
|
4923 |
|
|
return err;
|
4924 |
|
|
}
|
4925 |
|
|
}
|
4926 |
|
|
return 0;
|
4927 |
|
|
}
|
4928 |
|
|
#endif
|
4929 |
|
|
|
4930 |
|
|
static int __devinit snd_hdsp_create(struct snd_card *card,
|
4931 |
|
|
struct hdsp *hdsp)
|
4932 |
|
|
{
|
4933 |
|
|
struct pci_dev *pci = hdsp->pci;
|
4934 |
|
|
int err;
|
4935 |
|
|
int is_9652 = 0;
|
4936 |
|
|
int is_9632 = 0;
|
4937 |
|
|
|
4938 |
|
|
hdsp->irq = -1;
|
4939 |
|
|
hdsp->state = 0;
|
4940 |
|
|
hdsp->midi[0].rmidi = NULL;
|
4941 |
|
|
hdsp->midi[1].rmidi = NULL;
|
4942 |
|
|
hdsp->midi[0].input = NULL;
|
4943 |
|
|
hdsp->midi[1].input = NULL;
|
4944 |
|
|
hdsp->midi[0].output = NULL;
|
4945 |
|
|
hdsp->midi[1].output = NULL;
|
4946 |
|
|
hdsp->midi[0].pending = 0;
|
4947 |
|
|
hdsp->midi[1].pending = 0;
|
4948 |
|
|
spin_lock_init(&hdsp->midi[0].lock);
|
4949 |
|
|
spin_lock_init(&hdsp->midi[1].lock);
|
4950 |
|
|
hdsp->iobase = NULL;
|
4951 |
|
|
hdsp->control_register = 0;
|
4952 |
|
|
hdsp->control2_register = 0;
|
4953 |
|
|
hdsp->io_type = Undefined;
|
4954 |
|
|
hdsp->max_channels = 26;
|
4955 |
|
|
|
4956 |
|
|
hdsp->card = card;
|
4957 |
|
|
|
4958 |
|
|
spin_lock_init(&hdsp->lock);
|
4959 |
|
|
|
4960 |
|
|
tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
|
4961 |
|
|
|
4962 |
|
|
pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
|
4963 |
|
|
hdsp->firmware_rev &= 0xff;
|
4964 |
|
|
|
4965 |
|
|
/* From Martin Bjoernsen :
|
4966 |
|
|
"It is important that the card's latency timer register in
|
4967 |
|
|
the PCI configuration space is set to a value much larger
|
4968 |
|
|
than 0 by the computer's BIOS or the driver.
|
4969 |
|
|
The windows driver always sets this 8 bit register [...]
|
4970 |
|
|
to its maximum 255 to avoid problems with some computers."
|
4971 |
|
|
*/
|
4972 |
|
|
pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
|
4973 |
|
|
|
4974 |
|
|
strcpy(card->driver, "H-DSP");
|
4975 |
|
|
strcpy(card->mixername, "Xilinx FPGA");
|
4976 |
|
|
|
4977 |
|
|
if (hdsp->firmware_rev < 0xa)
|
4978 |
|
|
return -ENODEV;
|
4979 |
|
|
else if (hdsp->firmware_rev < 0x64)
|
4980 |
|
|
hdsp->card_name = "RME Hammerfall DSP";
|
4981 |
|
|
else if (hdsp->firmware_rev < 0x96) {
|
4982 |
|
|
hdsp->card_name = "RME HDSP 9652";
|
4983 |
|
|
is_9652 = 1;
|
4984 |
|
|
} else {
|
4985 |
|
|
hdsp->card_name = "RME HDSP 9632";
|
4986 |
|
|
hdsp->max_channels = 16;
|
4987 |
|
|
is_9632 = 1;
|
4988 |
|
|
}
|
4989 |
|
|
|
4990 |
|
|
if ((err = pci_enable_device(pci)) < 0)
|
4991 |
|
|
return err;
|
4992 |
|
|
|
4993 |
|
|
pci_set_master(hdsp->pci);
|
4994 |
|
|
|
4995 |
|
|
if ((err = pci_request_regions(pci, "hdsp")) < 0)
|
4996 |
|
|
return err;
|
4997 |
|
|
hdsp->port = pci_resource_start(pci, 0);
|
4998 |
|
|
if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
|
4999 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
|
5000 |
|
|
return -EBUSY;
|
5001 |
|
|
}
|
5002 |
|
|
|
5003 |
|
|
if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
|
5004 |
|
|
"hdsp", hdsp)) {
|
5005 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
|
5006 |
|
|
return -EBUSY;
|
5007 |
|
|
}
|
5008 |
|
|
|
5009 |
|
|
hdsp->irq = pci->irq;
|
5010 |
|
|
hdsp->precise_ptr = 0;
|
5011 |
|
|
hdsp->use_midi_tasklet = 1;
|
5012 |
|
|
hdsp->dds_value = 0;
|
5013 |
|
|
|
5014 |
|
|
if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
|
5015 |
|
|
return err;
|
5016 |
|
|
|
5017 |
|
|
if (!is_9652 && !is_9632) {
|
5018 |
|
|
/* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
|
5019 |
|
|
ssleep(2);
|
5020 |
|
|
|
5021 |
|
|
if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
|
5022 |
|
|
#ifdef HDSP_FW_LOADER
|
5023 |
|
|
if ((err = hdsp_request_fw_loader(hdsp)) < 0)
|
5024 |
|
|
/* we don't fail as this can happen
|
5025 |
|
|
if userspace is not ready for
|
5026 |
|
|
firmware upload
|
5027 |
|
|
*/
|
5028 |
|
|
snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
|
5029 |
|
|
else
|
5030 |
|
|
/* init is complete, we return */
|
5031 |
|
|
return 0;
|
5032 |
|
|
#endif
|
5033 |
|
|
/* no iobox connected, we defer initialization */
|
5034 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
|
5035 |
|
|
if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
|
5036 |
|
|
return err;
|
5037 |
|
|
return 0;
|
5038 |
|
|
} else {
|
5039 |
|
|
snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
|
5040 |
|
|
if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
|
5041 |
|
|
hdsp->io_type = Multiface;
|
5042 |
|
|
else
|
5043 |
|
|
hdsp->io_type = Digiface;
|
5044 |
|
|
}
|
5045 |
|
|
}
|
5046 |
|
|
|
5047 |
|
|
if ((err = snd_hdsp_enable_io(hdsp)) != 0)
|
5048 |
|
|
return err;
|
5049 |
|
|
|
5050 |
|
|
if (is_9652)
|
5051 |
|
|
hdsp->io_type = H9652;
|
5052 |
|
|
|
5053 |
|
|
if (is_9632)
|
5054 |
|
|
hdsp->io_type = H9632;
|
5055 |
|
|
|
5056 |
|
|
if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
|
5057 |
|
|
return err;
|
5058 |
|
|
|
5059 |
|
|
snd_hdsp_initialize_channels(hdsp);
|
5060 |
|
|
snd_hdsp_initialize_midi_flush(hdsp);
|
5061 |
|
|
|
5062 |
|
|
hdsp->state |= HDSP_FirmwareLoaded;
|
5063 |
|
|
|
5064 |
|
|
if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
|
5065 |
|
|
return err;
|
5066 |
|
|
|
5067 |
|
|
return 0;
|
5068 |
|
|
}
|
5069 |
|
|
|
5070 |
|
|
static int snd_hdsp_free(struct hdsp *hdsp)
|
5071 |
|
|
{
|
5072 |
|
|
if (hdsp->port) {
|
5073 |
|
|
/* stop the audio, and cancel all interrupts */
|
5074 |
|
|
tasklet_kill(&hdsp->midi_tasklet);
|
5075 |
|
|
hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
|
5076 |
|
|
hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
|
5077 |
|
|
}
|
5078 |
|
|
|
5079 |
|
|
if (hdsp->irq >= 0)
|
5080 |
|
|
free_irq(hdsp->irq, (void *)hdsp);
|
5081 |
|
|
|
5082 |
|
|
snd_hdsp_free_buffers(hdsp);
|
5083 |
|
|
|
5084 |
|
|
if (hdsp->iobase)
|
5085 |
|
|
iounmap(hdsp->iobase);
|
5086 |
|
|
|
5087 |
|
|
if (hdsp->port)
|
5088 |
|
|
pci_release_regions(hdsp->pci);
|
5089 |
|
|
|
5090 |
|
|
pci_disable_device(hdsp->pci);
|
5091 |
|
|
return 0;
|
5092 |
|
|
}
|
5093 |
|
|
|
5094 |
|
|
static void snd_hdsp_card_free(struct snd_card *card)
|
5095 |
|
|
{
|
5096 |
|
|
struct hdsp *hdsp = (struct hdsp *) card->private_data;
|
5097 |
|
|
|
5098 |
|
|
if (hdsp)
|
5099 |
|
|
snd_hdsp_free(hdsp);
|
5100 |
|
|
}
|
5101 |
|
|
|
5102 |
|
|
static int __devinit snd_hdsp_probe(struct pci_dev *pci,
|
5103 |
|
|
const struct pci_device_id *pci_id)
|
5104 |
|
|
{
|
5105 |
|
|
static int dev;
|
5106 |
|
|
struct hdsp *hdsp;
|
5107 |
|
|
struct snd_card *card;
|
5108 |
|
|
int err;
|
5109 |
|
|
|
5110 |
|
|
if (dev >= SNDRV_CARDS)
|
5111 |
|
|
return -ENODEV;
|
5112 |
|
|
if (!enable[dev]) {
|
5113 |
|
|
dev++;
|
5114 |
|
|
return -ENOENT;
|
5115 |
|
|
}
|
5116 |
|
|
|
5117 |
|
|
if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp))))
|
5118 |
|
|
return -ENOMEM;
|
5119 |
|
|
|
5120 |
|
|
hdsp = (struct hdsp *) card->private_data;
|
5121 |
|
|
card->private_free = snd_hdsp_card_free;
|
5122 |
|
|
hdsp->dev = dev;
|
5123 |
|
|
hdsp->pci = pci;
|
5124 |
|
|
snd_card_set_dev(card, &pci->dev);
|
5125 |
|
|
|
5126 |
|
|
if ((err = snd_hdsp_create(card, hdsp)) < 0) {
|
5127 |
|
|
snd_card_free(card);
|
5128 |
|
|
return err;
|
5129 |
|
|
}
|
5130 |
|
|
|
5131 |
|
|
strcpy(card->shortname, "Hammerfall DSP");
|
5132 |
|
|
sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
|
5133 |
|
|
hdsp->port, hdsp->irq);
|
5134 |
|
|
|
5135 |
|
|
if ((err = snd_card_register(card)) < 0) {
|
5136 |
|
|
snd_card_free(card);
|
5137 |
|
|
return err;
|
5138 |
|
|
}
|
5139 |
|
|
pci_set_drvdata(pci, card);
|
5140 |
|
|
dev++;
|
5141 |
|
|
return 0;
|
5142 |
|
|
}
|
5143 |
|
|
|
5144 |
|
|
static void __devexit snd_hdsp_remove(struct pci_dev *pci)
|
5145 |
|
|
{
|
5146 |
|
|
snd_card_free(pci_get_drvdata(pci));
|
5147 |
|
|
pci_set_drvdata(pci, NULL);
|
5148 |
|
|
}
|
5149 |
|
|
|
5150 |
|
|
static struct pci_driver driver = {
|
5151 |
|
|
.name = "RME Hammerfall DSP",
|
5152 |
|
|
.id_table = snd_hdsp_ids,
|
5153 |
|
|
.probe = snd_hdsp_probe,
|
5154 |
|
|
.remove = __devexit_p(snd_hdsp_remove),
|
5155 |
|
|
};
|
5156 |
|
|
|
5157 |
|
|
static int __init alsa_card_hdsp_init(void)
|
5158 |
|
|
{
|
5159 |
|
|
return pci_register_driver(&driver);
|
5160 |
|
|
}
|
5161 |
|
|
|
5162 |
|
|
static void __exit alsa_card_hdsp_exit(void)
|
5163 |
|
|
{
|
5164 |
|
|
pci_unregister_driver(&driver);
|
5165 |
|
|
}
|
5166 |
|
|
|
5167 |
|
|
module_init(alsa_card_hdsp_init)
|
5168 |
|
|
module_exit(alsa_card_hdsp_exit)
|