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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [debug_if/] [dbg_cpu.v] - Blame information for rev 42

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  dbg_cpu.v                                                   ////
4
////                                                              ////
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////                                                              ////
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////  This file is part of the SoC Debug Interface.               ////
7
////  http://www.opencores.org/projects/DebugInterface/           ////
8
////                                                              ////
9
////  Author(s):                                                  ////
10
////       Igor Mohor (igorm@opencores.org)                       ////
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////                                                              ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
14
////  file.                                                       ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2000 - 2004 Authors                            ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: dbg_cpu.v,v $
46
// Revision 1.12  2004/04/08 14:15:10  igorm
47
// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
48
// check-in.
49
//
50
// Revision 1.11  2004/04/07 19:28:55  igorm
51
// Zero is shifted out when CTRL_READ command is active.
52
//
53
// Revision 1.10  2004/04/01 10:22:45  igorm
54
// Signals for easier debugging removed.
55
//
56
// Revision 1.9  2004/03/31 14:34:09  igorm
57
// data_cnt_lim length changed to reduce number of warnings.
58
//
59
// Revision 1.8  2004/03/28 20:27:01  igorm
60
// New release of the debug interface (3rd. release).
61
//
62
// Revision 1.7  2004/01/25 14:04:18  mohor
63
// All flipflops are reset.
64
//
65
// Revision 1.6  2004/01/22 13:58:53  mohor
66
// Port signals are all set to zero after reset.
67
//
68
// Revision 1.5  2004/01/19 07:32:41  simons
69
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
70
//
71
// Revision 1.4  2004/01/17 18:38:11  mohor
72
// cpu_tall_o is set with cpu_stb_o or register.
73
//
74
// Revision 1.3  2004/01/17 18:01:24  mohor
75
// New version.
76
//
77
// Revision 1.2  2004/01/17 17:01:14  mohor
78
// Almost finished.
79
//
80
// Revision 1.1  2004/01/16 14:53:31  mohor
81
// *** empty log message ***
82
//
83
//
84
//
85
 
86
// synopsys translate_off
87
`include "timescale.v"
88
// synopsys translate_on
89
`include "dbg_cpu_defines.v"
90
 
91
// Top module
92
module dbg_cpu(
93
                // JTAG signals
94
                tck_i,
95
                tdi_i,
96
                tdo_o,
97
 
98
                // TAP states
99
                shift_dr_i,
100
                pause_dr_i,
101
                update_dr_i,
102
 
103
                cpu_ce_i,
104
                crc_match_i,
105
                crc_en_o,
106
                shift_crc_o,
107
                rst_i,
108
 
109
                // CPU
110
                cpu_clk_i,
111
                cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
112
                cpu_stb_o,
113
                cpu_we_o, cpu_ack_i, cpu_rst_o
114
 
115
              );
116
 
117
// JTAG signals
118
input         tck_i;
119
input         tdi_i;
120
output        tdo_o;
121
 
122
// TAP states
123
input         shift_dr_i;
124
input         pause_dr_i;
125
input         update_dr_i;
126
 
127
input         cpu_ce_i;
128
input         crc_match_i;
129
output        crc_en_o;
130
output        shift_crc_o;
131
input         rst_i;
132
 
133
// CPU
134
input         cpu_clk_i;
135
output [31:0] cpu_addr_o;
136
output [31:0] cpu_data_o;
137
input         cpu_bp_i;
138
output        cpu_stall_o;
139
input  [31:0] cpu_data_i;
140
output        cpu_stb_o;
141
output        cpu_we_o;
142
input         cpu_ack_i;
143
output        cpu_rst_o;
144
 
145
reg           cpu_stb_o;
146
wire          cpu_reg_stall;
147
reg           tdo_o;
148
reg           cpu_ack_q;
149
reg           cpu_ack_csff;
150
reg           cpu_ack_tck;
151
 
152
reg    [31:0] cpu_dat_tmp, cpu_data_dsff;
153
reg    [31:0] cpu_addr_dsff;
154
reg           cpu_we_dsff;
155
reg    [`DBG_CPU_DR_LEN -1 :0] dr;
156
wire          enable;
157
wire          cmd_cnt_en;
158
reg     [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
159
wire          cmd_cnt_end;
160
reg           cmd_cnt_end_q;
161
reg           addr_len_cnt_en;
162
reg     [5:0] addr_len_cnt;
163
wire          addr_len_cnt_end;
164
reg           addr_len_cnt_end_q;
165
reg           crc_cnt_en;
166
reg     [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
167
wire          crc_cnt_end;
168
reg           crc_cnt_end_q;
169
reg           data_cnt_en;
170
reg    [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
171
reg    [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
172
wire          data_cnt_end;
173
reg           data_cnt_end_q;
174
reg           crc_match_reg;
175
 
176
reg    [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
177
reg    [`DBG_CPU_ADR_LEN -1:0] adr;
178
reg    [`DBG_CPU_LEN_LEN -1:0] len;
179
reg    [`DBG_CPU_LEN_LEN:0]    len_var;
180
wire   [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
181
reg           start_rd_tck;
182
reg           rd_tck_started;
183
reg           start_rd_csff;
184
reg           start_cpu_rd;
185
reg           start_cpu_rd_q;
186
reg           start_wr_tck;
187
reg           start_wr_csff;
188
reg           start_cpu_wr;
189
reg           start_cpu_wr_q;
190
 
191
reg           status_cnt_en;
192
wire          status_cnt_end;
193
 
194
wire          half, long;
195
reg           half_q, long_q;
196
 
197
reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
198
 
199
reg [`DBG_CPU_STATUS_LEN -1:0] status;
200
 
201
reg           cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
202
reg           underrun_tck;
203
 
204
reg           busy_cpu;
205
reg           busy_tck;
206
reg           cpu_end;
207
reg           cpu_end_rst;
208
reg           cpu_end_rst_csff;
209
reg           cpu_end_csff;
210
reg           cpu_end_tck, cpu_end_tck_q;
211
reg           busy_csff;
212
reg           latch_data;
213
reg           update_dr_csff, update_dr_cpu;
214
wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
215
wire                          cpu_reg_we;
216
 
217
reg           set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
218
wire   [31:0] input_data;
219
 
220
wire          len_eq_0;
221
wire          crc_cnt_31;
222
 
223
reg           fifo_full;
224
reg     [7:0] mem [0:3];
225
reg           cpu_ce_csff;
226
reg           mem_ptr_init;
227
reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
228
wire          curr_cmd_go;
229
reg           curr_cmd_go_q;
230
wire          curr_cmd_wr_comm;
231
wire          curr_cmd_wr_ctrl;
232
wire          curr_cmd_rd_comm;
233
wire          curr_cmd_rd_ctrl;
234
wire          acc_type_read;
235
wire          acc_type_write;
236
 
237
 
238
assign enable = cpu_ce_i & shift_dr_i;
239
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
240
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
241
 
242
assign curr_cmd_go      = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
243
assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
244
assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
245
assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
246
assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
247
 
248
assign acc_type_read    = (acc_type == `DBG_CPU_READ);
249
assign acc_type_write   = (acc_type == `DBG_CPU_WRITE);
250
 
251
 
252
 
253
// Shift register for shifting in and out the data
254
always @ (posedge tck_i or posedge rst_i)
255
begin
256
  if (rst_i)
257
    begin
258
      latch_data <= #1 1'b0;
259
      dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
260
    end
261
  else if (curr_cmd_rd_comm && crc_cnt_31)  // Latching data (from internal regs)
262
    begin
263
      dr[`DBG_CPU_DR_LEN -1:0] <= #1 {acc_type, adr, len};
264
    end
265
  else if (curr_cmd_rd_ctrl && crc_cnt_31)  // Latching data (from control regs)
266
    begin
267
      dr[`DBG_CPU_DR_LEN -1:0] <= #1 {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
268
    end
269
  else if (acc_type_read && curr_cmd_go && crc_cnt_31)  // Latchind first data (from WB)
270
    begin
271
      dr[31:0] <= #1 input_data[31:0];
272
      latch_data <= #1 1'b1;
273
    end
274
  else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
275
    begin
276
      case (acc_type)  // synthesis parallel_case full_case
277
        `DBG_CPU_READ: begin
278
                      if(long & (~long_q))
279
                        begin
280
                          dr[31:0] <= #1 input_data[31:0];
281
                          latch_data <= #1 1'b1;
282
                        end
283
                      else
284
                        begin
285
                          dr[31:0] <= #1 {dr[30:0], 1'b0};
286
                          latch_data <= #1 1'b0;
287
                        end
288
                    end
289
      endcase
290
    end
291
  else if (enable && (!addr_len_cnt_end))
292
    begin
293
      dr <= #1 {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
294
    end
295
end
296
 
297
 
298
 
299
assign cmd_cnt_en = enable & (~cmd_cnt_end);
300
 
301
 
302
// Command counter
303
always @ (posedge tck_i or posedge rst_i)
304
begin
305
  if (rst_i)
306
    cmd_cnt <= #1 {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
307
  else if (update_dr_i)
308
    cmd_cnt <= #1 {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
309
  else if (cmd_cnt_en)
310
    cmd_cnt <= #1 cmd_cnt + 1'b1;
311
end
312
 
313
 
314
// Assigning current command
315
always @ (posedge tck_i or posedge rst_i)
316
begin
317
  if (rst_i)
318
    curr_cmd <= #1 {`DBG_CPU_CMD_LEN{1'b0}};
319
  else if (update_dr_i)
320
    curr_cmd <= #1 {`DBG_CPU_CMD_LEN{1'b0}};
321
  else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
322
    curr_cmd <= #1 {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
323
end
324
 
325
 
326
// Assigning current command
327
always @ (posedge tck_i or posedge rst_i)
328
begin
329
  if (rst_i)
330
    curr_cmd_go_q <= #1 1'b0;
331
  else
332
    curr_cmd_go_q <= #1 curr_cmd_go;
333
end
334
 
335
 
336
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
337
begin
338
  if (enable && (!addr_len_cnt_end))
339
    begin
340
      if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
341
        addr_len_cnt_en = 1'b1;
342
      else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
343
        addr_len_cnt_en = 1'b1;
344
      else
345
        addr_len_cnt_en = 1'b0;
346
    end
347
  else
348
    addr_len_cnt_en = 1'b0;
349
end
350
 
351
 
352
// Address/length counter
353
always @ (posedge tck_i or posedge rst_i)
354
begin
355
  if (rst_i)
356
    addr_len_cnt <= #1 6'h0;
357
  else if (update_dr_i)
358
    addr_len_cnt <= #1 6'h0;
359
  else if (addr_len_cnt_en)
360
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
361
end
362
 
363
 
364
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
365
begin
366
  if (enable && (!data_cnt_end))
367
    begin
368
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
369
        data_cnt_en = 1'b1;
370
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
371
        data_cnt_en = 1'b1;
372
      else
373
        data_cnt_en = 1'b0;
374
    end
375
  else
376
    data_cnt_en = 1'b0;
377
end
378
 
379
 
380
// Data counter
381
always @ (posedge tck_i or posedge rst_i)
382
begin
383
  if (rst_i)
384
    data_cnt <= #1 {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
385
  else if (update_dr_i)
386
    data_cnt <= #1 {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
387
  else if (data_cnt_en)
388
    data_cnt <= #1 data_cnt + 1'b1;
389
end
390
 
391
 
392
 
393
// Upper limit. Data counter counts until this value is reached.
394
always @ (posedge tck_i or posedge rst_i)
395
begin
396
  if (rst_i)
397
    data_cnt_limit <= #1 {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
398
  else if (update_dr_i)
399
    data_cnt_limit <= #1 len + 1'b1;
400
end
401
 
402
 
403
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
404
begin
405
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
406
    begin
407
      if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
408
        crc_cnt_en = 1'b1;
409
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
410
        crc_cnt_en = 1'b1;
411
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
412
        crc_cnt_en = 1'b1;
413
      else
414
        crc_cnt_en = 1'b0;
415
    end
416
  else
417
    crc_cnt_en = 1'b0;
418
end
419
 
420
 
421
// crc counter
422
always @ (posedge tck_i or posedge rst_i)
423
begin
424
  if (rst_i)
425
    crc_cnt <= #1 {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
426
  else if(crc_cnt_en)
427
    crc_cnt <= #1 crc_cnt + 1'b1;
428
  else if (update_dr_i)
429
    crc_cnt <= #1 {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
430
end
431
 
432
assign cmd_cnt_end      = cmd_cnt      == `DBG_CPU_CMD_LEN;
433
assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
434
assign crc_cnt_end      = crc_cnt      == `DBG_CPU_CRC_CNT_WIDTH'd32;
435
assign crc_cnt_31       = crc_cnt      == `DBG_CPU_CRC_CNT_WIDTH'd31;
436
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
437
 
438
always @ (posedge tck_i or posedge rst_i)
439
begin
440
  if (rst_i)
441
    begin
442
      crc_cnt_end_q       <= #1 1'b0;
443
      cmd_cnt_end_q       <= #1 1'b0;
444
      data_cnt_end_q      <= #1 1'b0;
445
      addr_len_cnt_end_q  <= #1 1'b0;
446
    end
447
  else
448
    begin
449
      crc_cnt_end_q       <= #1 crc_cnt_end;
450
      cmd_cnt_end_q       <= #1 cmd_cnt_end;
451
      data_cnt_end_q      <= #1 data_cnt_end;
452
      addr_len_cnt_end_q  <= #1 addr_len_cnt_end;
453
    end
454
end
455
 
456
 
457
// Status counter is made of 4 serialy connected registers
458
always @ (posedge tck_i or posedge rst_i)
459
begin
460
  if (rst_i)
461
    status_cnt <= #1 {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
462
  else if (update_dr_i)
463
    status_cnt <= #1 {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
464
  else if (status_cnt_en)
465
    status_cnt <= #1 status_cnt + 1'b1;
466
end
467
 
468
 
469
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
470
          curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
471
          acc_type_read or data_cnt_end or addr_len_cnt_end)
472
begin
473
  if (enable && (!status_cnt_end))
474
    begin
475
      if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
476
        status_cnt_en = 1'b1;
477
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
478
        status_cnt_en = 1'b1;
479
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
480
        status_cnt_en = 1'b1;
481
      else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
482
        status_cnt_en = 1'b1;
483
      else
484
        status_cnt_en = 1'b0;
485
    end
486
  else
487
    status_cnt_en = 1'b0;
488
end
489
 
490
 
491
assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
492
 
493
 
494
// Latching acc_type, address and length
495
always @ (posedge tck_i or posedge rst_i)
496
begin
497
  if (rst_i)
498
    begin
499
      acc_type  <= #1 {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
500
      adr       <= #1 {`DBG_CPU_ADR_LEN{1'b0}};
501
      len       <= #1 {`DBG_CPU_LEN_LEN{1'b0}};
502
      set_addr  <= #1 1'b0;
503
    end
504
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
505
    begin
506
      acc_type  <= #1 dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
507
      adr       <= #1 dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
508
      len       <= #1 dr[`DBG_CPU_LEN_LEN -1:0];
509
      set_addr  <= #1 1'b1;
510
    end
511
  else if(cpu_end_tck)               // Writing back the address
512
    begin
513
      adr  <= #1 cpu_addr_dsff;
514
    end
515
  else
516
    set_addr <= #1 1'b0;
517
end
518
 
519
 
520
always @ (posedge tck_i or posedge rst_i)
521
begin
522
  if (rst_i)
523
    crc_match_reg <= #1 1'b0;
524
  else if(crc_cnt_end & (~crc_cnt_end_q))
525
    crc_match_reg <= #1 crc_match_i;
526
end
527
 
528
 
529
// Length counter
530
always @ (posedge tck_i or posedge rst_i)
531
begin
532
  if (rst_i)
533
    len_var <= #1 {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
534
  else if(update_dr_i)
535
    len_var <= #1 len + 1'b1;
536
  else if (start_rd_tck)
537
    begin
538
      if (len_var > 'd4)
539
        len_var <= #1 len_var - 3'd4;
540
      else
541
        len_var <= #1 {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
542
    end
543
end
544
 
545
 
546
assign len_eq_0 = len_var == 'h0;
547
 
548
 
549
assign half = data_cnt[3:0] == 4'd15;
550
assign long = data_cnt[4:0] == 5'd31;
551
 
552
 
553
always @ (posedge tck_i or posedge rst_i)
554
begin
555
  if (rst_i)
556
    begin
557
      half_q <= #1  1'b0;
558
      long_q <= #1  1'b0;
559
    end
560
  else
561
    begin
562
      half_q <= #1 half;
563
      long_q <= #1 long;
564
    end
565
end
566
 
567
 
568
// Start cpu write cycle
569
always @ (posedge tck_i or posedge rst_i)
570
begin
571
  if (rst_i)
572
    begin
573
      start_wr_tck <= #1 1'b0;
574
      cpu_dat_tmp <= #1 32'h0;
575
    end
576
  else if (curr_cmd_go && acc_type_write)
577
    begin
578
      if (long_q)
579
        begin
580
          start_wr_tck <= #1 1'b1;
581
          cpu_dat_tmp <= #1 dr[31:0];
582
        end
583
      else
584
        begin
585
          start_wr_tck <= #1 1'b0;
586
        end
587
    end
588
  else
589
    start_wr_tck <= #1 1'b0;
590
end
591
 
592
 
593
// cpu_data_o in WB clk domain
594
always @ (posedge cpu_clk_i)
595
begin
596
  cpu_data_dsff <= #1 cpu_dat_tmp;
597
end
598
 
599
assign cpu_data_o = cpu_data_dsff;
600
 
601
 
602
// Start cpu read cycle
603
always @ (posedge tck_i or posedge rst_i)
604
begin
605
  if (rst_i)
606
    start_rd_tck <= #1 1'b0;
607
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)              // First read after cmd is entered
608
    start_rd_tck <= #1 1'b1;
609
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
610
    start_rd_tck <= #1 1'b1;
611
  else
612
    start_rd_tck <= #1 1'b0;
613
end
614
 
615
 
616
always @ (posedge tck_i or posedge rst_i)
617
begin
618
  if (rst_i)
619
    rd_tck_started <= #1 1'b0;
620
  else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
621
    rd_tck_started <= #1 1'b0;
622
  else if (start_rd_tck)
623
    rd_tck_started <= #1 1'b1;
624
end
625
 
626
 
627
 
628
always @ (posedge cpu_clk_i or posedge rst_i)
629
begin
630
  if (rst_i)
631
    begin
632
      start_rd_csff   <= #1 1'b0;
633
      start_cpu_rd    <= #1 1'b0;
634
      start_cpu_rd_q  <= #1 1'b0;
635
 
636
      start_wr_csff   <= #1 1'b0;
637
      start_cpu_wr    <= #1 1'b0;
638
      start_cpu_wr_q  <= #1 1'b0;
639
 
640
      set_addr_csff   <= #1 1'b0;
641
      set_addr_cpu    <= #1 1'b0;
642
      set_addr_cpu_q  <= #1 1'b0;
643
 
644
      cpu_ack_q       <= #1 1'b0;
645
    end
646
  else
647
    begin
648
      start_rd_csff   <= #1 start_rd_tck;
649
      start_cpu_rd    <= #1 start_rd_csff;
650
      start_cpu_rd_q  <= #1 start_cpu_rd;
651
 
652
      start_wr_csff   <= #1 start_wr_tck;
653
      start_cpu_wr    <= #1 start_wr_csff;
654
      start_cpu_wr_q  <= #1 start_cpu_wr;
655
 
656
      set_addr_csff   <= #1 set_addr;
657
      set_addr_cpu    <= #1 set_addr_csff;
658
      set_addr_cpu_q  <= #1 set_addr_cpu;
659
 
660
      cpu_ack_q       <= #1 cpu_ack_i;
661
    end
662
end
663
 
664
 
665
// cpu_stb_o
666
always @ (posedge cpu_clk_i or posedge rst_i)
667
begin
668
  if (rst_i)
669
    cpu_stb_o <= #1 1'b0;
670
  else if (cpu_ack_i)
671
    cpu_stb_o <= #1 1'b0;
672
  else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
673
    cpu_stb_o <= #1 1'b1;
674
end
675
 
676
 
677
assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
678
 
679
 
680
// cpu_addr_o logic
681
always @ (posedge cpu_clk_i or posedge rst_i)
682
begin
683
  if (rst_i)
684
    cpu_addr_dsff <= #1 32'h0;
685
  else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
686
    cpu_addr_dsff <= #1 adr;
687
  else if (cpu_ack_i && (!cpu_ack_q))
688
    cpu_addr_dsff <= #1 cpu_addr_dsff + 3'd4;
689
end
690
 
691
 
692
assign cpu_addr_o = cpu_addr_dsff;
693
 
694
 
695
always @ (posedge cpu_clk_i)
696
begin
697
  cpu_we_dsff <= #1 curr_cmd_go && acc_type_write;
698
end
699
 
700
 
701
assign cpu_we_o = cpu_we_dsff;
702
 
703
 
704
 
705
// Logic for detecting end of transaction
706
always @ (posedge cpu_clk_i or posedge rst_i)
707
begin
708
  if (rst_i)
709
    cpu_end <= #1 1'b0;
710
  else if (cpu_ack_i && (!cpu_ack_q))
711
    cpu_end <= #1 1'b1;
712
  else if (cpu_end_rst)
713
    cpu_end <= #1 1'b0;
714
end
715
 
716
 
717
always @ (posedge tck_i or posedge rst_i)
718
begin
719
  if (rst_i)
720
    begin
721
      cpu_end_csff  <= #1 1'b0;
722
      cpu_end_tck   <= #1 1'b0;
723
      cpu_end_tck_q <= #1 1'b0;
724
    end
725
  else
726
    begin
727
      cpu_end_csff  <= #1 cpu_end;
728
      cpu_end_tck   <= #1 cpu_end_csff;
729
      cpu_end_tck_q <= #1 cpu_end_tck;
730
    end
731
end
732
 
733
 
734
always @ (posedge cpu_clk_i or posedge rst_i)
735
begin
736
  if (rst_i)
737
    begin
738
      cpu_end_rst_csff <= #1 1'b0;
739
      cpu_end_rst      <= #1 1'b0;
740
    end
741
  else
742
    begin
743
      cpu_end_rst_csff <= #1 cpu_end_tck;
744
      cpu_end_rst      <= #1 cpu_end_rst_csff;
745
    end
746
end
747
 
748
 
749
always @ (posedge cpu_clk_i or posedge rst_i)
750
begin
751
  if (rst_i)
752
    busy_cpu <= #1 1'b0;
753
  else if (cpu_end_rst)
754
    busy_cpu <= #1 1'b0;
755
  else if (cpu_stb_o)
756
    busy_cpu <= #1 1'b1;
757
end
758
 
759
 
760
always @ (posedge tck_i or posedge rst_i)
761
begin
762
  if (rst_i)
763
    begin
764
      busy_csff       <= #1 1'b0;
765
      busy_tck        <= #1 1'b0;
766
 
767
      update_dr_csff  <= #1 1'b0;
768
      update_dr_cpu   <= #1 1'b0;
769
    end
770
  else
771
    begin
772
      busy_csff       <= #1 busy_cpu;
773
      busy_tck        <= #1 busy_csff;
774
 
775
      update_dr_csff  <= #1 update_dr_i;
776
      update_dr_cpu   <= #1 update_dr_csff;
777
    end
778
end
779
 
780
 
781
// Detecting overrun when write operation.
782
always @ (posedge cpu_clk_i or posedge rst_i)
783
begin
784
  if (rst_i)
785
    cpu_overrun <= #1 1'b0;
786
  else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
787
    cpu_overrun <= #1 1'b1;
788
  else if(update_dr_cpu) // error remains active until update_dr arrives
789
    cpu_overrun <= #1 1'b0;
790
end
791
 
792
 
793
// Detecting underrun when read operation
794
always @ (posedge tck_i or posedge rst_i)
795
begin
796
  if (rst_i)
797
    underrun_tck <= #1 1'b0;
798
  else if(latch_data && (!fifo_full) && (!data_cnt_end))
799
    underrun_tck <= #1 1'b1;
800
  else if(update_dr_i) // error remains active until update_dr arrives
801
    underrun_tck <= #1 1'b0;
802
end
803
 
804
 
805
always @ (posedge tck_i or posedge rst_i)
806
begin
807
  if (rst_i)
808
    begin
809
      cpu_overrun_csff <= #1 1'b0;
810
      cpu_overrun_tck  <= #1 1'b0;
811
 
812
      cpu_ack_csff     <= #1 1'b0;
813
      cpu_ack_tck      <= #1 1'b0;
814
    end
815
  else
816
    begin
817
      cpu_overrun_csff <= #1 cpu_overrun;
818
      cpu_overrun_tck  <= #1 cpu_overrun_csff;
819
 
820
      cpu_ack_csff     <= #1 cpu_ack_i;
821
      cpu_ack_tck      <= #1 cpu_ack_csff;
822
    end
823
end
824
 
825
 
826
 
827
always @ (posedge cpu_clk_i or posedge rst_i)
828
begin
829
  if (rst_i)
830
    begin
831
      cpu_ce_csff  <= #1 1'b0;
832
      mem_ptr_init      <= #1 1'b0;
833
    end
834
  else
835
    begin
836
      cpu_ce_csff  <= #1  cpu_ce_i;
837
      mem_ptr_init      <= #1 ~cpu_ce_csff;
838
    end
839
end
840
 
841
 
842
// Logic for latching data that is read from cpu
843
always @ (posedge cpu_clk_i)
844
begin
845
  if (cpu_ack_i && (!cpu_ack_q))
846
    begin
847
      mem[0] <= #1 cpu_data_i[31:24];
848
      mem[1] <= #1 cpu_data_i[23:16];
849
      mem[2] <= #1 cpu_data_i[15:08];
850
      mem[3] <= #1 cpu_data_i[07:00];
851
    end
852
end
853
 
854
 
855
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
856
 
857
 
858
// Fifo counter and empty/full detection
859
always @ (posedge tck_i or posedge rst_i)
860
begin
861
  if (rst_i)
862
    fifo_full <= #1 1'h0;
863
  else if (update_dr_i)
864
    fifo_full <= #1 1'h0;
865
  else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full))  // incrementing
866
    fifo_full <= #1 1'b1;
867
  else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full))  // decrementing
868
    fifo_full <= #1 1'h0;
869
end
870
 
871
 
872
 
873
// TDO multiplexer
874
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
875
begin
876
  if (pause_dr_i)
877
    begin
878
    tdo_o = busy_tck;
879
    end
880
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
881
    begin
882
      tdo_o = ~crc_match_i;
883
    end
884
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
885
    begin
886
      tdo_o = dr[31];
887
    end
888
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
889
    begin
890
      tdo_o = ~crc_match_reg;
891
    end
892
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
893
    begin
894
      tdo_o = ~crc_match_reg;
895
    end
896
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
897
    begin
898
      tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
899
    end
900
  else if (status_cnt_en)
901
    begin
902
      tdo_o = status[3];
903
    end
904
  else
905
    begin
906
      tdo_o = 1'b0;
907
    end
908
end
909
 
910
 
911
// Status register
912
always @ (posedge tck_i or posedge rst_i)
913
begin
914
  if (rst_i)
915
    begin
916
    status <= #1 {`DBG_CPU_STATUS_LEN{1'b0}};
917
    end
918
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
919
    begin
920
    status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
921
    end
922
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
923
    begin
924
    status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
925
    end
926
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
927
    begin
928
    status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
929
    end
930
  else if (shift_dr_i && (!status_cnt_end))
931
    begin
932
    status <= #1 {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
933
    end
934
end
935
// Following status is shifted out (MSB first):
936
// 3. bit:          1 if crc is OK, else 0
937
// 2. bit:          1'b0
938
// 1. bit:          0
939
// 0. bit:          1 if overrun occured during write (data couldn't be written fast enough)
940
//                    or underrun occured during read (data couldn't be read fast enough)
941
 
942
 
943
 
944
// Connecting cpu registers
945
assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
946
assign cpu_reg_data_i = dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN];
947
 
948
dbg_cpu_registers i_dbg_cpu_registers
949
  (
950
    .data_i          (cpu_reg_data_i),
951
    .we_i            (cpu_reg_we),
952
    .tck_i           (tck_i),
953
    .bp_i            (cpu_bp_i),
954
    .rst_i           (rst_i),
955
    .cpu_clk_i       (cpu_clk_i),
956
    .ctrl_reg_o      (ctrl_reg),
957
    .cpu_stall_o     (cpu_reg_stall),
958
    .cpu_rst_o       (cpu_rst_o)
959
  );
960
 
961
 
962
 
963
 
964
 
965
endmodule
966
 

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