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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_cpu_defines.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_cpu_defines.v,v $
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// Revision 1.6 2004/04/05 13:52:54 igorm
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// CPU_WR_CTRL and CPU_RD_CTRL defines changed.
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//
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// Revision 1.5 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.4 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.3 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.1 2004/01/16 14:53:33 mohor
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// *** empty log message ***
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//
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//
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//
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// Defining length of the command
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`define DBG_CPU_CMD_LEN 3'd4
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`define DBG_CPU_CMD_CNT_WIDTH 3
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// Defining length of the access_type field
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`define DBG_CPU_ACC_TYPE_LEN 3'd4
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// Defining length of the address
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`define DBG_CPU_ADR_LEN 6'd32
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// Defining length of the length register
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`define DBG_CPU_LEN_LEN 5'd16
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// Defining total length of the DR needed
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//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
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`define DBG_CPU_DR_LEN 52
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// Defining length of the CRC
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`define DBG_CPU_CRC_LEN 6'd32
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`define DBG_CPU_CRC_CNT_WIDTH 6
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// Defining length of status
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`define DBG_CPU_STATUS_LEN 3'd4
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`define DBG_CPU_STATUS_CNT_WIDTH 3
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// Defining length of the data
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//define DBG_CPU_DATA_CNT_WIDTH `DBG_CPU_LEN_LEN + 3
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`define DBG_CPU_DATA_CNT_WIDTH 19
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//define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
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`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
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// Defining length of the control register
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`define DBG_CPU_CTRL_LEN 2
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//Defining commands
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`define DBG_CPU_GO 4'h0
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`define DBG_CPU_RD_COMM 4'h1
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`define DBG_CPU_WR_COMM 4'h2
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`define DBG_CPU_RD_CTRL 4'h3
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`define DBG_CPU_WR_CTRL 4'h4
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// Defining access types for wishbone
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`define DBG_CPU_WRITE 4'h2
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`define DBG_CPU_READ 4'h6
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