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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [debug_if/] [dbg_top_ip.v] - Blame information for rev 18

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1 18 unneback 
`timescale 1ns/10ps
2 
module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
3 
input         data;
4 
input         enable;
5 
input         shift;
6 
input         rst;
7 
input         sync_rst;
8 
input         clk;
9 
output        crc_out;
10 
output        crc_match;
11 
reg    [31:0] crc;
12 
wire   [31:0] new_crc;
13 
assign new_crc[0] = data          ^ crc[31];
14 
assign new_crc[1] = data          ^ crc[0]  ^ crc[31];
15 
assign new_crc[2] = data          ^ crc[1]  ^ crc[31];
16 
assign new_crc[3] = crc[2];
17 
assign new_crc[4] = data          ^ crc[3]  ^ crc[31];
18 
assign new_crc[5] = data          ^ crc[4]  ^ crc[31];
19 
assign new_crc[6] = crc[5];
20 
assign new_crc[7] = data          ^ crc[6]  ^ crc[31];
21 
assign new_crc[8] = data          ^ crc[7]  ^ crc[31];
22 
assign new_crc[9] = crc[8];
23 
assign new_crc[10] = data         ^ crc[9]  ^ crc[31];
24 
assign new_crc[11] = data         ^ crc[10] ^ crc[31];
25 
assign new_crc[12] = data         ^ crc[11] ^ crc[31];
26 
assign new_crc[13] = crc[12];
27 
assign new_crc[14] = crc[13];
28 
assign new_crc[15] = crc[14];
29 
assign new_crc[16] = data         ^ crc[15] ^ crc[31];
30 
assign new_crc[17] = crc[16];
31 
assign new_crc[18] = crc[17];
32 
assign new_crc[19] = crc[18];
33 
assign new_crc[20] = crc[19];
34 
assign new_crc[21] = crc[20];
35 
assign new_crc[22] = data         ^ crc[21] ^ crc[31];
36 
assign new_crc[23] = data         ^ crc[22] ^ crc[31];
37 
assign new_crc[24] = crc[23];
38 
assign new_crc[25] = crc[24];
39 
assign new_crc[26] = data         ^ crc[25] ^ crc[31];
40 
assign new_crc[27] = crc[26];
41 
assign new_crc[28] = crc[27];
42 
assign new_crc[29] = crc[28];
43 
assign new_crc[30] = crc[29];
44 
assign new_crc[31] = crc[30];
45 
always @ (posedge clk or posedge rst)
46 
begin
47 
  if(rst)
48 
    crc[31:0] <= #1 32'hffffffff;
49 
  else if(sync_rst)
50 
    crc[31:0] <= #1 32'hffffffff;
51 
  else if(enable)
52 
    crc[31:0] <= #1 new_crc;
53 
  else if (shift)
54 
    crc[31:0] <= #1 {crc[30:0], 1'b0};
55 
end
56 
assign crc_match = (crc == 32'h0);
57 
assign crc_out = crc[31];
58 
endmodule
59 
`timescale 1ns/10ps
60 
module dbg_register (
61 
                      data_in,
62 
                      data_out,
63 
                      write,
64 
                      clk,
65 
                      reset
66 
                    );
67 
parameter WIDTH = 8;
68 
parameter RESET_VALUE = 0;
69 
input   [WIDTH-1:0] data_in;
70 
input               write;
71 
input               clk;
72 
input               reset;
73 
output  [WIDTH-1:0] data_out;
74 
reg     [WIDTH-1:0] data_out;
75 
always @ (posedge clk or posedge reset)
76 
begin
77 
  if(reset)
78 
    data_out[WIDTH-1:0] <= #1 RESET_VALUE;
79 
  else if(write)
80 
    data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0];
81 
end
82 
endmodule
83 
`timescale 1ns/10ps
84 
module dbg_cpu_registers  (
85 
                            data_i,
86 
                            we_i,
87 
                            tck_i,
88 
                            bp_i,
89 
                            rst_i,
90 
                            cpu_clk_i,
91 
                            ctrl_reg_o,
92 
                            cpu_stall_o,
93 
                            cpu_rst_o
94 
                          );
95 
input  [2 -1:0] data_i;
96 
input                   we_i;
97 
input                   tck_i;
98 
input                   bp_i;
99 
input                   rst_i;
100 
input                   cpu_clk_i;
101 
output [2 -1:0]ctrl_reg_o;
102 
output                  cpu_stall_o;
103 
output                  cpu_rst_o;
104 
reg                     cpu_reset;
105 
wire             [2:1]  cpu_op_out;
106 
reg                     stall_bp, stall_bp_csff, stall_bp_tck;
107 
reg                     stall_reg, stall_reg_csff, stall_reg_cpu;
108 
reg                     cpu_reset_csff;
109 
reg                     cpu_rst_o;
110 
always @ (posedge cpu_clk_i or posedge rst_i)
111 
begin
112 
  if(rst_i)
113 
    stall_bp <= #1 1'b0;
114 
  else if(bp_i)
115 
    stall_bp <= #1 1'b1;
116 
  else if(stall_reg_cpu)
117 
    stall_bp <= #1 1'b0;
118 
end
119 
always @ (posedge tck_i or posedge rst_i)
120 
begin
121 
  if (rst_i)
122 
    begin
123 
      stall_bp_csff <= #1 1'b0;
124 
      stall_bp_tck  <= #1 1'b0;
125 
    end
126 
  else
127 
    begin
128 
      stall_bp_csff <= #1 stall_bp;
129 
      stall_bp_tck  <= #1 stall_bp_csff;
130 
    end
131 
end
132 
always @ (posedge cpu_clk_i or posedge rst_i)
133 
begin
134 
  if (rst_i)
135 
    begin
136 
      stall_reg_csff <= #1 1'b0;
137 
      stall_reg_cpu  <= #1 1'b0;
138 
    end
139 
  else
140 
    begin
141 
      stall_reg_csff <= #1 stall_reg;
142 
      stall_reg_cpu  <= #1 stall_reg_csff;
143 
    end
144 
end
145 
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
146 
always @ (posedge tck_i or posedge rst_i)
147 
begin
148 
  if (rst_i)
149 
    stall_reg <= #1 1'b0;
150 
  else if (stall_bp_tck)
151 
    stall_reg <= #1 1'b1;
152 
  else if (we_i)
153 
    stall_reg <= #1 data_i[0];
154 
end
155 
always @ (posedge tck_i or posedge rst_i)
156 
begin
157 
  if (rst_i)
158 
    cpu_reset  <= #1 1'b0;
159 
  else if(we_i)
160 
    cpu_reset  <= #1 data_i[1];
161 
end
162 
always @ (posedge cpu_clk_i or posedge rst_i)
163 
begin
164 
  if (rst_i)
165 
    begin
166 
      cpu_reset_csff      <= #1 1'b0;
167 
      cpu_rst_o           <= #1 1'b0;
168 
    end
169 
  else
170 
    begin
171 
      cpu_reset_csff      <= #1 cpu_reset;
172 
      cpu_rst_o           <= #1 cpu_reset_csff;
173 
    end
174 
end
175 
assign ctrl_reg_o = {cpu_reset, stall_reg};
176 
endmodule
177 
`timescale 1ns/10ps
178 
module dbg_cpu(
179 
                tck_i,
180 
                tdi_i,
181 
                tdo_o,
182 
                shift_dr_i,
183 
                pause_dr_i,
184 
                update_dr_i,
185 
                cpu_ce_i,
186 
                crc_match_i,
187 
                crc_en_o,
188 
                shift_crc_o,
189 
                rst_i,
190 
                cpu_clk_i,
191 
                cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
192 
                cpu_stb_o,
193 
                cpu_we_o, cpu_ack_i, cpu_rst_o
194 
              );
195 
input         tck_i;
196 
input         tdi_i;
197 
output        tdo_o;
198 
input         shift_dr_i;
199 
input         pause_dr_i;
200 
input         update_dr_i;
201 
input         cpu_ce_i;
202 
input         crc_match_i;
203 
output        crc_en_o;
204 
output        shift_crc_o;
205 
input         rst_i;
206 
input         cpu_clk_i;
207 
output [31:0] cpu_addr_o;
208 
output [31:0] cpu_data_o;
209 
input         cpu_bp_i;
210 
output        cpu_stall_o;
211 
input  [31:0] cpu_data_i;
212 
output        cpu_stb_o;
213 
output        cpu_we_o;
214 
input         cpu_ack_i;
215 
output        cpu_rst_o;
216 
reg           cpu_stb_o;
217 
wire          cpu_reg_stall;
218 
reg           tdo_o;
219 
reg           cpu_ack_q;
220 
reg           cpu_ack_csff;
221 
reg           cpu_ack_tck;
222 
reg    [31:0] cpu_dat_tmp, cpu_data_dsff;
223 
reg    [31:0] cpu_addr_dsff;
224 
reg           cpu_we_dsff;
225 
reg    [52 -1 :0] dr;
226 
wire          enable;
227 
wire          cmd_cnt_en;
228 
reg     [3 -1:0] cmd_cnt;
229 
wire          cmd_cnt_end;
230 
reg           cmd_cnt_end_q;
231 
reg           addr_len_cnt_en;
232 
reg     [5:0] addr_len_cnt;
233 
wire          addr_len_cnt_end;
234 
reg           addr_len_cnt_end_q;
235 
reg           crc_cnt_en;
236 
reg     [6 -1:0] crc_cnt;
237 
wire          crc_cnt_end;
238 
reg           crc_cnt_end_q;
239 
reg           data_cnt_en;
240 
reg    [19:0] data_cnt;
241 
reg    [16:0] data_cnt_limit;
242 
wire          data_cnt_end;
243 
reg           data_cnt_end_q;
244 
reg           crc_match_reg;
245 
reg    [3'd4 -1:0] acc_type;
246 
reg    [6'd32 -1:0] adr;
247 
reg    [5'd16 -1:0] len;
248 
reg    [5'd16:0]    len_var;
249 
wire   [2 -1:0]ctrl_reg;
250 
reg           start_rd_tck;
251 
reg           rd_tck_started;
252 
reg           start_rd_csff;
253 
reg           start_cpu_rd;
254 
reg           start_cpu_rd_q;
255 
reg           start_wr_tck;
256 
reg           start_wr_csff;
257 
reg           start_cpu_wr;
258 
reg           start_cpu_wr_q;
259 
reg           status_cnt_en;
260 
wire          status_cnt_end;
261 
wire          half, long;
262 
reg           half_q, long_q;
263 
reg [3 -1:0] status_cnt;
264 
reg [3'd4 -1:0] status;
265 
reg           cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
266 
reg           underrun_tck;
267 
reg           busy_cpu;
268 
reg           busy_tck;
269 
reg           cpu_end;
270 
reg           cpu_end_rst;
271 
reg           cpu_end_rst_csff;
272 
reg           cpu_end_csff;
273 
reg           cpu_end_tck, cpu_end_tck_q;
274 
reg           busy_csff;
275 
reg           latch_data;
276 
reg           update_dr_csff, update_dr_cpu;
277 
wire [2 -1:0] cpu_reg_data_i;
278 
wire                          cpu_reg_we;
279 
reg           set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
280 
wire   [31:0] input_data;
281 
wire          len_eq_0;
282 
wire          crc_cnt_31;
283 
reg           fifo_full;
284 
reg     [7:0] mem [0:3];
285 
reg           cpu_ce_csff;
286 
reg           mem_ptr_init;
287 
reg [3'd4 -1: 0] curr_cmd;
288 
wire          curr_cmd_go;
289 
reg           curr_cmd_go_q;
290 
wire          curr_cmd_wr_comm;
291 
wire          curr_cmd_wr_ctrl;
292 
wire          curr_cmd_rd_comm;
293 
wire          curr_cmd_rd_ctrl;
294 
wire          acc_type_read;
295 
wire          acc_type_write;
296 
assign enable = cpu_ce_i & shift_dr_i;
297 
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
298 
assign shift_crc_o = enable & status_cnt_end;
299 
assign curr_cmd_go      = (curr_cmd == 4'h0) && cmd_cnt_end;
300 
assign curr_cmd_wr_comm = (curr_cmd == 4'h2) && cmd_cnt_end;
301 
assign curr_cmd_wr_ctrl = (curr_cmd == 4'h4) && cmd_cnt_end;
302 
assign curr_cmd_rd_comm = (curr_cmd == 4'h1) && cmd_cnt_end;
303 
assign curr_cmd_rd_ctrl = (curr_cmd == 4'h3) && cmd_cnt_end;
304 
assign acc_type_read    = (acc_type == 4'h6);
305 
assign acc_type_write   = (acc_type == 4'h2);
306 
always @ (posedge tck_i or posedge rst_i)
307 
begin
308 
  if (rst_i)
309 
    begin
310 
      latch_data <= #1 1'b0;
311 
      dr <= #1 {52{1'b0}};
312 
    end
313 
  else if (curr_cmd_rd_comm && crc_cnt_31)
314 
    begin
315 
      dr[52 -1:0] <= #1 {acc_type, adr, len};
316 
    end
317 
  else if (curr_cmd_rd_ctrl && crc_cnt_31)
318 
    begin
319 
      dr[52 -1:0] <= #1 {ctrl_reg, {52 -2{1'b0}}};
320 
    end
321 
  else if (acc_type_read && curr_cmd_go && crc_cnt_31)
322 
    begin
323 
      dr[31:0] <= #1 input_data[31:0];
324 
      latch_data <= #1 1'b1;
325 
    end
326 
  else if (acc_type_read && curr_cmd_go && crc_cnt_end)
327 
    begin
328 
      case (acc_type)
329 
        4'h6: begin
330 
                      if(long & (~long_q))
331 
                        begin
332 
                          dr[31:0] <= #1 input_data[31:0];
333 
                          latch_data <= #1 1'b1;
334 
                        end
335 
                      else
336 
                        begin
337 
                          dr[31:0] <= #1 {dr[30:0], 1'b0};
338 
                          latch_data <= #1 1'b0;
339 
                        end
340 
                    end
341 
      endcase
342 
    end
343 
  else if (enable && (!addr_len_cnt_end))
344 
    begin
345 
      dr <= #1 {dr[52 -2:0], tdi_i};
346 
    end
347 
end
348 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
349 
always @ (posedge tck_i or posedge rst_i)
350 
begin
351 
  if (rst_i)
352 
    cmd_cnt <= #1 {3{1'b0}};
353 
  else if (update_dr_i)
354 
    cmd_cnt <= #1 {3{1'b0}};
355 
  else if (cmd_cnt_en)
356 
    cmd_cnt <= #1 cmd_cnt + 1'b1;
357 
end
358 
always @ (posedge tck_i or posedge rst_i)
359 
begin
360 
  if (rst_i)
361 
    curr_cmd <= #1 {3'd4{1'b0}};
362 
  else if (update_dr_i)
363 
    curr_cmd <= #1 {3'd4{1'b0}};
364 
  else if (cmd_cnt == (3'd4 -1))
365 
    curr_cmd <= #1 {dr[3'd4-2 :0], tdi_i};
366 
end
367 
always @ (posedge tck_i or posedge rst_i)
368 
begin
369 
  if (rst_i)
370 
    curr_cmd_go_q <= #1 1'b0;
371 
  else
372 
    curr_cmd_go_q <= #1 curr_cmd_go;
373 
end
374 
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
375 
begin
376 
  if (enable && (!addr_len_cnt_end))
377 
    begin
378 
      if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
379 
        addr_len_cnt_en = 1'b1;
380 
      else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
381 
        addr_len_cnt_en = 1'b1;
382 
      else
383 
        addr_len_cnt_en = 1'b0;
384 
    end
385 
  else
386 
    addr_len_cnt_en = 1'b0;
387 
end
388 
always @ (posedge tck_i or posedge rst_i)
389 
begin
390 
  if (rst_i)
391 
    addr_len_cnt <= #1 6'h0;
392 
  else if (update_dr_i)
393 
    addr_len_cnt <= #1 6'h0;
394 
  else if (addr_len_cnt_en)
395 
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
396 
end
397 
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
398 
begin
399 
  if (enable && (!data_cnt_end))
400 
    begin
401 
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
402 
        data_cnt_en = 1'b1;
403 
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
404 
        data_cnt_en = 1'b1;
405 
      else
406 
        data_cnt_en = 1'b0;
407 
    end
408 
  else
409 
    data_cnt_en = 1'b0;
410 
end
411 
always @ (posedge tck_i or posedge rst_i)
412 
begin
413 
  if (rst_i)
414 
    data_cnt <= #1 {19{1'b0}};
415 
  else if (update_dr_i)
416 
    data_cnt <= #1 {19{1'b0}};
417 
  else if (data_cnt_en)
418 
    data_cnt <= #1 data_cnt + 1'b1;
419 
end
420 
always @ (posedge tck_i or posedge rst_i)
421 
begin
422 
  if (rst_i)
423 
    data_cnt_limit <= #1 {16{1'b0}};
424 
  else if (update_dr_i)
425 
    data_cnt_limit <= #1 len + 1'b1;
426 
end
427 
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
428 
begin
429 
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
430 
    begin
431 
      if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
432 
        crc_cnt_en = 1'b1;
433 
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
434 
        crc_cnt_en = 1'b1;
435 
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
436 
        crc_cnt_en = 1'b1;
437 
      else
438 
        crc_cnt_en = 1'b0;
439 
    end
440 
  else
441 
    crc_cnt_en = 1'b0;
442 
end
443 
always @ (posedge tck_i or posedge rst_i)
444 
begin
445 
  if (rst_i)
446 
    crc_cnt <= #1 {6{1'b0}};
447 
  else if(crc_cnt_en)
448 
    crc_cnt <= #1 crc_cnt + 1'b1;
449 
  else if (update_dr_i)
450 
    crc_cnt <= #1 {6{1'b0}};
451 
end
452 
assign cmd_cnt_end      = cmd_cnt      == 3'd4;
453 
assign addr_len_cnt_end = addr_len_cnt == 52;
454 
assign crc_cnt_end      = crc_cnt      == 6'd32;
455 
assign crc_cnt_31       = crc_cnt      == 6'd31;
456 
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
457 
always @ (posedge tck_i or posedge rst_i)
458 
begin
459 
  if (rst_i)
460 
    begin
461 
      crc_cnt_end_q       <= #1 1'b0;
462 
      cmd_cnt_end_q       <= #1 1'b0;
463 
      data_cnt_end_q      <= #1 1'b0;
464 
      addr_len_cnt_end_q  <= #1 1'b0;
465 
    end
466 
  else
467 
    begin
468 
      crc_cnt_end_q       <= #1 crc_cnt_end;
469 
      cmd_cnt_end_q       <= #1 cmd_cnt_end;
470 
      data_cnt_end_q      <= #1 data_cnt_end;
471 
      addr_len_cnt_end_q  <= #1 addr_len_cnt_end;
472 
    end
473 
end
474 
always @ (posedge tck_i or posedge rst_i)
475 
begin
476 
  if (rst_i)
477 
    status_cnt <= #1 {3{1'b0}};
478 
  else if (update_dr_i)
479 
    status_cnt <= #1 {3{1'b0}};
480 
  else if (status_cnt_en)
481 
    status_cnt <= #1 status_cnt + 1'b1;
482 
end
483 
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
484 
          curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
485 
          acc_type_read or data_cnt_end or addr_len_cnt_end)
486 
begin
487 
  if (enable && (!status_cnt_end))
488 
    begin
489 
      if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
490 
        status_cnt_en = 1'b1;
491 
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
492 
        status_cnt_en = 1'b1;
493 
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
494 
        status_cnt_en = 1'b1;
495 
      else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
496 
        status_cnt_en = 1'b1;
497 
      else
498 
        status_cnt_en = 1'b0;
499 
    end
500 
  else
501 
    status_cnt_en = 1'b0;
502 
end
503 
assign status_cnt_end = status_cnt == 3'd4;
504 
always @ (posedge tck_i or posedge rst_i)
505 
begin
506 
  if (rst_i)
507 
    begin
508 
      acc_type  <= #1 {3'd4{1'b0}};
509 
      adr       <= #1 {6'd32{1'b0}};
510 
      len       <= #1 {5'd16{1'b0}};
511 
      set_addr  <= #1 1'b0;
512 
    end
513 
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
514 
    begin
515 
      acc_type  <= #1 dr[3'd4 + 6'd32 + 5'd16 -1 : 6'd32 + 5'd16];
516 
      adr       <= #1 dr[6'd32 + 5'd16 -1 : 5'd16];
517 
      len       <= #1 dr[5'd16 -1:0];
518 
      set_addr  <= #1 1'b1;
519 
    end
520 
  else if(cpu_end_tck)
521 
    begin
522 
      adr  <= #1 cpu_addr_dsff;
523 
    end
524 
  else
525 
    set_addr <= #1 1'b0;
526 
end
527 
always @ (posedge tck_i or posedge rst_i)
528 
begin
529 
  if (rst_i)
530 
    crc_match_reg <= #1 1'b0;
531 
  else if(crc_cnt_end & (~crc_cnt_end_q))
532 
    crc_match_reg <= #1 crc_match_i;
533 
end
534 
always @ (posedge tck_i or posedge rst_i)
535 
begin
536 
  if (rst_i)
537 
    len_var <= #1 {1'b0, {5'd16{1'b0}}};
538 
  else if(update_dr_i)
539 
    len_var <= #1 len + 1'b1;
540 
  else if (start_rd_tck)
541 
    begin
542 
      if (len_var > 'd4)
543 
        len_var <= #1 len_var - 3'd4;
544 
      else
545 
        len_var <= #1 {1'b0, {5'd16{1'b0}}};
546 
    end
547 
end
548 
assign len_eq_0 = len_var == 'h0;
549 
assign half = data_cnt[3:0] == 4'd15;
550 
assign long = data_cnt[4:0] == 5'd31;
551 
always @ (posedge tck_i or posedge rst_i)
552 
begin
553 
  if (rst_i)
554 
    begin
555 
      half_q <= #1  1'b0;
556 
      long_q <= #1  1'b0;
557 
    end
558 
  else
559 
    begin
560 
      half_q <= #1 half;
561 
      long_q <= #1 long;
562 
    end
563 
end
564 
always @ (posedge tck_i or posedge rst_i)
565 
begin
566 
  if (rst_i)
567 
    begin
568 
      start_wr_tck <= #1 1'b0;
569 
      cpu_dat_tmp <= #1 32'h0;
570 
    end
571 
  else if (curr_cmd_go && acc_type_write)
572 
    begin
573 
      if (long_q)
574 
        begin
575 
          start_wr_tck <= #1 1'b1;
576 
          cpu_dat_tmp <= #1 dr[31:0];
577 
        end
578 
      else
579 
        begin
580 
          start_wr_tck <= #1 1'b0;
581 
        end
582 
    end
583 
  else
584 
    start_wr_tck <= #1 1'b0;
585 
end
586 
always @ (posedge cpu_clk_i)
587 
begin
588 
  cpu_data_dsff <= #1 cpu_dat_tmp;
589 
end
590 
assign cpu_data_o = cpu_data_dsff;
591 
always @ (posedge tck_i or posedge rst_i)
592 
begin
593 
  if (rst_i)
594 
    start_rd_tck <= #1 1'b0;
595 
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
596 
    start_rd_tck <= #1 1'b1;
597 
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
598 
    start_rd_tck <= #1 1'b1;
599 
  else
600 
    start_rd_tck <= #1 1'b0;
601 
end
602 
always @ (posedge tck_i or posedge rst_i)
603 
begin
604 
  if (rst_i)
605 
    rd_tck_started <= #1 1'b0;
606 
  else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
607 
    rd_tck_started <= #1 1'b0;
608 
  else if (start_rd_tck)
609 
    rd_tck_started <= #1 1'b1;
610 
end
611 
always @ (posedge cpu_clk_i or posedge rst_i)
612 
begin
613 
  if (rst_i)
614 
    begin
615 
      start_rd_csff   <= #1 1'b0;
616 
      start_cpu_rd    <= #1 1'b0;
617 
      start_cpu_rd_q  <= #1 1'b0;
618 
      start_wr_csff   <= #1 1'b0;
619 
      start_cpu_wr    <= #1 1'b0;
620 
      start_cpu_wr_q  <= #1 1'b0;
621 
      set_addr_csff   <= #1 1'b0;
622 
      set_addr_cpu    <= #1 1'b0;
623 
      set_addr_cpu_q  <= #1 1'b0;
624 
      cpu_ack_q       <= #1 1'b0;
625 
    end
626 
  else
627 
    begin
628 
      start_rd_csff   <= #1 start_rd_tck;
629 
      start_cpu_rd    <= #1 start_rd_csff;
630 
      start_cpu_rd_q  <= #1 start_cpu_rd;
631 
      start_wr_csff   <= #1 start_wr_tck;
632 
      start_cpu_wr    <= #1 start_wr_csff;
633 
      start_cpu_wr_q  <= #1 start_cpu_wr;
634 
      set_addr_csff   <= #1 set_addr;
635 
      set_addr_cpu    <= #1 set_addr_csff;
636 
      set_addr_cpu_q  <= #1 set_addr_cpu;
637 
      cpu_ack_q       <= #1 cpu_ack_i;
638 
    end
639 
end
640 
always @ (posedge cpu_clk_i or posedge rst_i)
641 
begin
642 
  if (rst_i)
643 
    cpu_stb_o <= #1 1'b0;
644 
  else if (cpu_ack_i)
645 
    cpu_stb_o <= #1 1'b0;
646 
  else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
647 
    cpu_stb_o <= #1 1'b1;
648 
end
649 
assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
650 
always @ (posedge cpu_clk_i or posedge rst_i)
651 
begin
652 
  if (rst_i)
653 
    cpu_addr_dsff <= #1 32'h0;
654 
  else if (set_addr_cpu && (!set_addr_cpu_q))
655 
    cpu_addr_dsff <= #1 adr;
656 
  else if (cpu_ack_i && (!cpu_ack_q))
657 
    cpu_addr_dsff <= #1 cpu_addr_dsff + 3'd4;
658 
end
659 
assign cpu_addr_o = cpu_addr_dsff;
660 
always @ (posedge cpu_clk_i)
661 
begin
662 
  cpu_we_dsff <= #1 curr_cmd_go && acc_type_write;
663 
end
664 
assign cpu_we_o = cpu_we_dsff;
665 
always @ (posedge cpu_clk_i or posedge rst_i)
666 
begin
667 
  if (rst_i)
668 
    cpu_end <= #1 1'b0;
669 
  else if (cpu_ack_i && (!cpu_ack_q))
670 
    cpu_end <= #1 1'b1;
671 
  else if (cpu_end_rst)
672 
    cpu_end <= #1 1'b0;
673 
end
674 
always @ (posedge tck_i or posedge rst_i)
675 
begin
676 
  if (rst_i)
677 
    begin
678 
      cpu_end_csff  <= #1 1'b0;
679 
      cpu_end_tck   <= #1 1'b0;
680 
      cpu_end_tck_q <= #1 1'b0;
681 
    end
682 
  else
683 
    begin
684 
      cpu_end_csff  <= #1 cpu_end;
685 
      cpu_end_tck   <= #1 cpu_end_csff;
686 
      cpu_end_tck_q <= #1 cpu_end_tck;
687 
    end
688 
end
689 
always @ (posedge cpu_clk_i or posedge rst_i)
690 
begin
691 
  if (rst_i)
692 
    begin
693 
      cpu_end_rst_csff <= #1 1'b0;
694 
      cpu_end_rst      <= #1 1'b0;
695 
    end
696 
  else
697 
    begin
698 
      cpu_end_rst_csff <= #1 cpu_end_tck;
699 
      cpu_end_rst      <= #1 cpu_end_rst_csff;
700 
    end
701 
end
702 
always @ (posedge cpu_clk_i or posedge rst_i)
703 
begin
704 
  if (rst_i)
705 
    busy_cpu <= #1 1'b0;
706 
  else if (cpu_end_rst)
707 
    busy_cpu <= #1 1'b0;
708 
  else if (cpu_stb_o)
709 
    busy_cpu <= #1 1'b1;
710 
end
711 
always @ (posedge tck_i or posedge rst_i)
712 
begin
713 
  if (rst_i)
714 
    begin
715 
      busy_csff       <= #1 1'b0;
716 
      busy_tck        <= #1 1'b0;
717 
      update_dr_csff  <= #1 1'b0;
718 
      update_dr_cpu   <= #1 1'b0;
719 
    end
720 
  else
721 
    begin
722 
      busy_csff       <= #1 busy_cpu;
723 
      busy_tck        <= #1 busy_csff;
724 
      update_dr_csff  <= #1 update_dr_i;
725 
      update_dr_cpu   <= #1 update_dr_csff;
726 
    end
727 
end
728 
always @ (posedge cpu_clk_i or posedge rst_i)
729 
begin
730 
  if (rst_i)
731 
    cpu_overrun <= #1 1'b0;
732 
  else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
733 
    cpu_overrun <= #1 1'b1;
734 
  else if(update_dr_cpu)
735 
    cpu_overrun <= #1 1'b0;
736 
end
737 
always @ (posedge tck_i or posedge rst_i)
738 
begin
739 
  if (rst_i)
740 
    underrun_tck <= #1 1'b0;
741 
  else if(latch_data && (!fifo_full) && (!data_cnt_end))
742 
    underrun_tck <= #1 1'b1;
743 
  else if(update_dr_i)
744 
    underrun_tck <= #1 1'b0;
745 
end
746 
always @ (posedge tck_i or posedge rst_i)
747 
begin
748 
  if (rst_i)
749 
    begin
750 
      cpu_overrun_csff <= #1 1'b0;
751 
      cpu_overrun_tck  <= #1 1'b0;
752 
      cpu_ack_csff     <= #1 1'b0;
753 
      cpu_ack_tck      <= #1 1'b0;
754 
    end
755 
  else
756 
    begin
757 
      cpu_overrun_csff <= #1 cpu_overrun;
758 
      cpu_overrun_tck  <= #1 cpu_overrun_csff;
759 
      cpu_ack_csff     <= #1 cpu_ack_i;
760 
      cpu_ack_tck      <= #1 cpu_ack_csff;
761 
    end
762 
end
763 
always @ (posedge cpu_clk_i or posedge rst_i)
764 
begin
765 
  if (rst_i)
766 
    begin
767 
      cpu_ce_csff  <= #1 1'b0;
768 
      mem_ptr_init      <= #1 1'b0;
769 
    end
770 
  else
771 
    begin
772 
      cpu_ce_csff  <= #1  cpu_ce_i;
773 
      mem_ptr_init      <= #1 ~cpu_ce_csff;
774 
    end
775 
end
776 
always @ (posedge cpu_clk_i)
777 
begin
778 
  if (cpu_ack_i && (!cpu_ack_q))
779 
    begin
780 
      mem[0] <= #1 cpu_data_i[31:24];
781 
      mem[1] <= #1 cpu_data_i[23:16];
782 
      mem[2] <= #1 cpu_data_i[15:08];
783 
      mem[3] <= #1 cpu_data_i[07:00];
784 
    end
785 
end
786 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
787 
always @ (posedge tck_i or posedge rst_i)
788 
begin
789 
  if (rst_i)
790 
    fifo_full <= #1 1'h0;
791 
  else if (update_dr_i)
792 
    fifo_full <= #1 1'h0;
793 
  else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full))
794 
    fifo_full <= #1 1'b1;
795 
  else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full))
796 
    fifo_full <= #1 1'h0;
797 
end
798 
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
799 
begin
800 
  if (pause_dr_i)
801 
    begin
802 
    tdo_o = busy_tck;
803 
    end
804 
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
805 
    begin
806 
      tdo_o = ~crc_match_i;
807 
    end
808 
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
809 
    begin
810 
      tdo_o = dr[31];
811 
    end
812 
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
813 
    begin
814 
      tdo_o = ~crc_match_reg;
815 
    end
816 
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
817 
    begin
818 
      tdo_o = ~crc_match_reg;
819 
    end
820 
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
821 
    begin
822 
      tdo_o = dr[3'd4 + 6'd32 + 5'd16 -1];
823 
    end
824 
  else if (status_cnt_en)
825 
    begin
826 
      tdo_o = status[3];
827 
    end
828 
  else
829 
    begin
830 
      tdo_o = 1'b0;
831 
    end
832 
end
833 
always @ (posedge tck_i or posedge rst_i)
834 
begin
835 
  if (rst_i)
836 
    begin
837 
    status <= #1 {3'd4{1'b0}};
838 
    end
839 
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
840 
    begin
841 
    status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
842 
    end
843 
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
844 
    begin
845 
    status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
846 
    end
847 
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
848 
    begin
849 
    status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
850 
    end
851 
  else if (shift_dr_i && (!status_cnt_end))
852 
    begin
853 
    status <= #1 {status[3'd4 -2:0], status[3'd4 -1]};
854 
    end
855 
end
856 
assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
857 
assign cpu_reg_data_i = dr[52 -1:52 -2];
858 
dbg_cpu_registers i_dbg_cpu_registers
859 
  (
860 
    .data_i          (cpu_reg_data_i),
861 
    .we_i            (cpu_reg_we),
862 
    .tck_i           (tck_i),
863 
    .bp_i            (cpu_bp_i),
864 
    .rst_i           (rst_i),
865 
    .cpu_clk_i       (cpu_clk_i),
866 
    .ctrl_reg_o      (ctrl_reg),
867 
    .cpu_stall_o     (cpu_reg_stall),
868 
    .cpu_rst_o       (cpu_rst_o)
869 
  );
870 
endmodule
871 
`timescale 1ns/10ps
872 
module dbg_wb(
873 
                tck_i,
874 
                tdi_i,
875 
                tdo_o,
876 
                shift_dr_i,
877 
                pause_dr_i,
878 
                update_dr_i,
879 
                wishbone_ce_i,
880 
                crc_match_i,
881 
                crc_en_o,
882 
                shift_crc_o,
883 
                rst_i,
884 
                wb_clk_i,
885 
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
886 
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
887 
              );
888 
input         tck_i;
889 
input         tdi_i;
890 
output        tdo_o;
891 
input         shift_dr_i;
892 
input         pause_dr_i;
893 
input         update_dr_i;
894 
input         wishbone_ce_i;
895 
input         crc_match_i;
896 
output        crc_en_o;
897 
output        shift_crc_o;
898 
input         rst_i;
899 
input         wb_clk_i;
900 
output [31:0] wb_adr_o;
901 
output [31:0] wb_dat_o;
902 
input  [31:0] wb_dat_i;
903 
output        wb_cyc_o;
904 
output        wb_stb_o;
905 
output  [3:0] wb_sel_o;
906 
output        wb_we_o;
907 
input         wb_ack_i;
908 
output        wb_cab_o;
909 
input         wb_err_i;
910 
output  [2:0] wb_cti_o;
911 
output  [1:0] wb_bte_o;
912 
reg           wb_cyc_o;
913 
reg           tdo_o;
914 
reg    [31:0] wb_dat_tmp, wb_dat_dsff;
915 
reg    [31:0] wb_adr_dsff;
916 
reg     [3:0] wb_sel_dsff;
917 
reg           wb_we_dsff;
918 
reg    [(3'd4 + 6'd32 + 5'd16) -1 :0] dr;
919 
wire          enable;
920 
wire          cmd_cnt_en;
921 
reg     [3 -1:0] cmd_cnt;
922 
wire          cmd_cnt_end;
923 
reg           cmd_cnt_end_q;
924 
reg           addr_len_cnt_en;
925 
reg     [5:0] addr_len_cnt;
926 
wire          addr_len_cnt_end;
927 
reg           addr_len_cnt_end_q;
928 
reg           crc_cnt_en;
929 
reg     [6 -1:0] crc_cnt;
930 
wire          crc_cnt_end;
931 
reg           crc_cnt_end_q;
932 
reg           data_cnt_en;
933 
reg    [(5'd16 + 3):0] data_cnt;
934 
reg    [5'd16:0] data_cnt_limit;
935 
wire          data_cnt_end;
936 
reg           data_cnt_end_q;
937 
reg           crc_match_reg;
938 
reg    [3'd4 -1:0] acc_type;
939 
reg    [6'd32 -1:0] adr;
940 
reg    [5'd16 -1:0] len;
941 
reg    [5'd16:0]    len_var;
942 
reg           start_rd_tck;
943 
reg           rd_tck_started;
944 
reg           start_rd_csff;
945 
reg           start_wb_rd;
946 
reg           start_wb_rd_q;
947 
reg           start_wr_tck;
948 
reg           start_wr_csff;
949 
reg           start_wb_wr;
950 
reg           start_wb_wr_q;
951 
reg           status_cnt_en;
952 
wire          status_cnt_end;
953 
wire          byte, half, long;
954 
reg           byte_q, half_q, long_q;
955 
reg [3 -1:0] status_cnt;
956 
reg [3'd4 -1:0] status;
957 
reg           wb_error, wb_error_csff, wb_error_tck;
958 
reg           wb_overrun, wb_overrun_csff, wb_overrun_tck;
959 
reg           underrun_tck;
960 
reg           busy_wb;
961 
reg           busy_tck;
962 
reg           wb_end;
963 
reg           wb_end_rst;
964 
reg           wb_end_rst_csff;
965 
reg           wb_end_csff;
966 
reg           wb_end_tck, wb_end_tck_q;
967 
reg           busy_csff;
968 
reg           latch_data;
969 
reg           update_dr_csff, update_dr_wb;
970 
reg           set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
971 
wire   [31:0] input_data;
972 
wire          len_eq_0;
973 
wire          crc_cnt_31;
974 
reg     [1:0] ptr;
975 
reg     [2:0] fifo_cnt;
976 
wire          fifo_full;
977 
wire          fifo_empty;
978 
reg     [7:0] mem [0:3];
979 
reg     [2:0] mem_ptr_dsff;
980 
reg           wishbone_ce_csff;
981 
reg           mem_ptr_init;
982 
reg [3'd4 -1: 0] curr_cmd;
983 
wire          curr_cmd_go;
984 
reg           curr_cmd_go_q;
985 
wire          curr_cmd_wr_comm;
986 
wire          curr_cmd_rd_comm;
987 
wire          acc_type_read;
988 
wire          acc_type_write;
989 
wire          acc_type_8bit;
990 
wire          acc_type_16bit;
991 
wire          acc_type_32bit;
992 
assign enable = wishbone_ce_i & shift_dr_i;
993 
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
994 
assign shift_crc_o = enable & status_cnt_end;
995 
assign curr_cmd_go      = (curr_cmd == 4'h0) && cmd_cnt_end;
996 
assign curr_cmd_wr_comm = (curr_cmd == 4'h2) && cmd_cnt_end;
997 
assign curr_cmd_rd_comm = (curr_cmd == 4'h1) && cmd_cnt_end;
998 
assign acc_type_read    = (acc_type == 4'h4  || acc_type == 4'h5  || acc_type == 4'h6);
999 
assign acc_type_write   = (acc_type == 4'h0 || acc_type == 4'h1 || acc_type == 4'h2);
1000 
assign acc_type_8bit    = (acc_type == 4'h4  || acc_type == 4'h0);
1001 
assign acc_type_16bit   = (acc_type == 4'h5 || acc_type == 4'h1);
1002 
assign acc_type_32bit   = (acc_type == 4'h6 || acc_type == 4'h2);
1003 
always @ (posedge tck_i or posedge rst_i)
1004 
begin
1005 
  if (rst_i)
1006 
    ptr <= #1 2'h0;
1007 
  else if (update_dr_i)
1008 
    ptr <= #1 2'h0;
1009 
  else if (curr_cmd_go && acc_type_read && crc_cnt_31)
1010 
    ptr <= #1 ptr + 1'b1;
1011 
  else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
1012 
    ptr <= ptr + 1'd1;
1013 
end
1014 
always @ (posedge tck_i or posedge rst_i)
1015 
begin
1016 
  if (rst_i)
1017 
    begin
1018 
      latch_data <= #1 1'b0;
1019 
      dr <= #1 {(3'd4 + 6'd32 + 5'd16){1'b0}};
1020 
    end
1021 
  else if (curr_cmd_rd_comm && crc_cnt_31)
1022 
    begin
1023 
      dr[3'd4 + 6'd32 + 5'd16 -1:0] <= #1 {acc_type, adr, len};
1024 
    end
1025 
  else if (acc_type_read && curr_cmd_go && crc_cnt_31)
1026 
    begin
1027 
      dr[31:0] <= #1 input_data[31:0];
1028 
      latch_data <= #1 1'b1;
1029 
    end
1030 
  else if (acc_type_read && curr_cmd_go && crc_cnt_end)
1031 
    begin
1032 
      if (acc_type == 4'h4)
1033 
        begin
1034 
          if(byte & (~byte_q))
1035 
            begin
1036 
              case (ptr)
1037 
                2'b00 : dr[31:24] <= #1 input_data[31:24];
1038 
                2'b01 : dr[31:24] <= #1 input_data[23:16];
1039 
                2'b10 : dr[31:24] <= #1 input_data[15:8];
1040 
                2'b11 : dr[31:24] <= #1 input_data[7:0];
1041 
              endcase
1042 
              latch_data <= #1 1'b1;
1043 
            end
1044 
          else
1045 
            begin
1046 
              dr[31:24] <= #1 {dr[30:24], 1'b0};
1047 
              latch_data <= #1 1'b0;
1048 
            end
1049 
        end
1050 
      else if (acc_type == 4'h5)
1051 
        begin
1052 
          if(half & (~half_q))
1053 
            begin
1054 
              if (ptr[1])
1055 
                dr[31:16] <= #1 input_data[15:0];
1056 
              else
1057 
                dr[31:16] <= #1 input_data[31:16];
1058 
              latch_data <= #1 1'b1;
1059 
            end
1060 
          else
1061 
            begin
1062 
              dr[31:16] <= #1 {dr[30:16], 1'b0};
1063 
              latch_data <= #1 1'b0;
1064 
            end
1065 
        end
1066 
      else if (acc_type == 4'h6)
1067 
        begin
1068 
          if(long & (~long_q))
1069 
            begin
1070 
              dr[31:0] <= #1 input_data[31:0];
1071 
              latch_data <= #1 1'b1;
1072 
            end
1073 
          else
1074 
            begin
1075 
              dr[31:0] <= #1 {dr[30:0], 1'b0};
1076 
              latch_data <= #1 1'b0;
1077 
            end
1078 
        end
1079 
    end
1080 
  else if (enable && (!addr_len_cnt_end))
1081 
    begin
1082 
      dr <= #1 {dr[(3'd4 + 6'd32 + 5'd16) -2:0], tdi_i};
1083 
    end
1084 
end
1085 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
1086 
always @ (posedge tck_i or posedge rst_i)
1087 
begin
1088 
  if (rst_i)
1089 
    cmd_cnt <= #1 {3{1'b0}};
1090 
  else if (update_dr_i)
1091 
    cmd_cnt <= #1 {3{1'b0}};
1092 
  else if (cmd_cnt_en)
1093 
    cmd_cnt <= #1 cmd_cnt + 1'b1;
1094 
end
1095 
always @ (posedge tck_i or posedge rst_i)
1096 
begin
1097 
  if (rst_i)
1098 
    curr_cmd <= #1 {3'd4{1'b0}};
1099 
  else if (update_dr_i)
1100 
    curr_cmd <= #1 {3'd4{1'b0}};
1101 
  else if (cmd_cnt == (3'd4 -1))
1102 
    curr_cmd <= #1 {dr[3'd4-2 :0], tdi_i};
1103 
end
1104 
always @ (posedge tck_i or posedge rst_i)
1105 
begin
1106 
  if (rst_i)
1107 
    curr_cmd_go_q <= #1 1'b0;
1108 
  else
1109 
    curr_cmd_go_q <= #1 curr_cmd_go;
1110 
end
1111 
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
1112 
begin
1113 
  if (enable && (!addr_len_cnt_end))
1114 
    begin
1115 
      if (cmd_cnt_end && curr_cmd_wr_comm)
1116 
        addr_len_cnt_en = 1'b1;
1117 
      else if (crc_cnt_end && curr_cmd_rd_comm)
1118 
        addr_len_cnt_en = 1'b1;
1119 
      else
1120 
        addr_len_cnt_en = 1'b0;
1121 
    end
1122 
  else
1123 
    addr_len_cnt_en = 1'b0;
1124 
end
1125 
always @ (posedge tck_i or posedge rst_i)
1126 
begin
1127 
  if (rst_i)
1128 
    addr_len_cnt <= #1 6'h0;
1129 
  else if (update_dr_i)
1130 
    addr_len_cnt <= #1 6'h0;
1131 
  else if (addr_len_cnt_en)
1132 
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
1133 
end
1134 
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
1135 
begin
1136 
  if (enable && (!data_cnt_end))
1137 
    begin
1138 
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
1139 
        data_cnt_en = 1'b1;
1140 
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
1141 
        data_cnt_en = 1'b1;
1142 
      else
1143 
        data_cnt_en = 1'b0;
1144 
    end
1145 
  else
1146 
    data_cnt_en = 1'b0;
1147 
end
1148 
always @ (posedge tck_i or posedge rst_i)
1149 
begin
1150 
  if (rst_i)
1151 
    data_cnt <= #1 {(5'd16 + 3){1'b0}};
1152 
  else if (update_dr_i)
1153 
    data_cnt <= #1 {(5'd16 + 3){1'b0}};
1154 
  else if (data_cnt_en)
1155 
    data_cnt <= #1 data_cnt + 1'b1;
1156 
end
1157 
always @ (posedge tck_i or posedge rst_i)
1158 
begin
1159 
  if (rst_i)
1160 
    data_cnt_limit <= #1 {5'd16{1'b0}};
1161 
  else if (update_dr_i)
1162 
    data_cnt_limit <= #1 len + 1'b1;
1163 
end
1164 
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
1165 
begin
1166 
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
1167 
    begin
1168 
      if (addr_len_cnt_end && curr_cmd_wr_comm)
1169 
        crc_cnt_en = 1'b1;
1170 
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
1171 
        crc_cnt_en = 1'b1;
1172 
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
1173 
        crc_cnt_en = 1'b1;
1174 
      else
1175 
        crc_cnt_en = 1'b0;
1176 
    end
1177 
  else
1178 
    crc_cnt_en = 1'b0;
1179 
end
1180 
always @ (posedge tck_i or posedge rst_i)
1181 
begin
1182 
  if (rst_i)
1183 
    crc_cnt <= #1 {6{1'b0}};
1184 
  else if(crc_cnt_en)
1185 
    crc_cnt <= #1 crc_cnt + 1'b1;
1186 
  else if (update_dr_i)
1187 
    crc_cnt <= #1 {6{1'b0}};
1188 
end
1189 
assign cmd_cnt_end      = cmd_cnt      == 3'd4;
1190 
assign addr_len_cnt_end = addr_len_cnt == (3'd4 + 6'd32 + 5'd16);
1191 
assign crc_cnt_end      = crc_cnt      == 6'd32;
1192 
assign crc_cnt_31       = crc_cnt      == 6'd31;
1193 
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
1194 
always @ (posedge tck_i or posedge rst_i)
1195 
begin
1196 
  if (rst_i)
1197 
    begin
1198 
      crc_cnt_end_q       <= #1 1'b0;
1199 
      cmd_cnt_end_q       <= #1 1'b0;
1200 
      data_cnt_end_q      <= #1 1'b0;
1201 
      addr_len_cnt_end_q  <= #1 1'b0;
1202 
    end
1203 
  else
1204 
    begin
1205 
      crc_cnt_end_q       <= #1 crc_cnt_end;
1206 
      cmd_cnt_end_q       <= #1 cmd_cnt_end;
1207 
      data_cnt_end_q      <= #1 data_cnt_end;
1208 
      addr_len_cnt_end_q  <= #1 addr_len_cnt_end;
1209 
    end
1210 
end
1211 
always @ (posedge tck_i or posedge rst_i)
1212 
begin
1213 
  if (rst_i)
1214 
    status_cnt <= #1 {3{1'b0}};
1215 
  else if (update_dr_i)
1216 
    status_cnt <= #1 {3{1'b0}};
1217 
  else if (status_cnt_en)
1218 
    status_cnt <= #1 status_cnt + 1'b1;
1219 
end
1220 
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
1221 
begin
1222 
  if (enable && (!status_cnt_end))
1223 
    begin
1224 
      if (crc_cnt_end && curr_cmd_wr_comm)
1225 
        status_cnt_en = 1'b1;
1226 
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
1227 
        status_cnt_en = 1'b1;
1228 
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
1229 
        status_cnt_en = 1'b1;
1230 
      else if (addr_len_cnt_end && curr_cmd_rd_comm)
1231 
        status_cnt_en = 1'b1;
1232 
      else
1233 
        status_cnt_en = 1'b0;
1234 
    end
1235 
  else
1236 
    status_cnt_en = 1'b0;
1237 
end
1238 
assign status_cnt_end = status_cnt == 3'd4;
1239 
always @ (posedge tck_i or posedge rst_i)
1240 
begin
1241 
  if (rst_i)
1242 
    begin
1243 
      acc_type  <= #1 {3'd4{1'b0}};
1244 
      adr       <= #1 {6'd32{1'b0}};
1245 
      len       <= #1 {5'd16{1'b0}};
1246 
      set_addr  <= #1 1'b0;
1247 
    end
1248 
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
1249 
    begin
1250 
      acc_type  <= #1 dr[3'd4 + 6'd32 + 5'd16 -1 : 6'd32 + 5'd16];
1251 
      adr       <= #1 dr[6'd32 + 5'd16 -1 : 5'd16];
1252 
      len       <= #1 dr[5'd16 -1:0];
1253 
      set_addr  <= #1 1'b1;
1254 
    end
1255 
  else if(wb_end_tck)
1256 
    begin
1257 
      adr  <= #1 wb_adr_dsff;
1258 
    end
1259 
  else
1260 
    set_addr <= #1 1'b0;
1261 
end
1262 
always @ (posedge tck_i or posedge rst_i)
1263 
begin
1264 
  if (rst_i)
1265 
    crc_match_reg <= #1 1'b0;
1266 
  else if(crc_cnt_end & (~crc_cnt_end_q))
1267 
    crc_match_reg <= #1 crc_match_i;
1268 
end
1269 
always @ (posedge tck_i or posedge rst_i)
1270 
begin
1271 
  if (rst_i)
1272 
    len_var <= #1 {1'b0, {5'd16{1'b0}}};
1273 
  else if(update_dr_i)
1274 
    len_var <= #1 len + 1'b1;
1275 
  else if (start_rd_tck)
1276 
    begin
1277 
      case (acc_type)
1278 
        4'h4 :
1279 
                    if (len_var > 'd1)
1280 
                      len_var <= #1 len_var - 1'd1;
1281 
                    else
1282 
                      len_var <= #1 {1'b0, {5'd16{1'b0}}};
1283 
        4'h5:
1284 
                    if (len_var > 'd2)
1285 
                      len_var <= #1 len_var - 2'd2;
1286 
                    else
1287 
                      len_var <= #1 {1'b0, {5'd16{1'b0}}};
1288 
        4'h6:
1289 
                    if (len_var > 'd4)
1290 
                      len_var <= #1 len_var - 3'd4;
1291 
                    else
1292 
                      len_var <= #1 {1'b0, {5'd16{1'b0}}};
1293 
        default:      len_var <= #1 {1'bx, {5'd16{1'bx}}};
1294 
      endcase
1295 
    end
1296 
end
1297 
assign len_eq_0 = len_var == 'h0;
1298 
assign byte = data_cnt[2:0] == 3'd7;
1299 
assign half = data_cnt[3:0] == 4'd15;
1300 
assign long = data_cnt[4:0] == 5'd31;
1301 
always @ (posedge tck_i or posedge rst_i)
1302 
begin
1303 
  if (rst_i)
1304 
    begin
1305 
      byte_q <= #1  1'b0;
1306 
      half_q <= #1  1'b0;
1307 
      long_q <= #1  1'b0;
1308 
    end
1309 
  else
1310 
    begin
1311 
      byte_q <= #1 byte;
1312 
      half_q <= #1 half;
1313 
      long_q <= #1 long;
1314 
    end
1315 
end
1316 
always @ (posedge tck_i or posedge rst_i)
1317 
begin
1318 
  if (rst_i)
1319 
    begin
1320 
      start_wr_tck <= #1 1'b0;
1321 
      wb_dat_tmp <= #1 32'h0;
1322 
    end
1323 
  else if (curr_cmd_go && acc_type_write)
1324 
    begin
1325 
      case (acc_type)
1326 
        4'h0  : begin
1327 
                        if (byte_q)
1328 
                          begin
1329 
                            start_wr_tck <= #1 1'b1;
1330 
                            wb_dat_tmp <= #1 {4{dr[7:0]}};
1331 
                          end
1332 
                        else
1333 
                          begin
1334 
                            start_wr_tck <= #1 1'b0;
1335 
                          end
1336 
                      end
1337 
        4'h1 : begin
1338 
                        if (half_q)
1339 
                          begin
1340 
                            start_wr_tck <= #1 1'b1;
1341 
                            wb_dat_tmp <= #1 {2{dr[15:0]}};
1342 
                          end
1343 
                        else
1344 
                          begin
1345 
                            start_wr_tck <= #1 1'b0;
1346 
                          end
1347 
                      end
1348 
        4'h2 : begin
1349 
                        if (long_q)
1350 
                          begin
1351 
                            start_wr_tck <= #1 1'b1;
1352 
                            wb_dat_tmp <= #1 dr[31:0];
1353 
                          end
1354 
                        else
1355 
                          begin
1356 
                            start_wr_tck <= #1 1'b0;
1357 
                          end
1358 
                      end
1359 
      endcase
1360 
    end
1361 
  else
1362 
    start_wr_tck <= #1 1'b0;
1363 
end
1364 
always @ (posedge wb_clk_i)
1365 
begin
1366 
  wb_dat_dsff <= #1 wb_dat_tmp;
1367 
end
1368 
assign wb_dat_o = wb_dat_dsff;
1369 
always @ (posedge tck_i or posedge rst_i)
1370 
begin
1371 
  if (rst_i)
1372 
    start_rd_tck <= #1 1'b0;
1373 
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
1374 
    start_rd_tck <= #1 1'b1;
1375 
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
1376 
    start_rd_tck <= #1 1'b1;
1377 
  else
1378 
    start_rd_tck <= #1 1'b0;
1379 
end
1380 
always @ (posedge tck_i or posedge rst_i)
1381 
begin
1382 
  if (rst_i)
1383 
    rd_tck_started <= #1 1'b0;
1384 
  else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
1385 
    rd_tck_started <= #1 1'b0;
1386 
  else if (start_rd_tck)
1387 
    rd_tck_started <= #1 1'b1;
1388 
end
1389 
always @ (posedge wb_clk_i or posedge rst_i)
1390 
begin
1391 
  if (rst_i)
1392 
    begin
1393 
      start_rd_csff   <= #1 1'b0;
1394 
      start_wb_rd     <= #1 1'b0;
1395 
      start_wb_rd_q   <= #1 1'b0;
1396 
      start_wr_csff   <= #1 1'b0;
1397 
      start_wb_wr     <= #1 1'b0;
1398 
      start_wb_wr_q   <= #1 1'b0;
1399 
      set_addr_csff   <= #1 1'b0;
1400 
      set_addr_wb     <= #1 1'b0;
1401 
      set_addr_wb_q   <= #1 1'b0;
1402 
    end
1403 
  else
1404 
    begin
1405 
      start_rd_csff   <= #1 start_rd_tck;
1406 
      start_wb_rd     <= #1 start_rd_csff;
1407 
      start_wb_rd_q   <= #1 start_wb_rd;
1408 
      start_wr_csff   <= #1 start_wr_tck;
1409 
      start_wb_wr     <= #1 start_wr_csff;
1410 
      start_wb_wr_q   <= #1 start_wb_wr;
1411 
      set_addr_csff   <= #1 set_addr;
1412 
      set_addr_wb     <= #1 set_addr_csff;
1413 
      set_addr_wb_q   <= #1 set_addr_wb;
1414 
    end
1415 
end
1416 
always @ (posedge wb_clk_i or posedge rst_i)
1417 
begin
1418 
  if (rst_i)
1419 
    wb_cyc_o <= #1 1'b0;
1420 
  else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
1421 
    wb_cyc_o <= #1 1'b1;
1422 
  else if (wb_ack_i || wb_err_i)
1423 
    wb_cyc_o <= #1 1'b0;
1424 
end
1425 
always @ (posedge wb_clk_i or posedge rst_i)
1426 
begin
1427 
  if (rst_i)
1428 
    wb_adr_dsff <= #1 32'h0;
1429 
  else if (set_addr_wb && (!set_addr_wb_q))
1430 
    wb_adr_dsff <= #1 adr;
1431 
  else if (wb_ack_i)
1432 
    begin
1433 
      if ((acc_type == 4'h0) || (acc_type == 4'h4))
1434 
        wb_adr_dsff <= #1 wb_adr_dsff + 1'd1;
1435 
      else if ((acc_type == 4'h1) || (acc_type == 4'h5))
1436 
        wb_adr_dsff <= #1 wb_adr_dsff + 2'd2;
1437 
      else
1438 
        wb_adr_dsff <= #1 wb_adr_dsff + 3'd4;
1439 
    end
1440 
end
1441 
assign wb_adr_o = wb_adr_dsff;
1442 
always @ (posedge wb_clk_i or posedge rst_i)
1443 
begin
1444 
  if (rst_i)
1445 
    wb_sel_dsff[3:0] <= #1 4'h0;
1446 
  else
1447 
    begin
1448 
      case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit})
1449 
        {2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8;
1450 
        {2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC;
1451 
        {2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF;
1452 
        {2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4;
1453 
        {2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2;
1454 
        {2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3;
1455 
        {2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1;
1456 
        default:         wb_sel_dsff[3:0] <= #1 4'hx;
1457 
      endcase
1458 
    end
1459 
end
1460 
assign wb_sel_o = wb_sel_dsff;
1461 
always @ (posedge wb_clk_i)
1462 
begin
1463 
  wb_we_dsff <= #1 curr_cmd_go && acc_type_write;
1464 
end
1465 
assign wb_we_o = wb_we_dsff;
1466 
assign wb_cab_o = 1'b0;
1467 
assign wb_stb_o = wb_cyc_o;
1468 
assign wb_cti_o = 3'h0;
1469 
assign wb_bte_o = 2'h0;
1470 
always @ (posedge wb_clk_i or posedge rst_i)
1471 
begin
1472 
  if (rst_i)
1473 
    wb_end <= #1 1'b0;
1474 
  else if (wb_ack_i || wb_err_i)
1475 
    wb_end <= #1 1'b1;
1476 
  else if (wb_end_rst)
1477 
    wb_end <= #1 1'b0;
1478 
end
1479 
always @ (posedge tck_i or posedge rst_i)
1480 
begin
1481 
  if (rst_i)
1482 
    begin
1483 
      wb_end_csff  <= #1 1'b0;
1484 
      wb_end_tck   <= #1 1'b0;
1485 
      wb_end_tck_q <= #1 1'b0;
1486 
    end
1487 
  else
1488 
    begin
1489 
      wb_end_csff  <= #1 wb_end;
1490 
      wb_end_tck   <= #1 wb_end_csff;
1491 
      wb_end_tck_q <= #1 wb_end_tck;
1492 
    end
1493 
end
1494 
always @ (posedge wb_clk_i or posedge rst_i)
1495 
begin
1496 
  if (rst_i)
1497 
    begin
1498 
      wb_end_rst_csff <= #1 1'b0;
1499 
      wb_end_rst      <= #1 1'b0;
1500 
    end
1501 
  else
1502 
    begin
1503 
      wb_end_rst_csff <= #1 wb_end_tck;
1504 
      wb_end_rst      <= #1 wb_end_rst_csff;
1505 
    end
1506 
end
1507 
always @ (posedge wb_clk_i or posedge rst_i)
1508 
begin
1509 
  if (rst_i)
1510 
    busy_wb <= #1 1'b0;
1511 
  else if (wb_end_rst)
1512 
    busy_wb <= #1 1'b0;
1513 
  else if (wb_cyc_o)
1514 
    busy_wb <= #1 1'b1;
1515 
end
1516 
always @ (posedge tck_i or posedge rst_i)
1517 
begin
1518 
  if (rst_i)
1519 
    begin
1520 
      busy_csff       <= #1 1'b0;
1521 
      busy_tck        <= #1 1'b0;
1522 
      update_dr_csff  <= #1 1'b0;
1523 
      update_dr_wb    <= #1 1'b0;
1524 
    end
1525 
  else
1526 
    begin
1527 
      busy_csff       <= #1 busy_wb;
1528 
      busy_tck        <= #1 busy_csff;
1529 
      update_dr_csff  <= #1 update_dr_i;
1530 
      update_dr_wb    <= #1 update_dr_csff;
1531 
    end
1532 
end
1533 
always @ (posedge wb_clk_i or posedge rst_i)
1534 
begin
1535 
  if (rst_i)
1536 
    wb_error <= #1 1'b0;
1537 
  else if(wb_err_i)
1538 
    wb_error <= #1 1'b1;
1539 
  else if(update_dr_wb)
1540 
    wb_error <= #1 1'b0;
1541 
end
1542 
always @ (posedge wb_clk_i or posedge rst_i)
1543 
begin
1544 
  if (rst_i)
1545 
    wb_overrun <= #1 1'b0;
1546 
  else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
1547 
    wb_overrun <= #1 1'b1;
1548 
  else if(update_dr_wb)
1549 
    wb_overrun <= #1 1'b0;
1550 
end
1551 
always @ (posedge tck_i or posedge rst_i)
1552 
begin
1553 
  if (rst_i)
1554 
    underrun_tck <= #1 1'b0;
1555 
  else if(latch_data && fifo_empty && (!data_cnt_end))
1556 
    underrun_tck <= #1 1'b1;
1557 
  else if(update_dr_i)
1558 
    underrun_tck <= #1 1'b0;
1559 
end
1560 
always @ (posedge tck_i or posedge rst_i)
1561 
begin
1562 
  if (rst_i)
1563 
    begin
1564 
      wb_error_csff   <= #1 1'b0;
1565 
      wb_error_tck    <= #1 1'b0;
1566 
      wb_overrun_csff <= #1 1'b0;
1567 
      wb_overrun_tck  <= #1 1'b0;
1568 
    end
1569 
  else
1570 
    begin
1571 
      wb_error_csff   <= #1 wb_error;
1572 
      wb_error_tck    <= #1 wb_error_csff;
1573 
      wb_overrun_csff <= #1 wb_overrun;
1574 
      wb_overrun_tck  <= #1 wb_overrun_csff;
1575 
    end
1576 
end
1577 
always @ (posedge wb_clk_i or posedge rst_i)
1578 
begin
1579 
  if (rst_i)
1580 
    begin
1581 
      wishbone_ce_csff  <= #1 1'b0;
1582 
      mem_ptr_init      <= #1 1'b0;
1583 
    end
1584 
  else
1585 
    begin
1586 
      wishbone_ce_csff  <= #1  wishbone_ce_i;
1587 
      mem_ptr_init      <= #1 ~wishbone_ce_csff;
1588 
    end
1589 
end
1590 
always @ (posedge wb_clk_i or posedge rst_i)
1591 
begin
1592 
  if (rst_i)
1593 
    mem_ptr_dsff <= #1 3'h0;
1594 
  else if(mem_ptr_init)
1595 
    mem_ptr_dsff <= #1 3'h0;
1596 
  else if (wb_ack_i)
1597 
    begin
1598 
      if (acc_type == 4'h4)
1599 
        mem_ptr_dsff <= #1 mem_ptr_dsff + 1'd1;
1600 
      else if (acc_type == 4'h5)
1601 
        mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
1602 
    end
1603 
end
1604 
always @ (posedge wb_clk_i)
1605 
begin
1606 
  if (wb_ack_i)
1607 
    begin
1608 
      case (wb_sel_dsff)
1609 
        4'b1000  :  mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
1610 
        4'b0100  :  mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16];
1611 
        4'b0010  :  mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
1612 
        4'b0001  :  mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00];
1613 
        4'b1100  :
1614 
                    begin
1615 
                      mem[mem_ptr_dsff[1:0]]      <= #1 wb_dat_i[31:24];
1616 
                      mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
1617 
                    end
1618 
        4'b0011  :
1619 
                    begin
1620 
                      mem[mem_ptr_dsff[1:0]]      <= #1 wb_dat_i[15:08];
1621 
                      mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
1622 
                    end
1623 
        4'b1111  :
1624 
                    begin
1625 
                      mem[0] <= #1 wb_dat_i[31:24];
1626 
                      mem[1] <= #1 wb_dat_i[23:16];
1627 
                      mem[2] <= #1 wb_dat_i[15:08];
1628 
                      mem[3] <= #1 wb_dat_i[07:00];
1629 
                    end
1630 
        default  :
1631 
                    begin
1632 
                      mem[0] <= #1 8'hxx;
1633 
                      mem[1] <= #1 8'hxx;
1634 
                      mem[2] <= #1 8'hxx;
1635 
                      mem[3] <= #1 8'hxx;
1636 
                    end
1637 
      endcase
1638 
    end
1639 
end
1640 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
1641 
always @ (posedge tck_i or posedge rst_i)
1642 
begin
1643 
  if (rst_i)
1644 
    fifo_cnt <= #1 3'h0;
1645 
  else if (update_dr_i)
1646 
    fifo_cnt <= #1 3'h0;
1647 
  else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full))
1648 
    begin
1649 
      case (acc_type)
1650 
        4'h4 : fifo_cnt <= #1 fifo_cnt + 1'd1;
1651 
        4'h5: fifo_cnt <= #1 fifo_cnt + 2'd2;
1652 
        4'h6: fifo_cnt <= #1 fifo_cnt + 3'd4;
1653 
        default:        fifo_cnt <= #1 3'bxxx;
1654 
      endcase
1655 
    end
1656 
  else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty))
1657 
    begin
1658 
      case (acc_type)
1659 
        4'h4 : fifo_cnt <= #1 fifo_cnt - 1'd1;
1660 
        4'h5: fifo_cnt <= #1 fifo_cnt - 2'd2;
1661 
        4'h6: fifo_cnt <= #1 fifo_cnt - 3'd4;
1662 
        default:        fifo_cnt <= #1 3'bxxx;
1663 
      endcase
1664 
    end
1665 
end
1666 
assign fifo_full  = fifo_cnt == 3'h4;
1667 
assign fifo_empty = fifo_cnt == 3'h0;
1668 
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
1669 
          curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
1670 
          or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
1671 
          or addr_len_cnt_end or addr_len_cnt_end_q)
1672 
begin
1673 
  if (pause_dr_i)
1674 
    begin
1675 
    tdo_o = busy_tck;
1676 
    end
1677 
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
1678 
    begin
1679 
      tdo_o = ~crc_match_i;
1680 
    end
1681 
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
1682 
    begin
1683 
      tdo_o = dr[31];
1684 
    end
1685 
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
1686 
    begin
1687 
      tdo_o = ~crc_match_reg;
1688 
    end
1689 
  else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
1690 
    begin
1691 
      tdo_o = ~crc_match_reg;
1692 
    end
1693 
  else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
1694 
    begin
1695 
      tdo_o = dr[3'd4 + 6'd32 + 5'd16 -1];
1696 
    end
1697 
  else if (status_cnt_en)
1698 
    begin
1699 
      tdo_o = status[3];
1700 
    end
1701 
  else
1702 
    begin
1703 
      tdo_o = 1'b0;
1704 
    end
1705 
end
1706 
always @ (posedge tck_i or posedge rst_i)
1707 
begin
1708 
  if (rst_i)
1709 
    begin
1710 
    status <= #1 {3'd4{1'b0}};
1711 
    end
1712 
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
1713 
    begin
1714 
    status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
1715 
    end
1716 
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
1717 
    begin
1718 
    status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
1719 
    end
1720 
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
1721 
    begin
1722 
    status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
1723 
    end
1724 
  else if (shift_dr_i && (!status_cnt_end))
1725 
    begin
1726 
    status <= #1 {status[3'd4 -2:0], status[3'd4 -1]};
1727 
    end
1728 
end
1729 
endmodule
1730 
`timescale 1ns/10ps
1731 
module dbg_top(
1732 
                tck_i,
1733 
                tdi_i,
1734 
                tdo_o,
1735 
                rst_i,
1736 
                shift_dr_i,
1737 
                pause_dr_i,
1738 
                update_dr_i,
1739 
                debug_select_i
1740 
                ,
1741 
                wb_clk_i,
1742 
                wb_adr_o,
1743 
                wb_dat_o,
1744 
                wb_dat_i,
1745 
                wb_cyc_o,
1746 
                wb_stb_o,
1747 
                wb_sel_o,
1748 
                wb_we_o,
1749 
                wb_ack_i,
1750 
                wb_cab_o,
1751 
                wb_err_i,
1752 
                wb_cti_o,
1753 
                wb_bte_o
1754 
                ,
1755 
                cpu0_clk_i,
1756 
                cpu0_addr_o,
1757 
                cpu0_data_i,
1758 
                cpu0_data_o,
1759 
                cpu0_bp_i,
1760 
                cpu0_stall_o,
1761 
                cpu0_stb_o,
1762 
                cpu0_we_o,
1763 
                cpu0_ack_i,
1764 
                cpu0_rst_o
1765 
              );
1766 
input   tck_i;
1767 
input   tdi_i;
1768 
output  tdo_o;
1769 
input   rst_i;
1770 
input   shift_dr_i;
1771 
input   pause_dr_i;
1772 
input   update_dr_i;
1773 
input   debug_select_i;
1774 
input         wb_clk_i;
1775 
output [31:0] wb_adr_o;
1776 
output [31:0] wb_dat_o;
1777 
input  [31:0] wb_dat_i;
1778 
output        wb_cyc_o;
1779 
output        wb_stb_o;
1780 
output  [3:0] wb_sel_o;
1781 
output        wb_we_o;
1782 
input         wb_ack_i;
1783 
output        wb_cab_o;
1784 
input         wb_err_i;
1785 
output  [2:0] wb_cti_o;
1786 
output  [1:0] wb_bte_o;
1787 
reg           wishbone_module;
1788 
reg           wishbone_ce;
1789 
wire          tdi_wb;
1790 
wire          tdo_wb;
1791 
wire          crc_en_wb;
1792 
wire          shift_crc_wb;
1793 
input         cpu0_clk_i;
1794 
output [31:0] cpu0_addr_o;
1795 
input  [31:0] cpu0_data_i;
1796 
output [31:0] cpu0_data_o;
1797 
input         cpu0_bp_i;
1798 
output        cpu0_stall_o;
1799 
output        cpu0_stb_o;
1800 
output        cpu0_we_o;
1801 
input         cpu0_ack_i;
1802 
output        cpu0_rst_o;
1803 
reg           cpu0_debug_module;
1804 
reg           cpu0_ce;
1805 
wire          cpu0_tdi;
1806 
wire          cpu0_tdo;
1807 
wire          cpu0_crc_en;
1808 
wire          cpu0_shift_crc;
1809 
wire          cpu1_crc_en = 1'b0;
1810 
wire          cpu1_shift_crc = 1'b0;
1811 
reg [3 -1:0]        data_cnt;
1812 
reg [6 -1:0]         crc_cnt;
1813 
reg [3 -1:0]      status_cnt;
1814 
reg [4 + 1 -1:0]  module_dr;
1815 
reg [4 -1:0] module_id;
1816 
wire module_latch_en;
1817 
wire data_cnt_end;
1818 
wire crc_cnt_end;
1819 
wire status_cnt_end;
1820 
reg  crc_cnt_end_q;
1821 
reg  module_select;
1822 
reg  module_select_error;
1823 
wire crc_out;
1824 
wire crc_match;
1825 
wire data_shift_en;
1826 
wire selecting_command;
1827 
reg tdo_o;
1828 
wire shift_crc;
1829 
always @ (posedge tck_i or posedge rst_i)
1830 
begin
1831 
  if (rst_i)
1832 
    data_cnt <= #1 {3{1'b0}};
1833 
  else if(shift_dr_i & (~data_cnt_end))
1834 
    data_cnt <= #1 data_cnt + 1'b1;
1835 
  else if (update_dr_i)
1836 
    data_cnt <= #1 {3{1'b0}};
1837 
end
1838 
assign data_cnt_end = data_cnt == 4 + 1;
1839 
always @ (posedge tck_i or posedge rst_i)
1840 
begin
1841 
  if (rst_i)
1842 
    crc_cnt <= #1 {6{1'b0}};
1843 
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
1844 
    crc_cnt <= #1 crc_cnt + 1'b1;
1845 
  else if (update_dr_i)
1846 
    crc_cnt <= #1 {6{1'b0}};
1847 
end
1848 
assign crc_cnt_end = crc_cnt == 32;
1849 
always @ (posedge tck_i or posedge rst_i)
1850 
begin
1851 
  if (rst_i)
1852 
    crc_cnt_end_q  <= #1 1'b0;
1853 
  else
1854 
    crc_cnt_end_q  <= #1 crc_cnt_end;
1855 
end
1856 
always @ (posedge tck_i or posedge rst_i)
1857 
begin
1858 
  if (rst_i)
1859 
    status_cnt <= #1 {3{1'b0}};
1860 
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
1861 
    status_cnt <= #1 status_cnt + 1'b1;
1862 
  else if (update_dr_i)
1863 
    status_cnt <= #1 {3{1'b0}};
1864 
end
1865 
assign status_cnt_end = status_cnt == 3'd4;
1866 
assign selecting_command = shift_dr_i & (data_cnt == 3'h0) & debug_select_i;
1867 
always @ (posedge tck_i or posedge rst_i)
1868 
begin
1869 
  if (rst_i)
1870 
    module_select <= #1 1'b0;
1871 
  else if(selecting_command & tdi_i)
1872 
    module_select <= #1 1'b1;
1873 
  else if (update_dr_i)
1874 
    module_select <= #1 1'b0;
1875 
end
1876 
always @ (module_id)
1877 
begin
1878 
  cpu0_debug_module  <= #1 1'b0;
1879 
  wishbone_module   <= #1 1'b0;
1880 
  module_select_error    <= #1 1'b0;
1881 
  case (module_id)
1882 
      4'h1     :   cpu0_debug_module   <= #1 1'b1;
1883 
      4'h0 :   wishbone_module     <= #1 1'b1;
1884 
    default                          :   module_select_error <= #1 1'b1;
1885 
  endcase
1886 
end
1887 
assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
1888 
always @ (posedge tck_i or posedge rst_i)
1889 
begin
1890 
  if (rst_i)
1891 
    module_id <= {4{1'b1}};
1892 
  else if(module_latch_en & crc_match)
1893 
    module_id <= #1 module_dr[4 + 1 -2:0];
1894 
end
1895 
assign data_shift_en = shift_dr_i & (~data_cnt_end);
1896 
always @ (posedge tck_i or posedge rst_i)
1897 
begin
1898 
  if (rst_i)
1899 
    module_dr <= #1 4 + 1'h0;
1900 
  else if (data_shift_en)
1901 
    module_dr[4 + 1 -1:0] <= #1 {module_dr[4 + 1 -2:0], tdi_i};
1902 
end
1903 
dbg_crc32_d1 i_dbg_crc32_d1_in
1904 
             (
1905 
              .data       (tdi_i),
1906 
              .enable     (shift_dr_i),
1907 
              .shift      (1'b0),
1908 
              .rst        (rst_i),
1909 
              .sync_rst   (update_dr_i),
1910 
              .crc_out    (),
1911 
              .clk        (tck_i),
1912 
              .crc_match  (crc_match)
1913 
             );
1914 
reg tdo_module_select;
1915 
wire crc_en;
1916 
wire crc_en_dbg;
1917 
reg crc_started;
1918 
assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
1919 
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
1920 
always @ (posedge tck_i or posedge rst_i)
1921 
begin
1922 
  if (rst_i)
1923 
    crc_started <= #1 1'b0;
1924 
  else if (crc_en)
1925 
    crc_started <= #1 1'b1;
1926 
  else if (update_dr_i)
1927 
    crc_started <= #1 1'b0;
1928 
end
1929 
reg tdo_tmp;
1930 
dbg_crc32_d1 i_dbg_crc32_d1_out
1931 
             (
1932 
              .data       (tdo_tmp),
1933 
              .enable     (crc_en),
1934 
              .shift      (shift_dr_i & crc_started & (~crc_en)),
1935 
              .rst        (rst_i),
1936 
              .sync_rst   (update_dr_i),
1937 
              .crc_out    (crc_out),
1938 
              .clk        (tck_i),
1939 
              .crc_match  ()
1940 
             );
1941 
always @ (status_cnt or crc_match or module_select_error or crc_out)
1942 
begin
1943 
  case (status_cnt)
1944 
    3'd0  : begin
1945 
                        tdo_module_select = ~crc_match;
1946 
                      end
1947 
    3'd1  : begin
1948 
                        tdo_module_select = module_select_error;
1949 
                      end
1950 
    3'd2  : begin
1951 
                        tdo_module_select = 1'b0;
1952 
                      end
1953 
    3'd3  : begin
1954 
                        tdo_module_select = 1'b0;
1955 
                      end
1956 
    3'd4  : begin
1957 
                        tdo_module_select = crc_out;
1958 
                      end
1959 
     default : begin    tdo_module_select = 1'b0; end
1960 
  endcase
1961 
end
1962 
assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
1963 
always @ (shift_crc or crc_out or tdo_module_select
1964 
 or wishbone_ce or tdo_wb
1965 
 or cpu0_ce or cpu0_tdo
1966 
         )
1967 
begin
1968 
  if (shift_crc)
1969 
    tdo_tmp = crc_out;
1970 
  else if (wishbone_ce)
1971 
    tdo_tmp = tdo_wb;
1972 
  else if (cpu0_ce)
1973 
    tdo_tmp = cpu0_tdo;
1974 
  else
1975 
    tdo_tmp = tdo_module_select;
1976 
end
1977 
always @ (negedge tck_i)
1978 
begin
1979 
  tdo_o <= #1 tdo_tmp;
1980 
end
1981 
always @ (posedge tck_i or posedge rst_i)
1982 
begin
1983 
  if (rst_i)
1984 
    begin
1985 
      wishbone_ce <= #1 1'b0;
1986 
      cpu0_ce <= #1 1'b0;
1987 
    end
1988 
  else if(selecting_command & (~tdi_i))
1989 
    begin
1990 
      if (wishbone_module)
1991 
        wishbone_ce <= #1 1'b1;
1992 
      if (cpu0_debug_module)
1993 
        cpu0_ce <= #1 1'b1;
1994 
    end
1995 
  else if (update_dr_i)
1996 
    begin
1997 
      wishbone_ce <= #1 1'b0;
1998 
      cpu0_ce <= #1 1'b0;
1999 
    end
2000 
end
2001 
assign tdi_wb  = wishbone_ce & tdi_i;
2002 
assign cpu0_tdi = cpu0_ce & tdi_i;
2003 
dbg_wb i_dbg_wb (
2004 
                  .tck_i            (tck_i),
2005 
                  .tdi_i            (tdi_wb),
2006 
                  .tdo_o            (tdo_wb),
2007 
                  .shift_dr_i       (shift_dr_i),
2008 
                  .pause_dr_i       (pause_dr_i),
2009 
                  .update_dr_i      (update_dr_i),
2010 
                  .wishbone_ce_i    (wishbone_ce),
2011 
                  .crc_match_i      (crc_match),
2012 
                  .crc_en_o         (crc_en_wb),
2013 
                  .shift_crc_o      (shift_crc_wb),
2014 
                  .rst_i            (rst_i),
2015 
                  .wb_clk_i         (wb_clk_i),
2016 
                  .wb_adr_o         (wb_adr_o),
2017 
                  .wb_dat_o         (wb_dat_o),
2018 
                  .wb_dat_i         (wb_dat_i),
2019 
                  .wb_cyc_o         (wb_cyc_o),
2020 
                  .wb_stb_o         (wb_stb_o),
2021 
                  .wb_sel_o         (wb_sel_o),
2022 
                  .wb_we_o          (wb_we_o),
2023 
                  .wb_ack_i         (wb_ack_i),
2024 
                  .wb_cab_o         (wb_cab_o),
2025 
                  .wb_err_i         (wb_err_i),
2026 
                  .wb_cti_o         (wb_cti_o),
2027 
                  .wb_bte_o         (wb_bte_o)
2028 
            );
2029 
dbg_cpu i_dbg_cpu_or1k (
2030 
                  .tck_i            (tck_i),
2031 
                  .tdi_i            (cpu0_tdi),
2032 
                  .tdo_o            (cpu0_tdo),
2033 
                  .shift_dr_i       (shift_dr_i),
2034 
                  .pause_dr_i       (pause_dr_i),
2035 
                  .update_dr_i      (update_dr_i),
2036 
                  .cpu_ce_i         (cpu0_ce),
2037 
                  .crc_match_i      (crc_match),
2038 
                  .crc_en_o         (cpu0_crc_en),
2039 
                  .shift_crc_o      (cpu0_shift_crc),
2040 
                  .rst_i            (rst_i),
2041 
                  .cpu_clk_i        (cpu0_clk_i),
2042 
                  .cpu_addr_o       (cpu0_addr_o),
2043 
                  .cpu_data_i       (cpu0_data_i),
2044 
                  .cpu_data_o       (cpu0_data_o),
2045 
                  .cpu_bp_i         (cpu0_bp_i),
2046 
                  .cpu_stall_o      (cpu0_stall_o),
2047 
                  .cpu_stb_o        (cpu0_stb_o),
2048 
                  .cpu_we_o         (cpu0_we_o),
2049 
                  .cpu_ack_i        (cpu0_ack_i),
2050 
                  .cpu_rst_o        (cpu0_rst_o)
2051 
              );
2052 
endmodule

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