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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_cop.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_cop.v,v $
// Revision 1.4  2003/06/13 11:55:37  mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.3  2002/10/10 16:43:59  mohor
// Minor $display change.
//
// Revision 1.2  2002/09/09 12:54:13  mohor
// error acknowledge cycle termination added to display.
//
// Revision 1.1  2002/08/14 17:16:07  mohor
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
// interfaces:
// - Host connects to the master interface
// - Ethernet master (DMA) connects to the second master interface
// - Memory interface connects to the slave interface
// - Ethernet slave interface (access to registers and BDs) connects to second
//   slave interface
//
//
//
//
//
 
`include "eth_defines.v"
`include "timescale.v"
 
module eth_cop
(
  // WISHBONE common
  wb_clk_i, wb_rst_i,
 
  // WISHBONE MASTER 1
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
  m1_wb_err_o,
 
  // WISHBONE MASTER 2
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
  m2_wb_err_o,
 
  // WISHBONE slave 1
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
        s1_wb_dat_o,
 
  // WISHBONE slave 2
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_dat_o
);
 
parameter Tp=1;
 
// WISHBONE common
input wb_clk_i, wb_rst_i;
 
// WISHBONE MASTER 1
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
input   [3:0] m1_wb_sel_i;
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output        m1_wb_ack_o, m1_wb_err_o;
 
// WISHBONE MASTER 2
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
input   [3:0] m2_wb_sel_i;
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output        m2_wb_ack_o, m2_wb_err_o;
 
// WISHBONE slave 1
input  [31:0] s1_wb_dat_i;
input         s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output  [3:0] s1_wb_sel_o;
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
 
// WISHBONE slave 2
input  [31:0] s2_wb_dat_i;
input         s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output  [3:0] s2_wb_sel_o;
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
 
reg           m1_in_progress;
reg           m2_in_progress;
reg    [31:0] s1_wb_adr_o;
reg     [3:0] s1_wb_sel_o;
reg           s1_wb_we_o;
reg    [31:0] s1_wb_dat_o;
reg           s1_wb_cyc_o;
reg           s1_wb_stb_o;
reg    [31:0] s2_wb_adr_o;
reg     [3:0] s2_wb_sel_o;
reg           s2_wb_we_o;
reg    [31:0] s2_wb_dat_o;
reg           s2_wb_cyc_o;
reg           s2_wb_stb_o;
 
reg           m1_wb_ack_o;
reg    [31:0] m1_wb_dat_o;
reg           m2_wb_ack_o;
reg    [31:0] m2_wb_dat_o;
 
reg           m1_wb_err_o;
reg           m2_wb_err_o;
 
   // Added to allow compilation with Verilator
   wire       M1_ADDRESSED_S1_wire;
   assign M1_ADDRESSED_S1_wire = `M1_ADDRESSED_S1;
   wire       M1_ADDRESSED_S2_wire;
   assign M1_ADDRESSED_S2_wire = `M1_ADDRESSED_S2;
   wire       M2_ADDRESSED_S1_wire;
   assign M2_ADDRESSED_S1_wire = `M2_ADDRESSED_S1;
   wire       M2_ADDRESSED_S2_wire;
   assign M2_ADDRESSED_S2_wire = `M2_ADDRESSED_S2;
 
 
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (M1_ADDRESSED_S1_wire | M1_ADDRESSED_S2_wire);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (M2_ADDRESSED_S1_wire | M2_ADDRESSED_S2_wire);
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      m1_in_progress <=#Tp 0;
      m2_in_progress <=#Tp 0;
      s1_wb_adr_o    <=#Tp 0;
      s1_wb_sel_o    <=#Tp 0;
      s1_wb_we_o     <=#Tp 0;
      s1_wb_dat_o    <=#Tp 0;
      s1_wb_cyc_o    <=#Tp 0;
      s1_wb_stb_o    <=#Tp 0;
      s2_wb_adr_o    <=#Tp 0;
      s2_wb_sel_o    <=#Tp 0;
      s2_wb_we_o     <=#Tp 0;
      s2_wb_dat_o    <=#Tp 0;
      s2_wb_cyc_o    <=#Tp 0;
      s2_wb_stb_o    <=#Tp 0;
    end
  else
    begin
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
        5'b00_10_0, 5'b00_11_0 :
          begin
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
            if(M1_ADDRESSED_S1_wire)
              begin
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
                s1_wb_we_o  <=#Tp m1_wb_we_i;
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(M1_ADDRESSED_S2_wire)
              begin
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
                s2_wb_we_o  <=#Tp m1_wb_we_i;
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b00_01_0 :
          begin
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
            if(M2_ADDRESSED_S1_wire)
              begin
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
                s1_wb_we_o  <=#Tp m2_wb_we_i;
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(M2_ADDRESSED_S2_wire)
              begin
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
                s2_wb_we_o  <=#Tp m2_wb_we_i;
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b10_10_1, 5'b10_11_1 :
          begin
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
            if(M1_ADDRESSED_S1_wire)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(M1_ADDRESSED_S2_wire)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
        5'b01_01_1, 5'b01_11_1 :
          begin
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
            if(M2_ADDRESSED_S1_wire)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(M2_ADDRESSED_S2_wire)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
      endcase
    end
end
 
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M1_ADDRESSED_S1_wire or M1_ADDRESSED_S2_wire)
begin
  if(m1_in_progress)
    begin
      if(M1_ADDRESSED_S1_wire) begin
        m1_wb_ack_o <= s1_wb_ack_i;
        m1_wb_dat_o <= s1_wb_dat_i;
      end
      else if(M1_ADDRESSED_S2_wire) begin
        m1_wb_ack_o <= s2_wb_ack_i;
        m1_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m1_wb_ack_o <= 0;
end
 
 
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire)
begin
  if(m2_in_progress)
    begin
      if(M2_ADDRESSED_S1_wire) begin
        m2_wb_ack_o <= s1_wb_ack_i;
        m2_wb_dat_o <= s1_wb_dat_i;
      end
      else if(M2_ADDRESSED_S2_wire) begin
        m2_wb_ack_o <= s2_wb_ack_i;
        m2_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m2_wb_ack_o <= 0;
end
 
 
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or
          m1_wb_cyc_i or m1_wb_stb_i)
begin
  if(m1_in_progress)  begin
    if(M1_ADDRESSED_S1_wire)
      m1_wb_err_o <= s1_wb_err_i;
    else if(M1_ADDRESSED_S2_wire)
      m1_wb_err_o <= s2_wb_err_i;
  end
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~M1_ADDRESSED_S1_wire & ~M1_ADDRESSED_S2_wire)
    m1_wb_err_o <= 1'b1;
  else
    m1_wb_err_o <= 1'b0;
end
 
 
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or
          m2_wb_cyc_i or m2_wb_stb_i)
begin
  if(m2_in_progress)  begin
    if(M2_ADDRESSED_S1_wire)
      m2_wb_err_o <= s1_wb_err_i;
    else if(M2_ADDRESSED_S2_wire)
      m2_wb_err_o <= s2_wb_err_i;
  end
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~M2_ADDRESSED_S1_wire & ~M2_ADDRESSED_S2_wire)
    m2_wb_err_o <= 1'b1;
  else
    m2_wb_err_o <= 1'b0;
end
 
 
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
 
 
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_cyc_o | s2_wb_cyc_o)
    cnt <=#Tp cnt+1;
end
 
always @ (posedge wb_clk_i)
begin
  if(cnt==1000) begin
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
    if(s1_wb_cyc_o) begin
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    end
    else if(s2_wb_cyc_o) begin
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    end
 
    $stop;
  end
end
 
 
always @ (posedge wb_clk_i)
begin
  if(s1_wb_err_i & s1_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    $stop;
  end
  if(s2_wb_err_i & s2_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    $stop;
  end
end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	18	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_cop.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: eth_cop.v,v $`
44			`// Revision 1.4 2003/06/13 11:55:37 mohor`
45			`// Define file in eth_cop.v is changed to eth_defines.v. Some defines were`
46			`// moved from tb_eth_defines.v to eth_defines.v.`
47			`//`
48			`// Revision 1.3 2002/10/10 16:43:59 mohor`
49			`// Minor $display change.`
50			`//`
51			`// Revision 1.2 2002/09/09 12:54:13 mohor`
52			`// error acknowledge cycle termination added to display.`
53			`//`
54			`// Revision 1.1 2002/08/14 17:16:07 mohor`
55			`// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave`
56			`// interfaces:`
57			`// - Host connects to the master interface`
58			`// - Ethernet master (DMA) connects to the second master interface`
59			`// - Memory interface connects to the slave interface`
60			`// - Ethernet slave interface (access to registers and BDs) connects to second`
61			`// slave interface`
62			`//`
63			`//`
64			`//`
65			`//`
66			`//`
67
68			`include "eth_defines.v"
69			`include "timescale.v"
70
71			`module eth_cop`
72			`(`
73			`// WISHBONE common`
74			`wb_clk_i, wb_rst_i,`
75
76			`// WISHBONE MASTER 1`
77			`m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,`
78			`m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,`
79			`m1_wb_err_o,`
80
81			`// WISHBONE MASTER 2`
82			`m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,`
83			`m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,`
84			`m2_wb_err_o,`
85
86			`// WISHBONE slave 1`
87			`s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,`
88			`s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,`
89			`s1_wb_dat_o,`
90
91			`// WISHBONE slave 2`
92			`s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,`
93			`s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,`
94			`s2_wb_dat_o`
95			`);`
96
97			`parameter Tp=1;`
98
99			`// WISHBONE common`
100			`input wb_clk_i, wb_rst_i;`
101
102			`// WISHBONE MASTER 1`
103			`input [31:0] m1_wb_adr_i, m1_wb_dat_i;`
104			`input [3:0] m1_wb_sel_i;`
105			`input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;`
106			`output [31:0] m1_wb_dat_o;`
107			`output m1_wb_ack_o, m1_wb_err_o;`
108
109			`// WISHBONE MASTER 2`
110			`input [31:0] m2_wb_adr_i, m2_wb_dat_i;`
111			`input [3:0] m2_wb_sel_i;`
112			`input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;`
113			`output [31:0] m2_wb_dat_o;`
114			`output m2_wb_ack_o, m2_wb_err_o;`
115
116			`// WISHBONE slave 1`
117			`input [31:0] s1_wb_dat_i;`
118			`input s1_wb_ack_i, s1_wb_err_i;`
119			`output [31:0] s1_wb_adr_o, s1_wb_dat_o;`
120			`output [3:0] s1_wb_sel_o;`
121			`output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;`
122
123			`// WISHBONE slave 2`
124			`input [31:0] s2_wb_dat_i;`
125			`input s2_wb_ack_i, s2_wb_err_i;`
126			`output [31:0] s2_wb_adr_o, s2_wb_dat_o;`
127			`output [3:0] s2_wb_sel_o;`
128			`output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;`
129
130			`reg m1_in_progress;`
131			`reg m2_in_progress;`
132			`reg [31:0] s1_wb_adr_o;`
133			`reg [3:0] s1_wb_sel_o;`
134			`reg s1_wb_we_o;`
135			`reg [31:0] s1_wb_dat_o;`
136			`reg s1_wb_cyc_o;`
137			`reg s1_wb_stb_o;`
138			`reg [31:0] s2_wb_adr_o;`
139			`reg [3:0] s2_wb_sel_o;`
140			`reg s2_wb_we_o;`
141			`reg [31:0] s2_wb_dat_o;`
142			`reg s2_wb_cyc_o;`
143			`reg s2_wb_stb_o;`
144
145			`reg m1_wb_ack_o;`
146			`reg [31:0] m1_wb_dat_o;`
147			`reg m2_wb_ack_o;`
148			`reg [31:0] m2_wb_dat_o;`
149
150			`reg m1_wb_err_o;`
151			`reg m2_wb_err_o;`
152
153	42	julius	`// Added to allow compilation with Verilator`
154			`wire M1_ADDRESSED_S1_wire;`
155			assign M1_ADDRESSED_S1_wire = `M1_ADDRESSED_S1;
156			`wire M1_ADDRESSED_S2_wire;`
157			assign M1_ADDRESSED_S2_wire = `M1_ADDRESSED_S2;
158			`wire M2_ADDRESSED_S1_wire;`
159			assign M2_ADDRESSED_S1_wire = `M2_ADDRESSED_S1;
160			`wire M2_ADDRESSED_S2_wire;`
161			assign M2_ADDRESSED_S2_wire = `M2_ADDRESSED_S2;
162
163
164	18	unneback	`wire m_wb_access_finished;`
165	42	julius	`wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (M1_ADDRESSED_S1_wire \| M1_ADDRESSED_S2_wire);`
166			`wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (M2_ADDRESSED_S1_wire \| M2_ADDRESSED_S2_wire);`
167	18	unneback
168			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
169			`begin`
170			`if(wb_rst_i)`
171			`begin`
172			`m1_in_progress <=#Tp 0;`
173			`m2_in_progress <=#Tp 0;`
174			`s1_wb_adr_o <=#Tp 0;`
175			`s1_wb_sel_o <=#Tp 0;`
176			`s1_wb_we_o <=#Tp 0;`
177			`s1_wb_dat_o <=#Tp 0;`
178			`s1_wb_cyc_o <=#Tp 0;`
179			`s1_wb_stb_o <=#Tp 0;`
180			`s2_wb_adr_o <=#Tp 0;`
181			`s2_wb_sel_o <=#Tp 0;`
182			`s2_wb_we_o <=#Tp 0;`
183			`s2_wb_dat_o <=#Tp 0;`
184			`s2_wb_cyc_o <=#Tp 0;`
185			`s2_wb_stb_o <=#Tp 0;`
186			`end`
187			`else`
188			`begin`
189			`case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case`
190			`5'b00_10_0, 5'b00_11_0 :`
191			`begin`
192			`m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m`
193	42	julius	`if(M1_ADDRESSED_S1_wire)`
194	18	unneback	`begin`
195			`s1_wb_adr_o <=#Tp m1_wb_adr_i;`
196			`s1_wb_sel_o <=#Tp m1_wb_sel_i;`
197			`s1_wb_we_o <=#Tp m1_wb_we_i;`
198			`s1_wb_dat_o <=#Tp m1_wb_dat_i;`
199			`s1_wb_cyc_o <=#Tp 1'b1;`
200			`s1_wb_stb_o <=#Tp 1'b1;`
201			`end`
202	42	julius	`else if(M1_ADDRESSED_S2_wire)`
203	18	unneback	`begin`
204			`s2_wb_adr_o <=#Tp m1_wb_adr_i;`
205			`s2_wb_sel_o <=#Tp m1_wb_sel_i;`
206			`s2_wb_we_o <=#Tp m1_wb_we_i;`
207			`s2_wb_dat_o <=#Tp m1_wb_dat_i;`
208			`s2_wb_cyc_o <=#Tp 1'b1;`
209			`s2_wb_stb_o <=#Tp 1'b1;`
210			`end`
211			`else`
212			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
213			`end`
214			`5'b00_01_0 :`
215			`begin`
216			`m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m`
217	42	julius	`if(M2_ADDRESSED_S1_wire)`
218	18	unneback	`begin`
219			`s1_wb_adr_o <=#Tp m2_wb_adr_i;`
220			`s1_wb_sel_o <=#Tp m2_wb_sel_i;`
221			`s1_wb_we_o <=#Tp m2_wb_we_i;`
222			`s1_wb_dat_o <=#Tp m2_wb_dat_i;`
223			`s1_wb_cyc_o <=#Tp 1'b1;`
224			`s1_wb_stb_o <=#Tp 1'b1;`
225			`end`
226	42	julius	`else if(M2_ADDRESSED_S2_wire)`
227	18	unneback	`begin`
228			`s2_wb_adr_o <=#Tp m2_wb_adr_i;`
229			`s2_wb_sel_o <=#Tp m2_wb_sel_i;`
230			`s2_wb_we_o <=#Tp m2_wb_we_i;`
231			`s2_wb_dat_o <=#Tp m2_wb_dat_i;`
232			`s2_wb_cyc_o <=#Tp 1'b1;`
233			`s2_wb_stb_o <=#Tp 1'b1;`
234			`end`
235			`else`
236			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
237			`end`
238			`5'b10_10_1, 5'b10_11_1 :`
239			`begin`
240			`m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.`
241	42	julius	`if(M1_ADDRESSED_S1_wire)`
242	18	unneback	`begin`
243			`s1_wb_cyc_o <=#Tp 1'b0;`
244			`s1_wb_stb_o <=#Tp 1'b0;`
245			`end`
246	42	julius	`else if(M1_ADDRESSED_S2_wire)`
247	18	unneback	`begin`
248			`s2_wb_cyc_o <=#Tp 1'b0;`
249			`s2_wb_stb_o <=#Tp 1'b0;`
250			`end`
251			`end`
252			`5'b01_01_1, 5'b01_11_1 :`
253			`begin`
254			`m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.`
255	42	julius	`if(M2_ADDRESSED_S1_wire)`
256	18	unneback	`begin`
257			`s1_wb_cyc_o <=#Tp 1'b0;`
258			`s1_wb_stb_o <=#Tp 1'b0;`
259			`end`
260	42	julius	`else if(M2_ADDRESSED_S2_wire)`
261	18	unneback	`begin`
262			`s2_wb_cyc_o <=#Tp 1'b0;`
263			`s2_wb_stb_o <=#Tp 1'b0;`
264			`end`
265			`end`
266			`endcase`
267			`end`
268			`end`
269
270			`// Generating Ack for master 1`
271	42	julius	`always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M1_ADDRESSED_S1_wire or M1_ADDRESSED_S2_wire)`
272	18	unneback	`begin`
273			`if(m1_in_progress)`
274			`begin`
275	42	julius	`if(M1_ADDRESSED_S1_wire) begin`
276	18	unneback	`m1_wb_ack_o <= s1_wb_ack_i;`
277			`m1_wb_dat_o <= s1_wb_dat_i;`
278			`end`
279	42	julius	`else if(M1_ADDRESSED_S2_wire) begin`
280	18	unneback	`m1_wb_ack_o <= s2_wb_ack_i;`
281			`m1_wb_dat_o <= s2_wb_dat_i;`
282			`end`
283			`end`
284			`else`
285			`m1_wb_ack_o <= 0;`
286			`end`
287
288
289			`// Generating Ack for master 2`
290	42	julius	`always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire)`
291	18	unneback	`begin`
292			`if(m2_in_progress)`
293			`begin`
294	42	julius	`if(M2_ADDRESSED_S1_wire) begin`
295	18	unneback	`m2_wb_ack_o <= s1_wb_ack_i;`
296			`m2_wb_dat_o <= s1_wb_dat_i;`
297			`end`
298	42	julius	`else if(M2_ADDRESSED_S2_wire) begin`
299	18	unneback	`m2_wb_ack_o <= s2_wb_ack_i;`
300			`m2_wb_dat_o <= s2_wb_dat_i;`
301			`end`
302			`end`
303			`else`
304			`m2_wb_ack_o <= 0;`
305			`end`
306
307
308			`// Generating Err for master 1`
309	42	julius	`always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or`
310	18	unneback	`m1_wb_cyc_i or m1_wb_stb_i)`
311			`begin`
312			`if(m1_in_progress) begin`
313	42	julius	`if(M1_ADDRESSED_S1_wire)`
314	18	unneback	`m1_wb_err_o <= s1_wb_err_i;`
315	42	julius	`else if(M1_ADDRESSED_S2_wire)`
316	18	unneback	`m1_wb_err_o <= s2_wb_err_i;`
317			`end`
318	42	julius	`else if(m1_wb_cyc_i & m1_wb_stb_i & ~M1_ADDRESSED_S1_wire & ~M1_ADDRESSED_S2_wire)`
319	18	unneback	`m1_wb_err_o <= 1'b1;`
320			`else`
321			`m1_wb_err_o <= 1'b0;`
322			`end`
323
324
325			`// Generating Err for master 2`
326	42	julius	`always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or`
327	18	unneback	`m2_wb_cyc_i or m2_wb_stb_i)`
328			`begin`
329			`if(m2_in_progress) begin`
330	42	julius	`if(M2_ADDRESSED_S1_wire)`
331	18	unneback	`m2_wb_err_o <= s1_wb_err_i;`
332	42	julius	`else if(M2_ADDRESSED_S2_wire)`
333	18	unneback	`m2_wb_err_o <= s2_wb_err_i;`
334			`end`
335	42	julius	`else if(m2_wb_cyc_i & m2_wb_stb_i & ~M2_ADDRESSED_S1_wire & ~M2_ADDRESSED_S2_wire)`
336	18	unneback	`m2_wb_err_o <= 1'b1;`
337			`else`
338			`m2_wb_err_o <= 1'b0;`
339			`end`
340
341
342			`assign m_wb_access_finished = m1_wb_ack_o \| m1_wb_err_o \| m2_wb_ack_o \| m2_wb_err_o;`
343
344
345			`// Activity monitor`
346			`integer cnt;`
347			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
348			`begin`
349			`if(wb_rst_i)`
350			`cnt <=#Tp 0;`
351			`else`
352			`if(s1_wb_ack_i \| s1_wb_err_i \| s2_wb_ack_i \| s2_wb_err_i)`
353			`cnt <=#Tp 0;`
354			`else`
355			`if(s1_wb_cyc_o \| s2_wb_cyc_o)`
356			`cnt <=#Tp cnt+1;`
357			`end`
358
359			`always @ (posedge wb_clk_i)`
360			`begin`
361			`if(cnt==1000) begin`
362			`$display("(%0t)(%m) ERROR: WB activity ??? ", $time);`
363			`if(s1_wb_cyc_o) begin`
364			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
365			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
366			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
367			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
368			`end`
369			`else if(s2_wb_cyc_o) begin`
370			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
371			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
372			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
373			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
374			`end`
375
376			`$stop;`
377			`end`
378			`end`
379
380
381			`always @ (posedge wb_clk_i)`
382			`begin`
383			`if(s1_wb_err_i & s1_wb_cyc_o) begin`
384			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
385			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
386			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
387			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
388			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
389			`$stop;`
390			`end`
391			`if(s2_wb_err_i & s2_wb_cyc_o) begin`
392			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
393			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
394			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
395			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
396			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
397			`$stop;`
398			`end`
399			`end`
400
401
402
403			`endmodule`

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