URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1200r2/] [or1200_immu_tlb.v] - Blame information for rev 42

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction TLB                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of ITLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 1.9  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6  2002/10/28 16:34:32  mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4  2002/08/14 06:23:50  lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Insn TLB
//
 
module or1200_immu_tlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:`OR1200_IMMU_PS]    ppn;
output                          uxe;
output                          sxe;
output                          ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [`OR1200_ITLB_TAG]      vpn;
wire                            v;
wire    [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_in;
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_out;
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_in;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_out;
 
// BIST
`ifdef OR1200_BIST
wire                        itlb_mr_ram_si;
wire                        itlb_mr_ram_so;
wire                        itlb_tr_ram_si;
wire                        itlb_tr_ram_so;
`endif
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19  v 0
// itlbwYtrX: ppn 31-13  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
            {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
                        {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
                        spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
 
 
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
 
 
//
// Instantiation of ITLB Match Registers
//
   or1200_spram #
     (
      .aw(6),
      .dw(14)
      )
   itlb_mr_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_mr_ram_si),
      .mbist_so_o(itlb_mr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_mr_en),
      .we(tlb_mr_we),
      //.oe(1'b1),
      .addr(tlb_index),
      .di(tlb_mr_ram_in),
      .doq(tlb_mr_ram_out)
      );
 
//
// Instantiation of ITLB Translate Registers
//
   or1200_spram #
     (
      .aw(6),
      .dw(22)
      )
   itlb_tr_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_tr_ram_si),
      .mbist_so_o(itlb_tr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_tr_en),
      .we(tlb_tr_we),
      //.oe(1'b1),
      .addr(tlb_index),
      .di(tlb_tr_ram_in),
      .doq(tlb_tr_ram_out)
      );
 
endmodule

Browse

Tools

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1200r2/] [or1200_immu_tlb.v] - Blame information for rev 42

Line No.	Rev	Author	Line
1	18	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of ITLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_immu_tlb.v,v $`
47			`// Revision 1.9 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.8 2004/04/05 08:29:57 lampret`
51			`// Merged branch_qmem into main tree.`
52			`//`
53			`// Revision 1.6.4.1 2003/12/09 11:46:48 simons`
54			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
55			`//`
56			`// Revision 1.6 2002/10/28 16:34:32 mohor`
57			`// RAMs wrong connected to the BIST scan chain.`
58			`//`
59			`// Revision 1.5 2002/10/17 20:04:40 lampret`
60			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
61			`//`
62			`// Revision 1.4 2002/08/14 06:23:50 lampret`
63			`// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.`
64			`//`
65			`// Revision 1.3 2002/02/11 04:33:17 lampret`
66			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
67			`//`
68			`// Revision 1.2 2002/01/28 01:16:00 lampret`
69			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
70			`//`
71			`// Revision 1.1 2002/01/03 08:16:15 lampret`
72			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
73			`//`
74			`// Revision 1.8 2001/10/21 17:57:16 lampret`
75			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
76			`//`
77			`// Revision 1.7 2001/10/14 13:12:09 lampret`
78			`// MP3 version.`
79			`//`
80			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
81			`// no message`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`//`
91			`// Insn TLB`
92			`//`
93
94			`module or1200_immu_tlb(`
95			`// Rst and clk`
96			`clk, rst,`
97
98			`// I/F for translation`
99			`tlb_en, vaddr, hit, ppn, uxe, sxe, ci,`
100
101			`ifdef OR1200_BIST
102			`// RAM BIST`
103			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
104			`endif
105
106			`// SPR access`
107			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
108			`);`
109
110			parameter dw = `OR1200_OPERAND_WIDTH;
111			parameter aw = `OR1200_OPERAND_WIDTH;
112
113			`//`
114			`// I/O`
115			`//`
116
117			`//`
118			`// Clock and reset`
119			`//`
120			`input clk;`
121			`input rst;`
122
123			`//`
124			`// I/F for translation`
125			`//`
126			`input tlb_en;`
127			`input [aw-1:0] vaddr;`
128			`output hit;`
129			output [31:`OR1200_IMMU_PS] ppn;
130			`output uxe;`
131			`output sxe;`
132			`output ci;`
133
134			`ifdef OR1200_BIST
135			`//`
136			`// RAM BIST`
137			`//`
138			`input mbist_si_i;`
139			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
140			`output mbist_so_o;`
141			`endif
142
143			`//`
144			`// SPR access`
145			`//`
146			`input spr_cs;`
147			`input spr_write;`
148			`input [31:0] spr_addr;`
149			`input [31:0] spr_dat_i;`
150			`output [31:0] spr_dat_o;`
151
152			`//`
153			`// Internal wires and regs`
154			`//`
155			wire [`OR1200_ITLB_TAG] vpn;
156			`wire v;`
157			wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
158			`wire tlb_mr_en;`
159			`wire tlb_mr_we;`
160			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
161			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
162			`wire tlb_tr_en;`
163			`wire tlb_tr_we;`
164			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
165			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
166
167			`// BIST`
168			`ifdef OR1200_BIST
169			`wire itlb_mr_ram_si;`
170			`wire itlb_mr_ram_so;`
171			`wire itlb_tr_ram_si;`
172			`wire itlb_tr_ram_so;`
173			`endif
174
175			`//`
176			`// Implemented bits inside match and translate registers`
177			`//`
178			`// itlbwYmrX: vpn 31-19 v 0`
179			`// itlbwYtrX: ppn 31-13 uxe 7 sxe 6`
180			`//`
181			`// itlb memory width:`
182			`// 19 bits for ppn`
183			`// 13 bits for vpn`
184			`// 1 bit for valid`
185			`// 2 bits for protection`
186			`// 1 bit for cache inhibit`
187
188			`//`
189			`// Enable for Match registers`
190			`//`
191			assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
192
193			`//`
194			`// Write enable for Match registers`
195			`//`
196			assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
197
198			`//`
199			`// Enable for Translate registers`
200			`//`
201			assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
202
203			`//`
204			`// Write enable for Translate registers`
205			`//`
206			assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
207
208			`//`
209			`// Output to SPRS unit`
210			`//`
211			assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
212			{vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
213			(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
214			{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
215			`32'h00000000;`
216
217			`//`
218			`// Assign outputs from Match registers`
219			`//`
220			`assign {vpn, v} = tlb_mr_ram_out;`
221
222			`//`
223			`// Assign to Match registers inputs`
224			`//`
225			assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
226
227			`//`
228			`// Assign outputs from Translate registers`
229			`//`
230			`assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;`
231
232			`//`
233			`// Assign to Translate registers inputs`
234			`//`
235			assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
236			spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
237			spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
238			spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
239
240			`//`
241			`// Generate hit`
242			`//`
243			assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
244
245			`//`
246			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
247			`// spr_addr[5:0].`
248			`//`
249			assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
250
251
252			`ifdef OR1200_BIST
253			`assign itlb_mr_ram_si = mbist_si_i;`
254			`assign itlb_tr_ram_si = itlb_mr_ram_so;`
255			`assign mbist_so_o = itlb_tr_ram_so;`
256			`endif
257
258
259			`//`
260			`// Instantiation of ITLB Match Registers`
261			`//`
262			`or1200_spram #`
263			`(`
264			`.aw(6),`
265			`.dw(14)`
266			`)`
267			`itlb_mr_ram`
268			`(`
269			`.clk(clk),`
270			`ifdef OR1200_BIST
271			`// RAM BIST`
272			`.mbist_si_i(itlb_mr_ram_si),`
273			`.mbist_so_o(itlb_mr_ram_so),`
274			`.mbist_ctrl_i(mbist_ctrl_i),`
275			`endif
276			`.ce(tlb_mr_en),`
277			`.we(tlb_mr_we),`
278			`//.oe(1'b1),`
279			`.addr(tlb_index),`
280			`.di(tlb_mr_ram_in),`
281			`.doq(tlb_mr_ram_out)`
282			`);`
283
284			`//`
285			`// Instantiation of ITLB Translate Registers`
286			`//`
287			`or1200_spram #`
288			`(`
289			`.aw(6),`
290			`.dw(22)`
291			`)`
292			`itlb_tr_ram`
293			`(`
294			`.clk(clk),`
295			`ifdef OR1200_BIST
296			`// RAM BIST`
297			`.mbist_si_i(itlb_tr_ram_si),`
298			`.mbist_so_o(itlb_tr_ram_so),`
299			`.mbist_ctrl_i(mbist_ctrl_i),`
300			`endif
301			`.ce(tlb_tr_en),`
302			`.we(tlb_tr_we),`
303			`//.oe(1'b1),`
304			`.addr(tlb_index),`
305			`.di(tlb_tr_ram_in),`
306			`.doq(tlb_tr_ram_out)`
307			`);`
308
309			`endmodule`