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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_top/] [Makefile] - Blame information for rev 18

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ba12_ip:
        cat ../../ba12/rtl/verilog/ba12_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1k_top_ip.v
 
or1200_ip:
        cat ../../or1200/rtl/verilog/or1200_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1200.v
 
or1200r2_ip:
        cat ../../or1200r2/rtl/verilog/or1200_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1200r2.v
 
all: or1200_ip or1200r2_ip ba12_ip

Line No.	Rev	Author	Line
1	18	unneback	`ba12_ip:`
2			`cat ../../ba12/rtl/verilog/ba12_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1k_top_ip.v`
3
4			`or1200_ip:`
5			`cat ../../or1200/rtl/verilog/or1200_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1200.v`
6
7			`or1200r2_ip:`
8			`cat ../../or1200r2/rtl/verilog/or1200_top_ip.v ../../debug_if/rtl/verilog/dbg_top_ip.v ../../tap/rtl/verilog/tap_ip.v or1k_top.v > or1200r2.v`
9
10			`all: or1200_ip or1200r2_ip ba12_ip`

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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_top/] [Makefile] - Blame information for rev 18