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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [smii/] [smii_txrx.v] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SMII                                                        ////
////                                                              ////
////  Description                                                 ////
////  Low pin count serial MII ethernet interface                 ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB          michael.unneback@orsoc.se           ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module smii_txrx
  (
   // SMII
    output     tx,
    input      rx,
   // MII
   // TX
    input [3:0] mtxd,
    input       mtxen,
    input       mtxerr,
    output      mtx_clk,
   // RX
    output reg [3:0] mrxd,
    output reg   mrxdv,
    output reg   mrxerr,
    output       mrx_clk,
    output       mcoll,
    output reg   mcrs,
`ifdef SMII_SPEED
    output reg   speed,
`endif
`ifdef SMII_DUPLEX
    output reg   duplex,
`endif
`ifdef SMII_LINK
    output reg   link,
`endif
   // internal
    input [1:10] state,
   // clock and reset
    input        clk,
    input        rst
   );
 
   reg [0:7]              tx_data_reg;
   reg                   tx_data_reg_valid;
   reg                   a0;
   reg                   state_data;
 
   reg [3:0]      rx_tmp;
 
`ifndef SMII_SPEED
   reg           speed;
`endif
`ifndef SMII_DUPLEX
   reg           duplex;
`endif
`ifndef SMII_LINK
   reg           link;
`endif
   reg           jabber;
 
   reg           mtx_clk_tmp, mrx_clk_tmp;
 
   reg [3:0]      tx_cnt;
   reg [3:0]      rx_cnt;
 
   /////////////////////////////////////////////////
   // Speed
 
   always @ (posedge clk or posedge rst)
     if (rst)
       tx_cnt <= 4'd0;
     else
       if (speed)
         tx_cnt <= 4'd0;
       else if (state[10])
         if (tx_cnt == 4'd9)
           tx_cnt <= 4'd0;
         else
           tx_cnt <= tx_cnt + 4'd1;
 
   /////////////////////////////////////////////////
   // Transmit
 
     always @ (posedge clk or posedge rst)
     if (rst)
       mtx_clk_tmp <= 1'b0;
     else
       if ((state[10] | state[5]) & (tx_cnt == 4'd0))
         mtx_clk_tmp <= 1'b1;
       else if (state[2] | state[7])
         mtx_clk_tmp <= 1'b0;
 
`ifdef ACTEL
   gbuf bufg1
     (
      .CLK(mtx_clk_tmp),
      .GL(mtx_clk)
      );
`else
   assign #1 mtx_clk = mtx_clk_tmp;
`endif
 
   // storage of data from MII
   always @ (posedge clk or posedge rst)
     if (rst)
       begin
          tx_data_reg <= 8'd0;
          tx_data_reg_valid <= 1'b0;
          a0 <= 1'b0;
       end
     else
       if ((state[4] | state[9]) & (tx_cnt == 4'd0))
         begin
            if (!mtxen)
              a0 <= 1'b0;
            else
              a0 <= ~a0;
            if (!mtxen & !a0)
              tx_data_reg_valid <= 1'b0;
            else if (a0)
              tx_data_reg_valid <= 1'b1;
            if (mtxen & !a0)
              tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
            else if (mtxen & a0)
              tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
         end // if ((state[4] | state[9]) & (tx_cnt == 4'd0))
 
 
   // state flag
   always @ (posedge clk or posedge rst)
     if (rst)
       state_data <= 1'b0;
     else
       if (state[1] & (tx_cnt == 4'd0))
         state_data <= tx_data_reg_valid;
 
   assign tx = state[1] ? mtxerr :
               state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
               state_data ? |(state[2:10] & tx_data_reg) :
               |(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
 
   /////////////////////////////////////////////////
   // Receive
 
   always @ (posedge clk or posedge rst)
     if (rst)
       rx_cnt <= 4'd0;
     else
       if (speed)
         rx_cnt <= 4'd0;
       else if (!mrxdv & state[8] & rx_tmp[3])
         rx_cnt <= 4'd9;
       else if (state[10])
         if (rx_cnt == 4'd9)
           rx_cnt <= 4'd0;
         else
           rx_cnt <= rx_cnt + 4'd1;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       begin
          {mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;
          rx_tmp <= 4'h0;
          mrxd <= 4'h0;
       end
     else
       begin
          rx_tmp[2:0] <= {rx,rx_tmp[2:1]};
          if (state[3])
            mcrs <= rx;
          if (state[4])
            rx_tmp[3] <= rx;
          if (rx_tmp[3]) //rxdv
            begin
               if (state[8])
                 {mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};
               else if (state[2])
                 mrxd <= #1 {rx,rx_tmp[2:0]};
            end
          else
            begin
               if (state[5])
                 mrxerr <= #1 rx;
               if (state[6])
                 speed <= #1 rx;
               if (state[7])
                 duplex <= #1 rx;
               if (state[8])
                 begin
                    link <= #1 rx;
                    mrxdv <= #1 1'b0;
                 end
               if (state[9])
                 jabber <= #1 rx;
            end
       end // else: !if(rst)
 
   always @ (posedge clk or posedge rst)
     if (rst)
       mrx_clk_tmp <= 1'b0;
     else
       if ((state[1] | state[6]) & (rx_cnt == 4'd0))
         mrx_clk_tmp <= 1'b1;
       else if (state[3] | state[8])
         mrx_clk_tmp <= 1'b0;
 
`ifdef ACTEL
   gbuf bufg2
     (
      .CLK(mrx_clk_tmp),
      .GL(mrx_clk)
      );
`else
   assign #1 mrx_clk = mrx_clk_tmp;
`endif
 
   assign mcoll = mcrs & mtxen;
 
endmodule // smii_top

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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [smii/] [smii_txrx.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SMII ////`
4			`//// ////`
5			`//// Description ////`
6			`//// Low pin count serial MII ethernet interface ////`
7			`//// ////`
8			`//// To Do: ////`
9			`//// - ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// - Michael Unneback, unneback@opencores.org ////`
13			`//// ORSoC AB michael.unneback@orsoc.se ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`module smii_txrx`
42			`(`
43			`// SMII`
44			`output tx,`
45			`input rx,`
46			`// MII`
47			`// TX`
48			`input [3:0] mtxd,`
49			`input mtxen,`
50			`input mtxerr,`
51			`output mtx_clk,`
52			`// RX`
53			`output reg [3:0] mrxd,`
54			`output reg mrxdv,`
55			`output reg mrxerr,`
56			`output mrx_clk,`
57			`output mcoll,`
58			`output reg mcrs,`
59			`ifdef SMII_SPEED
60			`output reg speed,`
61			`endif
62			`ifdef SMII_DUPLEX
63			`output reg duplex,`
64			`endif
65			`ifdef SMII_LINK
66			`output reg link,`
67			`endif
68			`// internal`
69			`input [1:10] state,`
70			`// clock and reset`
71			`input clk,`
72			`input rst`
73			`);`
74
75			`reg [0:7] tx_data_reg;`
76			`reg tx_data_reg_valid;`
77			`reg a0;`
78			`reg state_data;`
79
80			`reg [3:0] rx_tmp;`
81
82			`ifndef SMII_SPEED
83			`reg speed;`
84			`endif
85			`ifndef SMII_DUPLEX
86			`reg duplex;`
87			`endif
88			`ifndef SMII_LINK
89			`reg link;`
90			`endif
91			`reg jabber;`
92
93			`reg mtx_clk_tmp, mrx_clk_tmp;`
94
95			`reg [3:0] tx_cnt;`
96			`reg [3:0] rx_cnt;`
97
98			`/////////////////////////////////////////////////`
99			`// Speed`
100
101			`always @ (posedge clk or posedge rst)`
102			`if (rst)`
103			`tx_cnt <= 4'd0;`
104			`else`
105			`if (speed)`
106			`tx_cnt <= 4'd0;`
107			`else if (state[10])`
108			`if (tx_cnt == 4'd9)`
109			`tx_cnt <= 4'd0;`
110			`else`
111			`tx_cnt <= tx_cnt + 4'd1;`
112
113			`/////////////////////////////////////////////////`
114			`// Transmit`
115
116			`always @ (posedge clk or posedge rst)`
117			`if (rst)`
118			`mtx_clk_tmp <= 1'b0;`
119			`else`
120			`if ((state[10] \| state[5]) & (tx_cnt == 4'd0))`
121			`mtx_clk_tmp <= 1'b1;`
122			`else if (state[2] \| state[7])`
123			`mtx_clk_tmp <= 1'b0;`
124
125			`ifdef ACTEL
126			`gbuf bufg1`
127			`(`
128			`.CLK(mtx_clk_tmp),`
129			`.GL(mtx_clk)`
130			`);`
131			`else
132			`assign #1 mtx_clk = mtx_clk_tmp;`
133			`endif
134
135			`// storage of data from MII`
136			`always @ (posedge clk or posedge rst)`
137			`if (rst)`
138			`begin`
139			`tx_data_reg <= 8'd0;`
140			`tx_data_reg_valid <= 1'b0;`
141			`a0 <= 1'b0;`
142			`end`
143			`else`
144			`if ((state[4] \| state[9]) & (tx_cnt == 4'd0))`
145			`begin`
146			`if (!mtxen)`
147			`a0 <= 1'b0;`
148			`else`
149			`a0 <= ~a0;`
150			`if (!mtxen & !a0)`
151			`tx_data_reg_valid <= 1'b0;`
152			`else if (a0)`
153			`tx_data_reg_valid <= 1'b1;`
154			`if (mtxen & !a0)`
155			`tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};`
156			`else if (mtxen & a0)`
157			`tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};`
158			`end // if ((state[4] \| state[9]) & (tx_cnt == 4'd0))`
159
160
161			`// state flag`
162			`always @ (posedge clk or posedge rst)`
163			`if (rst)`
164			`state_data <= 1'b0;`
165			`else`
166			`if (state[1] & (tx_cnt == 4'd0))`
167			`state_data <= tx_data_reg_valid;`
168
169			`assign tx = state[1] ? mtxerr :`
170			`state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) \| state_data) :`
171			`state_data ? \|(state[2:10] & tx_data_reg) :`
172			`\|(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});`
173
174			`/////////////////////////////////////////////////`
175			`// Receive`
176
177			`always @ (posedge clk or posedge rst)`
178			`if (rst)`
179			`rx_cnt <= 4'd0;`
180			`else`
181			`if (speed)`
182			`rx_cnt <= 4'd0;`
183			`else if (!mrxdv & state[8] & rx_tmp[3])`
184			`rx_cnt <= 4'd9;`
185			`else if (state[10])`
186			`if (rx_cnt == 4'd9)`
187			`rx_cnt <= 4'd0;`
188			`else`
189			`rx_cnt <= rx_cnt + 4'd1;`
190
191			`always @ (posedge clk or posedge rst)`
192			`if (rst)`
193			`begin`
194			`{mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;`
195			`rx_tmp <= 4'h0;`
196			`mrxd <= 4'h0;`
197			`end`
198			`else`
199			`begin`
200			`rx_tmp[2:0] <= {rx,rx_tmp[2:1]};`
201			`if (state[3])`
202			`mcrs <= rx;`
203			`if (state[4])`
204			`rx_tmp[3] <= rx;`
205			`if (rx_tmp[3]) //rxdv`
206			`begin`
207			`if (state[8])`
208			`{mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};`
209			`else if (state[2])`
210			`mrxd <= #1 {rx,rx_tmp[2:0]};`
211			`end`
212			`else`
213			`begin`
214			`if (state[5])`
215			`mrxerr <= #1 rx;`
216			`if (state[6])`
217			`speed <= #1 rx;`
218			`if (state[7])`
219			`duplex <= #1 rx;`
220			`if (state[8])`
221			`begin`
222			`link <= #1 rx;`
223			`mrxdv <= #1 1'b0;`
224			`end`
225			`if (state[9])`
226			`jabber <= #1 rx;`
227			`end`
228			`end // else: !if(rst)`
229
230			`always @ (posedge clk or posedge rst)`
231			`if (rst)`
232			`mrx_clk_tmp <= 1'b0;`
233			`else`
234			`if ((state[1] \| state[6]) & (rx_cnt == 4'd0))`
235			`mrx_clk_tmp <= 1'b1;`
236			`else if (state[3] \| state[8])`
237			`mrx_clk_tmp <= 1'b0;`
238
239			`ifdef ACTEL
240			`gbuf bufg2`
241			`(`
242			`.CLK(mrx_clk_tmp),`
243			`.GL(mrx_clk)`
244			`);`
245			`else
246			`assign #1 mrx_clk = mrx_clk_tmp;`
247			`endif
248
249			`assign mcoll = mcrs & mtxen;`
250
251			`endmodule // smii_top`