OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [smii/] [tmp.v] - Blame information for rev 18

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 unneback 
`line 1 "smii_module_inst.v" 1
2 
//////////////////////////////////////////////////////////////////////
3 
////                                                              ////
4 
////  SMII                                                        ////
5 
////                                                              ////
6 
////  Description                                                 ////
7 
////  SMII low pin count ethernet PHY interface                   ////
8 
////                                                              ////
9 
////  To Do:                                                      ////
10 
////   -                                                          ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - Michael Unneback, unneback@opencores.org              ////
14 
////                          michael.unneback@orsoc.se           ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
// wire declarations
43 
`for (i=1;i<=SMII;i++)
44 
   // MII
45 
wire         m::`i::tx_clk;
46 
wire [3:0]            m::`i::txd;
47 
wire         m::`i::txen;
48 
wire         m::`i::txerr;
49 
wire         m::`i::rx_clk;
50 
wire [3:0]            m::`i::rxd;
51 
wire         m::`i::rxdv;
52 
wire         m::`i::rxerr;
53 
wire         m::`i::coll;
54 
wire         m::`i::crs;
55 
`endfor
56 
wire [1:10]          state;
57 
wire              sync;
58 
wire [1:8]    rx, tx;
59 
wire [1:8]    mdc_o, md_i, md_o, md_oe;
60 
smii_sync smii_sync1
61 
  (
62 
   .sync(sync),
63 
   .state(state),
64 
   .clk(eth_clk),
65 
   .rst(wb_rst)
66 
   );
67 
 
68 
 
69 
obufdff obufdff_sync
70 
  (
71 
   .d(sync),
72 
   .pad(eth_sync_pad_o),
73 
   .clk(eth_clk),
74 
   .rst(wb_rst)
75 
   );
76 
 
77 
 
78 
`for (i=1;i<=SMII;i++)
79 
// ethernet MAC
80 
eth_top eth_top::`i
81 
        (
82 
         // wb common
83 
         .wb_clk_i(wb_clk),
84 
         .wb_rst_i(wb_rst),
85 
         // wb slave
86 
         .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
87 
         .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
88 
         .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
89 
         .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
90 
         .wb_we_i(wbs_eth::`i::_cfg_we_i),
91 
         .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
92 
         .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
93 
         .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
94 
         .wb_err_o(wbs_eth::`i::_cfg_err_o),
95 
         // wb master
96 
         .m_wb_adr_o(wbm_eth::`i::_adr_o),
97 
         .m_wb_sel_o(wbm_eth::`i::_sel_o),
98 
         .m_wb_we_o(wbm_eth::`i::_we_o),
99 
         .m_wb_dat_o(wbm_eth::`i::_dat_o),
100 
         .m_wb_dat_i(wbm_eth::`i::_dat_i),
101 
         .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
102 
         .m_wb_stb_o(wbm_eth::`i::_stb_o),
103 
         .m_wb_ack_i(wbm_eth::`i::_ack_i),
104 
         .m_wb_err_i(wbm_eth::`i::_err_i),
105 
         .m_wb_cti_o(wbm_eth::`i::_cti_o),
106 
         .m_wb_bte_o(wbm_eth::`i::_bte_o),
107 
         // MII TX
108 
         .mtx_clk_pad_i(m::`i::tx_clk),
109 
         .mtxd_pad_o(m::`i::txd),
110 
         .mtxen_pad_o(m::`i::txen),
111 
         .mtxerr_pad_o(m::`i::txerr),
112 
         .mrx_clk_pad_i(m::`i::rx_clk),
113 
         .mrxd_pad_i(m::`i::rxd),
114 
         .mrxdv_pad_i(m::`i::rxdv),
115 
         .mrxerr_pad_i(m::`i::rxerr),
116 
         .mcoll_pad_i(m::`i::coll),
117 
         .mcrs_pad_i(m::`i::crs),
118 
         // MII management
119 
         .mdc_pad_o(mdc_o[`i]),
120 
         .md_pad_i(md_i[`i]),
121 
         .md_pad_o(md_o[`i]),
122 
         .md_padoe_o(md_oe[`i]),
123 
         .int_o(eth_int[`i])
124 
         );
125 
 
126 
iobuftri iobuftri::`i
127 
  (
128 
   .i(md_o[`i]),
129 
   .oe(md_oe[`i]),
130 
   .o(md_i[`i]),
131 
   .pad(eth_md_pad_io[`i])
132 
   );
133 
 
134 
obuf obuf::`i
135 
  (
136 
   .i(mdc_o[`i]),
137 
   .pad(eth_mdc_pad_o[`i])
138 
   );
139 
 
140 
smii_txrx smii_txrx::`i
141 
  (
142 
   .tx(tx[`i]),
143 
   .rx(rx[`i]),
144 
   .mtx_clk(m::`i::tx_clk),
145 
   .mtxd(m::`i::txd),
146 
   .mtxen(m::`i::txen),
147 
   .mtxerr(m::`i::txerr),
148 
   .mrx_clk(m::`i::rx_clk),
149 
   .mrxd(m::`i::rxd),
150 
   .mrxdv(m::`i::rxdv),
151 
   .mrxerr(m::`i::rxerr),
152 
   .mcoll(m::`i::coll),
153 
   .mcrs(m::`i::crs),
154 
   .state(state),
155 
   .clk(eth_clk),
156 
   .rst(wb_rst)
157 
   );
158 
 
159 
 
160 
 
161 
 
162 
 
163 
 
164 
 
165 
 
166 
 
167 
 
168 
`line 166 "smii_module_inst.v" 0
169 
 
170 
 
171 
obufdff obufdff_tx::`i
172 
  (
173 
   .d(tx[`i]),
174 
   .pad(eth_tx_pad_o[`i]),
175 
   .clk(eth_clk),
176 
   .rst(wb_rst)
177 
   );
178 
 
179 
ibufdff ibufdff_rx::`i
180 
  (
181 
   .pad(eth_rx_pad_i[`i]),
182 
   .q(rx[`i]),
183 
   .clk(eth_clk),
184 
   .rst(wb_rst)
185 
   );
186 
 
187 
`endfor
188 
 
189 
`line 186 "smii_module_inst.v" 2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.