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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [tap/] [tap_ip.v] - Blame information for rev 60

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`timescale 1ns/10ps
module tap_top(
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
                tdo_o,
                debug_tdi_i,
                bs_chain_tdi_i,
                mbist_tdi_i
              );
input   tms_pad_i;
input   tck_pad_i;
input   trst_pad_i;
input   tdi_pad_i;
output  tdo_pad_o;
output  tdo_padoe_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
output  tdo_o;
input   debug_tdi_i;
input   bs_chain_tdi_i;
input   mbist_tdi_i;
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir, shift_ir_neg;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
reg     tms_q1, tms_q2, tms_q3, tms_q4;
wire    tms_reset;
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
always @ (posedge tck_pad_i)
begin
  tms_q1 <= #1 tms_pad_i;
  tms_q2 <= #1 tms_q1;
  tms_q3 <= #1 tms_q2;
  tms_q4 <= #1 tms_q3;
end
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<=#1 1'b1;
  else if (tms_reset)
    test_logic_reset<=#1 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<=#1 1'b1;
      else
        test_logic_reset<=#1 1'b0;
    end
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<=#1 1'b0;
  else if (tms_reset)
    run_test_idle<=#1 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<=#1 1'b1;
  else
    run_test_idle<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<=#1 1'b0;
  else if (tms_reset)
    select_dr_scan<=#1 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<=#1 1'b1;
  else
    select_dr_scan<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<=#1 1'b0;
  else if (tms_reset)
    capture_dr<=#1 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<=#1 1'b1;
  else
    capture_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<=#1 1'b0;
  else if (tms_reset)
    shift_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<=#1 1'b1;
  else
    shift_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<=#1 1'b0;
  else if (tms_reset)
    exit1_dr<=#1 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<=#1 1'b1;
  else
    exit1_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<=#1 1'b0;
  else if (tms_reset)
    pause_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<=#1 1'b1;
  else
    pause_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<=#1 1'b0;
  else if (tms_reset)
    exit2_dr<=#1 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<=#1 1'b1;
  else
    exit2_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<=#1 1'b0;
  else if (tms_reset)
    update_dr<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<=#1 1'b1;
  else
    update_dr<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<=#1 1'b0;
  else if (tms_reset)
    select_ir_scan<=#1 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<=#1 1'b1;
  else
    select_ir_scan<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<=#1 1'b0;
  else if (tms_reset)
    capture_ir<=#1 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<=#1 1'b1;
  else
    capture_ir<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<=#1 1'b0;
  else if (tms_reset)
    shift_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<=#1 1'b1;
  else
    shift_ir<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<=#1 1'b0;
  else if (tms_reset)
    exit1_ir<=#1 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<=#1 1'b1;
  else
    exit1_ir<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<=#1 1'b0;
  else if (tms_reset)
    pause_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<=#1 1'b1;
  else
    pause_ir<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<=#1 1'b0;
  else if (tms_reset)
    exit2_ir<=#1 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<=#1 1'b1;
  else
    exit2_ir<=#1 1'b0;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<=#1 1'b0;
  else if (tms_reset)
    update_ir<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<=#1 1'b1;
  else
    update_ir<=#1 1'b0;
end
reg [4-1:0]  jtag_ir;
reg [4-1:0]  latched_jtag_ir, latched_jtag_ir_neg;
reg                   instruction_tdo;
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[4-1:0] <= #1 4'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;
  else if(shift_ir)
    jtag_ir[4-1:0] <= #1 {tdi_pad_i, jtag_ir[4-1:1]};
end
always @ (negedge tck_pad_i)
begin
  instruction_tdo <= #1 jtag_ir[0];
end
reg [31:0] idcode_reg;
reg        idcode_tdo;
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <= #1 32'h14951185;
end
always @ (negedge tck_pad_i)
begin
    idcode_tdo <= #1 idcode_reg;
end
reg  bypassed_tdo;
reg  bypass_reg;
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<=#1 1'b0;
  else if(shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <=#1 bypass_reg;
end
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <=#1 4'b0010;
  else if (tms_reset)
    latched_jtag_ir <=#1 4'b0010;
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
  case(latched_jtag_ir)
    4'b0000:            extest_select           = 1'b1;
    4'b0001:    sample_preload_select   = 1'b1;
    4'b0010:            idcode_select           = 1'b1;
    4'b1001:             mbist_select            = 1'b1;
    4'b1000:             debug_select            = 1'b1;
    4'b1111:            bypass_select           = 1'b1;
    default:            bypass_select           = 1'b1;
  endcase
end
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir_neg)
    tdo_pad_o = instruction_tdo;
  else
    begin
      case(latched_jtag_ir_neg)
        4'b0010:            tdo_pad_o = idcode_tdo;
        4'b1000:             tdo_pad_o = debug_tdi_i;
        4'b0001:    tdo_pad_o = bs_chain_tdi_i;
        4'b0000:            tdo_pad_o = bs_chain_tdi_i;
        4'b1001:             tdo_pad_o = mbist_tdi_i;
        default:            tdo_pad_o = bypassed_tdo;
      endcase
    end
end
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
end
always @ (negedge tck_pad_i)
begin
  shift_ir_neg <= #1 shift_ir;
  latched_jtag_ir_neg <= #1 latched_jtag_ir;
end
endmodule

Line No.	Rev	Author	Line
1	18	unneback	`timescale 1ns/10ps
2			`module tap_top(`
3			`tms_pad_i,`
4			`tck_pad_i,`
5			`trst_pad_i,`
6			`tdi_pad_i,`
7			`tdo_pad_o,`
8			`tdo_padoe_o,`
9			`shift_dr_o,`
10			`pause_dr_o,`
11			`update_dr_o,`
12			`capture_dr_o,`
13			`extest_select_o,`
14			`sample_preload_select_o,`
15			`mbist_select_o,`
16			`debug_select_o,`
17			`tdo_o,`
18			`debug_tdi_i,`
19			`bs_chain_tdi_i,`
20			`mbist_tdi_i`
21			`);`
22			`input tms_pad_i;`
23			`input tck_pad_i;`
24			`input trst_pad_i;`
25			`input tdi_pad_i;`
26			`output tdo_pad_o;`
27			`output tdo_padoe_o;`
28			`output shift_dr_o;`
29			`output pause_dr_o;`
30			`output update_dr_o;`
31			`output capture_dr_o;`
32			`output extest_select_o;`
33			`output sample_preload_select_o;`
34			`output mbist_select_o;`
35			`output debug_select_o;`
36			`output tdo_o;`
37			`input debug_tdi_i;`
38			`input bs_chain_tdi_i;`
39			`input mbist_tdi_i;`
40			`reg test_logic_reset;`
41			`reg run_test_idle;`
42			`reg select_dr_scan;`
43			`reg capture_dr;`
44			`reg shift_dr;`
45			`reg exit1_dr;`
46			`reg pause_dr;`
47			`reg exit2_dr;`
48			`reg update_dr;`
49			`reg select_ir_scan;`
50			`reg capture_ir;`
51			`reg shift_ir, shift_ir_neg;`
52			`reg exit1_ir;`
53			`reg pause_ir;`
54			`reg exit2_ir;`
55			`reg update_ir;`
56			`reg extest_select;`
57			`reg sample_preload_select;`
58			`reg idcode_select;`
59			`reg mbist_select;`
60			`reg debug_select;`
61			`reg bypass_select;`
62			`reg tdo_pad_o;`
63			`reg tdo_padoe_o;`
64			`reg tms_q1, tms_q2, tms_q3, tms_q4;`
65			`wire tms_reset;`
66			`assign tdo_o = tdi_pad_i;`
67			`assign shift_dr_o = shift_dr;`
68			`assign pause_dr_o = pause_dr;`
69			`assign update_dr_o = update_dr;`
70			`assign capture_dr_o = capture_dr;`
71			`assign extest_select_o = extest_select;`
72			`assign sample_preload_select_o = sample_preload_select;`
73			`assign mbist_select_o = mbist_select;`
74			`assign debug_select_o = debug_select;`
75			`always @ (posedge tck_pad_i)`
76			`begin`
77			`tms_q1 <= #1 tms_pad_i;`
78			`tms_q2 <= #1 tms_q1;`
79			`tms_q3 <= #1 tms_q2;`
80			`tms_q4 <= #1 tms_q3;`
81			`end`
82			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;`
83			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
84			`begin`
85			`if(trst_pad_i)`
86			`test_logic_reset<=#1 1'b1;`
87			`else if (tms_reset)`
88			`test_logic_reset<=#1 1'b1;`
89			`else`
90			`begin`
91			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
92			`test_logic_reset<=#1 1'b1;`
93			`else`
94			`test_logic_reset<=#1 1'b0;`
95			`end`
96			`end`
97			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
98			`begin`
99			`if(trst_pad_i)`
100			`run_test_idle<=#1 1'b0;`
101			`else if (tms_reset)`
102			`run_test_idle<=#1 1'b0;`
103			`else`
104			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
105			`run_test_idle<=#1 1'b1;`
106			`else`
107			`run_test_idle<=#1 1'b0;`
108			`end`
109			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
110			`begin`
111			`if(trst_pad_i)`
112			`select_dr_scan<=#1 1'b0;`
113			`else if (tms_reset)`
114			`select_dr_scan<=#1 1'b0;`
115			`else`
116			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
117			`select_dr_scan<=#1 1'b1;`
118			`else`
119			`select_dr_scan<=#1 1'b0;`
120			`end`
121			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
122			`begin`
123			`if(trst_pad_i)`
124			`capture_dr<=#1 1'b0;`
125			`else if (tms_reset)`
126			`capture_dr<=#1 1'b0;`
127			`else`
128			`if(~tms_pad_i & select_dr_scan)`
129			`capture_dr<=#1 1'b1;`
130			`else`
131			`capture_dr<=#1 1'b0;`
132			`end`
133			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
134			`begin`
135			`if(trst_pad_i)`
136			`shift_dr<=#1 1'b0;`
137			`else if (tms_reset)`
138			`shift_dr<=#1 1'b0;`
139			`else`
140			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
141			`shift_dr<=#1 1'b1;`
142			`else`
143			`shift_dr<=#1 1'b0;`
144			`end`
145			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
146			`begin`
147			`if(trst_pad_i)`
148			`exit1_dr<=#1 1'b0;`
149			`else if (tms_reset)`
150			`exit1_dr<=#1 1'b0;`
151			`else`
152			`if(tms_pad_i & (capture_dr \| shift_dr))`
153			`exit1_dr<=#1 1'b1;`
154			`else`
155			`exit1_dr<=#1 1'b0;`
156			`end`
157			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
158			`begin`
159			`if(trst_pad_i)`
160			`pause_dr<=#1 1'b0;`
161			`else if (tms_reset)`
162			`pause_dr<=#1 1'b0;`
163			`else`
164			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
165			`pause_dr<=#1 1'b1;`
166			`else`
167			`pause_dr<=#1 1'b0;`
168			`end`
169			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
170			`begin`
171			`if(trst_pad_i)`
172			`exit2_dr<=#1 1'b0;`
173			`else if (tms_reset)`
174			`exit2_dr<=#1 1'b0;`
175			`else`
176			`if(tms_pad_i & pause_dr)`
177			`exit2_dr<=#1 1'b1;`
178			`else`
179			`exit2_dr<=#1 1'b0;`
180			`end`
181			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
182			`begin`
183			`if(trst_pad_i)`
184			`update_dr<=#1 1'b0;`
185			`else if (tms_reset)`
186			`update_dr<=#1 1'b0;`
187			`else`
188			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
189			`update_dr<=#1 1'b1;`
190			`else`
191			`update_dr<=#1 1'b0;`
192			`end`
193			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
194			`begin`
195			`if(trst_pad_i)`
196			`select_ir_scan<=#1 1'b0;`
197			`else if (tms_reset)`
198			`select_ir_scan<=#1 1'b0;`
199			`else`
200			`if(tms_pad_i & select_dr_scan)`
201			`select_ir_scan<=#1 1'b1;`
202			`else`
203			`select_ir_scan<=#1 1'b0;`
204			`end`
205			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
206			`begin`
207			`if(trst_pad_i)`
208			`capture_ir<=#1 1'b0;`
209			`else if (tms_reset)`
210			`capture_ir<=#1 1'b0;`
211			`else`
212			`if(~tms_pad_i & select_ir_scan)`
213			`capture_ir<=#1 1'b1;`
214			`else`
215			`capture_ir<=#1 1'b0;`
216			`end`
217			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
218			`begin`
219			`if(trst_pad_i)`
220			`shift_ir<=#1 1'b0;`
221			`else if (tms_reset)`
222			`shift_ir<=#1 1'b0;`
223			`else`
224			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
225			`shift_ir<=#1 1'b1;`
226			`else`
227			`shift_ir<=#1 1'b0;`
228			`end`
229			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
230			`begin`
231			`if(trst_pad_i)`
232			`exit1_ir<=#1 1'b0;`
233			`else if (tms_reset)`
234			`exit1_ir<=#1 1'b0;`
235			`else`
236			`if(tms_pad_i & (capture_ir \| shift_ir))`
237			`exit1_ir<=#1 1'b1;`
238			`else`
239			`exit1_ir<=#1 1'b0;`
240			`end`
241			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
242			`begin`
243			`if(trst_pad_i)`
244			`pause_ir<=#1 1'b0;`
245			`else if (tms_reset)`
246			`pause_ir<=#1 1'b0;`
247			`else`
248			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
249			`pause_ir<=#1 1'b1;`
250			`else`
251			`pause_ir<=#1 1'b0;`
252			`end`
253			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
254			`begin`
255			`if(trst_pad_i)`
256			`exit2_ir<=#1 1'b0;`
257			`else if (tms_reset)`
258			`exit2_ir<=#1 1'b0;`
259			`else`
260			`if(tms_pad_i & pause_ir)`
261			`exit2_ir<=#1 1'b1;`
262			`else`
263			`exit2_ir<=#1 1'b0;`
264			`end`
265			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
266			`begin`
267			`if(trst_pad_i)`
268			`update_ir<=#1 1'b0;`
269			`else if (tms_reset)`
270			`update_ir<=#1 1'b0;`
271			`else`
272			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
273			`update_ir<=#1 1'b1;`
274			`else`
275			`update_ir<=#1 1'b0;`
276			`end`
277			`reg [4-1:0] jtag_ir;`
278			`reg [4-1:0] latched_jtag_ir, latched_jtag_ir_neg;`
279			`reg instruction_tdo;`
280			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
281			`begin`
282			`if(trst_pad_i)`
283			`jtag_ir[4-1:0] <= #1 4'b0;`
284			`else if(capture_ir)`
285			`jtag_ir <= #1 4'b0101;`
286			`else if(shift_ir)`
287			`jtag_ir[4-1:0] <= #1 {tdi_pad_i, jtag_ir[4-1:1]};`
288			`end`
289			`always @ (negedge tck_pad_i)`
290			`begin`
291			`instruction_tdo <= #1 jtag_ir[0];`
292			`end`
293			`reg [31:0] idcode_reg;`
294			`reg idcode_tdo;`
295			`always @ (posedge tck_pad_i)`
296			`begin`
297			`if(idcode_select & shift_dr)`
298			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
299			`else`
300			`idcode_reg <= #1 32'h14951185;`
301			`end`
302			`always @ (negedge tck_pad_i)`
303			`begin`
304			`idcode_tdo <= #1 idcode_reg;`
305			`end`
306			`reg bypassed_tdo;`
307			`reg bypass_reg;`
308			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
309			`begin`
310			`if (trst_pad_i)`
311			`bypass_reg<=#1 1'b0;`
312			`else if(shift_dr)`
313			`bypass_reg<=#1 tdi_pad_i;`
314			`end`
315			`always @ (negedge tck_pad_i)`
316			`begin`
317			`bypassed_tdo <=#1 bypass_reg;`
318			`end`
319			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
320			`begin`
321			`if(trst_pad_i)`
322			`latched_jtag_ir <=#1 4'b0010;`
323			`else if (tms_reset)`
324			`latched_jtag_ir <=#1 4'b0010;`
325			`else if(update_ir)`
326			`latched_jtag_ir <=#1 jtag_ir;`
327			`end`
328			`always @ (latched_jtag_ir)`
329			`begin`
330			`extest_select = 1'b0;`
331			`sample_preload_select = 1'b0;`
332			`idcode_select = 1'b0;`
333			`mbist_select = 1'b0;`
334			`debug_select = 1'b0;`
335			`bypass_select = 1'b0;`
336			`case(latched_jtag_ir)`
337			`4'b0000: extest_select = 1'b1;`
338			`4'b0001: sample_preload_select = 1'b1;`
339			`4'b0010: idcode_select = 1'b1;`
340			`4'b1001: mbist_select = 1'b1;`
341			`4'b1000: debug_select = 1'b1;`
342			`4'b1111: bypass_select = 1'b1;`
343			`default: bypass_select = 1'b1;`
344			`endcase`
345			`end`
346			`always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or`
347			`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or`
348			`bypassed_tdo)`
349			`begin`
350			`if(shift_ir_neg)`
351			`tdo_pad_o = instruction_tdo;`
352			`else`
353			`begin`
354			`case(latched_jtag_ir_neg)`
355			`4'b0010: tdo_pad_o = idcode_tdo;`
356			`4'b1000: tdo_pad_o = debug_tdi_i;`
357			`4'b0001: tdo_pad_o = bs_chain_tdi_i;`
358			`4'b0000: tdo_pad_o = bs_chain_tdi_i;`
359			`4'b1001: tdo_pad_o = mbist_tdi_i;`
360			`default: tdo_pad_o = bypassed_tdo;`
361			`endcase`
362			`end`
363			`end`
364			`always @ (negedge tck_pad_i)`
365			`begin`
366			`tdo_padoe_o <= #1 shift_ir \| shift_dr \| (pause_dr & debug_select);`
367			`end`
368			`always @ (negedge tck_pad_i)`
369			`begin`
370			`shift_ir_neg <= #1 shift_ir;`
371			`latched_jtag_ir_neg <= #1 latched_jtag_ir;`
372			`end`
373			`endmodule`

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