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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [tap/] [tap_top.v] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////  http://www.opencores.org/projects/jtag/                     ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_top.v,v $
// Revision 1.6  2004/01/27 10:00:33  mohor
// Unused registers removed.
//
// Revision 1.5  2004/01/18 09:27:39  simons
// Blocking non blocking assignmenst fixed.
//
// Revision 1.4  2004/01/17 17:37:44  mohor
// capture_dr_o added to ports.
//
// Revision 1.3  2004/01/14 13:50:56  mohor
// 5 consecutive TMS=1 causes reset of TAP.
//
// Revision 1.2  2004/01/08 10:29:44  mohor
// Control signals for tdo_pad_o mux are changed to negedge.
//
// Revision 1.1  2003/12/23 14:52:14  mohor
// Directory structure changed. New version of TAP.
//
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trst_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Registers
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir, shift_ir_neg;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
reg     tms_q1, tms_q2, tms_q3, tms_q4;
wire    tms_reset;
 
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
always @ (posedge tck_pad_i)
begin
  tms_q1 <= #1 tms_pad_i;
  tms_q2 <= #1 tms_q1;
  tms_q3 <= #1 tms_q2;
  tms_q4 <= #1 tms_q3;
end
 
 
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;    // 5 consecutive TMS=1 causes reset
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// test_logic_reset state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<=#1 1'b1;
  else if (tms_reset)
    test_logic_reset<=#1 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<=#1 1'b1;
      else
        test_logic_reset<=#1 1'b0;
    end
end
 
// run_test_idle state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<=#1 1'b0;
  else if (tms_reset)
    run_test_idle<=#1 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<=#1 1'b1;
  else
    run_test_idle<=#1 1'b0;
end
 
// select_dr_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<=#1 1'b0;
  else if (tms_reset)
    select_dr_scan<=#1 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<=#1 1'b1;
  else
    select_dr_scan<=#1 1'b0;
end
 
// capture_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<=#1 1'b0;
  else if (tms_reset)
    capture_dr<=#1 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<=#1 1'b1;
  else
    capture_dr<=#1 1'b0;
end
 
// shift_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<=#1 1'b0;
  else if (tms_reset)
    shift_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<=#1 1'b1;
  else
    shift_dr<=#1 1'b0;
end
 
// exit1_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<=#1 1'b0;
  else if (tms_reset)
    exit1_dr<=#1 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<=#1 1'b1;
  else
    exit1_dr<=#1 1'b0;
end
 
// pause_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<=#1 1'b0;
  else if (tms_reset)
    pause_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<=#1 1'b1;
  else
    pause_dr<=#1 1'b0;
end
 
// exit2_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<=#1 1'b0;
  else if (tms_reset)
    exit2_dr<=#1 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<=#1 1'b1;
  else
    exit2_dr<=#1 1'b0;
end
 
// update_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<=#1 1'b0;
  else if (tms_reset)
    update_dr<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<=#1 1'b1;
  else
    update_dr<=#1 1'b0;
end
 
// select_ir_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<=#1 1'b0;
  else if (tms_reset)
    select_ir_scan<=#1 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<=#1 1'b1;
  else
    select_ir_scan<=#1 1'b0;
end
 
// capture_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<=#1 1'b0;
  else if (tms_reset)
    capture_ir<=#1 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<=#1 1'b1;
  else
    capture_ir<=#1 1'b0;
end
 
// shift_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<=#1 1'b0;
  else if (tms_reset)
    shift_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<=#1 1'b1;
  else
    shift_ir<=#1 1'b0;
end
 
// exit1_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<=#1 1'b0;
  else if (tms_reset)
    exit1_ir<=#1 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<=#1 1'b1;
  else
    exit1_ir<=#1 1'b0;
end
 
// pause_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<=#1 1'b0;
  else if (tms_reset)
    pause_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<=#1 1'b1;
  else
    pause_ir<=#1 1'b0;
end
 
// exit2_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<=#1 1'b0;
  else if (tms_reset)
    exit2_ir<=#1 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<=#1 1'b1;
  else
    exit2_ir<=#1 1'b0;
end
 
// update_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<=#1 1'b0;
  else if (tms_reset)
    update_ir<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<=#1 1'b1;
  else
    update_ir<=#1 1'b0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir, latched_jtag_ir_neg;
reg                   instruction_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  instruction_tdo <= #1 jtag_ir[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
reg        idcode_tdo;
 
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <= #1 `IDCODE_VALUE;
end
 
always @ (negedge tck_pad_i)
begin
    idcode_tdo <= #1 idcode_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg  bypassed_tdo;
reg  bypass_reg;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<=#1 1'b0;
  else if(shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <=#1 bypass_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
// Updating jtag_ir (Instruction Register)
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if (tms_reset)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating jtag_ir (Instruction Register)
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir_neg)
    tdo_pad_o = instruction_tdo;
  else
    begin
      case(latched_jtag_ir_neg)    // synthesis parallel_case
        `IDCODE:            tdo_pad_o = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_pad_o = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_pad_o = mbist_tdi_i;      // Mbist test
        default:            tdo_pad_o = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// Tristate control for tdo_pad_o pin
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
always @ (negedge tck_pad_i)
begin
  shift_ir_neg <= #1 shift_ir;
  latched_jtag_ir_neg <= #1 latched_jtag_ir;
end
 
 
endmodule

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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [tap/] [tap_top.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// http://www.opencores.org/projects/jtag/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: tap_top.v,v $`
46			`// Revision 1.6 2004/01/27 10:00:33 mohor`
47			`// Unused registers removed.`
48			`//`
49			`// Revision 1.5 2004/01/18 09:27:39 simons`
50			`// Blocking non blocking assignmenst fixed.`
51			`//`
52			`// Revision 1.4 2004/01/17 17:37:44 mohor`
53			`// capture_dr_o added to ports.`
54			`//`
55			`// Revision 1.3 2004/01/14 13:50:56 mohor`
56			`// 5 consecutive TMS=1 causes reset of TAP.`
57			`//`
58			`// Revision 1.2 2004/01/08 10:29:44 mohor`
59			`// Control signals for tdo_pad_o mux are changed to negedge.`
60			`//`
61			`// Revision 1.1 2003/12/23 14:52:14 mohor`
62			`// Directory structure changed. New version of TAP.`
63			`//`
64			`// Revision 1.10 2003/10/23 18:08:01 mohor`
65			`// MBIST chain connection fixed.`
66			`//`
67			`// Revision 1.9 2003/10/23 16:17:02 mohor`
68			`// CRC logic changed.`
69			`//`
70			`// Revision 1.8 2003/10/21 09:48:31 simons`
71			`// Mbist support added.`
72			`//`
73			`// Revision 1.7 2002/11/06 14:30:10 mohor`
74			`// Trst active high. Inverted on higher layer.`
75			`//`
76			`// Revision 1.6 2002/04/22 12:55:56 mohor`
77			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
78			`//`
79			`// Revision 1.5 2002/03/26 14:23:38 mohor`
80			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
81			`//`
82			`// Revision 1.4 2002/03/25 13:16:15 mohor`
83			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
84			`// not named correctly.`
85			`//`
86			`// Revision 1.3 2002/03/12 14:30:05 mohor`
87			`// Few outputs for boundary scan chain added.`
88			`//`
89			`// Revision 1.2 2002/03/12 10:31:53 mohor`
90			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
91			`// contains only tap state machine and related logic. dbg_top contains all`
92			`// logic necessery for debugging.`
93			`//`
94			`// Revision 1.1 2002/03/08 15:28:16 mohor`
95			`// Structure changed. Hooks for jtag chain added.`
96			`//`
97			`//`
98			`//`
99			`//`
100
101			`// synopsys translate_off`
102			`include "timescale.v"
103			`// synopsys translate_on`
104			`include "tap_defines.v"
105
106			`// Top module`
107			`module tap_top(`
108			`// JTAG pads`
109			`tms_pad_i,`
110			`tck_pad_i,`
111			`trst_pad_i,`
112			`tdi_pad_i,`
113			`tdo_pad_o,`
114			`tdo_padoe_o,`
115
116			`// TAP states`
117			`shift_dr_o,`
118			`pause_dr_o,`
119			`update_dr_o,`
120			`capture_dr_o,`
121
122			`// Select signals for boundary scan or mbist`
123			`extest_select_o,`
124			`sample_preload_select_o,`
125			`mbist_select_o,`
126			`debug_select_o,`
127
128			`// TDO signal that is connected to TDI of sub-modules.`
129			`tdo_o,`
130
131			`// TDI signals from sub-modules`
132			`debug_tdi_i, // from debug module`
133			`bs_chain_tdi_i, // from Boundary Scan Chain`
134			`mbist_tdi_i // from Mbist Chain`
135			`);`
136
137
138			`// JTAG pins`
139			`input tms_pad_i; // JTAG test mode select pad`
140			`input tck_pad_i; // JTAG test clock pad`
141			`input trst_pad_i; // JTAG test reset pad`
142			`input tdi_pad_i; // JTAG test data input pad`
143			`output tdo_pad_o; // JTAG test data output pad`
144			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
145
146			`// TAP states`
147			`output shift_dr_o;`
148			`output pause_dr_o;`
149			`output update_dr_o;`
150			`output capture_dr_o;`
151
152			`// Select signals for boundary scan or mbist`
153			`output extest_select_o;`
154			`output sample_preload_select_o;`
155			`output mbist_select_o;`
156			`output debug_select_o;`
157
158			`// TDO signal that is connected to TDI of sub-modules.`
159			`output tdo_o;`
160
161			`// TDI signals from sub-modules`
162			`input debug_tdi_i; // from debug module`
163			`input bs_chain_tdi_i; // from Boundary Scan Chain`
164			`input mbist_tdi_i; // from Mbist Chain`
165
166			`// Registers`
167			`reg test_logic_reset;`
168			`reg run_test_idle;`
169			`reg select_dr_scan;`
170			`reg capture_dr;`
171			`reg shift_dr;`
172			`reg exit1_dr;`
173			`reg pause_dr;`
174			`reg exit2_dr;`
175			`reg update_dr;`
176			`reg select_ir_scan;`
177			`reg capture_ir;`
178			`reg shift_ir, shift_ir_neg;`
179			`reg exit1_ir;`
180			`reg pause_ir;`
181			`reg exit2_ir;`
182			`reg update_ir;`
183			`reg extest_select;`
184			`reg sample_preload_select;`
185			`reg idcode_select;`
186			`reg mbist_select;`
187			`reg debug_select;`
188			`reg bypass_select;`
189			`reg tdo_pad_o;`
190			`reg tdo_padoe_o;`
191			`reg tms_q1, tms_q2, tms_q3, tms_q4;`
192			`wire tms_reset;`
193
194			`assign tdo_o = tdi_pad_i;`
195			`assign shift_dr_o = shift_dr;`
196			`assign pause_dr_o = pause_dr;`
197			`assign update_dr_o = update_dr;`
198			`assign capture_dr_o = capture_dr;`
199
200			`assign extest_select_o = extest_select;`
201			`assign sample_preload_select_o = sample_preload_select;`
202			`assign mbist_select_o = mbist_select;`
203			`assign debug_select_o = debug_select;`
204
205
206			`always @ (posedge tck_pad_i)`
207			`begin`
208			`tms_q1 <= #1 tms_pad_i;`
209			`tms_q2 <= #1 tms_q1;`
210			`tms_q3 <= #1 tms_q2;`
211			`tms_q4 <= #1 tms_q3;`
212			`end`
213
214
215			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset`
216
217
218			`/**********************************************************************************`
219			`* *`
220			`* TAP State Machine: Fully JTAG compliant *`
221			`* *`
222			`**********************************************************************************/`
223
224			`// test_logic_reset state`
225			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
226			`begin`
227			`if(trst_pad_i)`
228			`test_logic_reset<=#1 1'b1;`
229			`else if (tms_reset)`
230			`test_logic_reset<=#1 1'b1;`
231			`else`
232			`begin`
233			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
234			`test_logic_reset<=#1 1'b1;`
235			`else`
236			`test_logic_reset<=#1 1'b0;`
237			`end`
238			`end`
239
240			`// run_test_idle state`
241			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
242			`begin`
243			`if(trst_pad_i)`
244			`run_test_idle<=#1 1'b0;`
245			`else if (tms_reset)`
246			`run_test_idle<=#1 1'b0;`
247			`else`
248			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
249			`run_test_idle<=#1 1'b1;`
250			`else`
251			`run_test_idle<=#1 1'b0;`
252			`end`
253
254			`// select_dr_scan state`
255			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
256			`begin`
257			`if(trst_pad_i)`
258			`select_dr_scan<=#1 1'b0;`
259			`else if (tms_reset)`
260			`select_dr_scan<=#1 1'b0;`
261			`else`
262			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
263			`select_dr_scan<=#1 1'b1;`
264			`else`
265			`select_dr_scan<=#1 1'b0;`
266			`end`
267
268			`// capture_dr state`
269			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
270			`begin`
271			`if(trst_pad_i)`
272			`capture_dr<=#1 1'b0;`
273			`else if (tms_reset)`
274			`capture_dr<=#1 1'b0;`
275			`else`
276			`if(~tms_pad_i & select_dr_scan)`
277			`capture_dr<=#1 1'b1;`
278			`else`
279			`capture_dr<=#1 1'b0;`
280			`end`
281
282			`// shift_dr state`
283			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
284			`begin`
285			`if(trst_pad_i)`
286			`shift_dr<=#1 1'b0;`
287			`else if (tms_reset)`
288			`shift_dr<=#1 1'b0;`
289			`else`
290			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
291			`shift_dr<=#1 1'b1;`
292			`else`
293			`shift_dr<=#1 1'b0;`
294			`end`
295
296			`// exit1_dr state`
297			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
298			`begin`
299			`if(trst_pad_i)`
300			`exit1_dr<=#1 1'b0;`
301			`else if (tms_reset)`
302			`exit1_dr<=#1 1'b0;`
303			`else`
304			`if(tms_pad_i & (capture_dr \| shift_dr))`
305			`exit1_dr<=#1 1'b1;`
306			`else`
307			`exit1_dr<=#1 1'b0;`
308			`end`
309
310			`// pause_dr state`
311			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
312			`begin`
313			`if(trst_pad_i)`
314			`pause_dr<=#1 1'b0;`
315			`else if (tms_reset)`
316			`pause_dr<=#1 1'b0;`
317			`else`
318			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
319			`pause_dr<=#1 1'b1;`
320			`else`
321			`pause_dr<=#1 1'b0;`
322			`end`
323
324			`// exit2_dr state`
325			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
326			`begin`
327			`if(trst_pad_i)`
328			`exit2_dr<=#1 1'b0;`
329			`else if (tms_reset)`
330			`exit2_dr<=#1 1'b0;`
331			`else`
332			`if(tms_pad_i & pause_dr)`
333			`exit2_dr<=#1 1'b1;`
334			`else`
335			`exit2_dr<=#1 1'b0;`
336			`end`
337
338			`// update_dr state`
339			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
340			`begin`
341			`if(trst_pad_i)`
342			`update_dr<=#1 1'b0;`
343			`else if (tms_reset)`
344			`update_dr<=#1 1'b0;`
345			`else`
346			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
347			`update_dr<=#1 1'b1;`
348			`else`
349			`update_dr<=#1 1'b0;`
350			`end`
351
352			`// select_ir_scan state`
353			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
354			`begin`
355			`if(trst_pad_i)`
356			`select_ir_scan<=#1 1'b0;`
357			`else if (tms_reset)`
358			`select_ir_scan<=#1 1'b0;`
359			`else`
360			`if(tms_pad_i & select_dr_scan)`
361			`select_ir_scan<=#1 1'b1;`
362			`else`
363			`select_ir_scan<=#1 1'b0;`
364			`end`
365
366			`// capture_ir state`
367			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
368			`begin`
369			`if(trst_pad_i)`
370			`capture_ir<=#1 1'b0;`
371			`else if (tms_reset)`
372			`capture_ir<=#1 1'b0;`
373			`else`
374			`if(~tms_pad_i & select_ir_scan)`
375			`capture_ir<=#1 1'b1;`
376			`else`
377			`capture_ir<=#1 1'b0;`
378			`end`
379
380			`// shift_ir state`
381			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
382			`begin`
383			`if(trst_pad_i)`
384			`shift_ir<=#1 1'b0;`
385			`else if (tms_reset)`
386			`shift_ir<=#1 1'b0;`
387			`else`
388			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
389			`shift_ir<=#1 1'b1;`
390			`else`
391			`shift_ir<=#1 1'b0;`
392			`end`
393
394			`// exit1_ir state`
395			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
396			`begin`
397			`if(trst_pad_i)`
398			`exit1_ir<=#1 1'b0;`
399			`else if (tms_reset)`
400			`exit1_ir<=#1 1'b0;`
401			`else`
402			`if(tms_pad_i & (capture_ir \| shift_ir))`
403			`exit1_ir<=#1 1'b1;`
404			`else`
405			`exit1_ir<=#1 1'b0;`
406			`end`
407
408			`// pause_ir state`
409			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
410			`begin`
411			`if(trst_pad_i)`
412			`pause_ir<=#1 1'b0;`
413			`else if (tms_reset)`
414			`pause_ir<=#1 1'b0;`
415			`else`
416			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
417			`pause_ir<=#1 1'b1;`
418			`else`
419			`pause_ir<=#1 1'b0;`
420			`end`
421
422			`// exit2_ir state`
423			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
424			`begin`
425			`if(trst_pad_i)`
426			`exit2_ir<=#1 1'b0;`
427			`else if (tms_reset)`
428			`exit2_ir<=#1 1'b0;`
429			`else`
430			`if(tms_pad_i & pause_ir)`
431			`exit2_ir<=#1 1'b1;`
432			`else`
433			`exit2_ir<=#1 1'b0;`
434			`end`
435
436			`// update_ir state`
437			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
438			`begin`
439			`if(trst_pad_i)`
440			`update_ir<=#1 1'b0;`
441			`else if (tms_reset)`
442			`update_ir<=#1 1'b0;`
443			`else`
444			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
445			`update_ir<=#1 1'b1;`
446			`else`
447			`update_ir<=#1 1'b0;`
448			`end`
449
450			`/**********************************************************************************`
451			`* *`
452			`* End: TAP State Machine *`
453			`* *`
454			`**********************************************************************************/`
455
456
457
458			`/**********************************************************************************`
459			`* *`
460			`* jtag_ir: JTAG Instruction Register *`
461			`* *`
462			`**********************************************************************************/`
463			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
464			reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
465			`reg instruction_tdo;`
466
467			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
468			`begin`
469			`if(trst_pad_i)`
470			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
471			`else if(capture_ir)`
472			`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
473			`else if(shift_ir)`
474			jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
475			`end`
476
477			`always @ (negedge tck_pad_i)`
478			`begin`
479			`instruction_tdo <= #1 jtag_ir[0];`
480			`end`
481			`/**********************************************************************************`
482			`* *`
483			`* End: jtag_ir *`
484			`* *`
485			`**********************************************************************************/`
486
487
488
489			`/**********************************************************************************`
490			`* *`
491			`* idcode logic *`
492			`* *`
493			`**********************************************************************************/`
494			`reg [31:0] idcode_reg;`
495			`reg idcode_tdo;`
496
497			`always @ (posedge tck_pad_i)`
498			`begin`
499			`if(idcode_select & shift_dr)`
500			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
501			`else`
502			idcode_reg <= #1 `IDCODE_VALUE;
503			`end`
504
505			`always @ (negedge tck_pad_i)`
506			`begin`
507			`idcode_tdo <= #1 idcode_reg;`
508			`end`
509			`/**********************************************************************************`
510			`* *`
511			`* End: idcode logic *`
512			`* *`
513			`**********************************************************************************/`
514
515
516			`/**********************************************************************************`
517			`* *`
518			`* Bypass logic *`
519			`* *`
520			`**********************************************************************************/`
521			`reg bypassed_tdo;`
522			`reg bypass_reg;`
523
524			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
525			`begin`
526			`if (trst_pad_i)`
527			`bypass_reg<=#1 1'b0;`
528			`else if(shift_dr)`
529			`bypass_reg<=#1 tdi_pad_i;`
530			`end`
531
532			`always @ (negedge tck_pad_i)`
533			`begin`
534			`bypassed_tdo <=#1 bypass_reg;`
535			`end`
536			`/**********************************************************************************`
537			`* *`
538			`* End: Bypass logic *`
539			`* *`
540			`**********************************************************************************/`
541
542
543			`/**********************************************************************************`
544			`* *`
545			`* Activating Instructions *`
546			`* *`
547			`**********************************************************************************/`
548			`// Updating jtag_ir (Instruction Register)`
549			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
550			`begin`
551			`if(trst_pad_i)`
552			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
553			`else if (tms_reset)`
554			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
555			`else if(update_ir)`
556			`latched_jtag_ir <=#1 jtag_ir;`
557			`end`
558
559			`/**********************************************************************************`
560			`* *`
561			`* End: Activating Instructions *`
562			`* *`
563			`**********************************************************************************/`
564
565
566			`// Updating jtag_ir (Instruction Register)`
567			`always @ (latched_jtag_ir)`
568			`begin`
569			`extest_select = 1'b0;`
570			`sample_preload_select = 1'b0;`
571			`idcode_select = 1'b0;`
572			`mbist_select = 1'b0;`
573			`debug_select = 1'b0;`
574			`bypass_select = 1'b0;`
575
576			`case(latched_jtag_ir) /* synthesis parallel_case */`
577			`EXTEST: extest_select = 1'b1; // External test
578			`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
579			`IDCODE: idcode_select = 1'b1; // ID Code
580			`MBIST: mbist_select = 1'b1; // Mbist test
581			`DEBUG: debug_select = 1'b1; // Debug
582			`BYPASS: bypass_select = 1'b1; // BYPASS
583			`default: bypass_select = 1'b1; // BYPASS`
584			`endcase`
585			`end`
586
587
588
589			`/**********************************************************************************`
590			`* *`
591			`* Multiplexing TDO data *`
592			`* *`
593			`**********************************************************************************/`
594			`always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or`
595			`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or`
596			`bypassed_tdo)`
597			`begin`
598			`if(shift_ir_neg)`
599			`tdo_pad_o = instruction_tdo;`
600			`else`
601			`begin`
602			`case(latched_jtag_ir_neg) // synthesis parallel_case`
603			`IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
604			`DEBUG: tdo_pad_o = debug_tdi_i; // Debug
605			`SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
606			`EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
607			`MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
608			`default: tdo_pad_o = bypassed_tdo; // BYPASS instruction`
609			`endcase`
610			`end`
611			`end`
612
613
614			`// Tristate control for tdo_pad_o pin`
615			`always @ (negedge tck_pad_i)`
616			`begin`
617			`tdo_padoe_o <= #1 shift_ir \| shift_dr \| (pause_dr & debug_select);`
618			`end`
619			`/**********************************************************************************`
620			`* *`
621			`* End: Multiplexing TDO data *`
622			`* *`
623			`**********************************************************************************/`
624
625
626			`always @ (negedge tck_pad_i)`
627			`begin`
628			`shift_ir_neg <= #1 shift_ir;`
629			`latched_jtag_ir_neg <= #1 latched_jtag_ir;`
630			`end`
631
632
633			`endmodule`