URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [uart16550/] [Makefile] - Blame information for rev 27

Line No.	Rev	Author	Line
1	18	unneback	`uart_ip:`
2			`cat raminfr.v uart_sync_flops.v uart_regs.v uart_rfifo.v uart_tfifo.v uart_receiver.v uart_transmitter.v uart_debug_if.v uart_wb.v uart_top.v > uart_ip.v`
3			`all: uart_ip`