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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [Makefile] - Blame information for rev 18

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Line No. Rev Author Line
1 18 unneback
define:
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        vpp wb_sdram_ctrl_defines.vpp > wb_sdram_ctrl_defines.v
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basic: define
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        perl fizzim.pl -terse < wb_sdram_ctrl_burst.fzm > wb_sdram_ctrl_burst.v
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        perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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MT48LC16M16:
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        cp ./MT48LC16M16.v ./defines.v
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fifo:
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        vpp wb_sdram_ctrl_fifo.vpp > fifo.v
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        vppp --simple fifo.v > wb_sdram_ctrl_fifo.v
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all: MT48LC16M16 fifo basic
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        vppp --simple delay.v wb_sdram_ctrl_fsm.v wb_sdram_ctrl_fifo.v wb_sdram_ctrl_top.v > wb_sdram_ctrl_ip.v
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