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//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's definitions                                        ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Parameters of the OR1200 core                               ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - add parameters that are missing                          ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: or1200_defines.v,v $
47 
// Revision 1.45  2006/04/09 01:32:29  lampret
48 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
49 
//
50 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
51 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
52 
//
53 
// Revision 1.43  2005/01/07 09:23:39  andreje
54 
// l.ff1 and l.cmov instructions added
55 
//
56 
// Revision 1.42  2004/06/08 18:17:36  lampret
57 
// Non-functional changes. Coding style fixes.
58 
//
59 
// Revision 1.41  2004/05/09 20:03:20  lampret
60 
// By default l.cust5 insns are disabled
61 
//
62 
// Revision 1.40  2004/05/09 19:49:04  lampret
63 
// Added some l.cust5 custom instructions as example
64 
//
65 
// Revision 1.39  2004/04/08 11:00:46  simont
66 
// Add support for 512B instruction cache.
67 
//
68 
// Revision 1.38  2004/04/05 08:29:57  lampret
69 
// Merged branch_qmem into main tree.
70 
//
71 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
72 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
73 
//
74 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
75 
// interface to debug changed; no more opselect; stb-ack protocol
76 
//
77 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
78 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
79 
//
80 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
81 
// Exception prefix configuration changed.
82 
//
83 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
84 
// Static exception prefix.
85 
//
86 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
87 
// Added embedded memory QMEM.
88 
//
89 
// Revision 1.35  2003/04/24 00:16:07  lampret
90 
// No functional changes. Added defines to disable implementation of multiplier/MAC
91 
//
92 
// Revision 1.34  2003/04/20 22:23:57  lampret
93 
// No functional change. Only added customization for exception vectors.
94 
//
95 
// Revision 1.33  2003/04/07 20:56:07  lampret
96 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
97 
//
98 
// Revision 1.32  2003/04/07 01:26:57  lampret
99 
// RFRAM defines comments updated. Altera LPM option added.
100 
//
101 
// Revision 1.31  2002/12/08 08:57:56  lampret
102 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
103 
//
104 
// Revision 1.30  2002/10/28 15:09:22  mohor
105 
// Previous check-in was done by mistake.
106 
//
107 
// Revision 1.29  2002/10/28 15:03:50  mohor
108 
// Signal scanb_sen renamed to scanb_en.
109 
//
110 
// Revision 1.28  2002/10/17 20:04:40  lampret
111 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
112 
//
113 
// Revision 1.27  2002/09/16 03:13:23  lampret
114 
// Removed obsolete comment.
115 
//
116 
// Revision 1.26  2002/09/08 05:52:16  lampret
117 
// Added optional l.div/l.divu insns. By default they are disabled.
118 
//
119 
// Revision 1.25  2002/09/07 19:16:10  lampret
120 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
121 
//
122 
// Revision 1.24  2002/09/07 05:42:02  lampret
123 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
124 
//
125 
// Revision 1.23  2002/09/04 00:50:34  lampret
126 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
127 
//
128 
// Revision 1.22  2002/09/03 22:28:21  lampret
129 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
130 
//
131 
// Revision 1.21  2002/08/22 02:18:55  lampret
132 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
133 
//
134 
// Revision 1.20  2002/08/18 21:59:45  lampret
135 
// Disable SB until it is tested
136 
//
137 
// Revision 1.19  2002/08/18 19:53:08  lampret
138 
// Added store buffer.
139 
//
140 
// Revision 1.18  2002/08/15 06:04:11  lampret
141 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
142 
//
143 
// Revision 1.17  2002/08/12 05:31:44  lampret
144 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
145 
//
146 
// Revision 1.16  2002/07/14 22:17:17  lampret
147 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
148 
//
149 
// Revision 1.15  2002/06/08 16:20:21  lampret
150 
// Added defines for enabling generic FF based memory macro for register file.
151 
//
152 
// Revision 1.14  2002/03/29 16:24:06  lampret
153 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
154 
//
155 
// Revision 1.13  2002/03/29 15:16:55  lampret
156 
// Some of the warnings fixed.
157 
//
158 
// Revision 1.12  2002/03/28 19:25:42  lampret
159 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
160 
//
161 
// Revision 1.11  2002/03/28 19:13:17  lampret
162 
// Updated defines.
163 
//
164 
// Revision 1.10  2002/03/14 00:30:24  lampret
165 
// Added alternative for critical path in DU.
166 
//
167 
// Revision 1.9  2002/03/11 01:26:26  lampret
168 
// Fixed async loop. Changed multiplier type for ASIC.
169 
//
170 
// Revision 1.8  2002/02/11 04:33:17  lampret
171 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
172 
//
173 
// Revision 1.7  2002/02/01 19:56:54  lampret
174 
// Fixed combinational loops.
175 
//
176 
// Revision 1.6  2002/01/19 14:10:22  lampret
177 
// Fixed OR1200_XILINX_RAM32X1D.
178 
//
179 
// Revision 1.5  2002/01/18 07:56:00  lampret
180 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
181 
//
182 
// Revision 1.4  2002/01/14 09:44:12  lampret
183 
// Default ASIC configuration does not sample WB inputs.
184 
//
185 
// Revision 1.3  2002/01/08 00:51:08  lampret
186 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
187 
//
188 
// Revision 1.2  2002/01/03 21:23:03  lampret
189 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
190 
//
191 
// Revision 1.1  2002/01/03 08:16:15  lampret
192 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
193 
//
194 
// Revision 1.20  2001/12/04 05:02:36  lampret
195 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
196 
//
197 
// Revision 1.19  2001/11/27 19:46:57  lampret
198 
// Now FPGA and ASIC target are separate.
199 
//
200 
// Revision 1.18  2001/11/23 21:42:31  simons
201 
// Program counter divided to PPC and NPC.
202 
//
203 
// Revision 1.17  2001/11/23 08:38:51  lampret
204 
// Changed DSR/DRR behavior and exception detection.
205 
//
206 
// Revision 1.16  2001/11/20 21:30:38  lampret
207 
// Added OR1200_REGISTERED_INPUTS.
208 
//
209 
// Revision 1.15  2001/11/19 14:29:48  simons
210 
// Cashes disabled.
211 
//
212 
// Revision 1.14  2001/11/13 10:02:21  lampret
213 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
214 
//
215 
// Revision 1.13  2001/11/12 01:45:40  lampret
216 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
217 
//
218 
// Revision 1.12  2001/11/10 03:43:57  lampret
219 
// Fixed exceptions.
220 
//
221 
// Revision 1.11  2001/11/02 18:57:14  lampret
222 
// Modified virtual silicon instantiations.
223 
//
224 
// Revision 1.10  2001/10/21 17:57:16  lampret
225 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
226 
//
227 
// Revision 1.9  2001/10/19 23:28:46  lampret
228 
// Fixed some synthesis warnings. Configured with caches and MMUs.
229 
//
230 
// Revision 1.8  2001/10/14 13:12:09  lampret
231 
// MP3 version.
232 
//
233 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
234 
// no message
235 
//
236 
// Revision 1.3  2001/08/17 08:01:19  lampret
237 
// IC enable/disable.
238 
//
239 
// Revision 1.2  2001/08/13 03:36:20  lampret
240 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
241 
//
242 
// Revision 1.1  2001/08/09 13:39:33  lampret
243 
// Major clean-up.
244 
//
245 
// Revision 1.2  2001/07/22 03:31:54  lampret
246 
// Fixed RAM's oen bug. Cache bypass under development.
247 
//
248 
// Revision 1.1  2001/07/20 00:46:03  lampret
249 
// Development version of RTL. Libraries are missing.
250 
//
251 
//
252 
 
253 
//
254 
// Dump VCD
255 
//
256 
//`define OR1200_VCD_DUMP
257 
 
258 
//
259 
// Generate debug messages during simulation
260 
//
261 
//`define OR1200_VERBOSE
262 
 
263 
//  `define OR1200_ASIC
264 
////////////////////////////////////////////////////////
265 
//
266 
// Typical configuration for an ASIC
267 
//
268 
`ifdef OR1200_ASIC
269 
 
270 
//
271 
// Target ASIC memories
272 
//
273 
//`define OR1200_ARTISAN_SSP
274 
//`define OR1200_ARTISAN_SDP
275 
//`define OR1200_ARTISAN_STP
276 
`define OR1200_VIRTUALSILICON_SSP
277 
//`define OR1200_VIRTUALSILICON_STP_T1
278 
//`define OR1200_VIRTUALSILICON_STP_T2
279 
 
280 
//
281 
// Do not implement Data cache
282 
//
283 
//`define OR1200_NO_DC
284 
 
285 
//
286 
// Do not implement Insn cache
287 
//
288 
//`define OR1200_NO_IC
289 
 
290 
//
291 
// Do not implement Data MMU
292 
//
293 
//`define OR1200_NO_DMMU
294 
 
295 
//
296 
// Do not implement Insn MMU
297 
//
298 
//`define OR1200_NO_IMMU
299 
 
300 
//
301 
// Select between ASIC optimized and generic multiplier
302 
//
303 
//`define OR1200_ASIC_MULTP2_32X32
304 
`define OR1200_GENERIC_MULTP2_32X32
305 
 
306 
//
307 
// Size/type of insn/data cache if implemented
308 
//
309 
// `define OR1200_IC_1W_512B
310 
// `define OR1200_IC_1W_4KB
311 
`define OR1200_IC_1W_8KB
312 
// `define OR1200_DC_1W_4KB
313 
`define OR1200_DC_1W_8KB
314 
 
315 
`else
316 
 
317 
 
318 
/////////////////////////////////////////////////////////
319 
//
320 
// Typical configuration for an FPGA
321 
//
322 
 
323 
//
324 
// Target FPGA memories
325 
//
326 
//`define OR1200_ALTERA_LPM
327 
//`define OR1200_XILINX_RAMB16
328 
//`define OR1200_XILINX_RAMB4
329 
//`define OR1200_XILINX_RAM32X1D
330 
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
331 
`define OR1200_ACTEL
332 
 
333 
//
334 
// Do not implement Data cache
335 
//
336 
`define OR1200_NO_DC
337 
 
338 
//
339 
// Do not implement Insn cache
340 
//
341 
//`define OR1200_NO_IC
342 
 
343 
//
344 
// Do not implement Data MMU
345 
//
346 
//`define OR1200_NO_DMMU
347 
 
348 
//
349 
// Do not implement Insn MMU
350 
//
351 
//`define OR1200_NO_IMMU
352 
 
353 
//
354 
// Select between ASIC and generic multiplier
355 
//
356 
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
357 
//
358 
//`define OR1200_ASIC_MULTP2_32X32
359 
`define OR1200_GENERIC_MULTP2_32X32
360 
 
361 
//
362 
// Size/type of insn/data cache if implemented
363 
// (consider available FPGA memory resources)
364 
//
365 
//`define OR1200_IC_1W_512B
366 
`define OR1200_IC_1W_4KB
367 
//`define OR1200_IC_1W_8KB
368 
`define OR1200_DC_1W_4KB
369 
//`define OR1200_DC_1W_8KB
370 
 
371 
`endif
372 
 
373 
 
374 
//////////////////////////////////////////////////////////
375 
//
376 
// Do not change below unless you know what you are doing
377 
//
378 
 
379 
//
380 
// Enable RAM BIST
381 
//
382 
// At the moment this only works for Virtual Silicon
383 
// single port RAMs. For other RAMs it has not effect.
384 
// Special wrapper for VS RAMs needs to be provided
385 
// with scan flops to facilitate bist scan.
386 
//
387 
//`define OR1200_BIST
388 
 
389 
//
390 
// Register OR1200 WISHBONE outputs
391 
// (must be defined/enabled)
392 
//
393 
`define OR1200_REGISTERED_OUTPUTS
394 
 
395 
//
396 
// Register OR1200 WISHBONE inputs
397 
//
398 
// (must be undefined/disabled)
399 
//
400 
//`define OR1200_REGISTERED_INPUTS
401 
 
402 
//
403 
// Disable bursts if they are not supported by the
404 
// memory subsystem (only affect cache line fill)
405 
//
406 
//`define OR1200_NO_BURSTS
407 
//
408 
 
409 
//
410 
// WISHBONE retry counter range
411 
//
412 
// 2^value range for retry counter. Retry counter
413 
// is activated whenever *wb_rty_i is asserted and
414 
// until retry counter expires, corresponding
415 
// WISHBONE interface is deactivated.
416 
//
417 
// To disable retry counters and *wb_rty_i all together,
418 
// undefine this macro.
419 
//
420 
//`define OR1200_WB_RETRY 7
421 
 
422 
//
423 
// WISHBONE Consecutive Address Burst
424 
//
425 
// This was used prior to WISHBONE B3 specification
426 
// to identify bursts. It is no longer needed but
427 
// remains enabled for compatibility with old designs.
428 
//
429 
// To remove *wb_cab_o ports undefine this macro.
430 
//
431 
//`define OR1200_WB_CAB
432 
 
433 
//
434 
// WISHBONE B3 compatible interface
435 
//
436 
// This follows the WISHBONE B3 specification.
437 
// It is not enabled by default because most
438 
// designs still don't use WB b3.
439 
//
440 
// To enable *wb_cti_o/*wb_bte_o ports,
441 
// define this macro.
442 
//
443 
`define OR1200_WB_B3
444 
 
445 
//
446 
// LOG all WISHBONE accesses
447 
//
448 
`define OR1200_LOG_WB_ACCESS
449 
 
450 
//
451 
// Enable additional synthesis directives if using
452 
// _Synopsys_ synthesis tool
453 
//
454 
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
455 
 
456 
//
457 
// Enables default statement in some case blocks
458 
// and disables Synopsys synthesis directive full_case
459 
//
460 
// By default it is enabled. When disabled it
461 
// can increase clock frequency.
462 
//
463 
`define OR1200_CASE_DEFAULT
464 
 
465 
//
466 
// Operand width / register file address width
467 
//
468 
// (DO NOT CHANGE)
469 
//
470 
`define OR1200_OPERAND_WIDTH            32
471 
`define OR1200_REGFILE_ADDR_WIDTH       5
472 
 
473 
//
474 
// l.add/l.addi/l.and and optional l.addc/l.addic
475 
// also set (compare) flag when result of their
476 
// operation equals zero
477 
//
478 
// At the time of writing this, default or32
479 
// C/C++ compiler doesn't generate code that
480 
// would benefit from this optimization.
481 
//
482 
// By default this optimization is disabled to
483 
// save area.
484 
//
485 
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
486 
 
487 
//
488 
// Implement l.addc/l.addic instructions
489 
//
490 
// By default implementation of l.addc/l.addic
491 
// instructions is enabled in case you need them.
492 
// If you don't use them, then disable implementation
493 
// to save area.
494 
//
495 
`define OR1200_IMPL_ADDC
496 
 
497 
//
498 
// Implement carry bit SR[CY]
499 
//
500 
// By default implementation of SR[CY] is enabled
501 
// to be compliant with the simulator. However
502 
// SR[CY] is explicitly only used by l.addc/l.addic
503 
// instructions and if these two insns are not
504 
// implemented there is not much point having SR[CY].
505 
//
506 
`define OR1200_IMPL_CY
507 
 
508 
//
509 
// Implement optional l.div/l.divu instructions
510 
//
511 
// By default divide instructions are not implemented
512 
// to save area and increase clock frequency. or32 C/C++
513 
// compiler can use soft library for division.
514 
//
515 
// To implement divide, multiplier needs to be implemented.
516 
//
517 
//`define OR1200_IMPL_DIV
518 
 
519 
//
520 
// Implement rotate in the ALU
521 
//
522 
// At the time of writing this, or32
523 
// C/C++ compiler doesn't generate rotate
524 
// instructions. However or32 assembler
525 
// can assemble code that uses rotate insn.
526 
// This means that rotate instructions
527 
// must be used manually inserted.
528 
//
529 
// By default implementation of rotate
530 
// is disabled to save area and increase
531 
// clock frequency.
532 
//
533 
//`define OR1200_IMPL_ALU_ROTATE
534 
 
535 
//
536 
// Type of ALU compare to implement
537 
//
538 
// Try either one to find what yields
539 
// higher clock frequencyin your case.
540 
//
541 
//`define OR1200_IMPL_ALU_COMP1
542 
`define OR1200_IMPL_ALU_COMP2
543 
 
544 
//
545 
// Implement multiplier
546 
//
547 
// By default multiplier is implemented
548 
//
549 
`define OR1200_MULT_IMPLEMENTED
550 
 
551 
//
552 
// Implement multiply-and-accumulate
553 
//
554 
// By default MAC is implemented. To
555 
// implement MAC, multiplier needs to be
556 
// implemented.
557 
//
558 
//`define OR1200_MAC_IMPLEMENTED
559 
 
560 
//
561 
// Low power, slower multiplier
562 
//
563 
// Select between low-power (larger) multiplier
564 
// and faster multiplier. The actual difference
565 
// is only AND logic that prevents distribution
566 
// of operands into the multiplier when instruction
567 
// in execution is not multiply instruction
568 
//
569 
//`define OR1200_LOWPWR_MULT
570 
 
571 
//
572 
// Clock ratio RISC clock versus WB clock
573 
//
574 
// If you plan to run WB:RISC clock fixed to 1:1, disable
575 
// both defines
576 
//
577 
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
578 
// and use clmode to set ratio
579 
//
580 
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
581 
// clmode to set ratio
582 
//
583 
`define OR1200_CLKDIV_2_SUPPORTED
584 
//`define OR1200_CLKDIV_4_SUPPORTED
585 
 
586 
//
587 
// Type of register file RAM
588 
//
589 
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
590 
//`define OR1200_RFRAM_TWOPORT
591 
//
592 
// Memory macro dual port (see or1200_dpram_32x32.v)
593 
`define OR1200_RFRAM_DUALPORT
594 
 
595 
//
596 
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
597 
//`define OR1200_RFRAM_GENERIC
598 
//  Generic register file supports - 16 registers
599 
`ifdef OR1200_RFRAM_GENERIC
600 
//    `define OR1200_RFRAM_16REG
601 
`endif
602 
 
603 
//
604 
// Type of mem2reg aligner to implement.
605 
//
606 
// Once OR1200_IMPL_MEM2REG2 yielded faster
607 
// circuit, however with today tools it will
608 
// most probably give you slower circuit.
609 
//
610 
`define OR1200_IMPL_MEM2REG1
611 
//`define OR1200_IMPL_MEM2REG2
612 
 
613 
//
614 
// ALUOPs
615 
//
616 
`define OR1200_ALUOP_WIDTH      4
617 
`define OR1200_ALUOP_NOP        4'd4
618 
/* Order defined by arith insns that have two source operands both in regs
619 
   (see binutils/include/opcode/or32.h) */
620 
`define OR1200_ALUOP_ADD        4'd0
621 
`define OR1200_ALUOP_ADDC       4'd1
622 
`define OR1200_ALUOP_SUB        4'd2
623 
`define OR1200_ALUOP_AND        4'd3
624 
`define OR1200_ALUOP_OR         4'd4
625 
`define OR1200_ALUOP_XOR        4'd5
626 
`define OR1200_ALUOP_MUL        4'd6
627 
`define OR1200_ALUOP_CUST5      4'd7
628 
`define OR1200_ALUOP_SHROT      4'd8
629 
`define OR1200_ALUOP_DIV        4'd9
630 
`define OR1200_ALUOP_DIVU       4'd10
631 
/* Order not specifically defined. */
632 
`define OR1200_ALUOP_IMM        4'd11
633 
`define OR1200_ALUOP_MOVHI      4'd12
634 
`define OR1200_ALUOP_COMP       4'd13
635 
`define OR1200_ALUOP_MTSR       4'd14
636 
`define OR1200_ALUOP_MFSR       4'd15
637 
`define OR1200_ALUOP_CMOV   4'd14
638 
`define OR1200_ALUOP_FF1    4'd15
639 
//
640 
// MACOPs
641 
//
642 
`define OR1200_MACOP_WIDTH      2
643 
`define OR1200_MACOP_NOP        2'b00
644 
`define OR1200_MACOP_MAC        2'b01
645 
`define OR1200_MACOP_MSB        2'b10
646 
 
647 
//
648 
// Shift/rotate ops
649 
//
650 
`define OR1200_SHROTOP_WIDTH    2
651 
`define OR1200_SHROTOP_NOP      2'd0
652 
`define OR1200_SHROTOP_SLL      2'd0
653 
`define OR1200_SHROTOP_SRL      2'd1
654 
`define OR1200_SHROTOP_SRA      2'd2
655 
`define OR1200_SHROTOP_ROR      2'd3
656 
 
657 
// Execution cycles per instruction
658 
`define OR1200_MULTICYCLE_WIDTH 2
659 
`define OR1200_ONE_CYCLE                2'd0
660 
`define OR1200_TWO_CYCLES               2'd1
661 
 
662 
// Operand MUX selects
663 
`define OR1200_SEL_WIDTH                2
664 
`define OR1200_SEL_RF                   2'd0
665 
`define OR1200_SEL_IMM                  2'd1
666 
`define OR1200_SEL_EX_FORW              2'd2
667 
`define OR1200_SEL_WB_FORW              2'd3
668 
 
669 
//
670 
// BRANCHOPs
671 
//
672 
`define OR1200_BRANCHOP_WIDTH           3
673 
`define OR1200_BRANCHOP_NOP             3'd0
674 
`define OR1200_BRANCHOP_J               3'd1
675 
`define OR1200_BRANCHOP_JR              3'd2
676 
`define OR1200_BRANCHOP_BAL             3'd3
677 
`define OR1200_BRANCHOP_BF              3'd4
678 
`define OR1200_BRANCHOP_BNF             3'd5
679 
`define OR1200_BRANCHOP_RFE             3'd6
680 
 
681 
//
682 
// LSUOPs
683 
//
684 
// Bit 0: sign extend
685 
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
686 
// Bit 3: 0 load, 1 store
687 
`define OR1200_LSUOP_WIDTH              4
688 
`define OR1200_LSUOP_NOP                4'b0000
689 
`define OR1200_LSUOP_LBZ                4'b0010
690 
`define OR1200_LSUOP_LBS                4'b0011
691 
`define OR1200_LSUOP_LHZ                4'b0100
692 
`define OR1200_LSUOP_LHS                4'b0101
693 
`define OR1200_LSUOP_LWZ                4'b0110
694 
`define OR1200_LSUOP_LWS                4'b0111
695 
`define OR1200_LSUOP_LD         4'b0001
696 
`define OR1200_LSUOP_SD         4'b1000
697 
`define OR1200_LSUOP_SB         4'b1010
698 
`define OR1200_LSUOP_SH         4'b1100
699 
`define OR1200_LSUOP_SW         4'b1110
700 
 
701 
// FETCHOPs
702 
`define OR1200_FETCHOP_WIDTH            1
703 
`define OR1200_FETCHOP_NOP              1'b0
704 
`define OR1200_FETCHOP_LW               1'b1
705 
 
706 
//
707 
// Register File Write-Back OPs
708 
//
709 
// Bit 0: register file write enable
710 
// Bits 2-1: write-back mux selects
711 
`define OR1200_RFWBOP_WIDTH             3
712 
`define OR1200_RFWBOP_NOP               3'b000
713 
`define OR1200_RFWBOP_ALU               3'b001
714 
`define OR1200_RFWBOP_LSU               3'b011
715 
`define OR1200_RFWBOP_SPRS              3'b101
716 
`define OR1200_RFWBOP_LR                3'b111
717 
 
718 
// Compare instructions
719 
`define OR1200_COP_SFEQ       3'b000
720 
`define OR1200_COP_SFNE       3'b001
721 
`define OR1200_COP_SFGT       3'b010
722 
`define OR1200_COP_SFGE       3'b011
723 
`define OR1200_COP_SFLT       3'b100
724 
`define OR1200_COP_SFLE       3'b101
725 
`define OR1200_COP_X          3'b111
726 
`define OR1200_SIGNED_COMPARE 'd3
727 
`define OR1200_COMPOP_WIDTH     4
728 
 
729 
//
730 
// TAGs for instruction bus
731 
//
732 
`define OR1200_ITAG_IDLE        4'h0    // idle bus
733 
`define OR1200_ITAG_NI          4'h1    // normal insn
734 
`define OR1200_ITAG_BE          4'hb    // Bus error exception
735 
`define OR1200_ITAG_PE          4'hc    // Page fault exception
736 
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
737 
 
738 
//
739 
// TAGs for data bus
740 
//
741 
`define OR1200_DTAG_IDLE        4'h0    // idle bus
742 
`define OR1200_DTAG_ND          4'h1    // normal data
743 
`define OR1200_DTAG_AE          4'ha    // Alignment exception
744 
`define OR1200_DTAG_BE          4'hb    // Bus error exception
745 
`define OR1200_DTAG_PE          4'hc    // Page fault exception
746 
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
747 
 
748 
 
749 
//////////////////////////////////////////////
750 
//
751 
// ORBIS32 ISA specifics
752 
//
753 
 
754 
// SHROT_OP position in machine word
755 
`define OR1200_SHROTOP_POS              7:6
756 
 
757 
// ALU instructions multicycle field in machine word
758 
`define OR1200_ALUMCYC_POS              9:8
759 
 
760 
//
761 
// Instruction opcode groups (basic)
762 
//
763 
`define OR1200_OR32_J                 6'b000000
764 
`define OR1200_OR32_JAL               6'b000001
765 
`define OR1200_OR32_BNF               6'b000011
766 
`define OR1200_OR32_BF                6'b000100
767 
`define OR1200_OR32_NOP               6'b000101
768 
`define OR1200_OR32_MOVHI             6'b000110
769 
`define OR1200_OR32_XSYNC             6'b001000
770 
`define OR1200_OR32_RFE               6'b001001
771 
/* */
772 
`define OR1200_OR32_JR                6'b010001
773 
`define OR1200_OR32_JALR              6'b010010
774 
`define OR1200_OR32_MACI              6'b010011
775 
/* */
776 
`define OR1200_OR32_LWZ               6'b100001
777 
`define OR1200_OR32_LBZ               6'b100011
778 
`define OR1200_OR32_LBS               6'b100100
779 
`define OR1200_OR32_LHZ               6'b100101
780 
`define OR1200_OR32_LHS               6'b100110
781 
`define OR1200_OR32_ADDI              6'b100111
782 
`define OR1200_OR32_ADDIC             6'b101000
783 
`define OR1200_OR32_ANDI              6'b101001
784 
`define OR1200_OR32_ORI               6'b101010
785 
`define OR1200_OR32_XORI              6'b101011
786 
`define OR1200_OR32_MULI              6'b101100
787 
`define OR1200_OR32_MFSPR             6'b101101
788 
`define OR1200_OR32_SH_ROTI           6'b101110
789 
`define OR1200_OR32_SFXXI             6'b101111
790 
/* */
791 
`define OR1200_OR32_MTSPR             6'b110000
792 
`define OR1200_OR32_MACMSB            6'b110001
793 
/* */
794 
`define OR1200_OR32_SW                6'b110101
795 
`define OR1200_OR32_SB                6'b110110
796 
`define OR1200_OR32_SH                6'b110111
797 
`define OR1200_OR32_ALU               6'b111000
798 
`define OR1200_OR32_SFXX              6'b111001
799 
//`define OR1200_OR32_CUST5             6'b111100
800 
 
801 
 
802 
/////////////////////////////////////////////////////
803 
//
804 
// Exceptions
805 
//
806 
 
807 
//
808 
// Exception vectors per OR1K architecture:
809 
// 0xPPPPP100 - reset
810 
// 0xPPPPP200 - bus error
811 
// ... etc
812 
// where P represents exception prefix.
813 
//
814 
// Exception vectors can be customized as per
815 
// the following formula:
816 
// 0xPPPPPNVV - exception N
817 
//
818 
// P represents exception prefix
819 
// N represents exception N
820 
// VV represents length of the individual vector space,
821 
//   usually it is 8 bits wide and starts with all bits zero
822 
//
823 
 
824 
//
825 
// PPPPP and VV parts
826 
//
827 
// Sum of these two defines needs to be 28
828 
//
829 
`define OR1200_EXCEPT_EPH0_P    20'h00000
830 
`define OR1200_EXCEPT_EPH1_P    20'hF0000
831 
`define OR1200_EXCEPT_V             8'h00
832 
 
833 
//
834 
// N part width
835 
//
836 
`define OR1200_EXCEPT_WIDTH 4
837 
 
838 
//
839 
// Definition of exception vectors
840 
//
841 
// To avoid implementation of a certain exception,
842 
// simply comment out corresponding line
843 
//
844 
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
845 
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
846 
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
847 
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
848 
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
849 
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
850 
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
851 
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
852 
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
853 
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
854 
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
855 
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
856 
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
857 
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
858 
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
859 
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
860 
 
861 
 
862 
/////////////////////////////////////////////////////
863 
//
864 
// SPR groups
865 
//
866 
 
867 
// Bits that define the group
868 
`define OR1200_SPR_GROUP_BITS   15:11
869 
 
870 
// Width of the group bits
871 
`define OR1200_SPR_GROUP_WIDTH  5
872 
 
873 
// Bits that define offset inside the group
874 
`define OR1200_SPR_OFS_BITS 10:0
875 
 
876 
// List of groups
877 
`define OR1200_SPR_GROUP_SYS    5'd00
878 
`define OR1200_SPR_GROUP_DMMU   5'd01
879 
`define OR1200_SPR_GROUP_IMMU   5'd02
880 
`define OR1200_SPR_GROUP_DC     5'd03
881 
`define OR1200_SPR_GROUP_IC     5'd04
882 
`define OR1200_SPR_GROUP_MAC    5'd05
883 
`define OR1200_SPR_GROUP_DU     5'd06
884 
`define OR1200_SPR_GROUP_PM     5'd08
885 
`define OR1200_SPR_GROUP_PIC    5'd09
886 
`define OR1200_SPR_GROUP_TT     5'd10
887 
 
888 
 
889 
/////////////////////////////////////////////////////
890 
//
891 
// System group
892 
//
893 
 
894 
//
895 
// System registers
896 
//
897 
`define OR1200_SPR_CFGR         7'd0
898 
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
899 
`define OR1200_SPR_NPC          11'd16
900 
`define OR1200_SPR_SR           11'd17
901 
`define OR1200_SPR_PPC          11'd18
902 
`define OR1200_SPR_EPCR         11'd32
903 
`define OR1200_SPR_EEAR         11'd48
904 
`define OR1200_SPR_ESR          11'd64
905 
 
906 
//
907 
// SR bits
908 
//
909 
`define OR1200_SR_WIDTH 16
910 
`define OR1200_SR_SM   0
911 
`define OR1200_SR_TEE  1
912 
`define OR1200_SR_IEE  2
913 
`define OR1200_SR_DCE  3
914 
`define OR1200_SR_ICE  4
915 
`define OR1200_SR_DME  5
916 
`define OR1200_SR_IME  6
917 
`define OR1200_SR_LEE  7
918 
`define OR1200_SR_CE   8
919 
`define OR1200_SR_F    9
920 
`define OR1200_SR_CY   10       // Unused
921 
`define OR1200_SR_OV   11       // Unused
922 
`define OR1200_SR_OVE  12       // Unused
923 
`define OR1200_SR_DSX  13       // Unused
924 
`define OR1200_SR_EPH  14
925 
`define OR1200_SR_FO   15
926 
`define OR1200_SR_CID  31:28    // Unimplemented
927 
 
928 
//
929 
// Bits that define offset inside the group
930 
//
931 
`define OR1200_SPROFS_BITS 10:0
932 
 
933 
//
934 
// Default Exception Prefix
935 
//
936 
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
937 
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
938 
//
939 
`define OR1200_SR_EPH_DEF       1'b0
940 
 
941 
/////////////////////////////////////////////////////
942 
//
943 
// Power Management (PM)
944 
//
945 
 
946 
// Define it if you want PM implemented
947 
//`define OR1200_PM_IMPLEMENTED
948 
 
949 
// Bit positions inside PMR (don't change)
950 
`define OR1200_PM_PMR_SDF 3:0
951 
`define OR1200_PM_PMR_DME 4
952 
`define OR1200_PM_PMR_SME 5
953 
`define OR1200_PM_PMR_DCGE 6
954 
`define OR1200_PM_PMR_UNUSED 31:7
955 
 
956 
// PMR offset inside PM group of registers
957 
`define OR1200_PM_OFS_PMR 11'b0
958 
 
959 
// PM group
960 
`define OR1200_SPRGRP_PM 5'd8
961 
 
962 
// Define if PMR can be read/written at any address inside PM group
963 
`define OR1200_PM_PARTIAL_DECODING
964 
 
965 
// Define if reading PMR is allowed
966 
`define OR1200_PM_READREGS
967 
 
968 
// Define if unused PMR bits should be zero
969 
`define OR1200_PM_UNUSED_ZERO
970 
 
971 
 
972 
/////////////////////////////////////////////////////
973 
//
974 
// Debug Unit (DU)
975 
//
976 
 
977 
// Define it if you want DU implemented
978 
`define OR1200_DU_IMPLEMENTED
979 
 
980 
//
981 
// Define if you want HW Breakpoints
982 
// (if HW breakpoints are not implemented
983 
// only default software trapping is
984 
// possible with l.trap insn - this is
985 
// however already enough for use
986 
// with or32 gdb)
987 
//
988 
//`define OR1200_DU_HWBKPTS
989 
 
990 
// Number of DVR/DCR pairs if HW breakpoints enabled
991 
`define OR1200_DU_DVRDCR_PAIRS 8
992 
 
993 
// Define if you want trace buffer
994 
//`define OR1200_DU_TB_IMPLEMENTED
995 
 
996 
//
997 
// Address offsets of DU registers inside DU group
998 
//
999 
// To not implement a register, doq not define its address
1000 
//
1001 
`ifdef OR1200_DU_HWBKPTS
1002 
`define OR1200_DU_DVR0          11'd0
1003 
`define OR1200_DU_DVR1          11'd1
1004 
`define OR1200_DU_DVR2          11'd2
1005 
`define OR1200_DU_DVR3          11'd3
1006 
`define OR1200_DU_DVR4          11'd4
1007 
`define OR1200_DU_DVR5          11'd5
1008 
`define OR1200_DU_DVR6          11'd6
1009 
`define OR1200_DU_DVR7          11'd7
1010 
`define OR1200_DU_DCR0          11'd8
1011 
`define OR1200_DU_DCR1          11'd9
1012 
`define OR1200_DU_DCR2          11'd10
1013 
`define OR1200_DU_DCR3          11'd11
1014 
`define OR1200_DU_DCR4          11'd12
1015 
`define OR1200_DU_DCR5          11'd13
1016 
`define OR1200_DU_DCR6          11'd14
1017 
`define OR1200_DU_DCR7          11'd15
1018 
`endif
1019 
`define OR1200_DU_DMR1          11'd16
1020 
`ifdef OR1200_DU_HWBKPTS
1021 
`define OR1200_DU_DMR2          11'd17
1022 
`define OR1200_DU_DWCR0         11'd18
1023 
`define OR1200_DU_DWCR1         11'd19
1024 
`endif
1025 
`define OR1200_DU_DSR           11'd20
1026 
`define OR1200_DU_DRR           11'd21
1027 
`ifdef OR1200_DU_TB_IMPLEMENTED
1028 
`define OR1200_DU_TBADR         11'h0ff
1029 
`define OR1200_DU_TBIA          11'h1xx
1030 
`define OR1200_DU_TBIM          11'h2xx
1031 
`define OR1200_DU_TBAR          11'h3xx
1032 
`define OR1200_DU_TBTS          11'h4xx
1033 
`endif
1034 
 
1035 
// Position of offset bits inside SPR address
1036 
`define OR1200_DUOFS_BITS       10:0
1037 
 
1038 
// DCR bits
1039 
`define OR1200_DU_DCR_DP        0
1040 
`define OR1200_DU_DCR_CC        3:1
1041 
`define OR1200_DU_DCR_SC        4
1042 
`define OR1200_DU_DCR_CT        7:5
1043 
 
1044 
// DMR1 bits
1045 
`define OR1200_DU_DMR1_CW0      1:0
1046 
`define OR1200_DU_DMR1_CW1      3:2
1047 
`define OR1200_DU_DMR1_CW2      5:4
1048 
`define OR1200_DU_DMR1_CW3      7:6
1049 
`define OR1200_DU_DMR1_CW4      9:8
1050 
`define OR1200_DU_DMR1_CW5      11:10
1051 
`define OR1200_DU_DMR1_CW6      13:12
1052 
`define OR1200_DU_DMR1_CW7      15:14
1053 
`define OR1200_DU_DMR1_CW8      17:16
1054 
`define OR1200_DU_DMR1_CW9      19:18
1055 
`define OR1200_DU_DMR1_CW10     21:20
1056 
`define OR1200_DU_DMR1_ST       22
1057 
`define OR1200_DU_DMR1_BT       23
1058 
`define OR1200_DU_DMR1_DXFW     24
1059 
`define OR1200_DU_DMR1_ETE      25
1060 
 
1061 
// DMR2 bits
1062 
`define OR1200_DU_DMR2_WCE0     0
1063 
`define OR1200_DU_DMR2_WCE1     1
1064 
`define OR1200_DU_DMR2_AWTC     12:2
1065 
`define OR1200_DU_DMR2_WGB      23:13
1066 
 
1067 
// DWCR bits
1068 
`define OR1200_DU_DWCR_COUNT    15:0
1069 
`define OR1200_DU_DWCR_MATCH    31:16
1070 
 
1071 
// DSR bits
1072 
`define OR1200_DU_DSR_WIDTH     14
1073 
`define OR1200_DU_DSR_RSTE      0
1074 
`define OR1200_DU_DSR_BUSEE     1
1075 
`define OR1200_DU_DSR_DPFE      2
1076 
`define OR1200_DU_DSR_IPFE      3
1077 
`define OR1200_DU_DSR_TTE       4
1078 
`define OR1200_DU_DSR_AE        5
1079 
`define OR1200_DU_DSR_IIE       6
1080 
`define OR1200_DU_DSR_IE        7
1081 
`define OR1200_DU_DSR_DME       8
1082 
`define OR1200_DU_DSR_IME       9
1083 
`define OR1200_DU_DSR_RE        10
1084 
`define OR1200_DU_DSR_SCE       11
1085 
`define OR1200_DU_DSR_BE        12
1086 
`define OR1200_DU_DSR_TE        13
1087 
 
1088 
// DRR bits
1089 
`define OR1200_DU_DRR_RSTE      0
1090 
`define OR1200_DU_DRR_BUSEE     1
1091 
`define OR1200_DU_DRR_DPFE      2
1092 
`define OR1200_DU_DRR_IPFE      3
1093 
`define OR1200_DU_DRR_TTE       4
1094 
`define OR1200_DU_DRR_AE        5
1095 
`define OR1200_DU_DRR_IIE       6
1096 
`define OR1200_DU_DRR_IE        7
1097 
`define OR1200_DU_DRR_DME       8
1098 
`define OR1200_DU_DRR_IME       9
1099 
`define OR1200_DU_DRR_RE        10
1100 
`define OR1200_DU_DRR_SCE       11
1101 
`define OR1200_DU_DRR_BE        12
1102 
`define OR1200_DU_DRR_TE        13
1103 
 
1104 
// Define if reading DU regs is allowed
1105 
`define OR1200_DU_READREGS
1106 
 
1107 
// Define if unused DU registers bits should be zero
1108 
`define OR1200_DU_UNUSED_ZERO
1109 
 
1110 
// Define if IF/LSU status is not needed by devel i/f
1111 
`define OR1200_DU_STATUS_UNIMPLEMENTED
1112 
 
1113 
/////////////////////////////////////////////////////
1114 
//
1115 
// Programmable Interrupt Controller (PIC)
1116 
//
1117 
 
1118 
// Define it if you want PIC implemented
1119 
`define OR1200_PIC_IMPLEMENTED
1120 
 
1121 
// Define number of interrupt inputs (2-31)
1122 
`define OR1200_PIC_INTS 20
1123 
 
1124 
// Address offsets of PIC registers inside PIC group
1125 
`define OR1200_PIC_OFS_PICMR 2'd0
1126 
`define OR1200_PIC_OFS_PICSR 2'd2
1127 
 
1128 
// Position of offset bits inside SPR address
1129 
`define OR1200_PICOFS_BITS 1:0
1130 
 
1131 
// Define if you want these PIC registers to be implemented
1132 
`define OR1200_PIC_PICMR
1133 
`define OR1200_PIC_PICSR
1134 
 
1135 
// Define if reading PIC registers is allowed
1136 
`define OR1200_PIC_READREGS
1137 
 
1138 
// Define if unused PIC register bits should be zero
1139 
`define OR1200_PIC_UNUSED_ZERO
1140 
 
1141 
 
1142 
/////////////////////////////////////////////////////
1143 
//
1144 
// Tick Timer (TT)
1145 
//
1146 
 
1147 
// Define it if you want TT implemented
1148 
`define OR1200_TT_IMPLEMENTED
1149 
 
1150 
// Address offsets of TT registers inside TT group
1151 
`define OR1200_TT_OFS_TTMR 1'd0
1152 
`define OR1200_TT_OFS_TTCR 1'd1
1153 
 
1154 
// Position of offset bits inside SPR group
1155 
`define OR1200_TTOFS_BITS 0
1156 
 
1157 
// Define if you want these TT registers to be implemented
1158 
`define OR1200_TT_TTMR
1159 
`define OR1200_TT_TTCR
1160 
 
1161 
// TTMR bits
1162 
`define OR1200_TT_TTMR_TP 27:0
1163 
`define OR1200_TT_TTMR_IP 28
1164 
`define OR1200_TT_TTMR_IE 29
1165 
`define OR1200_TT_TTMR_M 31:30
1166 
 
1167 
// Define if reading TT registers is allowed
1168 
`define OR1200_TT_READREGS
1169 
 
1170 
 
1171 
//////////////////////////////////////////////
1172 
//
1173 
// MAC
1174 
//
1175 
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1176 
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1177 
 
1178 
//
1179 
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1180 
//
1181 
// According to architecture manual there is no shift, so default value is 0.
1182 
//
1183 
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1184 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1185 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1186 
// dest_GPR = {MACHI,MACLO}[59:28]
1187 
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1188 
 
1189 
 
1190 
//////////////////////////////////////////////
1191 
//
1192 
// Data MMU (DMMU)
1193 
//
1194 
 
1195 
//
1196 
// Address that selects between TLB TR and MR
1197 
//
1198 
`define OR1200_DTLB_TM_ADDR     7
1199 
 
1200 
//
1201 
// DTLBMR fields
1202 
//
1203 
`define OR1200_DTLBMR_V_BITS    0
1204 
`define OR1200_DTLBMR_CID_BITS  4:1
1205 
`define OR1200_DTLBMR_RES_BITS  11:5
1206 
`define OR1200_DTLBMR_VPN_BITS  31:13
1207 
 
1208 
//
1209 
// DTLBTR fields
1210 
//
1211 
`define OR1200_DTLBTR_CC_BITS   0
1212 
`define OR1200_DTLBTR_CI_BITS   1
1213 
`define OR1200_DTLBTR_WBC_BITS  2
1214 
`define OR1200_DTLBTR_WOM_BITS  3
1215 
`define OR1200_DTLBTR_A_BITS    4
1216 
`define OR1200_DTLBTR_D_BITS    5
1217 
`define OR1200_DTLBTR_URE_BITS  6
1218 
`define OR1200_DTLBTR_UWE_BITS  7
1219 
`define OR1200_DTLBTR_SRE_BITS  8
1220 
`define OR1200_DTLBTR_SWE_BITS  9
1221 
`define OR1200_DTLBTR_RES_BITS  11:10
1222 
`define OR1200_DTLBTR_PPN_BITS  31:13
1223 
 
1224 
//
1225 
// DTLB configuration
1226 
//
1227 
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1228 
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1229 
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1230 
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1231 
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1232 
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1233 
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1234 
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1235 
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1236 
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1237 
 
1238 
//
1239 
// Cache inhibit while DMMU is not enabled/implemented
1240 
//
1241 
// cache inhibited 0GB-4GB              1'b1
1242 
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1243 
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1244 
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1245 
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1246 
// cached 0GB-4GB                       1'b0
1247 
//
1248 
`define OR1200_DMMU_CI                  dcpu_cycstb_i && dcpu_adr_i[31]
1249 
 
1250 
 
1251 
//////////////////////////////////////////////
1252 
//
1253 
// Insn MMU (IMMU)
1254 
//
1255 
 
1256 
//
1257 
// Address that selects between TLB TR and MR
1258 
//
1259 
`define OR1200_ITLB_TM_ADDR     7
1260 
 
1261 
//
1262 
// ITLBMR fields
1263 
//
1264 
`define OR1200_ITLBMR_V_BITS    0
1265 
`define OR1200_ITLBMR_CID_BITS  4:1
1266 
`define OR1200_ITLBMR_RES_BITS  11:5
1267 
`define OR1200_ITLBMR_VPN_BITS  31:13
1268 
 
1269 
//
1270 
// ITLBTR fields
1271 
//
1272 
`define OR1200_ITLBTR_CC_BITS   0
1273 
`define OR1200_ITLBTR_CI_BITS   1
1274 
`define OR1200_ITLBTR_WBC_BITS  2
1275 
`define OR1200_ITLBTR_WOM_BITS  3
1276 
`define OR1200_ITLBTR_A_BITS    4
1277 
`define OR1200_ITLBTR_D_BITS    5
1278 
`define OR1200_ITLBTR_SXE_BITS  6
1279 
`define OR1200_ITLBTR_UXE_BITS  7
1280 
`define OR1200_ITLBTR_RES_BITS  11:8
1281 
`define OR1200_ITLBTR_PPN_BITS  31:13
1282 
 
1283 
//
1284 
// ITLB configuration
1285 
//
1286 
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1287 
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1288 
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1289 
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1290 
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1291 
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1292 
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1293 
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1294 
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1295 
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1296 
 
1297 
//
1298 
// Cache inhibit while IMMU is not enabled/implemented
1299 
// Note: all combinations that use icpu_adr_i cause async loop
1300 
//
1301 
// cache inhibited 0GB-4GB              1'b1
1302 
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1303 
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1304 
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1305 
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1306 
// cached 0GB-4GB                       1'b0
1307 
//
1308 
`define OR1200_IMMU_CI                  1'b0
1309 
 
1310 
 
1311 
/////////////////////////////////////////////////
1312 
//
1313 
// Insn cache (IC)
1314 
//
1315 
 
1316 
// 3 for 8 bytes, 4 for 16 bytes etc
1317 
`define OR1200_ICLS             4
1318 
 
1319 
//
1320 
// IC configurations
1321 
//
1322 
`ifdef OR1200_IC_1W_512B
1323 
`define OR1200_ICSIZE   9     // 512
1324 
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1325 
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1326 
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1327 
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1328 
`define OR1200_ICTAG_W  24
1329 
`endif
1330 
`ifdef OR1200_IC_1W_4KB
1331 
`define OR1200_ICSIZE                   12                      // 4096
1332 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1333 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1334 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1335 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1336 
`define OR1200_ICTAG_W                  21
1337 
`endif
1338 
`ifdef OR1200_IC_1W_8KB
1339 
`define OR1200_ICSIZE                   13                      // 8192
1340 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1341 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1342 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1343 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1344 
`define OR1200_ICTAG_W                  20
1345 
`endif
1346 
 
1347 
 
1348 
/////////////////////////////////////////////////
1349 
//
1350 
// Data cache (DC)
1351 
//
1352 
 
1353 
// 3 for 8 bytes, 4 for 16 bytes etc
1354 
`define OR1200_DCLS             4
1355 
 
1356 
// Define to perform store refill (potential performance penalty)
1357 
// `define OR1200_DC_STORE_REFILL
1358 
 
1359 
//
1360 
// DC configurations
1361 
//
1362 
`ifdef OR1200_DC_1W_4KB
1363 
`define OR1200_DCSIZE                   12                      // 4096
1364 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1365 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1366 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1367 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1368 
`define OR1200_DCTAG_W                  21
1369 
`endif
1370 
`ifdef OR1200_DC_1W_8KB
1371 
`define OR1200_DCSIZE                   13                      // 8192
1372 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1373 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1374 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1375 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1376 
`define OR1200_DCTAG_W                  20
1377 
`endif
1378 
 
1379 
/////////////////////////////////////////////////
1380 
//
1381 
// Store buffer (SB)
1382 
//
1383 
 
1384 
//
1385 
// Store buffer
1386 
//
1387 
// It will improve performance by "caching" CPU stores
1388 
// using store buffer. This is most important for function
1389 
// prologues because DC can only work in write though mode
1390 
// and all stores would have to complete external WB writes
1391 
// to memory.
1392 
// Store buffer is between DC and data BIU.
1393 
// All stores will be stored into store buffer and immediately
1394 
// completed by the CPU, even though actual external writes
1395 
// will be performed later. As a consequence store buffer masks
1396 
// all data bus errors related to stores (data bus errors
1397 
// related to loads are delivered normally).
1398 
// All pending CPU loads will wait until store buffer is empty to
1399 
// ensure strict memory model. Right now this is necessary because
1400 
// we don't make destinction between cached and cache inhibited
1401 
// address space, so we simply empty store buffer until loads
1402 
// can begin.
1403 
//
1404 
// It makes design a bit bigger, depending what is the number of
1405 
// entries in SB FIFO. Number of entries can be changed further
1406 
// down.
1407 
//
1408 
//`define OR1200_SB_IMPLEMENTED
1409 
 
1410 
//
1411 
// Number of store buffer entries
1412 
//
1413 
// Verified number of entries are 4 and 8 entries
1414 
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1415 
// always match 2**OR1200_SB_LOG.
1416 
// To disable store buffer, undefine
1417 
// OR1200_SB_IMPLEMENTED.
1418 
//
1419 
`define OR1200_SB_LOG           2       // 2 or 3
1420 
`define OR1200_SB_ENTRIES       4       // 4 or 8
1421 
 
1422 
 
1423 
/////////////////////////////////////////////////
1424 
//
1425 
// Quick Embedded Memory (QMEM)
1426 
//
1427 
 
1428 
//
1429 
// Quick Embedded Memory
1430 
//
1431 
// Instantiation of dedicated insn/data memory (RAM or ROM).
1432 
// Insn fetch has effective throughput 1insn / clock cycle.
1433 
// Data load takes two clock cycles / access, data store
1434 
// takes 1 clock cycle / access (if there is no insn fetch)).
1435 
// Memory instantiation is shared between insn and data,
1436 
// meaning if insn fetch are performed, data load/store
1437 
// performance will be lower.
1438 
//
1439 
// Main reason for QMEM is to put some time critical functions
1440 
// into this memory and to have predictable and fast access
1441 
// to these functions. (soft fpu, context switch, exception
1442 
// handlers, stack, etc)
1443 
//
1444 
// It makes design a bit bigger and slower. QMEM sits behind
1445 
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1446 
// used with QMEM and QMEM is seen by the CPU just like any other
1447 
// memory in the system). IC/DC are sitting behind QMEM so the
1448 
// whole design timing might be worse with QMEM implemented.
1449 
//
1450 
//`define OR1200_QMEM_IMPLEMENTED
1451 
 
1452 
//
1453 
// Base address and mask of QMEM
1454 
//
1455 
// Base address defines first address of QMEM. Mask defines
1456 
// QMEM range in address space. Actual size of QMEM is however
1457 
// determined with instantiated RAM/ROM. However bigger
1458 
// mask will reserve more address space for QMEM, but also
1459 
// make design faster, while more tight mask will take
1460 
// less address space but also make design slower. If
1461 
// instantiated RAM/ROM is smaller than space reserved with
1462 
// the mask, instatiated RAM/ROM will also be shadowed
1463 
// at higher addresses in reserved space.
1464 
//
1465 
`define OR1200_QMEM_IADDR       32'h0080_0000
1466 
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1467 
`define OR1200_QMEM_DADDR  32'h0080_0000
1468 
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1469 
 
1470 
//
1471 
// QMEM interface byte-select capability
1472 
//
1473 
// To enable qmem_sel* ports, define this macro.
1474 
//
1475 
//`define OR1200_QMEM_BSEL
1476 
 
1477 
//
1478 
// QMEM interface acknowledge
1479 
//
1480 
// To enable qmem_ack port, define this macro.
1481 
//
1482 
//`define OR1200_QMEM_ACK
1483 
 
1484 
/////////////////////////////////////////////////////
1485 
//
1486 
// VR, UPR and Configuration Registers
1487 
//
1488 
//
1489 
// VR, UPR and configuration registers are optional. If
1490 
// implemented, operating system can automatically figure
1491 
// out how to use the processor because it knows
1492 
// what units are available in the processor and how they
1493 
// are configured.
1494 
//
1495 
// This section must be last in or1200_defines.v file so
1496 
// that all units are already configured and thus
1497 
// configuration registers are properly set.
1498 
//
1499 
 
1500 
// Define if you want configuration registers implemented
1501 
`define OR1200_CFGR_IMPLEMENTED
1502 
 
1503 
// Define if you want full address decode inside SYS group
1504 
`define OR1200_SYS_FULL_DECODE
1505 
 
1506 
// Offsets of VR, UPR and CFGR registers
1507 
`define OR1200_SPRGRP_SYS_VR            4'h0
1508 
`define OR1200_SPRGRP_SYS_UPR           4'h1
1509 
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1510 
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1511 
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1512 
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1513 
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1514 
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1515 
 
1516 
// VR fields
1517 
`define OR1200_VR_REV_BITS              5:0
1518 
`define OR1200_VR_RES1_BITS             15:6
1519 
`define OR1200_VR_CFG_BITS              23:16
1520 
`define OR1200_VR_VER_BITS              31:24
1521 
 
1522 
// VR values
1523 
`define OR1200_VR_REV                   6'h01
1524 
`define OR1200_VR_RES1                  10'h000
1525 
`define OR1200_VR_CFG                   8'h00
1526 
`define OR1200_VR_VER                   8'h12
1527 
 
1528 
// UPR fields
1529 
`define OR1200_UPR_UP_BITS              0
1530 
`define OR1200_UPR_DCP_BITS             1
1531 
`define OR1200_UPR_ICP_BITS             2
1532 
`define OR1200_UPR_DMP_BITS             3
1533 
`define OR1200_UPR_IMP_BITS             4
1534 
`define OR1200_UPR_MP_BITS              5
1535 
`define OR1200_UPR_DUP_BITS             6
1536 
`define OR1200_UPR_PCUP_BITS            7
1537 
`define OR1200_UPR_PMP_BITS             8
1538 
`define OR1200_UPR_PICP_BITS            9
1539 
`define OR1200_UPR_TTP_BITS             10
1540 
`define OR1200_UPR_RES1_BITS            23:11
1541 
`define OR1200_UPR_CUP_BITS             31:24
1542 
 
1543 
// UPR values
1544 
`define OR1200_UPR_UP                   1'b1
1545 
`ifdef OR1200_NO_DC
1546 
`define OR1200_UPR_DCP                  1'b0
1547 
`else
1548 
`define OR1200_UPR_DCP                  1'b1
1549 
`endif
1550 
`ifdef OR1200_NO_IC
1551 
`define OR1200_UPR_ICP                  1'b0
1552 
`else
1553 
`define OR1200_UPR_ICP                  1'b1
1554 
`endif
1555 
`ifdef OR1200_NO_DMMU
1556 
`define OR1200_UPR_DMP                  1'b0
1557 
`else
1558 
`define OR1200_UPR_DMP                  1'b1
1559 
`endif
1560 
`ifdef OR1200_NO_IMMU
1561 
`define OR1200_UPR_IMP                  1'b0
1562 
`else
1563 
`define OR1200_UPR_IMP                  1'b1
1564 
`endif
1565 
`define OR1200_UPR_MP                   1'b1    // MAC always present
1566 
`ifdef OR1200_DU_IMPLEMENTED
1567 
`define OR1200_UPR_DUP                  1'b1
1568 
`else
1569 
`define OR1200_UPR_DUP                  1'b0
1570 
`endif
1571 
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1572 
`ifdef OR1200_DU_IMPLEMENTED
1573 
`define OR1200_UPR_PMP                  1'b1
1574 
`else
1575 
`define OR1200_UPR_PMP                  1'b0
1576 
`endif
1577 
`ifdef OR1200_DU_IMPLEMENTED
1578 
`define OR1200_UPR_PICP                 1'b1
1579 
`else
1580 
`define OR1200_UPR_PICP                 1'b0
1581 
`endif
1582 
`ifdef OR1200_DU_IMPLEMENTED
1583 
`define OR1200_UPR_TTP                  1'b1
1584 
`else
1585 
`define OR1200_UPR_TTP                  1'b0
1586 
`endif
1587 
`define OR1200_UPR_RES1                 13'h0000
1588 
`define OR1200_UPR_CUP                  8'h00
1589 
 
1590 
// CPUCFGR fields
1591 
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1592 
`define OR1200_CPUCFGR_HGF_BITS     4
1593 
`define OR1200_CPUCFGR_OB32S_BITS       5
1594 
`define OR1200_CPUCFGR_OB64S_BITS       6
1595 
`define OR1200_CPUCFGR_OF32S_BITS       7
1596 
`define OR1200_CPUCFGR_OF64S_BITS       8
1597 
`define OR1200_CPUCFGR_OV64S_BITS       9
1598 
`define OR1200_CPUCFGR_RES1_BITS        31:10
1599 
 
1600 
// CPUCFGR values
1601 
`define OR1200_CPUCFGR_NSGF                 4'h0
1602 
`ifdef OR1200_RFRAM_16REG
1603 
    `define OR1200_CPUCFGR_HGF                  1'b1
1604 
`else
1605 
    `define OR1200_CPUCFGR_HGF                  1'b0
1606 
`endif
1607 
`define OR1200_CPUCFGR_OB32S            1'b1
1608 
`define OR1200_CPUCFGR_OB64S            1'b0
1609 
`define OR1200_CPUCFGR_OF32S            1'b0
1610 
`define OR1200_CPUCFGR_OF64S            1'b0
1611 
`define OR1200_CPUCFGR_OV64S            1'b0
1612 
`define OR1200_CPUCFGR_RES1             22'h000000
1613 
 
1614 
// DMMUCFGR fields
1615 
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1616 
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1617 
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1618 
`define OR1200_DMMUCFGR_CRI_BITS        8
1619 
`define OR1200_DMMUCFGR_PRI_BITS        9
1620 
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1621 
`define OR1200_DMMUCFGR_HTR_BITS        11
1622 
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1623 
 
1624 
// DMMUCFGR values
1625 
`ifdef OR1200_NO_DMMU
1626 
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1627 
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1628 
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1629 
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1630 
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1631 
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1632 
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1633 
`define OR1200_DMMUCFGR_RES1            20'h00000
1634 
`else
1635 
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1636 
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1637 
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1638 
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1639 
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1640 
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1641 
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1642 
`define OR1200_DMMUCFGR_RES1            20'h00000
1643 
`endif
1644 
 
1645 
// IMMUCFGR fields
1646 
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1647 
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1648 
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1649 
`define OR1200_IMMUCFGR_CRI_BITS        8
1650 
`define OR1200_IMMUCFGR_PRI_BITS        9
1651 
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1652 
`define OR1200_IMMUCFGR_HTR_BITS        11
1653 
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1654 
 
1655 
// IMMUCFGR values
1656 
`ifdef OR1200_NO_IMMU
1657 
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1658 
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1659 
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1660 
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1661 
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1662 
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1663 
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1664 
`define OR1200_IMMUCFGR_RES1            20'h00000
1665 
`else
1666 
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1667 
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1668 
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1669 
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1670 
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1671 
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1672 
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1673 
`define OR1200_IMMUCFGR_RES1            20'h00000
1674 
`endif
1675 
 
1676 
// DCCFGR fields
1677 
`define OR1200_DCCFGR_NCW_BITS          2:0
1678 
`define OR1200_DCCFGR_NCS_BITS          6:3
1679 
`define OR1200_DCCFGR_CBS_BITS          7
1680 
`define OR1200_DCCFGR_CWS_BITS          8
1681 
`define OR1200_DCCFGR_CCRI_BITS         9
1682 
`define OR1200_DCCFGR_CBIRI_BITS        10
1683 
`define OR1200_DCCFGR_CBPRI_BITS        11
1684 
`define OR1200_DCCFGR_CBLRI_BITS        12
1685 
`define OR1200_DCCFGR_CBFRI_BITS        13
1686 
`define OR1200_DCCFGR_CBWBRI_BITS       14
1687 
`define OR1200_DCCFGR_RES1_BITS 31:15
1688 
 
1689 
// DCCFGR values
1690 
`ifdef OR1200_NO_DC
1691 
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1692 
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1693 
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1694 
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1695 
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1696 
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1697 
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1698 
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1699 
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1700 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1701 
`define OR1200_DCCFGR_RES1              17'h00000
1702 
`else
1703 
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1704 
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1705 
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1706 
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1707 
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1708 
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1709 
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1710 
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1711 
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1712 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1713 
`define OR1200_DCCFGR_RES1              17'h00000
1714 
`endif
1715 
 
1716 
// ICCFGR fields
1717 
`define OR1200_ICCFGR_NCW_BITS          2:0
1718 
`define OR1200_ICCFGR_NCS_BITS          6:3
1719 
`define OR1200_ICCFGR_CBS_BITS          7
1720 
`define OR1200_ICCFGR_CWS_BITS          8
1721 
`define OR1200_ICCFGR_CCRI_BITS         9
1722 
`define OR1200_ICCFGR_CBIRI_BITS        10
1723 
`define OR1200_ICCFGR_CBPRI_BITS        11
1724 
`define OR1200_ICCFGR_CBLRI_BITS        12
1725 
`define OR1200_ICCFGR_CBFRI_BITS        13
1726 
`define OR1200_ICCFGR_CBWBRI_BITS       14
1727 
`define OR1200_ICCFGR_RES1_BITS 31:15
1728 
 
1729 
// ICCFGR values
1730 
`ifdef OR1200_NO_IC
1731 
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1732 
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1733 
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1734 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1735 
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1736 
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1737 
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1738 
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1739 
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1740 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1741 
`define OR1200_ICCFGR_RES1              17'h00000
1742 
`else
1743 
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1744 
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1745 
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1746 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1747 
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1748 
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1749 
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1750 
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1751 
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1752 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1753 
`define OR1200_ICCFGR_RES1              17'h00000
1754 
`endif
1755 
 
1756 
// DCFGR fields
1757 
`define OR1200_DCFGR_NDP_BITS           2:0
1758 
`define OR1200_DCFGR_WPCI_BITS          3
1759 
`define OR1200_DCFGR_RES1_BITS          31:4
1760 
 
1761 
// DCFGR values
1762 
`ifdef OR1200_DU_HWBKPTS
1763 
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1764 
`ifdef OR1200_DU_DWCR0
1765 
`define OR1200_DCFGR_WPCI               1'b1
1766 
`else
1767 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1768 
`endif
1769 
`else
1770 
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1771 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1772 
`endif
1773 
`define OR1200_DCFGR_RES1               28'h0000000
1774 
 

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