OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sim/] [bin/] [Makefile] - Blame information for rev 32

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 julius
 
2
CUR_DIR=$(shell pwd)
3
PROJECT_ROOT=$(CUR_DIR)/../..
4
 
5
 
6 26 julius
#TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
7 32 julius
TESTS = basic-nocache cbasic-nocache-O2
8 22 julius
 
9
SIM_DIR=$(PROJECT_ROOT)/sim
10
SIM_RUN_DIR=$(SIM_DIR)/run
11
SIM_BIN_DIR=$(SIM_DIR)/bin
12
SIM_RESULTS_DIR=$(SIM_DIR)/results
13
 
14
BENCH_DIR=$(PROJECT_ROOT)/bench
15
BACKEND_DIR=$(PROJECT_ROOT)/backend
16
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
17
 
18
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
19
 
20
 
21
SW_DIR=$(PROJECT_ROOT)/sw
22
 
23
ICARUS=iverilog
24
ICARUS_VVP=vvp
25
ICARUS_COMMAND_FILE=icarus.scr
26
SIM_MEM_FILE="flash.in"
27 32 julius
SIM_SUCCESS_MESSAGE=deaddead
28 22 julius
 
29
.PHONY: prepare_rtl
30
prepare_rtl:
31 26 julius
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
32 22 julius
 
33 26 julius
.PHONY: prepare_sw
34
prepare_sw:
35
        @$(MAKE) -C $(SW_DIR)/support
36
        @$(MAKE) -C $(SW_DIR)/utils
37
 
38
test-make: prepare_sw prepare_rtl
39 22 julius
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
40
        @echo "Beginning tests"
41 31 julius
 
42
        @for TEST in $(TESTS); do \
43 32 julius
                echo; echo "\t#### Current test: $$TEST ####"; echo; \
44
                echo "\t#### Compiling software ####"; echo; \
45 22 julius
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
46
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
47
                rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
48
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
49
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
50
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
51
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
52
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
53
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
54 26 julius
                echo "+define+TEST_NAME_STRING=\"$$TEST\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
55
                if [ ! -z $$VCD ]; \
56
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
57
                fi; \
58 22 julius
                echo ; \
59 32 julius
                echo "\t#### Compiling RTL ####"; \
60 22 julius
                rm -f $(SIM_RUN_DIR)/a.out; \
61
                $(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
62
                echo; \
63 32 julius
                echo "\t#### Beginning simulation ####"; \
64
                $(ICARUS_VVP) a.out > $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log; \
65
                TEST_RESULT=`tail -n 1 $(SIM_RESULTS_DIR)/$$TEST-general.log | grep $(SIM_SUCCESS_MESSAGE) -c`; \
66
                echo; echo "\t####---------------------####"; \
67
                if [ ! -z $$TEST_RESULT ]; then \
68
                        echo "\t#### Test $$TEST PASSED ####";\
69
                else    echo "\t#### Test $$TEST FAILED ####";\
70
                fi; \
71
                echo "\t####---------------------####"; echo; \
72 22 julius
        done
73 31 julius
#ps aux | grep "xterm -e $(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log" | awk '{ print $2 }' | xargs kill; \
74 22 julius
 
75 31 julius
#               if [ ! -z $OR1K_MONITOR ]; then \
76
                        if [ ! -z $DISPLAY ]; then \
77
                                $(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log; \
78
                        fi; \
79
                fi; \
80 22 julius
 
81
 
82
clean-sw:
83
        @for TEST in $(TESTS); do \
84
                echo "Current test: $$TEST"; \
85
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
86
                echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
87
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
88
        done
89 31 julius
        $(MAKE) -C $(SW_DIR)/support clean
90
        $(MAKE) -C $(SW_DIR)/utils clean
91
 
92
clean-sim:
93
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.*

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.